108 lines
2.6 KiB
Plaintext
108 lines
2.6 KiB
Plaintext
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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{ name: "uart",
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clocking: [{clock: "clk_i", reset: "rst_ni"}],
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bus_interfaces: [
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{ protocol: "tlul", direction: "device" }
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],
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regwidth: "32",
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registers: [
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{ name: "CTRL",
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desc: "UART control register",
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swaccess: "rw",
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hwaccess: "hro",
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hwqe: "true",
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fields: [
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{ bits: "0",
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name: "TX_EN",
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desc: "TX enable"
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}
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{ bits: "1",
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name: "RX_EN",
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desc: "RX enable"
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}
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{ bits: "2",
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name: "TX_FIFO_EMPTY_INT_EN",
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desc: "Generate interrupt signal when tx fifo empty"
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}
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{ bits: "3",
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name: "RX_FIFO_NOT_EMPTY_INT_EN",
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desc: "Generate interrupt signal when rx fifo not empty"
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}
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{ bits: "4",
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name: "TX_FIFO_RST",
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desc: "Reset tx fifo",
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swaccess: "r0w1c"
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}
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{ bits: "5",
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name: "RX_FIFO_RST",
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desc: "Reset rx fifo",
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swaccess: "r0w1c"
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}
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{ bits: "31:16",
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name: "BAUD_DIV",
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desc: "Baud rate divider count",
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resval: "0xD9"
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}
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]
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}
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{ name: "STATUS"
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desc: "UART status register"
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swaccess: "ro"
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hwaccess: "hrw"
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hwext: "true"
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hwre: "true"
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fields: [
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{ bits: "0"
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name: "TXFULL"
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desc: "TX FIFO is full"
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}
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{ bits: "1"
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name: "RXFULL"
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desc: "RX FIFO is full"
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}
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{ bits: "2"
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name: "TXEMPTY"
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desc: "TX FIFO is empty"
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resval: "1"
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}
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{ bits: "3"
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name: "RXEMPTY"
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desc: "RX FIFO is empty"
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resval: "1"
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}
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{ bits: "4"
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name: "TXIDLE"
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desc: "TX FIFO is empty and all bits have been transmitted"
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resval: "1"
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}
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{ bits: "5"
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name: "RXIDLE"
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desc: "RX is idle"
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resval: "1"
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}
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]
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}
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{ name: "TXDATA",
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desc: "UART TX data register",
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swaccess: "wo",
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hwaccess: "hro",
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hwqe: "true",
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fields: [
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{ bits: "7:0" }
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]
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}
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{ name: "RXDATA",
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desc: "UART RX data register",
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swaccess: "ro",
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hwaccess: "hrw",
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hwext: "true",
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hwre: "true",
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fields: [
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{ bits: "7:0" }
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]
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}
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]
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}
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