474 lines
11 KiB
Systemverilog
474 lines
11 KiB
Systemverilog
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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//
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// Register Top module auto-generated by `reggen`
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module uart_reg_top (
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input logic clk_i,
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input logic rst_ni,
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// To HW
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output uart_reg_pkg::uart_reg2hw_t reg2hw, // Write
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input uart_reg_pkg::uart_hw2reg_t hw2reg, // Read
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input logic reg_we,
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input logic reg_re,
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input logic [31:0] reg_wdata,
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input logic [ 3:0] reg_be,
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input logic [31:0] reg_addr,
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output logic [31:0] reg_rdata
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);
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import uart_reg_pkg::* ;
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localparam int AW = 4;
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localparam int DW = 32;
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localparam int DBW = DW/8; // Byte Width
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logic reg_error;
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logic addrmiss, wr_err;
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logic [DW-1:0] reg_rdata_next;
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assign reg_rdata = reg_rdata_next;
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assign reg_error = wr_err;
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// Define SW related signals
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// Format: <reg>_<field>_{wd|we|qs}
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// or <reg>_{wd|we|qs} if field == 1 or 0
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logic ctrl_we;
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logic ctrl_tx_en_qs;
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logic ctrl_tx_en_wd;
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logic ctrl_rx_en_qs;
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logic ctrl_rx_en_wd;
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logic ctrl_tx_fifo_empty_int_en_qs;
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logic ctrl_tx_fifo_empty_int_en_wd;
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logic ctrl_rx_fifo_not_empty_int_en_qs;
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logic ctrl_rx_fifo_not_empty_int_en_wd;
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logic ctrl_tx_fifo_rst_wd;
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logic ctrl_rx_fifo_rst_wd;
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logic [15:0] ctrl_baud_div_qs;
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logic [15:0] ctrl_baud_div_wd;
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logic status_re;
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logic status_txfull_qs;
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logic status_rxfull_qs;
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logic status_txempty_qs;
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logic status_rxempty_qs;
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logic status_txidle_qs;
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logic status_rxidle_qs;
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logic txdata_we;
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logic [7:0] txdata_wd;
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logic rxdata_re;
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logic [7:0] rxdata_qs;
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// Register instances
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// R[ctrl]: V(False)
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// F[tx_en]: 0:0
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_tx_en (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_tx_en_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (reg2hw.ctrl.tx_en.qe),
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.q (reg2hw.ctrl.tx_en.q),
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// to register interface (read)
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.qs (ctrl_tx_en_qs)
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);
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// F[rx_en]: 1:1
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_rx_en (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_rx_en_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (reg2hw.ctrl.rx_en.qe),
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.q (reg2hw.ctrl.rx_en.q),
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// to register interface (read)
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.qs (ctrl_rx_en_qs)
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);
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// F[tx_fifo_empty_int_en]: 2:2
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_tx_fifo_empty_int_en (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_tx_fifo_empty_int_en_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (reg2hw.ctrl.tx_fifo_empty_int_en.qe),
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.q (reg2hw.ctrl.tx_fifo_empty_int_en.q),
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// to register interface (read)
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.qs (ctrl_tx_fifo_empty_int_en_qs)
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);
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// F[rx_fifo_not_empty_int_en]: 3:3
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prim_subreg #(
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.DW (1),
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.SWACCESS("RW"),
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.RESVAL (1'h0)
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) u_ctrl_rx_fifo_not_empty_int_en (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_rx_fifo_not_empty_int_en_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (reg2hw.ctrl.rx_fifo_not_empty_int_en.qe),
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.q (reg2hw.ctrl.rx_fifo_not_empty_int_en.q),
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// to register interface (read)
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.qs (ctrl_rx_fifo_not_empty_int_en_qs)
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);
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// F[tx_fifo_rst]: 4:4
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prim_subreg #(
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.DW (1),
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.SWACCESS("W1C"),
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.RESVAL (1'h0)
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) u_ctrl_tx_fifo_rst (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_tx_fifo_rst_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (reg2hw.ctrl.tx_fifo_rst.qe),
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.q (reg2hw.ctrl.tx_fifo_rst.q),
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// to register interface (read)
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.qs ()
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);
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// F[rx_fifo_rst]: 5:5
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prim_subreg #(
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.DW (1),
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.SWACCESS("W1C"),
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.RESVAL (1'h0)
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) u_ctrl_rx_fifo_rst (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_rx_fifo_rst_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (reg2hw.ctrl.rx_fifo_rst.qe),
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.q (reg2hw.ctrl.rx_fifo_rst.q),
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// to register interface (read)
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.qs ()
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);
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// F[baud_div]: 31:16
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prim_subreg #(
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.DW (16),
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.SWACCESS("RW"),
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.RESVAL (16'hd9)
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) u_ctrl_baud_div (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (ctrl_we),
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.wd (ctrl_baud_div_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (reg2hw.ctrl.baud_div.qe),
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.q (reg2hw.ctrl.baud_div.q),
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// to register interface (read)
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.qs (ctrl_baud_div_qs)
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);
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// R[status]: V(True)
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// F[txfull]: 0:0
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prim_subreg_ext #(
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.DW (1)
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) u_status_txfull (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.txfull.d),
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.qre (reg2hw.status.txfull.re),
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.qe (),
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.q (reg2hw.status.txfull.q),
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.qs (status_txfull_qs)
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);
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// F[rxfull]: 1:1
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prim_subreg_ext #(
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.DW (1)
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) u_status_rxfull (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.rxfull.d),
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.qre (reg2hw.status.rxfull.re),
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.qe (),
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.q (reg2hw.status.rxfull.q),
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.qs (status_rxfull_qs)
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);
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// F[txempty]: 2:2
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prim_subreg_ext #(
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.DW (1)
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) u_status_txempty (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.txempty.d),
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.qre (reg2hw.status.txempty.re),
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.qe (),
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.q (reg2hw.status.txempty.q),
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.qs (status_txempty_qs)
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);
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// F[rxempty]: 3:3
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prim_subreg_ext #(
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.DW (1)
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) u_status_rxempty (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.rxempty.d),
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.qre (reg2hw.status.rxempty.re),
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.qe (),
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.q (reg2hw.status.rxempty.q),
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.qs (status_rxempty_qs)
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);
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// F[txidle]: 4:4
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prim_subreg_ext #(
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.DW (1)
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) u_status_txidle (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.txidle.d),
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.qre (reg2hw.status.txidle.re),
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.qe (),
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.q (reg2hw.status.txidle.q),
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.qs (status_txidle_qs)
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);
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// F[rxidle]: 5:5
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prim_subreg_ext #(
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.DW (1)
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) u_status_rxidle (
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.re (status_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.status.rxidle.d),
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.qre (reg2hw.status.rxidle.re),
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.qe (),
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.q (reg2hw.status.rxidle.q),
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.qs (status_rxidle_qs)
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);
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// R[txdata]: V(False)
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prim_subreg #(
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.DW (8),
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.SWACCESS("WO"),
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.RESVAL (8'h0)
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) u_txdata (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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// from register interface
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.we (txdata_we),
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.wd (txdata_wd),
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// from internal hardware
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.de (1'b0),
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.d ('0),
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// to internal hardware
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.qe (reg2hw.txdata.qe),
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.q (reg2hw.txdata.q),
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// to register interface (read)
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.qs ()
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);
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// R[rxdata]: V(True)
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prim_subreg_ext #(
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.DW (8)
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) u_rxdata (
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.re (rxdata_re),
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.we (1'b0),
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.wd ('0),
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.d (hw2reg.rxdata.d),
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.qre (reg2hw.rxdata.re),
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.qe (),
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.q (reg2hw.rxdata.q),
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.qs (rxdata_qs)
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);
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logic [3:0] addr_hit;
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always_comb begin
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addr_hit = '0;
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addr_hit[0] = (reg_addr == UART_CTRL_OFFSET);
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addr_hit[1] = (reg_addr == UART_STATUS_OFFSET);
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addr_hit[2] = (reg_addr == UART_TXDATA_OFFSET);
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addr_hit[3] = (reg_addr == UART_RXDATA_OFFSET);
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end
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assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
|
||
|
|
|
||
|
|
// Check sub-word write is permitted
|
||
|
|
always_comb begin
|
||
|
|
wr_err = (reg_we &
|
||
|
|
((addr_hit[0] & (|(UART_PERMIT[0] & ~reg_be))) |
|
||
|
|
(addr_hit[1] & (|(UART_PERMIT[1] & ~reg_be))) |
|
||
|
|
(addr_hit[2] & (|(UART_PERMIT[2] & ~reg_be))) |
|
||
|
|
(addr_hit[3] & (|(UART_PERMIT[3] & ~reg_be)))));
|
||
|
|
end
|
||
|
|
|
||
|
|
assign ctrl_we = addr_hit[0] & reg_we & !reg_error;
|
||
|
|
|
||
|
|
assign ctrl_tx_en_wd = reg_wdata[0];
|
||
|
|
|
||
|
|
assign ctrl_rx_en_wd = reg_wdata[1];
|
||
|
|
|
||
|
|
assign ctrl_tx_fifo_empty_int_en_wd = reg_wdata[2];
|
||
|
|
|
||
|
|
assign ctrl_rx_fifo_not_empty_int_en_wd = reg_wdata[3];
|
||
|
|
|
||
|
|
assign ctrl_tx_fifo_rst_wd = reg_wdata[4];
|
||
|
|
|
||
|
|
assign ctrl_rx_fifo_rst_wd = reg_wdata[5];
|
||
|
|
|
||
|
|
assign ctrl_baud_div_wd = reg_wdata[31:16];
|
||
|
|
assign status_re = addr_hit[1] & reg_re & !reg_error;
|
||
|
|
assign txdata_we = addr_hit[2] & reg_we & !reg_error;
|
||
|
|
|
||
|
|
assign txdata_wd = reg_wdata[7:0];
|
||
|
|
assign rxdata_re = addr_hit[3] & reg_re & !reg_error;
|
||
|
|
|
||
|
|
// Read data return
|
||
|
|
always_comb begin
|
||
|
|
reg_rdata_next = '0;
|
||
|
|
unique case (1'b1)
|
||
|
|
addr_hit[0]: begin
|
||
|
|
reg_rdata_next[0] = ctrl_tx_en_qs;
|
||
|
|
reg_rdata_next[1] = ctrl_rx_en_qs;
|
||
|
|
reg_rdata_next[2] = ctrl_tx_fifo_empty_int_en_qs;
|
||
|
|
reg_rdata_next[3] = ctrl_rx_fifo_not_empty_int_en_qs;
|
||
|
|
reg_rdata_next[4] = '0;
|
||
|
|
reg_rdata_next[5] = '0;
|
||
|
|
reg_rdata_next[31:16] = ctrl_baud_div_qs;
|
||
|
|
end
|
||
|
|
|
||
|
|
addr_hit[1]: begin
|
||
|
|
reg_rdata_next[0] = status_txfull_qs;
|
||
|
|
reg_rdata_next[1] = status_rxfull_qs;
|
||
|
|
reg_rdata_next[2] = status_txempty_qs;
|
||
|
|
reg_rdata_next[3] = status_rxempty_qs;
|
||
|
|
reg_rdata_next[4] = status_txidle_qs;
|
||
|
|
reg_rdata_next[5] = status_rxidle_qs;
|
||
|
|
end
|
||
|
|
|
||
|
|
addr_hit[2]: begin
|
||
|
|
reg_rdata_next[7:0] = '0;
|
||
|
|
end
|
||
|
|
|
||
|
|
addr_hit[3]: begin
|
||
|
|
reg_rdata_next[7:0] = rxdata_qs;
|
||
|
|
end
|
||
|
|
|
||
|
|
default: begin
|
||
|
|
reg_rdata_next = '1;
|
||
|
|
end
|
||
|
|
endcase
|
||
|
|
end
|
||
|
|
|
||
|
|
// Unused signal tieoff
|
||
|
|
|
||
|
|
// wdata / byte enable are not always fully used
|
||
|
|
// add a blanket unused statement to handle lint waivers
|
||
|
|
logic unused_wdata;
|
||
|
|
logic unused_be;
|
||
|
|
assign unused_wdata = ^reg_wdata;
|
||
|
|
assign unused_be = ^reg_be;
|
||
|
|
|
||
|
|
endmodule
|