87 lines
2.1 KiB
Plaintext
87 lines
2.1 KiB
Plaintext
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// Copyright lowRISC contributors.
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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{ name: "i2c",
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clocking: [{clock: "clk_i", reset: "rst_ni"}],
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bus_interfaces: [
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{ protocol: "tlul", direction: "device" }
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],
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regwidth: "32",
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registers: [
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{ name: "CTRL",
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desc: "I2C control register",
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swaccess: "rw",
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hwaccess: "hrw",
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hwqe: "true",
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fields: [
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{ bits: "0",
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name: "START",
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desc: "I2C start",
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}
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{ bits: "1",
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name: "INT_EN",
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desc: "I2C interrupt enable",
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}
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{ bits: "2",
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name: "INT_PENDING",
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swaccess: "rw1c",
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desc: "I2C interrupt pending",
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}
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{ bits: "3",
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name: "MODE",
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desc: "I2C mode, 0: master, 1: slave",
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}
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{ bits: "4",
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name: "WRITE",
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desc: "0: write, 1: read",
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}
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{ bits: "5",
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name: "ACK",
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swaccess: "ro",
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desc: "0: ack, 1: nack",
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}
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{ bits: "6",
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name: "ERROR",
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swaccess: "ro",
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desc: "0: no error, 1: error",
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}
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{ bits: "31:16",
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name: "CLK_DIV",
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desc: "I2C clock divider count",
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}
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]
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}
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{ name: "MASTER_DATA",
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desc: "I2C master transfer data register",
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swaccess: "rw",
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hwaccess: "hrw",
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fields: [
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{ bits: "7:0",
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name: "ADDRESS",
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desc: "I2C slave address",
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}
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{ bits: "15:8",
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name: "REGREG",
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desc: "I2C write or read reg",
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}
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{ bits: "23:16",
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name: "DATA",
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desc: "I2C write or read data",
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}
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]
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}
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{ name: "SLAVE_DATA",
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desc: "I2C slave received data register",
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swaccess: "ro",
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hwaccess: "hrw",
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hwext: "true",
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hwre: "true",
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fields: [
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{ bits: "7:0",
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desc: "I2C slave received data(fifo)",
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}
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]
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}
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]
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}
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