118 lines
3.7 KiB
Systemverilog
118 lines
3.7 KiB
Systemverilog
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/*
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Copyright 2021 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module machine_timer(
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input wire clk,
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input wire rst_n,
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input wire[31:0] addr_i,
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input wire[31:0] data_i,
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input wire[3:0] sel_i,
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input wire we_i,
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output wire[31:0] data_o,
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output wire irq_o
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);
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localparam mtime_ctrl_reg = 4'h0;
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localparam mtime_cmp_reg = 4'h4;
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localparam mtime_count_reg = 4'h8;
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localparam start = 0;
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localparam irq_pending = 1;
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reg[31:0] mtime_ctrl_d, mtime_ctrl_q;
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reg[31:0] mtime_cmp_d, mtime_cmp_q;
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reg[31:0] mtime_count_q;
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reg data_q;
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wire[3:0] rw_addr = addr_i[3:0];
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wire w0 = we_i & sel_i[0];
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wire w1 = we_i & sel_i[1];
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wire w2 = we_i & sel_i[2];
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wire w3 = we_i & sel_i[3];
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// write
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always @ (*) begin
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mtime_cmp_d = mtime_cmp_q;
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mtime_ctrl_d = mtime_ctrl_q;
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case (rw_addr)
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mtime_ctrl_reg: begin
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if (w0) begin
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mtime_ctrl_d[0] = data_i[0];
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mtime_ctrl_d[irq_pending] = mtime_ctrl_q & (~data_i[irq_pending]);
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end
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end
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mtime_cmp_reg: begin
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if (w0) mtime_cmp_d[7:0] = data_i[7:0];
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if (w1) mtime_cmp_d[15:8] = data_i[15:8];
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if (w2) mtime_cmp_d[23:16] = data_i[23:16];
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if (w3) mtime_cmp_d[31:24] = data_i[31:24];
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end
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default:;
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endcase
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if (mtime_count_q == mtime_cmp_q) begin
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mtime_ctrl_d[irq_pending] = 1'b1;
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end
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end
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assign irq_o = mtime_ctrl_q[irq_pending] & mtime_ctrl_q[start];
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// read
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always @ (*) begin
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data_q = 32'h0;
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case (rw_addr)
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mtime_ctrl_reg: data_q = mtime_ctrl_q;
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mtime_cmp_reg: data_q = mtime_cmp_q;
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mtime_count_reg: data_q = mtime_count_q;
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default:;
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endcase
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end
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assign data_o = data_q;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mtime_ctrl_q <= 32'h0;
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mtime_cmp_q <= 32'h0;
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end else begin
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mtime_ctrl_q <= mtime_ctrl_d;
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mtime_cmp_q <= mtime_cmp_d;
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end
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end
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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mtime_count_q <= 32'h0;
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end else begin
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if (mtime_ctrl_q[start]) begin
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mtime_count_q <= mtime_count_q + 1'b1;
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if (mtime_count_q == mtime_cmp_q) begin
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mtime_count_q <= 32'h0;
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end
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end else begin
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mtime_count_q <= 32'h0;
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end
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end
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end
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endmodule
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