58 lines
1.9 KiB
Systemverilog
58 lines
1.9 KiB
Systemverilog
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/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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module vld_rdy #(
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parameter CUT_READY = 0)(
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input wire clk,
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input wire rst_n,
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input wire vld_i,
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output wire rdy_o,
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input wire rdy_i,
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output wire vld_o
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);
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wire vld_set;
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wire vld_clr;
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wire vld_ena;
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wire vld_r;
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wire vld_nxt;
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// The valid will be set when input handshaked
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assign vld_set = vld_i & rdy_o;
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// The valid will be clr when output handshaked
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assign vld_clr = vld_o & rdy_i;
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assign vld_ena = vld_set | vld_clr;
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assign vld_nxt = vld_set | (~vld_clr);
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gen_en_dff #(1) vld_dff(clk, rst_n, vld_ena, vld_nxt, vld_r);
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assign vld_o = vld_r;
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if (CUT_READY == 1) begin
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// If cut ready, then only accept when stage is not full
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assign rdy_o = (~vld_r);
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end else begin
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// If not cut ready, then can accept when stage is not full or it is popping
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assign rdy_o = (~vld_r) | vld_clr;
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end
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endmodule
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