60 lines
1.9 KiB
Systemverilog
60 lines
1.9 KiB
Systemverilog
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/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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`include "defines.sv"
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// 复位控制模块
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module rst_ctrl(
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input wire clk,
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input wire rst_ext_i,
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input wire rst_jtag_i,
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output wire core_rst_n_o,
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output wire jtag_rst_n_o
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);
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wire ext_rst_r;
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gen_ticks_sync #(
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.DP(2),
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.DW(1)
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) ext_rst_sync(
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.rst_n(rst_ext_i),
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.clk(clk),
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.din(1'b1),
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.dout(ext_rst_r)
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);
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reg[`JTAG_RESET_FF_LEVELS-1:0] jtag_rst_r;
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always @ (posedge clk) begin
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if (!rst_ext_i) begin
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jtag_rst_r[`JTAG_RESET_FF_LEVELS-1:0] <= {`JTAG_RESET_FF_LEVELS{1'b1}};
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end if (rst_jtag_i) begin
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jtag_rst_r[`JTAG_RESET_FF_LEVELS-1:0] <= {`JTAG_RESET_FF_LEVELS{1'b0}};
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end else begin
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jtag_rst_r[`JTAG_RESET_FF_LEVELS-1:0] <= {jtag_rst_r[`JTAG_RESET_FF_LEVELS-2:0], 1'b1};
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end
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end
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assign core_rst_n_o = ext_rst_r & jtag_rst_r[`JTAG_RESET_FF_LEVELS-1];
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assign jtag_rst_n_o = ext_rst_r;
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endmodule
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