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add mie and mstatus reg 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-04-25 17:13:12 +08:00
parent 4a530ab894
commit 02d19b9e6f
1 changed files with 50 additions and 10 deletions
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60
rtl/core/csr_reg.v
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@ -23,22 +23,27 @@ module csr_reg(
input wire rst,
// form ex
input wire we_i,
input wire[`MemAddrBus] raddr_i,
input wire[`MemAddrBus] waddr_i,
input wire[`RegBus] data_i,
input wire we_i, // ex模块写寄存器标志
input wire[`MemAddrBus] raddr_i, // ex模块读寄存器地址
input wire[`MemAddrBus] waddr_i, // ex模块写寄存器地址
input wire[`RegBus] data_i, // ex模块写寄存器数据
// from clint
input wire clint_we_i,
input wire[`MemAddrBus] clint_raddr_i,
input wire[`MemAddrBus] clint_waddr_i,
input wire[`RegBus] clint_data_i,
input wire clint_we_i, // clint模块写寄存器标志
input wire[`MemAddrBus] clint_raddr_i, // clint模块读寄存器地址
input wire[`MemAddrBus] clint_waddr_i, // clint模块写寄存器地址
input wire[`RegBus] clint_data_i, // clint模块写寄存器数据
output wire global_int_en_o, // 全局中断使能标志
// to clint
output reg[`RegBus] clint_data_o,
output reg[`RegBus] clint_data_o, // clint模块读寄存器数据
output wire[`RegBus] clint_csr_mtvec, // mtvec
output wire[`RegBus] clint_csr_mepc, // mepc
output wire[`RegBus] clint_csr_mstatus, // mstatus
// to ex
output reg[`RegBus] data_o
output reg[`RegBus] data_o // ex模块读寄存器数据
);
@ -47,6 +52,15 @@ module csr_reg(
reg[`RegBus] mtvec;
reg[`RegBus] mcause;
reg[`RegBus] mepc;
reg[`RegBus] mie;
reg[`RegBus] mstatus;
assign global_int_en_o = (mstatus[3] == 1'b1)? `True: `False;
assign clint_csr_mtvec = mtvec;
assign clint_csr_mepc = mepc;
assign clint_csr_mstatus = mstatus;
// cycle counter
@ -66,6 +80,8 @@ module csr_reg(
mtvec <= `ZeroWord;
mcause <= `ZeroWord;
mepc <= `ZeroWord;
mie <= `ZeroWord;
mstatus <= `ZeroWord;
end else begin
// 优先响应ex模块的写操作
if (we_i == `WriteEnable) begin
@ -79,6 +95,12 @@ module csr_reg(
`CSR_MEPC: begin
mepc <= data_i;
end
`CSR_MIE: begin
mie <= data_i;
end
`CSR_MSTATUS: begin
mstatus <= data_i;
end
default: begin
end
@ -95,6 +117,12 @@ module csr_reg(
`CSR_MEPC: begin
mepc <= clint_data_i;
end
`CSR_MIE: begin
mie <= clint_data_i;
end
`CSR_MSTATUS: begin
mstatus <= clint_data_i;
end
default: begin
end
@ -125,6 +153,12 @@ module csr_reg(
`CSR_MEPC: begin
data_o <= mepc;
end
`CSR_MIE: begin
data_o <= mie;
end
`CSR_MSTATUS: begin
data_o <= mstatus;
end
default: begin
data_o <= `ZeroWord;
end
@ -154,6 +188,12 @@ module csr_reg(
`CSR_MEPC: begin
clint_data_o <= mepc;
end
`CSR_MIE: begin
clint_data_o <= mie;
end
`CSR_MSTATUS: begin
clint_data_o <= mstatus;
end
default: begin
clint_data_o <= `ZeroWord;
end