use = instead of <= in combination logic

Signed-off-by: liangkangnan <liangkangnan@163.com>

rtl/perips/gpio.v

@@ -57,11 +57,14 @@ module gpio(
 
     always @ (*) begin
         if (rst == 1'b0) begin
-            data_o <= 32'h0;
+            data_o = 32'h0;
         end else begin
             case (addr_i[3:0])
                 GPIO_DATA: begin
-                    data_o <= gpio_data;
+                    data_o = gpio_data;
+                end
+                default: begin
+                    data_o = 32'h0;
                 end
             endcase
         end

rtl/perips/ram.v

@@ -47,9 +47,9 @@ module ram(
 
     always @ (*) begin
         if (rst == `RstEnable) begin
-            data_o <= `ZeroWord;
+            data_o = `ZeroWord;
         end else begin
-            data_o <= _ram[addr_i[31:2]];
+            data_o = _ram[addr_i[31:2]];
         end
     end
 

rtl/perips/rom.v

@@ -47,9 +47,9 @@ module rom(
 
     always @ (*) begin
         if (rst == `RstEnable) begin
-            data_o <= `ZeroWord;
+            data_o = `ZeroWord;
         end else begin
-            data_o <= _rom[addr_i[31:2]];
+            data_o = _rom[addr_i[31:2]];
         end
     end
 

rtl/perips/timer.v

@@ -105,20 +105,20 @@ module timer(
     // read regs
     always @ (*) begin
         if (rst == `RstEnable) begin
-            data_o <= `ZeroWord;
+            data_o = `ZeroWord;
         end else begin
             case (addr_i[3:0])
                 REG_VALUE: begin
-                    data_o <= timer_value;
+                    data_o = timer_value;
                 end
                 REG_CTRL: begin
-                    data_o <= timer_ctrl;
+                    data_o = timer_ctrl;
                 end
                 REG_COUNT: begin
-                    data_o <= timer_count;
+                    data_o = timer_count;
                 end
                 default: begin
-                    data_o <= `ZeroWord;
+                    data_o = `ZeroWord;
                 end
             endcase
         end

rtl/perips/uart_tx.v

@@ -104,20 +104,20 @@ module uart_tx(
 
     always @ (*) begin
         if (rst == 1'b0) begin
-            data_o <= 32'h0;
+            data_o = 32'h0;
         end else begin
             case (addr_i[3:0])
                 UART_CTRL: begin
-                    data_o <= uart_ctrl;
+                    data_o = uart_ctrl;
                 end
                 UART_STATUS: begin
-                    data_o <= uart_status;
+                    data_o = uart_status;
                 end
                 UART_BAUD: begin
-                    data_o <= uart_baud;
+                    data_o = uart_baud;
                 end
                 default: begin
-                    data_o <= 32'h0;
+                    data_o = 32'h0;
                 end
             endcase
         end