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reorganize example and optimize interrupt 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-04-11 19:03:49 +08:00
parent 20d1055ea4
commit 0e188d4934
48 changed files with 132152 additions and 52192 deletions
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55
rtl/core/clint.v
View File

@ -23,33 +23,66 @@ module clint(
input wire clk, input wire clk,
input wire rst, input wire rst,
input wire we_i, // write enable input wire[`INT_BUS] int_flag_i,
input wire[`RegAddrBus] addr_i, // addr input wire[`InstBus] inst_i,
input wire[`RegBus] data_i, // write data input wire[`InstAddrBus] inst_addr_i,
input wire[`Hold_Flag_Bus] hold_flag_i,
input wire[`RegBus] data_i,
output reg[`RegBus] data_o // read data output reg we_o,
output reg[`MemAddrBus] waddr_o,
output reg[`MemAddrBus] raddr_o,
output reg[`RegBus] data_o,
output reg[`InstAddrBus] int_addr_o,
output reg int_assert_o
); );
reg[`RegBus] regs[0:`RegNum - 1];
reg in_int_context;
reg[`InstAddrBus] int_return_addr;
// write reg
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
regs[0] <= `ZeroWord; in_int_context <= `False;
int_return_addr <= `ZeroWord;
int_assert_o <= `INT_DEASSERT;
int_addr_o <= `ZeroWord;
end else begin end else begin
if (we_i == `WriteEnable) begin if (int_flag_i != `INT_NONE && in_int_context == `False) begin
regs[addr_i] <= data_i; int_assert_o <= `INT_ASSERT;
in_int_context <= `True;
int_return_addr <= inst_addr_i;
int_addr_o <= data_i;
end else if (inst_i == `INST_MRET) begin
in_int_context <= `False;
int_assert_o <= `INT_ASSERT;
int_addr_o <= int_return_addr;
end else begin
int_assert_o <= `INT_DEASSERT;
end end
end end
end end
always @ (*) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
raddr_o <= `ZeroWord;
end else begin
raddr_o <= {20'h0, `CSR_MTVEC};
end
end
always @ (posedge clk) begin
if (rst == `RstEnable) begin
we_o <= `WriteDisable;
waddr_o <= `ZeroWord;
data_o <= `ZeroWord; data_o <= `ZeroWord;
end else begin end else begin
data_o <= regs[addr_i]; we_o <= `WriteEnable;
waddr_o <= {20'h0, `CSR_MCAUSE};
data_o <= {24'h0, int_flag_i};
end end
end end

85
rtl/core/csr_reg.v
View File

@ -27,37 +27,83 @@ module csr_reg(
input wire[`MemAddrBus] waddr_i, input wire[`MemAddrBus] waddr_i,
input wire[`RegBus] data_i, input wire[`RegBus] data_i,
input wire clint_we_i,
input wire[`MemAddrBus] clint_raddr_i,
input wire[`MemAddrBus] clint_waddr_i,
input wire[`RegBus] clint_data_i,
output reg[`RegBus] clint_data_o,
output reg[`RegBus] data_o output reg[`RegBus] data_o
); );
localparam CSR_CYCLE = 12'hc00; reg[`DoubleRegBus] cycle;
localparam CSR_CYCLEH = 12'hc80; reg[`RegBus] mtvec;
reg[`RegBus] mcause;
reg[63:0] cycle;
// cycle counter
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
cycle <= 64'h0; cycle <= {`ZeroWord, `ZeroWord};
end else begin end else begin
cycle <= cycle + 1'b1; cycle <= cycle + 1'b1;
end end
end end
// write reg
always @ (posedge clk) begin
if (rst == `RstEnable) begin
mtvec <= `ZeroWord;
mcause <= `ZeroWord;
end else begin
if (we_i == `WriteEnable) begin
case (waddr_i[11:0])
`CSR_MTVEC: begin
mtvec <= data_i;
end
`CSR_MCAUSE: begin
mcause <= data_i;
end
default: begin
end
endcase
end else if (clint_we_i == `WriteEnable) begin
case (clint_waddr_i[11:0])
`CSR_MTVEC: begin
mtvec <= clint_data_i;
end
`CSR_MCAUSE: begin
mcause <= clint_data_i;
end
default: begin
end
endcase
end
end
end
// read reg // read reg
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
data_o <= `ZeroWord; data_o <= `ZeroWord;
end else begin end else begin
case (raddr_i[11:0]) case (raddr_i[11:0])
CSR_CYCLE: begin `CSR_CYCLE: begin
data_o <= cycle[31:0]; data_o <= cycle[31:0];
end end
CSR_CYCLEH: begin `CSR_CYCLEH: begin
data_o <= cycle[63:32]; data_o <= cycle[63:32];
end end
`CSR_MTVEC: begin
data_o <= mtvec;
end
`CSR_MCAUSE: begin
data_o <= mcause;
end
default: begin default: begin
data_o <= `ZeroWord; data_o <= `ZeroWord;
end end
@ -65,4 +111,29 @@ module csr_reg(
end end
end end
// read reg
always @ (*) begin
if (rst == `RstEnable) begin
clint_data_o <= `ZeroWord;
end else begin
case (clint_raddr_i[11:0])
`CSR_CYCLE: begin
clint_data_o <= cycle[31:0];
end
`CSR_CYCLEH: begin
clint_data_o <= cycle[63:32];
end
`CSR_MTVEC: begin
clint_data_o <= mtvec;
end
`CSR_MCAUSE: begin
clint_data_o <= mcause;
end
default: begin
clint_data_o <= `ZeroWord;
end
endcase
end
end
endmodule endmodule

12
rtl/core/ctrl.v
View File

@ -25,8 +25,6 @@ module ctrl(
input wire hold_flag_ex_i, input wire hold_flag_ex_i,
input wire hold_flag_rib_i, input wire hold_flag_rib_i,
input wire jtag_halt_flag_i, input wire jtag_halt_flag_i,
input wire[`INT_BUS] int_flag_i,
input wire[`InstAddrBus] int_return_addr_i,
output reg[`Hold_Flag_Bus] hold_flag_o, output reg[`Hold_Flag_Bus] hold_flag_o,
output reg jump_flag_o, output reg jump_flag_o,
@ -44,15 +42,7 @@ module ctrl(
jump_addr_o <= jump_addr_i; jump_addr_o <= jump_addr_i;
jump_flag_o <= jump_flag_i; jump_flag_o <= jump_flag_i;
hold_flag_o <= `Hold_None; hold_flag_o <= `Hold_None;
if (int_flag_i == `INT_TIMER0) begin if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable) begin
jump_addr_o <= `INT_TIMER0_ENTRY_ADDR;
jump_flag_o <= `JumpEnable;
hold_flag_o <= `Hold_Id;
end else if (int_flag_i == `INT_RET) begin
jump_addr_o <= int_return_addr_i;
jump_flag_o <= `JumpEnable;
hold_flag_o <= `Hold_Id;
end else if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable) begin
hold_flag_o <= `Hold_Id; hold_flag_o <= `Hold_Id;
end else if (hold_flag_rib_i == `HoldEnable) begin end else if (hold_flag_rib_i == `HoldEnable) begin
hold_flag_o <= `Hold_Pc; hold_flag_o <= `Hold_Pc;

6
rtl/core/defines.v
View File

@ -132,6 +132,12 @@
`define INST_CSRRSI 3'b110 `define INST_CSRRSI 3'b110
`define INST_CSRRCI 3'b111 `define INST_CSRRCI 3'b111
// CSR reg addr
`define CSR_CYCLE 12'hc00
`define CSR_CYCLEH 12'hc80
`define CSR_MTVEC 12'h305
`define CSR_MCAUSE 12'h342
`define RomNum 2048 // rom depth(how many words) `define RomNum 2048 // rom depth(how many words)
`define MemNum 2048 // memory depth(how many words) `define MemNum 2048 // memory depth(how many words)

201
rtl/core/ex.v
View File

@ -31,6 +31,8 @@ module ex(
input wire csr_we_i, input wire csr_we_i,
input wire[`MemAddrBus] csr_waddr_i, input wire[`MemAddrBus] csr_waddr_i,
input wire[`RegBus] csr_rdata_i, input wire[`RegBus] csr_rdata_i,
input wire int_assert_i,
input wire[`InstAddrBus] int_addr_i,
// from mem // from mem
input wire[`MemBus] mem_rdata_i, // mem read data input wire[`MemBus] mem_rdata_i, // mem read data
@ -42,18 +44,12 @@ module ex(
input wire[2:0] div_op_i, input wire[2:0] div_op_i,
input wire[`RegAddrBus] div_reg_waddr_i, input wire[`RegAddrBus] div_reg_waddr_i,
// from core
input wire[`INT_BUS] int_flag_i,
// from clint
input wire[`RegBus] clint_data_i,
// to mem // to mem
output reg[`MemBus] mem_wdata_o, // mem write data output reg[`MemBus] mem_wdata_o, // mem write data
output reg[`MemAddrBus] mem_raddr_o, // mem read addr output reg[`MemAddrBus] mem_raddr_o, // mem read addr
output reg[`MemAddrBus] mem_waddr_o, // mem write addr output reg[`MemAddrBus] mem_waddr_o, // mem write addr
output reg mem_we_o, // mem write enable output wire mem_we_o, // mem write enable
output reg mem_req_o, output wire mem_req_o,
// to regs // to regs
output wire[`RegBus] reg_wdata_o, // reg write data output wire[`RegBus] reg_wdata_o, // reg write data
@ -72,14 +68,7 @@ module ex(
output reg[2:0] div_op_o, output reg[2:0] div_op_o,
output reg[`RegAddrBus] div_reg_waddr_o, output reg[`RegAddrBus] div_reg_waddr_o,
// to clint
output reg clint_we_o,
output reg[`RegAddrBus] clint_addr_o,
output reg[`RegBus] clint_data_o,
// to ctrl // to ctrl
output reg[`InstAddrBus] int_return_addr_o,
output reg[`INT_BUS] int_flag_o,
output wire hold_flag_o, output wire hold_flag_o,
output wire jump_flag_o, // whether jump or not flag output wire jump_flag_o, // whether jump or not flag
output wire[`InstAddrBus] jump_addr_o // jump dest addr output wire[`InstAddrBus] jump_addr_o // jump dest addr
@ -111,6 +100,8 @@ module ex(
reg hold_flag; reg hold_flag;
reg jump_flag; reg jump_flag;
reg[`InstAddrBus] jump_addr; reg[`InstAddrBus] jump_addr;
reg mem_we;
reg mem_req;
assign opcode = inst_i[6:0]; assign opcode = inst_i[6:0];
assign funct3 = inst_i[14:12]; assign funct3 = inst_i[14:12];
@ -128,53 +119,21 @@ module ex(
assign mem_waddr_index = ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11; assign mem_waddr_index = ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11;
assign reg_wdata_o = reg_wdata | div_wdata; assign reg_wdata_o = reg_wdata | div_wdata;
assign reg_we_o = reg_we || div_we; assign reg_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: (reg_we || div_we);
assign reg_waddr_o = reg_waddr | div_waddr; assign reg_waddr_o = reg_waddr | div_waddr;
assign hold_flag_o = hold_flag || div_hold_flag; assign mem_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: mem_we;
assign jump_flag_o = jump_flag || div_jump_flag;
assign jump_addr_o = jump_addr | div_jump_addr;
assign csr_we_o = csr_we_i; assign mem_req_o = (int_assert_i == `INT_ASSERT)? `RIB_NREQ: mem_req;
assign hold_flag_o = hold_flag || div_hold_flag;
assign jump_flag_o = jump_flag || div_jump_flag || ((int_assert_i == `INT_ASSERT)? `JumpEnable: `JumpDisable);
assign jump_addr_o = (int_assert_i == `INT_ASSERT)? int_addr_i: (jump_addr | div_jump_addr);
assign csr_we_o = (int_assert_i == `INT_ASSERT)? `WriteDisable: csr_we_i;
assign csr_waddr_o = csr_waddr_i; assign csr_waddr_o = csr_waddr_i;
// handle interrupt
always @ (*) begin
if (rst == `RstEnable) begin
int_flag_o <= `INT_NONE;
clint_we_o <= `WriteDisable;
clint_addr_o <= `ZeroWord;
clint_data_o <= `ZeroWord;
int_return_addr_o <= `ZeroWord;
end else if (int_flag_i != `INT_NONE) begin
clint_addr_o <= `ZeroWord;
int_return_addr_o <= `ZeroWord;
if (clint_data_i[0] == 1'b0) begin
int_flag_o <= int_flag_i;
clint_we_o <= `WriteEnable;
clint_data_o <= inst_addr_i + 4'h4 + 1'b1; // save return address and set interrupt flag
end else begin
int_flag_o <= `INT_NONE;
clint_we_o <= `WriteDisable;
clint_data_o <= `ZeroWord;
end
end else begin
clint_addr_o <= `ZeroWord;
int_return_addr_o <= `ZeroWord;
if (inst_i == `INST_MRET) begin
int_flag_o <= `INT_RET;
int_return_addr_o <= {clint_data_i[31:2], 2'b00};
clint_we_o <= `WriteEnable;
clint_data_o <= `ZeroWord;
end else begin
int_flag_o <= `INT_NONE;
clint_we_o <= `WriteDisable;
clint_data_o <= `ZeroWord;
end
end
end
// handle mul // handle mul
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
@ -315,8 +274,8 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
mem_req_o <= `RIB_NREQ; mem_req <= `RIB_NREQ;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
reg_we <= `WriteDisable; reg_we <= `WriteDisable;
reg_waddr <= `ZeroWord; reg_waddr <= `ZeroWord;
@ -324,7 +283,7 @@ module ex(
end else begin end else begin
reg_we <= reg_we_i; reg_we <= reg_we_i;
reg_waddr <= reg_waddr_i; reg_waddr <= reg_waddr_i;
mem_req_o <= `RIB_NREQ; mem_req <= `RIB_NREQ;
csr_wdata_o <= `ZeroWord; csr_wdata_o <= `ZeroWord;
case (opcode) case (opcode)
@ -337,7 +296,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; reg_wdata <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
end end
`INST_SLTI: begin `INST_SLTI: begin
@ -347,7 +306,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin
if (reg1_rdata_i < sign_extend_tmp) begin if (reg1_rdata_i < sign_extend_tmp) begin
reg_wdata <= 32'h00000001; reg_wdata <= 32'h00000001;
@ -373,7 +332,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin
if (reg1_rdata_i < sign_extend_tmp) begin if (reg1_rdata_i < sign_extend_tmp) begin
reg_wdata <= 32'h00000001; reg_wdata <= 32'h00000001;
@ -399,7 +358,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= reg1_rdata_i ^ {{20{inst_i[31]}}, inst_i[31:20]}; reg_wdata <= reg1_rdata_i ^ {{20{inst_i[31]}}, inst_i[31:20]};
end end
`INST_ORI: begin `INST_ORI: begin
@ -409,7 +368,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= reg1_rdata_i | {{20{inst_i[31]}}, inst_i[31:20]}; reg_wdata <= reg1_rdata_i | {{20{inst_i[31]}}, inst_i[31:20]};
end end
`INST_ANDI: begin `INST_ANDI: begin
@ -419,7 +378,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= reg1_rdata_i & {{20{inst_i[31]}}, inst_i[31:20]}; reg_wdata <= reg1_rdata_i & {{20{inst_i[31]}}, inst_i[31:20]};
end end
`INST_SLLI: begin `INST_SLLI: begin
@ -429,7 +388,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= reg1_rdata_i << shift_bits; reg_wdata <= reg1_rdata_i << shift_bits;
end end
`INST_SRI: begin `INST_SRI: begin
@ -439,7 +398,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
if (inst_i[30] == 1'b1) begin if (inst_i[30] == 1'b1) begin
reg_wdata <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, shift_bits})) | (reg1_rdata_i >> shift_bits); reg_wdata <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, shift_bits})) | (reg1_rdata_i >> shift_bits);
end else begin end else begin
@ -453,7 +412,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
endcase endcase
@ -468,7 +427,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
if (inst_i[30] == 1'b0) begin if (inst_i[30] == 1'b0) begin
reg_wdata <= reg1_rdata_i + reg2_rdata_i; reg_wdata <= reg1_rdata_i + reg2_rdata_i;
end else begin end else begin
@ -482,7 +441,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= reg1_rdata_i << reg2_rdata_i[4:0]; reg_wdata <= reg1_rdata_i << reg2_rdata_i[4:0];
end end
`INST_SLT: begin `INST_SLT: begin
@ -492,7 +451,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
if (reg1_rdata_i < reg2_rdata_i) begin if (reg1_rdata_i < reg2_rdata_i) begin
reg_wdata <= 32'h00000001; reg_wdata <= 32'h00000001;
@ -518,7 +477,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
if (reg1_rdata_i < reg2_rdata_i) begin if (reg1_rdata_i < reg2_rdata_i) begin
reg_wdata <= 32'h00000001; reg_wdata <= 32'h00000001;
@ -544,7 +503,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= reg1_rdata_i ^ reg2_rdata_i; reg_wdata <= reg1_rdata_i ^ reg2_rdata_i;
end end
`INST_SR: begin `INST_SR: begin
@ -554,7 +513,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
if (inst_i[30] == 1'b1) begin if (inst_i[30] == 1'b1) begin
reg_wdata <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]); reg_wdata <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]);
end else begin end else begin
@ -568,7 +527,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= reg1_rdata_i | reg2_rdata_i; reg_wdata <= reg1_rdata_i | reg2_rdata_i;
end end
`INST_AND: begin `INST_AND: begin
@ -578,7 +537,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= reg1_rdata_i & reg2_rdata_i; reg_wdata <= reg1_rdata_i & reg2_rdata_i;
end end
default: begin default: begin
@ -588,7 +547,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
endcase endcase
@ -601,7 +560,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= mul_temp[31:0]; reg_wdata <= mul_temp[31:0];
end end
`INST_MULHU: begin `INST_MULHU: begin
@ -611,7 +570,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= mul_temp[63:32]; reg_wdata <= mul_temp[63:32];
end end
`INST_MULH: begin `INST_MULH: begin
@ -621,7 +580,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
if ((reg1_rdata_i[31] == 1'b0) && (reg2_rdata_i[31] == 1'b0)) begin if ((reg1_rdata_i[31] == 1'b0) && (reg2_rdata_i[31] == 1'b0)) begin
reg_wdata <= mul_temp[63:32]; reg_wdata <= mul_temp[63:32];
end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b1)) begin end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b1)) begin
@ -639,7 +598,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
if (reg1_rdata_i[31] == 1'b1) begin if (reg1_rdata_i[31] == 1'b1) begin
reg_wdata <= mul_temp_invert[63:32]; reg_wdata <= mul_temp_invert[63:32];
end else begin end else begin
@ -653,7 +612,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
`INST_DIVU: begin `INST_DIVU: begin
@ -663,7 +622,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
`INST_REM: begin `INST_REM: begin
@ -673,7 +632,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
`INST_REMU: begin `INST_REMU: begin
@ -683,7 +642,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end*/ end*/
default: begin default: begin
@ -693,7 +652,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
endcase endcase
@ -704,7 +663,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
end end
@ -716,8 +675,8 @@ module ex(
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req_o <= `RIB_REQ; //mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
if (mem_raddr_index == 2'b0) begin if (mem_raddr_index == 2'b0) begin
reg_wdata <= {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]}; reg_wdata <= {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]};
@ -735,8 +694,8 @@ module ex(
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req_o <= `RIB_REQ; //mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
if (mem_raddr_index == 2'b0) begin if (mem_raddr_index == 2'b0) begin
reg_wdata <= {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]}; reg_wdata <= {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]};
@ -750,8 +709,8 @@ module ex(
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req_o <= `RIB_REQ; //mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
reg_wdata <= mem_rdata_i; reg_wdata <= mem_rdata_i;
end end
@ -761,8 +720,8 @@ module ex(
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req_o <= `RIB_REQ; //mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
if (mem_raddr_index == 2'b0) begin if (mem_raddr_index == 2'b0) begin
reg_wdata <= {24'h0, mem_rdata_i[7:0]}; reg_wdata <= {24'h0, mem_rdata_i[7:0]};
@ -780,8 +739,8 @@ module ex(
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
//mem_req_o <= `RIB_REQ; //mem_req <= `RIB_REQ;
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
if (mem_raddr_index == 2'b0) begin if (mem_raddr_index == 2'b0) begin
reg_wdata <= {16'h0, mem_rdata_i[15:0]}; reg_wdata <= {16'h0, mem_rdata_i[15:0]};
@ -796,7 +755,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
endcase endcase
@ -808,8 +767,8 @@ module ex(
hold_flag <= `HoldDisable; hold_flag <= `HoldDisable;
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
mem_we_o <= `WriteEnable; mem_we <= `WriteEnable;
mem_req_o <= `RIB_REQ; mem_req <= `RIB_REQ;
mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
if (mem_waddr_index == 2'b00) begin if (mem_waddr_index == 2'b00) begin
@ -827,8 +786,8 @@ module ex(
hold_flag <= `HoldDisable; hold_flag <= `HoldDisable;
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
mem_we_o <= `WriteEnable; mem_we <= `WriteEnable;
mem_req_o <= `RIB_REQ; mem_req <= `RIB_REQ;
mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
if (mem_waddr_index == 2'b00) begin if (mem_waddr_index == 2'b00) begin
@ -842,8 +801,8 @@ module ex(
hold_flag <= `HoldDisable; hold_flag <= `HoldDisable;
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
mem_we_o <= `WriteEnable; mem_we <= `WriteEnable;
mem_req_o <= `RIB_REQ; mem_req <= `RIB_REQ;
mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
mem_wdata_o <= reg2_rdata_i; mem_wdata_o <= reg2_rdata_i;
@ -855,7 +814,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
endcase endcase
@ -867,7 +826,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
if (reg1_rdata_i == reg2_rdata_i) begin if (reg1_rdata_i == reg2_rdata_i) begin
jump_flag <= `JumpEnable; jump_flag <= `JumpEnable;
@ -882,7 +841,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
if (reg1_rdata_i != reg2_rdata_i) begin if (reg1_rdata_i != reg2_rdata_i) begin
jump_flag <= `JumpEnable; jump_flag <= `JumpEnable;
@ -897,7 +856,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
jump_flag <= `JumpEnable; jump_flag <= `JumpEnable;
@ -928,7 +887,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
jump_flag <= `JumpEnable; jump_flag <= `JumpEnable;
@ -959,7 +918,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
jump_flag <= `JumpDisable; jump_flag <= `JumpDisable;
@ -990,7 +949,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
jump_flag <= `JumpDisable; jump_flag <= `JumpDisable;
@ -1023,7 +982,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
endcase endcase
@ -1033,7 +992,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
jump_flag <= `JumpEnable; jump_flag <= `JumpEnable;
jump_addr <= inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0}; jump_addr <= inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
reg_wdata <= inst_addr_i + 4'h4; reg_wdata <= inst_addr_i + 4'h4;
@ -1043,7 +1002,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
jump_flag <= `JumpEnable; jump_flag <= `JumpEnable;
jump_addr <= (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe); jump_addr <= (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe);
reg_wdata <= inst_addr_i + 4'h4; reg_wdata <= inst_addr_i + 4'h4;
@ -1053,7 +1012,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
jump_flag <= `JumpDisable; jump_flag <= `JumpDisable;
reg_wdata <= {inst_i[31:12], 12'b0}; reg_wdata <= {inst_i[31:12], 12'b0};
@ -1063,7 +1022,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
jump_addr <= `ZeroWord; jump_addr <= `ZeroWord;
jump_flag <= `JumpDisable; jump_flag <= `JumpDisable;
reg_wdata <= {inst_i[31:12], 12'b0} + inst_addr_i; reg_wdata <= {inst_i[31:12], 12'b0} + inst_addr_i;
@ -1075,7 +1034,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
`INST_FENCE: begin `INST_FENCE: begin
@ -1083,7 +1042,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
jump_flag <= `JumpEnable; jump_flag <= `JumpEnable;
jump_addr <= inst_addr_i + 4'h4; jump_addr <= inst_addr_i + 4'h4;
@ -1095,7 +1054,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
case (funct3) case (funct3)
`INST_CSRRW: begin `INST_CSRRW: begin
csr_wdata_o <= reg1_rdata_i; csr_wdata_o <= reg1_rdata_i;
@ -1128,7 +1087,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
endcase endcase
@ -1140,7 +1099,7 @@ module ex(
mem_wdata_o <= `ZeroWord; mem_wdata_o <= `ZeroWord;
mem_raddr_o <= `ZeroWord; mem_raddr_o <= `ZeroWord;
mem_waddr_o <= `ZeroWord; mem_waddr_o <= `ZeroWord;
mem_we_o <= `WriteDisable; mem_we <= `WriteDisable;
reg_wdata <= `ZeroWord; reg_wdata <= `ZeroWord;
end end
endcase endcase

3
rtl/core/id.v
View File

@ -34,7 +34,6 @@ module id(
// from ex // from ex
input wire ex_jump_flag_i, input wire ex_jump_flag_i,
input wire[`INT_BUS] ex_int_flag_i,
// to regs // to regs
output reg[`RegAddrBus] reg1_raddr_o, // reg1 read addr output reg[`RegAddrBus] reg1_raddr_o, // reg1 read addr
@ -67,7 +66,7 @@ module id(
reg mem_req; reg mem_req;
assign mem_req_o = ((mem_req == `RIB_REQ) && (ex_jump_flag_i == `JumpDisable) && (ex_int_flag_i == `INT_NONE)); assign mem_req_o = ((mem_req == `RIB_REQ) && (ex_jump_flag_i == `JumpDisable));
always @ (*) begin always @ (*) begin

2
rtl/core/id_ex.v
View File

@ -60,7 +60,7 @@ module id_ex(
end else begin end else begin
if (hold_flag_i >= `Hold_Id) begin if (hold_flag_i >= `Hold_Id) begin
inst_o <= `INST_NOP; inst_o <= `INST_NOP;
inst_addr_o <= `ZeroWord; inst_addr_o <= inst_addr_i;
reg_we_o <= `WriteDisable; reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord; reg_waddr_o <= `ZeroWord;
reg1_rdata_o <= `ZeroWord; reg1_rdata_o <= `ZeroWord;

2
rtl/core/if_id.v
View File

@ -38,7 +38,7 @@ module if_id(
inst_addr_o <= `ZeroWord; inst_addr_o <= `ZeroWord;
end else if (hold_flag_i >= `Hold_If) begin end else if (hold_flag_i >= `Hold_If) begin
inst_o <= `INST_NOP; inst_o <= `INST_NOP;
inst_addr_o <= `ZeroWord; inst_addr_o <= inst_addr_i;
end else begin end else begin
inst_o <= inst_i; inst_o <= inst_i;
inst_addr_o <= inst_addr_i; inst_addr_o <= inst_addr_i;

45
rtl/core/tinyriscv.v
View File

@ -94,11 +94,6 @@ module tinyriscv(
wire[`RegBus] ex_div_divisor_o; wire[`RegBus] ex_div_divisor_o;
wire[2:0] ex_div_op_o; wire[2:0] ex_div_op_o;
wire[`RegAddrBus] ex_div_reg_waddr_o; wire[`RegAddrBus] ex_div_reg_waddr_o;
wire[`INT_BUS] ex_int_flag_o;
wire[`InstAddrBus] ex_int_return_addr_o;
wire ex_clint_we_o;
wire[`RegAddrBus] ex_clint_addr_o;
wire[`RegBus] ex_clint_data_o;
wire[`RegBus] ex_csr_wdata_o; wire[`RegBus] ex_csr_wdata_o;
wire ex_csr_we_o; wire ex_csr_we_o;
wire[`MemAddrBus] ex_csr_waddr_o; wire[`MemAddrBus] ex_csr_waddr_o;
@ -109,6 +104,7 @@ module tinyriscv(
// csr reg // csr reg
wire[`RegBus] csr_data_o; wire[`RegBus] csr_data_o;
wire[`RegBus] csr_clint_data_o;
// ctrl // ctrl
wire[`Hold_Flag_Bus] ctrl_hold_flag_o; wire[`Hold_Flag_Bus] ctrl_hold_flag_o;
@ -123,7 +119,12 @@ module tinyriscv(
wire[`RegAddrBus] div_reg_waddr_o; wire[`RegAddrBus] div_reg_waddr_o;
// clint // clint
wire clint_we_o;
wire[`MemAddrBus] clint_waddr_o;
wire[`MemAddrBus] clint_raddr_o;
wire[`RegBus] clint_data_o; wire[`RegBus] clint_data_o;
wire[`InstAddrBus] clint_int_addr_o;
wire clint_int_assert_o;
assign rib_ex_addr_o = (ex_mem_we_o == `WriteEnable)? ex_mem_waddr_o: ex_mem_raddr_o; assign rib_ex_addr_o = (ex_mem_we_o == `WriteEnable)? ex_mem_waddr_o: ex_mem_raddr_o;
@ -151,8 +152,6 @@ module tinyriscv(
.hold_flag_ex_i(ex_hold_flag_o), .hold_flag_ex_i(ex_hold_flag_o),
.hold_flag_rib_i(rib_hold_flag_i), .hold_flag_rib_i(rib_hold_flag_i),
.hold_flag_o(ctrl_hold_flag_o), .hold_flag_o(ctrl_hold_flag_o),
.int_flag_i(ex_int_flag_o),
.int_return_addr_i(ex_int_return_addr_o),
.jump_flag_o(ctrl_jump_flag_o), .jump_flag_o(ctrl_jump_flag_o),
.jump_addr_o(ctrl_jump_addr_o), .jump_addr_o(ctrl_jump_addr_o),
.jtag_halt_flag_i(jtag_halt_flag_i) .jtag_halt_flag_i(jtag_halt_flag_i)
@ -181,7 +180,12 @@ module tinyriscv(
.raddr_i(id_csr_raddr_o), .raddr_i(id_csr_raddr_o),
.waddr_i(ex_csr_waddr_o), .waddr_i(ex_csr_waddr_o),
.data_i(ex_csr_wdata_o), .data_i(ex_csr_wdata_o),
.data_o(csr_data_o) .data_o(csr_data_o),
.clint_we_i(clint_we_o),
.clint_raddr_i(clint_raddr_o),
.clint_waddr_i(clint_waddr_o),
.clint_data_i(clint_data_o),
.clint_data_o(csr_clint_data_o)
); );
if_id u_if_id( if_id u_if_id(
@ -201,7 +205,6 @@ module tinyriscv(
.reg1_rdata_i(regs_rdata1_o), .reg1_rdata_i(regs_rdata1_o),
.reg2_rdata_i(regs_rdata2_o), .reg2_rdata_i(regs_rdata2_o),
.ex_jump_flag_i(ex_jump_flag_o), .ex_jump_flag_i(ex_jump_flag_o),
.ex_int_flag_i(ex_int_flag_o),
.reg1_raddr_o(id_reg1_raddr_o), .reg1_raddr_o(id_reg1_raddr_o),
.reg2_raddr_o(id_reg2_raddr_o), .reg2_raddr_o(id_reg2_raddr_o),
.mem_req_o(id_mem_req_o), .mem_req_o(id_mem_req_o),
@ -259,16 +262,11 @@ module tinyriscv(
.reg_wdata_o(ex_reg_wdata_o), .reg_wdata_o(ex_reg_wdata_o),
.reg_we_o(ex_reg_we_o), .reg_we_o(ex_reg_we_o),
.reg_waddr_o(ex_reg_waddr_o), .reg_waddr_o(ex_reg_waddr_o),
.clint_we_o(ex_clint_we_o),
.clint_addr_o(ex_clint_addr_o),
.clint_data_o(ex_clint_data_o),
.clint_data_i(clint_data_o),
.int_return_addr_o(ex_int_return_addr_o),
.hold_flag_o(ex_hold_flag_o), .hold_flag_o(ex_hold_flag_o),
.jump_flag_o(ex_jump_flag_o), .jump_flag_o(ex_jump_flag_o),
.jump_addr_o(ex_jump_addr_o), .jump_addr_o(ex_jump_addr_o),
.int_flag_i(int_i), .int_assert_i(clint_int_assert_o),
.int_flag_o(ex_int_flag_o), .int_addr_i(clint_int_addr_o),
.div_ready_i(div_ready_o), .div_ready_i(div_ready_o),
.div_result_i(div_result_o), .div_result_i(div_result_o),
.div_busy_i(div_busy_o), .div_busy_i(div_busy_o),
@ -305,10 +303,17 @@ module tinyriscv(
clint u_clint( clint u_clint(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.we_i(ex_clint_we_o), .int_flag_i(int_i),
.addr_i(ex_clint_addr_o), .inst_i(id_inst_o),
.data_i(ex_clint_data_o), .inst_addr_i(id_inst_addr_o),
.data_o(clint_data_o) .hold_flag_i(ctrl_hold_flag_o),
.data_i(csr_clint_data_o),
.we_o(clint_we_o),
.waddr_o(clint_waddr_o),
.raddr_o(clint_raddr_o),
.data_o(clint_data_o),
.int_addr_o(clint_int_addr_o),
.int_assert_o(clint_int_assert_o)
); );
endmodule endmodule

0
rtl/core/ram.v → rtl/perips/ram.v
View File

0
rtl/core/rom.v → rtl/perips/rom.v
View File

67
rtl/perips/timer.v
View File

@ -34,9 +34,9 @@ module timer(
); );
localparam ctrl_reg = 32'h00; localparam REG_CTRL = 4'h0;
localparam count_reg = 32'h04; localparam REG_COUNT = 4'h4;
localparam value_reg = 32'h08; localparam REG_VALUE = 4'h8;
// [0]: timer enable // [0]: timer enable
// [1]: timer int enable // [1]: timer int enable
@ -53,28 +53,16 @@ module timer(
reg[31:0] timer_value; reg[31:0] timer_value;
assign int_sig_o = ((timer_ctrl[0] == 1'b1) && (timer_ctrl[1] == 1'b1) && (timer_ctrl[2] == 1'b1)) ? `INT_ASSERT : `INT_DEASSERT; assign int_sig_o = (timer_ctrl[2:1] == 3'h3)? `INT_ASSERT: `INT_DEASSERT;
// write timer regs // write ctrl reg
always @ (posedge clk) begin always @ (posedge clk) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
timer_count <= `ZeroWord;
timer_value <= `ZeroWord;
timer_ctrl <= `ZeroWord; timer_ctrl <= `ZeroWord;
ack_o <= `RIB_ACK;
end else begin end else begin
if (timer_ctrl[0] == 1'b1) begin
timer_count <= timer_count + 1'b1;
if (timer_count == timer_value) begin
timer_ctrl[2] <= 1'b1;
timer_count <= `ZeroWord;
end
end
if (we_i == `WriteEnable) begin if (we_i == `WriteEnable) begin
if (addr_i == value_reg) begin if (addr_i[3:0] == REG_CTRL) begin
timer_value <= data_i;
end else if (addr_i == ctrl_reg) begin
if (data_i[2] == 1'b0) begin if (data_i[2] == 1'b0) begin
timer_ctrl <= {data_i[31:3], timer_ctrl[2], data_i[1:0]}; timer_ctrl <= {data_i[31:3], timer_ctrl[2], data_i[1:0]};
// write 1 to clear pending // write 1 to clear pending
@ -82,6 +70,41 @@ module timer(
timer_ctrl <= {data_i[31:3], 1'b0, data_i[1:0]}; timer_ctrl <= {data_i[31:3], 1'b0, data_i[1:0]};
end end
end end
end else begin
// generate int pending
if (timer_count >= timer_value && timer_value > 32'h0) begin
timer_ctrl[2] <= 1'b1;
timer_ctrl[0] <= 1'b0;
end
end
end
end
// write value reg
always @ (posedge clk) begin
if (rst == `RstEnable) begin
timer_value <= `ZeroWord;
end else begin
if (we_i == `WriteEnable) begin
if (addr_i[3:0] == REG_VALUE) begin
timer_value <= data_i;
end
end
end
end
// counter
always @ (posedge clk) begin
if (rst == `RstEnable) begin
timer_count <= `ZeroWord;
end else begin
if (timer_ctrl[0] == 1'b1 && timer_value > 32'h0) begin
timer_count <= timer_count + 1'b1;
//if (timer_count == timer_value) begin
// timer_count <= `ZeroWord;
//end
end else begin
timer_count <= `ZeroWord;
end end
end end
end end
@ -91,14 +114,14 @@ module timer(
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
data_o <= `ZeroWord; data_o <= `ZeroWord;
end else begin end else begin
case (addr_i) case (addr_i[3:0])
value_reg: begin REG_VALUE: begin
data_o <= timer_value; data_o <= timer_value;
end end
ctrl_reg: begin REG_CTRL: begin
data_o <= timer_ctrl; data_o <= timer_ctrl;
end end
count_reg: begin REG_COUNT: begin
data_o <= timer_count; data_o <= timer_count;
end end
default: begin default: begin

526
sim/inst.data
View File

@ -1,354 +1,182 @@
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22552
sim/out.vvp
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File diff suppressed because one or more lines are too long

2
sim/sim_default_nowave.bat
View File

@ -1,2 +1,2 @@
iverilog -s tinyriscv_soc_tb -o out.vvp -I ..\rtl\core tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\core\ram.v ..\rtl\core\rom.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart_tx.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v iverilog -s tinyriscv_soc_tb -o out.vvp -I ..\rtl\core tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart_tx.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v
vvp out.vvp vvp out.vvp

2
sim/sim_new_nowave.bat
View File

@ -1,3 +1,3 @@
..\tools\BinToMem_CLI.exe %1 %2 ..\tools\BinToMem_CLI.exe %1 %2
iverilog -s tinyriscv_soc_tb -o out.vvp -I ..\rtl\core tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\core\ram.v ..\rtl\core\rom.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart_tx.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v iverilog -s tinyriscv_soc_tb -o out.vvp -I ..\rtl\core tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart_tx.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v
vvp out.vvp vvp out.vvp

158161
sim/tinyriscv_soc_tb.vcd
View File

File diff suppressed because it is too large Load Diff

56
tests/example/common.mk
View File

@ -1,13 +1,6 @@
RISCV_ARCH := rv32im
RISCV_ABI := ilp32
RISCV_PATH := ../../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/ RISCV_PATH := ../../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/
CFLAGS += -march=$(RISCV_ARCH)
CFLAGS += -mabi=$(RISCV_ABI)
CFLAGS += -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc) RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
RISCV_AS := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-as) RISCV_AS := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-as)
RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++) RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
@ -16,3 +9,52 @@ RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar) RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
RISCV_OBJCOPY := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objcopy) RISCV_OBJCOPY := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objcopy)
RISCV_READELF := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-readelf) RISCV_READELF := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-readelf)
.PHONY: all
all: $(TARGET)
COMMON_DIR = ..
ASM_SRCS += $(COMMON_DIR)/start.S
ASM_SRCS += $(COMMON_DIR)/trap_entry.S
C_SRCS += $(COMMON_DIR)/init.c
C_SRCS += $(COMMON_DIR)/lib/utils.c
C_SRCS += $(COMMON_DIR)/lib/xprintf.c
LINKER_SCRIPT := $(COMMON_DIR)/link.lds
INCLUDES += -I$(COMMON_DIR)
LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles -Wl,--gc-sections -Wl,--check-sections
ASM_OBJS := $(ASM_SRCS:.S=.o)
C_OBJS := $(C_SRCS:.c=.o)
LINK_OBJS += $(ASM_OBJS) $(C_OBJS)
LINK_DEPS += $(LINKER_SCRIPT)
CLEAN_OBJS += $(TARGET) $(LINK_OBJS) $(TARGET).dump $(TARGET).bin
#CFLAGS += -g
CFLAGS += -march=$(RISCV_ARCH)
CFLAGS += -mabi=$(RISCV_ABI)
CFLAGS += -mcmodel=medany -ffunction-sections -fdata-sections -fno-builtin-printf -fno-builtin-malloc
$(TARGET): $(LINK_OBJS) $(LINK_DEPS)
$(RISCV_GCC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS)
$(RISCV_OBJCOPY) -O binary $@ $@.bin
$(RISCV_OBJDUMP) --disassemble-all $@ > $@.dump
$(ASM_OBJS): %.o: %.S
$(RISCV_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
$(C_OBJS): %.o: %.c
$(RISCV_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
.PHONY: clean
clean:
rm -f $(CLEAN_OBJS)

23
tests/example/gpio/Makefile
View File

@ -1,9 +1,18 @@
RISCV_ARCH := rv32im
RISCV_ABI := ilp32
TARGET = gpio
#CFLAGS += -DSIMULATION
#CFLAGS += -O2
#ASM_SRCS +=
#LDFLAGS +=
#INCLUDES += -I.
C_SRCS := \
main.c \
include ../common.mk include ../common.mk
.PHONY: all
all:
$(RISCV_GCC) $(CFLAGS) ../start.S main.c -T ../link.lds -o gpio
$(RISCV_OBJCOPY) -O binary gpio gpio.bin
$(RISCV_OBJDUMP) --disassemble-all gpio > gpio.dump

BIN
tests/example/gpio/gpio
View File

Binary file not shown.

BIN
tests/example/gpio/gpio.bin
View File

Binary file not shown.

279
tests/example/gpio/gpio.dump
View File

@ -5,38 +5,38 @@ gpio: file format elf32-littleriscv
Disassembly of section .init: Disassembly of section .init:
00000000 <_start>: 00000000 <_start>:
0: 0080006f j 8 <_reset_handler> 0: 10001197 auipc gp,0x10001
4: 0640006f j 68 <_timer0_handler> 4: 80018193 addi gp,gp,-2048 # 10000800 <__global_pointer$>
8: 10002117 auipc sp,0x10002
00000008 <_reset_handler>: c: ff810113 addi sp,sp,-8 # 10002000 <_sp>
8: 10000197 auipc gp,0x10000 10: 34000513 li a0,832
c: 7f818193 addi gp,gp,2040 # 10000800 <__global_pointer$> 14: 10000597 auipc a1,0x10000
10: 00018113 mv sp,gp 18: fec58593 addi a1,a1,-20 # 10000000 <__bss_start>
14: 2d400513 li a0,724 1c: 10000617 auipc a2,0x10000
18: 10000597 auipc a1,0x10000 20: fe460613 addi a2,a2,-28 # 10000000 <__bss_start>
1c: fe858593 addi a1,a1,-24 # 10000000 <_data> 24: 00c5fc63 bgeu a1,a2,3c <_start+0x3c>
20: 10000617 auipc a2,0x10000 28: 00052283 lw t0,0(a0)
24: fe060613 addi a2,a2,-32 # 10000000 <_data> 2c: 0055a023 sw t0,0(a1)
28: 00c5fc63 bgeu a1,a2,40 <_reset_handler+0x38> 30: 00450513 addi a0,a0,4
2c: 00052283 lw t0,0(a0) 34: 00458593 addi a1,a1,4
30: 0055a023 sw t0,0(a1) 38: fec5e8e3 bltu a1,a2,28 <_start+0x28>
34: 00450513 addi a0,a0,4 3c: 10000517 auipc a0,0x10000
38: 00458593 addi a1,a1,4 40: fc450513 addi a0,a0,-60 # 10000000 <__bss_start>
3c: fec5e8e3 bltu a1,a2,2c <_reset_handler+0x24> 44: 10000597 auipc a1,0x10000
40: 10000517 auipc a0,0x10000 48: fbc58593 addi a1,a1,-68 # 10000000 <__bss_start>
44: fc050513 addi a0,a0,-64 # 10000000 <_data> 4c: 00b57863 bgeu a0,a1,5c <_start+0x5c>
48: 10000597 auipc a1,0x10000 50: 00052023 sw zero,0(a0)
4c: fb858593 addi a1,a1,-72 # 10000000 <_data> 54: 00450513 addi a0,a0,4
50: 00b57863 bgeu a0,a1,60 <_reset_handler+0x58> 58: feb56ce3 bltu a0,a1,50 <_start+0x50>
54: 00052023 sw zero,0(a0) 5c: 188000ef jal ra,1e4 <_init>
58: 00450513 addi a0,a0,4 60: 118000ef jal ra,178 <main>
5c: feb56ce3 bltu a0,a1,54 <_reset_handler+0x4c>
60: 23c000ef jal ra,29c <main>
00000064 <loop>: 00000064 <loop>:
64: 0000006f j 64 <loop> 64: 0000006f j 64 <loop>
00000068 <_timer0_handler>: Disassembly of section .text:
00000068 <trap_entry>:
68: f8010113 addi sp,sp,-128 68: f8010113 addi sp,sp,-128
6c: 00112223 sw ra,4(sp) 6c: 00112223 sw ra,4(sp)
70: 00212423 sw sp,8(sp) 70: 00212423 sw sp,8(sp)
@ -69,8 +69,8 @@ Disassembly of section .init:
dc: 07d12a23 sw t4,116(sp) dc: 07d12a23 sw t4,116(sp)
e0: 07e12c23 sw t5,120(sp) e0: 07e12c23 sw t5,120(sp)
e4: 07f12e23 sw t6,124(sp) e4: 07f12e23 sw t6,124(sp)
e8: 00000097 auipc ra,0x0 e8: 34202573 csrr a0,mcause
ec: 000000e7 jalr zero # 0 <_start> ec: 0c8000ef jal ra,1b4 <trap_handler>
f0: 00412083 lw ra,4(sp) f0: 00412083 lw ra,4(sp)
f4: 00812103 lw sp,8(sp) f4: 00812103 lw sp,8(sp)
f8: 00c12183 lw gp,12(sp) f8: 00c12183 lw gp,12(sp)
@ -104,104 +104,135 @@ Disassembly of section .init:
168: 07c12f83 lw t6,124(sp) 168: 07c12f83 lw t6,124(sp)
16c: 08010113 addi sp,sp,128 16c: 08010113 addi sp,sp,128
170: 30200073 mret 170: 30200073 mret
174: 0000006f j 174 <trap_entry+0x10c>
Disassembly of section .text: 00000178 <main>:
178: ff010113 addi sp,sp,-16
17c: 00112623 sw ra,12(sp)
180: 00812423 sw s0,8(sp)
184: 01010413 addi s0,sp,16
188: 400007b7 lui a5,0x40000
18c: 00478793 addi a5,a5,4 # 40000004 <_sp+0x2fffe004>
190: 0007a703 lw a4,0(a5)
194: 400007b7 lui a5,0x40000
198: 00478793 addi a5,a5,4 # 40000004 <_sp+0x2fffe004>
19c: 00174713 xori a4,a4,1
1a0: 00e7a023 sw a4,0(a5)
1a4: 0007a7b7 lui a5,0x7a
1a8: 12078513 addi a0,a5,288 # 7a120 <__stack_size+0x79920>
1ac: 0e0000ef jal ra,28c <busy_wait>
1b0: fd9ff06f j 188 <main+0x10>
00000174 <delay_ms>: 000001b4 <trap_handler>:
174: fb010113 addi sp,sp,-80 1b4: fe010113 addi sp,sp,-32
178: 04812623 sw s0,76(sp) 1b8: 00112e23 sw ra,28(sp)
17c: 05010413 addi s0,sp,80 1bc: 00812c23 sw s0,24(sp)
180: faa42e23 sw a0,-68(s0) 1c0: 02010413 addi s0,sp,32
184: c0002773 rdcycle a4 1c4: fea42623 sw a0,-20(s0)
188: fee42623 sw a4,-20(s0) 1c8: 00000097 auipc ra,0x0
18c: fec42703 lw a4,-20(s0) 1cc: 000000e7 jalr zero # 0 <_start>
190: fee42023 sw a4,-32(s0) 1d0: 00000013 nop
194: fe042223 sw zero,-28(s0) 1d4: 01c12083 lw ra,28(sp)
198: c8002773 rdcycleh a4 1d8: 01812403 lw s0,24(sp)
19c: fce42e23 sw a4,-36(s0) 1dc: 02010113 addi sp,sp,32
1a0: fdc42703 lw a4,-36(s0) 1e0: 00008067 ret
1a4: 00070793 mv a5,a4
1a8: 00000813 li a6,0
1ac: 00079e93 slli t4,a5,0x0
1b0: 00000e13 li t3,0
1b4: fe042683 lw a3,-32(s0)
1b8: fe442703 lw a4,-28(s0)
1bc: 01c687b3 add a5,a3,t3
1c0: 00078513 mv a0,a5
1c4: 00d53533 sltu a0,a0,a3
1c8: 01d70833 add a6,a4,t4
1cc: 01050733 add a4,a0,a6
1d0: 00070813 mv a6,a4
1d4: fef42023 sw a5,-32(s0)
1d8: ff042223 sw a6,-28(s0)
1dc: c00027f3 rdcycle a5
1e0: fcf42c23 sw a5,-40(s0)
1e4: fd842783 lw a5,-40(s0)
1e8: fcf42823 sw a5,-48(s0)
1ec: fc042a23 sw zero,-44(s0)
1f0: c80027f3 rdcycleh a5
1f4: fcf42623 sw a5,-52(s0)
1f8: fcc42783 lw a5,-52(s0)
1fc: 00078f13 mv t5,a5
200: 00000f93 li t6,0
204: 000f1393 slli t2,t5,0x0
208: 00000313 li t1,0
20c: fd042683 lw a3,-48(s0)
210: fd442703 lw a4,-44(s0)
214: 006687b3 add a5,a3,t1
218: 00078513 mv a0,a5
21c: 00d53533 sltu a0,a0,a3
220: 00770833 add a6,a4,t2
224: 01050733 add a4,a0,a6
228: 00070813 mv a6,a4
22c: fcf42823 sw a5,-48(s0)
230: fd042a23 sw a6,-44(s0)
234: fbc42703 lw a4,-68(s0)
238: 0000c7b7 lui a5,0xc
23c: 35078793 addi a5,a5,848 # c350 <__stack_size+0xbf50>
240: 02f707b3 mul a5,a4,a5
244: 00078593 mv a1,a5
248: 00000613 li a2,0
24c: fe042683 lw a3,-32(s0)
250: fe442703 lw a4,-28(s0)
254: 00d587b3 add a5,a1,a3
258: 00078513 mv a0,a5
25c: 00b53533 sltu a0,a0,a1
260: 00e60833 add a6,a2,a4
264: 01050733 add a4,a0,a6
268: 00070813 mv a6,a4
26c: fd442703 lw a4,-44(s0)
270: 00080693 mv a3,a6
274: f6d764e3 bltu a4,a3,1dc <delay_ms+0x68>
278: fd442703 lw a4,-44(s0)
27c: 00080693 mv a3,a6
280: 00d71663 bne a4,a3,28c <delay_ms+0x118>
284: fd042703 lw a4,-48(s0)
288: f4f76ae3 bltu a4,a5,1dc <delay_ms+0x68>
28c: 00000013 nop
290: 04c12403 lw s0,76(sp)
294: 05010113 addi sp,sp,80
298: 00008067 ret
0000029c <main>: 000001e4 <_init>:
29c: ff010113 addi sp,sp,-16 1e4: ff010113 addi sp,sp,-16
2a0: 00112623 sw ra,12(sp) 1e8: 00812623 sw s0,12(sp)
2a4: 00812423 sw s0,8(sp) 1ec: 01010413 addi s0,sp,16
2a8: 01010413 addi s0,sp,16 1f0: 00000797 auipc a5,0x0
2ac: 400007b7 lui a5,0x40000 1f4: e7878793 addi a5,a5,-392 # 68 <trap_entry>
2b0: 00478793 addi a5,a5,4 # 40000004 <__global_pointer$+0x2ffff804> 1f8: 30579073 csrw mtvec,a5
2b4: 0007a703 lw a4,0(a5) 1fc: 00000013 nop
2b8: 400007b7 lui a5,0x40000 200: 00c12403 lw s0,12(sp)
2bc: 00478793 addi a5,a5,4 # 40000004 <__global_pointer$+0x2ffff804> 204: 01010113 addi sp,sp,16
2c0: 00174713 xori a4,a4,1 208: 00008067 ret
2c4: 00e7a023 sw a4,0(a5)
2c8: 1f400513 li a0,500 0000020c <get_cycle_value>:
2cc: ea9ff0ef jal ra,174 <delay_ms> 20c: fd010113 addi sp,sp,-48
2d0: fddff06f j 2ac <main+0x10> 210: 02812623 sw s0,44(sp)
214: 03010413 addi s0,sp,48
218: c0002773 rdcycle a4
21c: fee42623 sw a4,-20(s0)
220: fec42703 lw a4,-20(s0)
224: fee42023 sw a4,-32(s0)
228: fe042223 sw zero,-28(s0)
22c: c8002773 rdcycleh a4
230: fce42e23 sw a4,-36(s0)
234: fdc42703 lw a4,-36(s0)
238: 00070793 mv a5,a4
23c: 00000813 li a6,0
240: 00079613 slli a2,a5,0x0
244: 00000593 li a1,0
248: fe042683 lw a3,-32(s0)
24c: fe442703 lw a4,-28(s0)
250: 00b687b3 add a5,a3,a1
254: 00078513 mv a0,a5
258: 00d53533 sltu a0,a0,a3
25c: 00c70833 add a6,a4,a2
260: 01050733 add a4,a0,a6
264: 00070813 mv a6,a4
268: fef42023 sw a5,-32(s0)
26c: ff042223 sw a6,-28(s0)
270: fe042783 lw a5,-32(s0)
274: fe442803 lw a6,-28(s0)
278: 00078513 mv a0,a5
27c: 00080593 mv a1,a6
280: 02c12403 lw s0,44(sp)
284: 03010113 addi sp,sp,48
288: 00008067 ret
0000028c <busy_wait>:
28c: fd010113 addi sp,sp,-48
290: 02112623 sw ra,44(sp)
294: 02812423 sw s0,40(sp)
298: 03212223 sw s2,36(sp)
29c: 03312023 sw s3,32(sp)
2a0: 03010413 addi s0,sp,48
2a4: fca42e23 sw a0,-36(s0)
2a8: fdc42703 lw a4,-36(s0)
2ac: 03200793 li a5,50
2b0: 02f707b3 mul a5,a4,a5
2b4: fef42623 sw a5,-20(s0)
2b8: f55ff0ef jal ra,20c <get_cycle_value>
2bc: fea42023 sw a0,-32(s0)
2c0: feb42223 sw a1,-28(s0)
2c4: 00000013 nop
2c8: f45ff0ef jal ra,20c <get_cycle_value>
2cc: 00058613 mv a2,a1
2d0: 00050593 mv a1,a0
2d4: fec42783 lw a5,-20(s0)
2d8: 00078913 mv s2,a5
2dc: 00000993 li s3,0
2e0: fe042683 lw a3,-32(s0)
2e4: fe442703 lw a4,-28(s0)
2e8: 00d907b3 add a5,s2,a3
2ec: 00078513 mv a0,a5
2f0: 01253533 sltu a0,a0,s2
2f4: 00e98833 add a6,s3,a4
2f8: 01050733 add a4,a0,a6
2fc: 00070813 mv a6,a4
300: 00080693 mv a3,a6
304: 00060713 mv a4,a2
308: fcd760e3 bltu a4,a3,2c8 <busy_wait+0x3c>
30c: 00080693 mv a3,a6
310: 00060713 mv a4,a2
314: 00e69863 bne a3,a4,324 <busy_wait+0x98>
318: 00078713 mv a4,a5
31c: 00058793 mv a5,a1
320: fae7e4e3 bltu a5,a4,2c8 <busy_wait+0x3c>
324: 00000013 nop
328: 02c12083 lw ra,44(sp)
32c: 02812403 lw s0,40(sp)
330: 02412903 lw s2,36(sp)
334: 02012983 lw s3,32(sp)
338: 03010113 addi sp,sp,48
33c: 00008067 ret
Disassembly of section .stack: Disassembly of section .stack:
10000400 <_sp-0x400>: 10001800 <_sp-0x800>:
... ...
Disassembly of section .comment: Disassembly of section .comment:
@ -211,11 +242,11 @@ Disassembly of section .comment:
4: 2820 fld fs0,80(s0) 4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm 6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19 a: 434d li t1,19
c: 2055 jal b0 <_timer0_handler+0x48> c: 2055 jal b0 <trap_entry+0x48>
e: 6345 lui t1,0x11 e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0) 10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4) 12: 7370 flw fa2,100(a4)
14: 2065 jal bc <_timer0_handler+0x54> 14: 2065 jal bc <trap_entry+0x54>
16: 4952 lw s2,20(sp) 16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353 18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0) 1c: 4520 lw s0,72(a0)

22
tests/example/gpio/main.c
View File

@ -4,30 +4,10 @@
#include "../include/utils.h" #include "../include/utils.h"
#define MS(ms) (ms * 50000)
static void delay_ms(uint32_t ms)
{
uint64_t tmp;
uint64_t cycle;
tmp = read_csr(cycle);
tmp += (uint64_t)(read_csr(cycleh)) << 32;
do {
cycle = read_csr(cycle);
cycle += (uint64_t)(read_csr(cycleh)) << 32;
} while (cycle < tmp + MS(ms));
}
int main() int main()
{ {
while (1) { while (1) {
GPIO_REG(GPIO_DATA) ^= 0x1; GPIO_REG(GPIO_DATA) ^= 0x1;
delay_ms(500); busy_wait(500 * 1000); // delay 500ms
} }
} }

19
tests/example/include/utils.h
View File

@ -1,9 +1,28 @@
#ifndef _UTILS_H_ #ifndef _UTILS_H_
#define _UTILS_H_ #define _UTILS_H_
#define CPU_FREQ_HZ (50000000) // 50MHz
#define CPU_FREQ_MHZ (50) // 50MHz
#define read_csr(reg) ({ unsigned long __tmp; \ #define read_csr(reg) ({ unsigned long __tmp; \
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
__tmp; }) __tmp; })
#define write_csr(reg, val) ({ \
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
else \
asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
#ifdef SIMULATION
#define set_test_pass() asm("li x27, 0x01")
#define set_test_fail() asm("li x27, 0x00")
#endif
uint64_t get_cycle_value();
void busy_wait(uint32_t us);
#endif #endif

0
tests/example/uart_tx/xprintf.h → tests/example/include/xprintf.h
View File

20
tests/example/init.c Normal file
View File

@ -0,0 +1,20 @@
#include <stdint.h>
#include "include/utils.h"
extern void trap_entry();
extern void timer0_irq_handler() __attribute__((weak));
void trap_handler(uint32_t mcause)
{
// we have only timer0 interrupt here
timer0_irq_handler();
}
void _init()
{
write_csr(mtvec, &trap_entry);
}

26
tests/example/lib/utils.c Normal file
View File

@ -0,0 +1,26 @@
#include <stdint.h>
#include "../include/utils.h"
uint64_t get_cycle_value()
{
uint64_t cycle;
cycle = read_csr(cycle);
cycle += (uint64_t)(read_csr(cycleh)) << 32;
return cycle;
}
void busy_wait(uint32_t us)
{
uint64_t tmp;
uint32_t count;
count = us * CPU_FREQ_MHZ;
tmp = get_cycle_value();
while (get_cycle_value() < (tmp + count));
}

2
tests/example/uart_tx/xprintf.c → tests/example/lib/xprintf.c
View File

@ -11,7 +11,7 @@
/ /
/-------------------------------------------------------------------------*/ /-------------------------------------------------------------------------*/
#include "xprintf.h" #include "../include/xprintf.h"
#include <stdarg.h> #include <stdarg.h>

6
tests/example/link.lds
View File

@ -4,14 +4,14 @@ ENTRY(_start)
MEMORY MEMORY
{ {
flash (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 4K flash (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 8K
ram (wxa!ri) : ORIGIN = 0x10000000, LENGTH = 2K ram (wxa!ri) : ORIGIN = 0x10000000, LENGTH = 8K
} }
SECTIONS SECTIONS
{ {
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K; __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
.init : .init :
{ {

31
tests/example/simple/Makefile
View File

@ -1,25 +1,18 @@
RISCV_ARCH := rv32im RISCV_ARCH := rv32im
RISCV_ABI := ilp32 RISCV_ABI := ilp32
RISCV_PATH := ../../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/
CFLAGS += -march=$(RISCV_ARCH) TARGET = simple
CFLAGS += -mabi=$(RISCV_ABI)
CFLAGS += -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
RISCV_AS := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-as)
RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
RISCV_OBJCOPY := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objcopy)
RISCV_READELF := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-readelf)
.PHONY: all CFLAGS += -DSIMULATION
all: #CFLAGS += -O2
$(RISCV_GCC) $(CFLAGS) start.S main.c -Tlink.ld -o simple #ASM_SRCS +=
$(RISCV_OBJCOPY) -O binary simple simple.bin #LDFLAGS +=
$(RISCV_OBJDUMP) --disassemble-all simple > simple.dump #INCLUDES += -I.
C_SRCS := \
main.c \
include ../common.mk

147
tests/example/simple/link.ld
View File

@ -1,147 +0,0 @@
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
MEMORY
{
flash (wxa!ri) : ORIGIN = 0x00000000, LENGTH = 4K
ram (wxa!ri) : ORIGIN = 0x10000000, LENGTH = 2K
}
SECTIONS
{
__stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
.init :
{
KEEP (*(SORT_NONE(.init)))
} >flash AT>flash
.text :
{
*(.text.unlikely .text.unlikely.*)
*(.text.startup .text.startup.*)
*(.text .text.*)
*(.gnu.linkonce.t.*)
} >flash AT>flash
. = ALIGN(4);
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >flash AT>flash
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >flash AT>flash
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >flash AT>flash
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >flash AT>flash
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >flash AT>flash
.lalign :
{
. = ALIGN(4);
PROVIDE( _data_lma = . );
} >flash AT>flash
.dalign :
{
. = ALIGN(4);
PROVIDE( _data = . );
} >ram AT>flash
.data :
{
*(.rdata)
*(.rodata .rodata.*)
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
} >ram AT>flash
. = ALIGN(4);
PROVIDE( _edata = . );
PROVIDE( edata = . );
PROVIDE( _fbss = . );
PROVIDE( __bss_start = . );
.bss :
{
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss .bss.*)
*(.gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
} >ram AT>ram
. = ALIGN(8);
PROVIDE( _end = . );
PROVIDE( end = . );
.stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
{
PROVIDE( _heap_end = . );
. = __stack_size;
PROVIDE( _sp = . );
} >ram AT>ram
}

15
tests/example/simple/main.c
View File

@ -1,26 +1,17 @@
#include <stdint.h>
static void set_test_pass() #include "../include/utils.h"
{
asm("li x27, 0x01");
}
static void set_test_fail()
{
asm("li x27, 0x00");
}
int mul = 3; int mul = 3;
int div = 3; int div = 3;
int main() int main()
{ {
int i; int i;
int sum; int sum;
mul = 6; mul = 6;
//div = 3;
sum = 0; sum = 0;
// sum = 5050 // sum = 5050

BIN
tests/example/simple/simple
View File

Binary file not shown.

BIN
tests/example/simple/simple.bin
View File

Binary file not shown.

259
tests/example/simple/simple.dump
View File

@ -5,117 +5,186 @@ simple: file format elf32-littleriscv
Disassembly of section .init: Disassembly of section .init:
00000000 <_start>: 00000000 <_start>:
0: 0040006f j 4 <_reset_handler> 0: 10001197 auipc gp,0x10001
4: 80018193 addi gp,gp,-2048 # 10000800 <__global_pointer$>
00000004 <_reset_handler>: 8: 10002117 auipc sp,0x10002
4: 10000197 auipc gp,0x10000 c: ff810113 addi sp,sp,-8 # 10002000 <_sp>
8: 7fc18193 addi gp,gp,2044 # 10000800 <__global_pointer$>
c: 00018113 mv sp,gp
10: 00000d13 li s10,0 10: 00000d13 li s10,0
14: 00000d93 li s11,0 14: 00000d93 li s11,0
18: 18c00513 li a0,396 18: 2a000513 li a0,672
1c: 10000597 auipc a1,0x10000 1c: 10000597 auipc a1,0x10000
20: fe458593 addi a1,a1,-28 # 10000000 <_data> 20: fe458593 addi a1,a1,-28 # 10000000 <_data>
24: 80818613 addi a2,gp,-2040 # 10000008 <__bss_start> 24: 80818613 addi a2,gp,-2040 # 10000008 <__bss_start>
28: 00c5fc63 bgeu a1,a2,40 <_reset_handler+0x3c> 28: 00c5fc63 bgeu a1,a2,40 <_start+0x40>
2c: 00052283 lw t0,0(a0) 2c: 00052283 lw t0,0(a0)
30: 0055a023 sw t0,0(a1) 30: 0055a023 sw t0,0(a1)
34: 00450513 addi a0,a0,4 34: 00450513 addi a0,a0,4
38: 00458593 addi a1,a1,4 38: 00458593 addi a1,a1,4
3c: fec5e8e3 bltu a1,a2,2c <_reset_handler+0x28> 3c: fec5e8e3 bltu a1,a2,2c <_start+0x2c>
40: 80818513 addi a0,gp,-2040 # 10000008 <__bss_start> 40: 80818513 addi a0,gp,-2040 # 10000008 <__bss_start>
44: 80818593 addi a1,gp,-2040 # 10000008 <__bss_start> 44: 80818593 addi a1,gp,-2040 # 10000008 <__bss_start>
48: 00b57863 bgeu a0,a1,58 <_reset_handler+0x54> 48: 00b57863 bgeu a0,a1,58 <_start+0x58>
4c: 00052023 sw zero,0(a0) 4c: 00052023 sw zero,0(a0)
50: 00450513 addi a0,a0,4 50: 00450513 addi a0,a0,4
54: feb56ce3 bltu a0,a1,4c <_reset_handler+0x48> 54: feb56ce3 bltu a0,a1,4c <_start+0x4c>
58: 04c000ef jal ra,a4 <main> 58: 220000ef jal ra,278 <_init>
5c: 00100d13 li s10,1 5c: 10c000ef jal ra,168 <main>
60: 00100d13 li s10,1
00000060 <loop>: 00000064 <loop>:
60: 0000006f j 60 <loop> 64: 0000006f j 64 <loop>
Disassembly of section .text: Disassembly of section .text:
00000064 <set_test_pass>: 00000068 <trap_entry>:
64: ff010113 addi sp,sp,-16 68: f8010113 addi sp,sp,-128
68: 00812623 sw s0,12(sp) 6c: 00112223 sw ra,4(sp)
6c: 01010413 addi s0,sp,16 70: 00212423 sw sp,8(sp)
70: 00100d93 li s11,1 74: 00312623 sw gp,12(sp)
74: 00000013 nop 78: 00412823 sw tp,16(sp)
78: 00c12403 lw s0,12(sp) 7c: 00512a23 sw t0,20(sp)
7c: 01010113 addi sp,sp,16 80: 00612c23 sw t1,24(sp)
80: 00008067 ret 84: 00712e23 sw t2,28(sp)
88: 02812023 sw s0,32(sp)
8c: 02912223 sw s1,36(sp)
90: 02a12423 sw a0,40(sp)
94: 02b12623 sw a1,44(sp)
98: 02c12823 sw a2,48(sp)
9c: 02d12a23 sw a3,52(sp)
a0: 02e12c23 sw a4,56(sp)
a4: 02f12e23 sw a5,60(sp)
a8: 05012023 sw a6,64(sp)
ac: 05112223 sw a7,68(sp)
b0: 05212423 sw s2,72(sp)
b4: 05312623 sw s3,76(sp)
b8: 05412823 sw s4,80(sp)
bc: 05512a23 sw s5,84(sp)
c0: 05612c23 sw s6,88(sp)
c4: 05712e23 sw s7,92(sp)
c8: 07812023 sw s8,96(sp)
cc: 07912223 sw s9,100(sp)
d0: 07c12823 sw t3,112(sp)
d4: 07d12a23 sw t4,116(sp)
d8: 07e12c23 sw t5,120(sp)
dc: 07f12e23 sw t6,124(sp)
e0: 34202573 csrr a0,mcause
e4: 164000ef jal ra,248 <trap_handler>
e8: 00412083 lw ra,4(sp)
ec: 00812103 lw sp,8(sp)
f0: 00c12183 lw gp,12(sp)
f4: 01012203 lw tp,16(sp)
f8: 01412283 lw t0,20(sp)
fc: 01812303 lw t1,24(sp)
100: 01c12383 lw t2,28(sp)
104: 02012403 lw s0,32(sp)
108: 02412483 lw s1,36(sp)
10c: 02812503 lw a0,40(sp)
110: 02c12583 lw a1,44(sp)
114: 03012603 lw a2,48(sp)
118: 03412683 lw a3,52(sp)
11c: 03812703 lw a4,56(sp)
120: 03c12783 lw a5,60(sp)
124: 04012803 lw a6,64(sp)
128: 04412883 lw a7,68(sp)
12c: 04812903 lw s2,72(sp)
130: 04c12983 lw s3,76(sp)
134: 05012a03 lw s4,80(sp)
138: 05412a83 lw s5,84(sp)
13c: 05812b03 lw s6,88(sp)
140: 05c12b83 lw s7,92(sp)
144: 06012c03 lw s8,96(sp)
148: 06412c83 lw s9,100(sp)
14c: 07012e03 lw t3,112(sp)
150: 07412e83 lw t4,116(sp)
154: 07812f03 lw t5,120(sp)
158: 07c12f83 lw t6,124(sp)
15c: 08010113 addi sp,sp,128
160: 30200073 mret
164: 0000006f j 164 <trap_entry+0xfc>
00000084 <set_test_fail>: 00000168 <main>:
84: ff010113 addi sp,sp,-16 168: fe010113 addi sp,sp,-32
88: 00812623 sw s0,12(sp) 16c: 00812e23 sw s0,28(sp)
8c: 01010413 addi s0,sp,16 170: 02010413 addi s0,sp,32
90: 00000d93 li s11,0 174: 10000797 auipc a5,0x10000
94: 00000013 nop 178: e8c78793 addi a5,a5,-372 # 10000000 <_data>
98: 00c12403 lw s0,12(sp) 17c: 00600713 li a4,6
9c: 01010113 addi sp,sp,16 180: 00e7a023 sw a4,0(a5)
a0: 00008067 ret 184: fe042423 sw zero,-24(s0)
188: fe042623 sw zero,-20(s0)
18c: 0200006f j 1ac <main+0x44>
190: fe842703 lw a4,-24(s0)
194: fec42783 lw a5,-20(s0)
198: 00f707b3 add a5,a4,a5
19c: fef42423 sw a5,-24(s0)
1a0: fec42783 lw a5,-20(s0)
1a4: 00178793 addi a5,a5,1
1a8: fef42623 sw a5,-20(s0)
1ac: fec42703 lw a4,-20(s0)
1b0: 06400793 li a5,100
1b4: fce7dee3 bge a5,a4,190 <main+0x28>
1b8: fe042623 sw zero,-20(s0)
1bc: 0200006f j 1dc <main+0x74>
1c0: fe842703 lw a4,-24(s0)
1c4: fec42783 lw a5,-20(s0)
1c8: 40f707b3 sub a5,a4,a5
1cc: fef42423 sw a5,-24(s0)
1d0: fec42783 lw a5,-20(s0)
1d4: 00178793 addi a5,a5,1
1d8: fef42623 sw a5,-20(s0)
1dc: fec42703 lw a4,-20(s0)
1e0: 03200793 li a5,50
1e4: fce7dee3 bge a5,a4,1c0 <main+0x58>
1e8: 10000797 auipc a5,0x10000
1ec: e1878793 addi a5,a5,-488 # 10000000 <_data>
1f0: 0007a783 lw a5,0(a5)
1f4: fe842703 lw a4,-24(s0)
1f8: 02f707b3 mul a5,a4,a5
1fc: fef42423 sw a5,-24(s0)
200: 10000797 auipc a5,0x10000
204: e0478793 addi a5,a5,-508 # 10000004 <div>
208: 0007a783 lw a5,0(a5)
20c: fe842703 lw a4,-24(s0)
210: 02f747b3 div a5,a4,a5
214: fef42423 sw a5,-24(s0)
218: fe842703 lw a4,-24(s0)
21c: 000027b7 lui a5,0x2
220: d7e78793 addi a5,a5,-642 # 1d7e <__stack_size+0x157e>
224: 00f71663 bne a4,a5,230 <main+0xc8>
228: 00100d93 li s11,1
22c: 0080006f j 234 <main+0xcc>
230: 00000d93 li s11,0
234: 00000793 li a5,0
238: 00078513 mv a0,a5
23c: 01c12403 lw s0,28(sp)
240: 02010113 addi sp,sp,32
244: 00008067 ret
000000a4 <main>: 00000248 <trap_handler>:
a4: fe010113 addi sp,sp,-32 248: fe010113 addi sp,sp,-32
a8: 00112e23 sw ra,28(sp) 24c: 00112e23 sw ra,28(sp)
ac: 00812c23 sw s0,24(sp) 250: 00812c23 sw s0,24(sp)
b0: 02010413 addi s0,sp,32 254: 02010413 addi s0,sp,32
b4: 10000797 auipc a5,0x10000 258: fea42623 sw a0,-20(s0)
b8: f4c78793 addi a5,a5,-180 # 10000000 <_data> 25c: 00000097 auipc ra,0x0
bc: 00600713 li a4,6 260: 000000e7 jalr zero # 0 <_start>
c0: 00e7a023 sw a4,0(a5) 264: 00000013 nop
c4: fe042423 sw zero,-24(s0) 268: 01c12083 lw ra,28(sp)
c8: fe042623 sw zero,-20(s0) 26c: 01812403 lw s0,24(sp)
cc: 0200006f j ec <main+0x48> 270: 02010113 addi sp,sp,32
d0: fe842703 lw a4,-24(s0) 274: 00008067 ret
d4: fec42783 lw a5,-20(s0)
d8: 00f707b3 add a5,a4,a5 00000278 <_init>:
dc: fef42423 sw a5,-24(s0) 278: ff010113 addi sp,sp,-16
e0: fec42783 lw a5,-20(s0) 27c: 00812623 sw s0,12(sp)
e4: 00178793 addi a5,a5,1 280: 01010413 addi s0,sp,16
e8: fef42623 sw a5,-20(s0) 284: 00000797 auipc a5,0x0
ec: fec42703 lw a4,-20(s0) 288: de478793 addi a5,a5,-540 # 68 <trap_entry>
f0: 06400793 li a5,100 28c: 30579073 csrw mtvec,a5
f4: fce7dee3 bge a5,a4,d0 <main+0x2c> 290: 00000013 nop
f8: fe042623 sw zero,-20(s0) 294: 00c12403 lw s0,12(sp)
fc: 0200006f j 11c <main+0x78> 298: 01010113 addi sp,sp,16
100: fe842703 lw a4,-24(s0) 29c: 00008067 ret
104: fec42783 lw a5,-20(s0)
108: 40f707b3 sub a5,a4,a5
10c: fef42423 sw a5,-24(s0)
110: fec42783 lw a5,-20(s0)
114: 00178793 addi a5,a5,1
118: fef42623 sw a5,-20(s0)
11c: fec42703 lw a4,-20(s0)
120: 03200793 li a5,50
124: fce7dee3 bge a5,a4,100 <main+0x5c>
128: 10000797 auipc a5,0x10000
12c: ed878793 addi a5,a5,-296 # 10000000 <_data>
130: 0007a783 lw a5,0(a5)
134: fe842703 lw a4,-24(s0)
138: 02f707b3 mul a5,a4,a5
13c: fef42423 sw a5,-24(s0)
140: 10000797 auipc a5,0x10000
144: ec478793 addi a5,a5,-316 # 10000004 <div>
148: 0007a783 lw a5,0(a5)
14c: fe842703 lw a4,-24(s0)
150: 02f747b3 div a5,a4,a5
154: fef42423 sw a5,-24(s0)
158: fe842703 lw a4,-24(s0)
15c: 000027b7 lui a5,0x2
160: d7e78793 addi a5,a5,-642 # 1d7e <__stack_size+0x197e>
164: 00f71663 bne a4,a5,170 <main+0xcc>
168: efdff0ef jal ra,64 <set_test_pass>
16c: 0080006f j 174 <main+0xd0>
170: f15ff0ef jal ra,84 <set_test_fail>
174: 00000793 li a5,0
178: 00078513 mv a0,a5
17c: 01c12083 lw ra,28(sp)
180: 01812403 lw s0,24(sp)
184: 02010113 addi sp,sp,32
188: 00008067 ret
Disassembly of section .data: Disassembly of section .data:
@ -127,7 +196,7 @@ Disassembly of section .data:
Disassembly of section .stack: Disassembly of section .stack:
10000400 <_sp-0x400>: 10001800 <_sp-0x800>:
... ...
Disassembly of section .comment: Disassembly of section .comment:
@ -137,11 +206,11 @@ Disassembly of section .comment:
4: 2820 fld fs0,80(s0) 4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm 6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19 a: 434d li t1,19
c: 2055 jal b0 <main+0xc> c: 2055 jal b0 <trap_entry+0x48>
e: 6345 lui t1,0x11 e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0) 10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4) 12: 7370 flw fa2,100(a4)
14: 2065 jal bc <main+0x18> 14: 2065 jal bc <trap_entry+0x54>
16: 4952 lw s2,20(sp) 16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353 18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0) 1c: 4520 lw s0,72(a0)

46
tests/example/simple/start.S
View File

@ -1,46 +0,0 @@
.section .init;
.globl _start;
.type _start,@function
_start:
j _reset_handler
_reset_handler:
.option push
.option norelax
la gp, __global_pointer$
.option pop
la sp, _sp
li x26, 0x00
li x27, 0x00
/* Load data section */
la a0, _data_lma
la a1, _data
la a2, _edata
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* Clear bss section */
la a0, __bss_start
la a1, _end
bgeu a0, a1, 2f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
2:
call main
li x26, 0x01
loop:
j loop

90
tests/example/start.S
View File

@ -1,23 +1,19 @@
#define REGBYTES 4
#define STORE sw
#define LOAD lw
.section .init; .section .init;
.globl _start; .globl _start;
.type _start,@function .type _start,@function
.weak TIMER0_IRQHandler
_start: _start:
j _reset_handler
j _timer0_handler
_reset_handler:
.option push .option push
.option norelax .option norelax
la gp, __global_pointer$ la gp, __global_pointer$
.option pop .option pop
la sp, _sp la sp, _sp
#ifdef SIMULATION
li x26, 0x00
li x27, 0x00
#endif
/* Load data section */ /* Load data section */
la a0, _data_lma la a0, _data_lma
@ -42,80 +38,12 @@ _reset_handler:
bltu a0, a1, 1b bltu a0, a1, 1b
2: 2:
call _init
call main call main
#ifdef SIMULATION
li x26, 0x01
#endif
loop: loop:
j loop j loop
_timer0_handler:
addi sp, sp, -32*REGBYTES
STORE x1, 1*REGBYTES(sp)
STORE x2, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
call TIMER0_IRQHandler
LOAD x1, 1*REGBYTES(sp)
LOAD x2, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret

23
tests/example/timer_int/Makefile
View File

@ -1,9 +1,18 @@
RISCV_ARCH := rv32im
RISCV_ABI := ilp32
TARGET = timer_int
CFLAGS += -DSIMULATION
#CFLAGS += -O2
#ASM_SRCS +=
#LDFLAGS +=
#INCLUDES += -I.
C_SRCS := \
main.c \
include ../common.mk include ../common.mk
.PHONY: all
all:
$(RISCV_GCC) $(CFLAGS) ../start.S main.c -T ../link.lds -o timer_int
$(RISCV_OBJCOPY) -O binary timer_int timer_int.bin
$(RISCV_OBJDUMP) --disassemble-all timer_int > timer_int.dump

43
tests/example/timer_int/main.c
View File

@ -2,33 +2,62 @@
#include "../include/timer.h" #include "../include/timer.h"
#include "../include/gpio.h" #include "../include/gpio.h"
#include "../include/utils.h"
static uint32_t count; static volatile uint32_t count;
static volatile uint8_t int_flag;
int main() int main()
{ {
count = 0; count = 0;
int_flag = 0;
TIMER0_REG(TIMER0_VALUE) = 50000; // 1ms period #ifdef SIMULATION
TIMER0_REG(TIMER0_VALUE) = 500; // 10us period
TIMER0_REG(TIMER0_CTRL) = 0x07; // enable interrupt and start timer
while (1) {
if (int_flag) {
TIMER0_REG(TIMER0_CTRL) |= (1 << 0); // restart timer
int_flag = 0;
count++;
if (count == 2) {
TIMER0_REG(TIMER0_CTRL) = 0x00; // stop timer
count = 0;
// TODO: do something
set_test_pass();
break;
}
}
}
#else
TIMER0_REG(TIMER0_VALUE) = 500000; // 10ms period
TIMER0_REG(TIMER0_CTRL) = 0x07; // enable interrupt and start timer TIMER0_REG(TIMER0_CTRL) = 0x07; // enable interrupt and start timer
GPIO_REG(GPIO_DATA) = 0x1; GPIO_REG(GPIO_DATA) = 0x1;
while (1) { while (1) {
if (count >= 500) { if (int_flag) {
TIMER0_REG(TIMER0_CTRL) |= (1 << 0); // restart timer
int_flag = 0;
count++;
// 500ms
if (count == 50) {
count = 0; count = 0;
GPIO_REG(GPIO_DATA) ^= 0x1; GPIO_REG(GPIO_DATA) ^= 0x1; // toggle led
} }
} }
}
#endif
return 0; return 0;
} }
void TIMER0_IRQHandler() void timer0_irq_handler()
{ {
TIMER0_REG(TIMER0_CTRL) = 0x07; // clear int pending TIMER0_REG(TIMER0_CTRL) |= (1 << 2); // clear int pending
count++; int_flag = 1;
} }

BIN
tests/example/timer_int/timer_int
View File

Binary file not shown.

BIN
tests/example/timer_int/timer_int.bin
View File

Binary file not shown.

333
tests/example/timer_int/timer_int.dump
View File

@ -5,173 +5,216 @@ timer_int: file format elf32-littleriscv
Disassembly of section .init: Disassembly of section .init:
00000000 <_start>: 00000000 <_start>:
0: 0080006f j 8 <_reset_handler> 0: 10001197 auipc gp,0x10001
4: 0600006f j 64 <_timer0_handler> 4: 80018193 addi gp,gp,-2048 # 10000800 <__global_pointer$>
8: 10002117 auipc sp,0x10002
c: ff810113 addi sp,sp,-8 # 10002000 <_sp>
10: 00000d13 li s10,0
14: 00000d93 li s11,0
18: 2d800513 li a0,728
1c: 10000597 auipc a1,0x10000
20: fe458593 addi a1,a1,-28 # 10000000 <_data>
24: 10000617 auipc a2,0x10000
28: fdc60613 addi a2,a2,-36 # 10000000 <_data>
2c: 00c5fc63 bgeu a1,a2,44 <_start+0x44>
30: 00052283 lw t0,0(a0)
34: 0055a023 sw t0,0(a1)
38: 00450513 addi a0,a0,4
3c: 00458593 addi a1,a1,4
40: fec5e8e3 bltu a1,a2,30 <_start+0x30>
44: 10000517 auipc a0,0x10000
48: fbc50513 addi a0,a0,-68 # 10000000 <_data>
4c: 80818593 addi a1,gp,-2040 # 10000008 <_end>
50: 00b57863 bgeu a0,a1,60 <_start+0x60>
54: 00052023 sw zero,0(a0)
58: 00450513 addi a0,a0,4
5c: feb56ce3 bltu a0,a1,54 <_start+0x54>
60: 250000ef jal ra,2b0 <_init>
64: 10c000ef jal ra,170 <main>
68: 00100d13 li s10,1
00000008 <_reset_handler>: 0000006c <loop>:
8: 10000197 auipc gp,0x10000 6c: 0000006f j 6c <loop>
c: 7f818193 addi gp,gp,2040 # 10000800 <__global_pointer$>
10: 00018113 mv sp,gp
14: 24400513 li a0,580
18: 10000597 auipc a1,0x10000
1c: fe858593 addi a1,a1,-24 # 10000000 <_data>
20: 10000617 auipc a2,0x10000
24: fe060613 addi a2,a2,-32 # 10000000 <_data>
28: 00c5fc63 bgeu a1,a2,40 <_reset_handler+0x38>
2c: 00052283 lw t0,0(a0)
30: 0055a023 sw t0,0(a1)
34: 00450513 addi a0,a0,4
38: 00458593 addi a1,a1,4
3c: fec5e8e3 bltu a1,a2,2c <_reset_handler+0x24>
40: 10000517 auipc a0,0x10000
44: fc050513 addi a0,a0,-64 # 10000000 <_data>
48: 80818593 addi a1,gp,-2040 # 10000008 <_end>
4c: 00b57863 bgeu a0,a1,5c <_reset_handler+0x54>
50: 00052023 sw zero,0(a0)
54: 00450513 addi a0,a0,4
58: feb56ce3 bltu a0,a1,50 <_reset_handler+0x48>
5c: 110000ef jal ra,16c <main>
00000060 <loop>: Disassembly of section .text:
60: 0000006f j 60 <loop>
00000064 <_timer0_handler>: 00000070 <trap_entry>:
64: f8010113 addi sp,sp,-128 70: f8010113 addi sp,sp,-128
68: 00112223 sw ra,4(sp) 74: 00112223 sw ra,4(sp)
6c: 00212423 sw sp,8(sp) 78: 00212423 sw sp,8(sp)
70: 00312623 sw gp,12(sp) 7c: 00312623 sw gp,12(sp)
74: 00412823 sw tp,16(sp) 80: 00412823 sw tp,16(sp)
78: 00512a23 sw t0,20(sp) 84: 00512a23 sw t0,20(sp)
7c: 00612c23 sw t1,24(sp) 88: 00612c23 sw t1,24(sp)
80: 00712e23 sw t2,28(sp) 8c: 00712e23 sw t2,28(sp)
84: 02812023 sw s0,32(sp) 90: 02812023 sw s0,32(sp)
88: 02912223 sw s1,36(sp) 94: 02912223 sw s1,36(sp)
8c: 02a12423 sw a0,40(sp) 98: 02a12423 sw a0,40(sp)
90: 02b12623 sw a1,44(sp) 9c: 02b12623 sw a1,44(sp)
94: 02c12823 sw a2,48(sp) a0: 02c12823 sw a2,48(sp)
98: 02d12a23 sw a3,52(sp) a4: 02d12a23 sw a3,52(sp)
9c: 02e12c23 sw a4,56(sp) a8: 02e12c23 sw a4,56(sp)
a0: 02f12e23 sw a5,60(sp) ac: 02f12e23 sw a5,60(sp)
a4: 05012023 sw a6,64(sp) b0: 05012023 sw a6,64(sp)
a8: 05112223 sw a7,68(sp) b4: 05112223 sw a7,68(sp)
ac: 05212423 sw s2,72(sp) b8: 05212423 sw s2,72(sp)
b0: 05312623 sw s3,76(sp) bc: 05312623 sw s3,76(sp)
b4: 05412823 sw s4,80(sp) c0: 05412823 sw s4,80(sp)
b8: 05512a23 sw s5,84(sp) c4: 05512a23 sw s5,84(sp)
bc: 05612c23 sw s6,88(sp) c8: 05612c23 sw s6,88(sp)
c0: 05712e23 sw s7,92(sp) cc: 05712e23 sw s7,92(sp)
c4: 07812023 sw s8,96(sp) d0: 07812023 sw s8,96(sp)
c8: 07912223 sw s9,100(sp) d4: 07912223 sw s9,100(sp)
cc: 07a12423 sw s10,104(sp) d8: 07c12823 sw t3,112(sp)
d0: 07b12623 sw s11,108(sp) dc: 07d12a23 sw t4,116(sp)
d4: 07c12823 sw t3,112(sp) e0: 07e12c23 sw t5,120(sp)
d8: 07d12a23 sw t4,116(sp) e4: 07f12e23 sw t6,124(sp)
dc: 07e12c23 sw t5,120(sp) e8: 34202573 csrr a0,mcause
e0: 07f12e23 sw t6,124(sp) ec: 198000ef jal ra,284 <trap_handler>
e4: 110000ef jal ra,1f4 <TIMER0_IRQHandler> f0: 00412083 lw ra,4(sp)
e8: 00412083 lw ra,4(sp) f4: 00812103 lw sp,8(sp)
ec: 00812103 lw sp,8(sp) f8: 00c12183 lw gp,12(sp)
f0: 00c12183 lw gp,12(sp) fc: 01012203 lw tp,16(sp)
f4: 01012203 lw tp,16(sp) 100: 01412283 lw t0,20(sp)
f8: 01412283 lw t0,20(sp) 104: 01812303 lw t1,24(sp)
fc: 01812303 lw t1,24(sp) 108: 01c12383 lw t2,28(sp)
100: 01c12383 lw t2,28(sp) 10c: 02012403 lw s0,32(sp)
104: 02012403 lw s0,32(sp) 110: 02412483 lw s1,36(sp)
108: 02412483 lw s1,36(sp) 114: 02812503 lw a0,40(sp)
10c: 02812503 lw a0,40(sp) 118: 02c12583 lw a1,44(sp)
110: 02c12583 lw a1,44(sp) 11c: 03012603 lw a2,48(sp)
114: 03012603 lw a2,48(sp) 120: 03412683 lw a3,52(sp)
118: 03412683 lw a3,52(sp) 124: 03812703 lw a4,56(sp)
11c: 03812703 lw a4,56(sp) 128: 03c12783 lw a5,60(sp)
120: 03c12783 lw a5,60(sp) 12c: 04012803 lw a6,64(sp)
124: 04012803 lw a6,64(sp) 130: 04412883 lw a7,68(sp)
128: 04412883 lw a7,68(sp) 134: 04812903 lw s2,72(sp)
12c: 04812903 lw s2,72(sp) 138: 04c12983 lw s3,76(sp)
130: 04c12983 lw s3,76(sp) 13c: 05012a03 lw s4,80(sp)
134: 05012a03 lw s4,80(sp) 140: 05412a83 lw s5,84(sp)
138: 05412a83 lw s5,84(sp) 144: 05812b03 lw s6,88(sp)
13c: 05812b03 lw s6,88(sp) 148: 05c12b83 lw s7,92(sp)
140: 05c12b83 lw s7,92(sp) 14c: 06012c03 lw s8,96(sp)
144: 06012c03 lw s8,96(sp) 150: 06412c83 lw s9,100(sp)
148: 06412c83 lw s9,100(sp)
14c: 06812d03 lw s10,104(sp)
150: 06c12d83 lw s11,108(sp)
154: 07012e03 lw t3,112(sp) 154: 07012e03 lw t3,112(sp)
158: 07412e83 lw t4,116(sp) 158: 07412e83 lw t4,116(sp)
15c: 07812f03 lw t5,120(sp) 15c: 07812f03 lw t5,120(sp)
160: 07c12f83 lw t6,124(sp) 160: 07c12f83 lw t6,124(sp)
164: 08010113 addi sp,sp,128 164: 08010113 addi sp,sp,128
168: 30200073 mret 168: 30200073 mret
16c: 0000006f j 16c <trap_entry+0xfc>
Disassembly of section .text: 00000170 <main>:
170: ff010113 addi sp,sp,-16
0000016c <main>: 174: 00812623 sw s0,12(sp)
16c: ff010113 addi sp,sp,-16 178: 01010413 addi s0,sp,16
170: 00812623 sw s0,12(sp) 17c: 10000797 auipc a5,0x10000
174: 01010413 addi s0,sp,16 180: e8478793 addi a5,a5,-380 # 10000000 <_data>
178: 10000797 auipc a5,0x10000 184: 0007a023 sw zero,0(a5)
17c: e8878793 addi a5,a5,-376 # 10000000 <_data> 188: 10000797 auipc a5,0x10000
180: 0007a023 sw zero,0(a5) 18c: e7c78793 addi a5,a5,-388 # 10000004 <int_flag>
184: 200007b7 lui a5,0x20000 190: 00078023 sb zero,0(a5)
188: 00878793 addi a5,a5,8 # 20000008 <__global_pointer$+0xffff808> 194: 200007b7 lui a5,0x20000
18c: 0000c737 lui a4,0xc 198: 00878793 addi a5,a5,8 # 20000008 <_sp+0xfffe008>
190: 35070713 addi a4,a4,848 # c350 <__stack_size+0xbf50> 19c: 1f400713 li a4,500
194: 00e7a023 sw a4,0(a5) 1a0: 00e7a023 sw a4,0(a5)
198: 200007b7 lui a5,0x20000 1a4: 200007b7 lui a5,0x20000
19c: 00700713 li a4,7 1a8: 00700713 li a4,7
1a0: 00e7a023 sw a4,0(a5) # 20000000 <__global_pointer$+0xffff800> 1ac: 00e7a023 sw a4,0(a5) # 20000000 <_sp+0xfffe000>
1a4: 400007b7 lui a5,0x40000 1b0: 10000797 auipc a5,0x10000
1a8: 00478793 addi a5,a5,4 # 40000004 <__global_pointer$+0x2ffff804> 1b4: e5478793 addi a5,a5,-428 # 10000004 <int_flag>
1ac: 00100713 li a4,1 1b8: 0007c783 lbu a5,0(a5)
1b0: 00e7a023 sw a4,0(a5) 1bc: 0ff7f793 andi a5,a5,255
1b4: 10000797 auipc a5,0x10000 1c0: fe0788e3 beqz a5,1b0 <main+0x40>
1b8: e4c78793 addi a5,a5,-436 # 10000000 <_data> 1c4: 200007b7 lui a5,0x20000
1bc: 0007a703 lw a4,0(a5) 1c8: 0007a703 lw a4,0(a5) # 20000000 <_sp+0xfffe000>
1c0: 1f300793 li a5,499 1cc: 200007b7 lui a5,0x20000
1c4: fee7f8e3 bgeu a5,a4,1b4 <main+0x48> 1d0: 00176713 ori a4,a4,1
1c8: 10000797 auipc a5,0x10000 1d4: 00e7a023 sw a4,0(a5) # 20000000 <_sp+0xfffe000>
1cc: e3878793 addi a5,a5,-456 # 10000000 <_data> 1d8: 10000797 auipc a5,0x10000
1d0: 0007a023 sw zero,0(a5) 1dc: e2c78793 addi a5,a5,-468 # 10000004 <int_flag>
1d4: 400007b7 lui a5,0x40000 1e0: 00078023 sb zero,0(a5)
1d8: 00478793 addi a5,a5,4 # 40000004 <__global_pointer$+0x2ffff804> 1e4: 10000797 auipc a5,0x10000
1dc: 0007a703 lw a4,0(a5) 1e8: e1c78793 addi a5,a5,-484 # 10000000 <_data>
1e0: 400007b7 lui a5,0x40000 1ec: 0007a783 lw a5,0(a5)
1e4: 00478793 addi a5,a5,4 # 40000004 <__global_pointer$+0x2ffff804> 1f0: 00178713 addi a4,a5,1
1e8: 00174713 xori a4,a4,1 1f4: 10000797 auipc a5,0x10000
1ec: 00e7a023 sw a4,0(a5) 1f8: e0c78793 addi a5,a5,-500 # 10000000 <_data>
1f0: fc5ff06f j 1b4 <main+0x48> 1fc: 00e7a023 sw a4,0(a5)
200: 10000797 auipc a5,0x10000
000001f4 <TIMER0_IRQHandler>: 204: e0078793 addi a5,a5,-512 # 10000000 <_data>
1f4: ff010113 addi sp,sp,-16 208: 0007a703 lw a4,0(a5)
1f8: 00812623 sw s0,12(sp) 20c: 00200793 li a5,2
1fc: 01010413 addi s0,sp,16 210: faf710e3 bne a4,a5,1b0 <main+0x40>
200: 200007b7 lui a5,0x20000 214: 200007b7 lui a5,0x20000
204: 00700713 li a4,7 218: 0007a023 sw zero,0(a5) # 20000000 <_sp+0xfffe000>
208: 00e7a023 sw a4,0(a5) # 20000000 <__global_pointer$+0xffff800>
20c: 10000797 auipc a5,0x10000
210: df478793 addi a5,a5,-524 # 10000000 <_data>
214: 0007a783 lw a5,0(a5)
218: 00178713 addi a4,a5,1
21c: 10000797 auipc a5,0x10000 21c: 10000797 auipc a5,0x10000
220: de478793 addi a5,a5,-540 # 10000000 <_data> 220: de478793 addi a5,a5,-540 # 10000000 <_data>
224: 00e7a023 sw a4,0(a5) 224: 0007a023 sw zero,0(a5)
228: 400007b7 lui a5,0x40000 228: 00100d93 li s11,1
22c: 00478793 addi a5,a5,4 # 40000004 <__global_pointer$+0x2ffff804> 22c: 00000013 nop
230: 0007a023 sw zero,0(a5) 230: 00000793 li a5,0
234: 00000013 nop 234: 00078513 mv a0,a5
238: 00c12403 lw s0,12(sp) 238: 00c12403 lw s0,12(sp)
23c: 01010113 addi sp,sp,16 23c: 01010113 addi sp,sp,16
240: 00008067 ret 240: 00008067 ret
00000244 <timer0_irq_handler>:
244: ff010113 addi sp,sp,-16
248: 00812623 sw s0,12(sp)
24c: 01010413 addi s0,sp,16
250: 200007b7 lui a5,0x20000
254: 0007a703 lw a4,0(a5) # 20000000 <_sp+0xfffe000>
258: 200007b7 lui a5,0x20000
25c: 00476713 ori a4,a4,4
260: 00e7a023 sw a4,0(a5) # 20000000 <_sp+0xfffe000>
264: 10000797 auipc a5,0x10000
268: da078793 addi a5,a5,-608 # 10000004 <int_flag>
26c: 00100713 li a4,1
270: 00e78023 sb a4,0(a5)
274: 00000013 nop
278: 00c12403 lw s0,12(sp)
27c: 01010113 addi sp,sp,16
280: 00008067 ret
00000284 <trap_handler>:
284: fe010113 addi sp,sp,-32
288: 00112e23 sw ra,28(sp)
28c: 00812c23 sw s0,24(sp)
290: 02010413 addi s0,sp,32
294: fea42623 sw a0,-20(s0)
298: fadff0ef jal ra,244 <timer0_irq_handler>
29c: 00000013 nop
2a0: 01c12083 lw ra,28(sp)
2a4: 01812403 lw s0,24(sp)
2a8: 02010113 addi sp,sp,32
2ac: 00008067 ret
000002b0 <_init>:
2b0: ff010113 addi sp,sp,-16
2b4: 00812623 sw s0,12(sp)
2b8: 01010413 addi s0,sp,16
2bc: 00000797 auipc a5,0x0
2c0: db478793 addi a5,a5,-588 # 70 <trap_entry>
2c4: 30579073 csrw mtvec,a5
2c8: 00000013 nop
2cc: 00c12403 lw s0,12(sp)
2d0: 01010113 addi sp,sp,16
2d4: 00008067 ret
Disassembly of section .bss: Disassembly of section .bss:
10000000 <__bss_start>: 10000000 <__bss_start>:
10000000: 0000 unimp 10000000: 0000 unimp
... ...
10000004 <int_flag>:
10000004: 0000 unimp
...
Disassembly of section .stack: Disassembly of section .stack:
10000400 <_sp-0x400>: 10001800 <_sp-0x800>:
... ...
Disassembly of section .comment: Disassembly of section .comment:
@ -181,11 +224,11 @@ Disassembly of section .comment:
4: 2820 fld fs0,80(s0) 4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm 6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19 a: 434d li t1,19
c: 2055 jal b0 <_timer0_handler+0x4c> c: 2055 jal b0 <trap_entry+0x40>
e: 6345 lui t1,0x11 e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0) 10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4) 12: 7370 flw fa2,100(a4)
14: 2065 jal bc <_timer0_handler+0x58> 14: 2065 jal bc <trap_entry+0x4c>
16: 4952 lw s2,20(sp) 16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353 18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0) 1c: 4520 lw s0,72(a0)

92
tests/example/trap_entry.S Normal file
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@ -0,0 +1,92 @@
#define REGBYTES 4
#define STORE sw
#define LOAD lw
.section .text.entry
.align 2
.global trap_entry
trap_entry:
addi sp, sp, -32*REGBYTES
STORE x1, 1*REGBYTES(sp)
STORE x2, 2*REGBYTES(sp)
STORE x3, 3*REGBYTES(sp)
STORE x4, 4*REGBYTES(sp)
STORE x5, 5*REGBYTES(sp)
STORE x6, 6*REGBYTES(sp)
STORE x7, 7*REGBYTES(sp)
STORE x8, 8*REGBYTES(sp)
STORE x9, 9*REGBYTES(sp)
STORE x10, 10*REGBYTES(sp)
STORE x11, 11*REGBYTES(sp)
STORE x12, 12*REGBYTES(sp)
STORE x13, 13*REGBYTES(sp)
STORE x14, 14*REGBYTES(sp)
STORE x15, 15*REGBYTES(sp)
STORE x16, 16*REGBYTES(sp)
STORE x17, 17*REGBYTES(sp)
STORE x18, 18*REGBYTES(sp)
STORE x19, 19*REGBYTES(sp)
STORE x20, 20*REGBYTES(sp)
STORE x21, 21*REGBYTES(sp)
STORE x22, 22*REGBYTES(sp)
STORE x23, 23*REGBYTES(sp)
STORE x24, 24*REGBYTES(sp)
STORE x25, 25*REGBYTES(sp)
#ifndef SIMULATION
STORE x26, 26*REGBYTES(sp)
STORE x27, 27*REGBYTES(sp)
#endif
STORE x28, 28*REGBYTES(sp)
STORE x29, 29*REGBYTES(sp)
STORE x30, 30*REGBYTES(sp)
STORE x31, 31*REGBYTES(sp)
csrr a0, mcause
call trap_handler
LOAD x1, 1*REGBYTES(sp)
LOAD x2, 2*REGBYTES(sp)
LOAD x3, 3*REGBYTES(sp)
LOAD x4, 4*REGBYTES(sp)
LOAD x5, 5*REGBYTES(sp)
LOAD x6, 6*REGBYTES(sp)
LOAD x7, 7*REGBYTES(sp)
LOAD x8, 8*REGBYTES(sp)
LOAD x9, 9*REGBYTES(sp)
LOAD x10, 10*REGBYTES(sp)
LOAD x11, 11*REGBYTES(sp)
LOAD x12, 12*REGBYTES(sp)
LOAD x13, 13*REGBYTES(sp)
LOAD x14, 14*REGBYTES(sp)
LOAD x15, 15*REGBYTES(sp)
LOAD x16, 16*REGBYTES(sp)
LOAD x17, 17*REGBYTES(sp)
LOAD x18, 18*REGBYTES(sp)
LOAD x19, 19*REGBYTES(sp)
LOAD x20, 20*REGBYTES(sp)
LOAD x21, 21*REGBYTES(sp)
LOAD x22, 22*REGBYTES(sp)
LOAD x23, 23*REGBYTES(sp)
LOAD x24, 24*REGBYTES(sp)
LOAD x25, 25*REGBYTES(sp)
#ifndef SIMULATION
LOAD x26, 26*REGBYTES(sp)
LOAD x27, 27*REGBYTES(sp)
#endif
LOAD x28, 28*REGBYTES(sp)
LOAD x29, 29*REGBYTES(sp)
LOAD x30, 30*REGBYTES(sp)
LOAD x31, 31*REGBYTES(sp)
addi sp, sp, 32*REGBYTES
mret
.weak trap_handler
trap_handler:
1:
j 1b

23
tests/example/uart_tx/Makefile
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@ -1,9 +1,18 @@
RISCV_ARCH := rv32im
RISCV_ABI := ilp32
TARGET = uart_tx
#CFLAGS += -DSIMULATION
#CFLAGS += -O2
#ASM_SRCS +=
#LDFLAGS +=
#INCLUDES += -I.
C_SRCS := \
main.c \
include ../common.mk include ../common.mk
.PHONY: all
all:
$(RISCV_GCC) $(CFLAGS) ../start.S main.c xprintf.c -T ../link.lds -o uart_tx
$(RISCV_OBJCOPY) -O binary uart_tx uart_tx.bin
$(RISCV_OBJDUMP) --disassemble-all uart_tx > uart_tx.dump

2
tests/example/uart_tx/main.c
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@ -1,7 +1,7 @@
#include <stdint.h> #include <stdint.h>
#include "../include/uart.h" #include "../include/uart.h"
#include "xprintf.h" #include "../include/xprintf.h"

BIN
tests/example/uart_tx/uart_tx
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BIN
tests/example/uart_tx/uart_tx.bin
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1064
tests/example/uart_tx/uart_tx.dump
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