diff --git a/rtl/core/rib.v b/rtl/core/rib.v
index 7de343e..95d1746 100644
--- a/rtl/core/rib.v
+++ b/rtl/core/rib.v
@@ -27,7 +27,6 @@ module rib(
     input wire[`MemAddrBus] m0_addr_i,     // 主设备0读、写地址
     input wire[`MemBus] m0_data_i,         // 主设备0写数据
     output reg[`MemBus] m0_data_o,         // 主设备0读取到的数据
-    output reg m0_ack_o,                   // 主设备0访问完成标志
     input wire m0_req_i,                   // 主设备0访问请求标志
     input wire m0_we_i,                    // 主设备0写标志
 
@@ -35,7 +34,6 @@ module rib(
     input wire[`MemAddrBus] m1_addr_i,     // 主设备1读、写地址
     input wire[`MemBus] m1_data_i,         // 主设备1写数据
     output reg[`MemBus] m1_data_o,         // 主设备1读取到的数据
-    output reg m1_ack_o,                   // 主设备1访问完成标志
     input wire m1_req_i,                   // 主设备1访问请求标志
     input wire m1_we_i,                    // 主设备1写标志
 
@@ -43,7 +41,6 @@ module rib(
     input wire[`MemAddrBus] m2_addr_i,     // 主设备2读、写地址
     input wire[`MemBus] m2_data_i,         // 主设备2写数据
     output reg[`MemBus] m2_data_o,         // 主设备2读取到的数据
-    output reg m2_ack_o,                   // 主设备2访问完成标志
     input wire m2_req_i,                   // 主设备2访问请求标志
     input wire m2_we_i,                    // 主设备2写标志
 
@@ -51,7 +48,6 @@ module rib(
     input wire[`MemAddrBus] m3_addr_i,     // 主设备3读、写地址
     input wire[`MemBus] m3_data_i,         // 主设备3写数据
     output reg[`MemBus] m3_data_o,         // 主设备3读取到的数据
-    output reg m3_ack_o,                   // 主设备3访问完成标志
     input wire m3_req_i,                   // 主设备3访问请求标志
     input wire m3_we_i,                    // 主设备3写标志
 
@@ -59,48 +55,36 @@ module rib(
     output reg[`MemAddrBus] s0_addr_o,     // 从设备0读、写地址
     output reg[`MemBus] s0_data_o,         // 从设备0写数据
     input wire[`MemBus] s0_data_i,         // 从设备0读取到的数据
-    input wire s0_ack_i,                   // 从设备0访问完成标志
-    output reg s0_req_o,                   // 从设备0访问请求标志
     output reg s0_we_o,                    // 从设备0写标志
 
     // slave 1 interface
     output reg[`MemAddrBus] s1_addr_o,     // 从设备1读、写地址
     output reg[`MemBus] s1_data_o,         // 从设备1写数据
     input wire[`MemBus] s1_data_i,         // 从设备1读取到的数据
-    input wire s1_ack_i,                   // 从设备1访问完成标志
-    output reg s1_req_o,                   // 从设备1访问请求标志
     output reg s1_we_o,                    // 从设备1写标志
 
     // slave 2 interface
     output reg[`MemAddrBus] s2_addr_o,     // 从设备2读、写地址
     output reg[`MemBus] s2_data_o,         // 从设备2写数据
     input wire[`MemBus] s2_data_i,         // 从设备2读取到的数据
-    input wire s2_ack_i,                   // 从设备2访问完成标志
-    output reg s2_req_o,                   // 从设备2访问请求标志
     output reg s2_we_o,                    // 从设备2写标志
 
     // slave 3 interface
     output reg[`MemAddrBus] s3_addr_o,     // 从设备3读、写地址
     output reg[`MemBus] s3_data_o,         // 从设备3写数据
     input wire[`MemBus] s3_data_i,         // 从设备3读取到的数据
-    input wire s3_ack_i,                   // 从设备3访问完成标志
-    output reg s3_req_o,                   // 从设备3访问请求标志
     output reg s3_we_o,                    // 从设备3写标志
 
     // slave 4 interface
     output reg[`MemAddrBus] s4_addr_o,     // 从设备4读、写地址
     output reg[`MemBus] s4_data_o,         // 从设备4写数据
     input wire[`MemBus] s4_data_i,         // 从设备4读取到的数据
-    input wire s4_ack_i,                   // 从设备4访问完成标志
-    output reg s4_req_o,                   // 从设备4访问请求标志
     output reg s4_we_o,                    // 从设备4写标志
 
     // slave 5 interface
     output reg[`MemAddrBus] s5_addr_o,     // 从设备5读、写地址
     output reg[`MemBus] s5_data_o,         // 从设备5写数据
     input wire[`MemBus] s5_data_i,         // 从设备5读取到的数据
-    input wire s5_ack_i,                   // 从设备5访问完成标志
-    output reg s5_req_o,                   // 从设备5访问请求标志
     output reg s5_we_o,                    // 从设备5写标志
 
     output reg hold_flag_o                 // 暂停流水线标志
@@ -156,10 +140,6 @@ module rib(
     // 根据仲裁结果，选择(访问)对应的从设备
     always @ (*) begin
         if (rst == `RstEnable) begin
-            m0_ack_o = `RIB_NACK;
-            m1_ack_o = `RIB_NACK;
-            m2_ack_o = `RIB_NACK;
-            m3_ack_o = `RIB_NACK;
             m0_data_o = `ZeroWord;
             m1_data_o = `INST_NOP;
             m2_data_o = `ZeroWord;
@@ -177,12 +157,6 @@ module rib(
             s3_data_o = `ZeroWord;
             s4_data_o = `ZeroWord;
             s5_data_o = `ZeroWord;
-            s0_req_o = `RIB_NREQ;
-            s1_req_o = `RIB_NREQ;
-            s2_req_o = `RIB_NREQ;
-            s3_req_o = `RIB_NREQ;
-            s4_req_o = `RIB_NREQ;
-            s5_req_o = `RIB_NREQ;
             s0_we_o = `WriteDisable;
             s1_we_o = `WriteDisable;
             s2_we_o = `WriteDisable;
@@ -190,10 +164,6 @@ module rib(
             s4_we_o = `WriteDisable;
             s5_we_o = `WriteDisable;
         end else begin
-            m0_ack_o = `RIB_NACK;
-            m1_ack_o = `RIB_NACK;
-            m2_ack_o = `RIB_NACK;
-            m3_ack_o = `RIB_NACK;
             m0_data_o = `ZeroWord;
             m1_data_o = `INST_NOP;
             m2_data_o = `ZeroWord;
@@ -211,12 +181,6 @@ module rib(
             s3_data_o = `ZeroWord;
             s4_data_o = `ZeroWord;
             s5_data_o = `ZeroWord;
-            s0_req_o = `RIB_NREQ;
-            s1_req_o = `RIB_NREQ;
-            s2_req_o = `RIB_NREQ;
-            s3_req_o = `RIB_NREQ;
-            s4_req_o = `RIB_NREQ;
-            s5_req_o = `RIB_NREQ;
             s0_we_o = `WriteDisable;
             s1_we_o = `WriteDisable;
             s2_we_o = `WriteDisable;
@@ -228,51 +192,39 @@ module rib(
                 grant0: begin
                     case (m0_addr_i[31:28])
                         slave_0: begin
-                            s0_req_o = m0_req_i;
                             s0_we_o = m0_we_i;
                             s0_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
                             s0_data_o = m0_data_i;
-                            m0_ack_o = s0_ack_i;
                             m0_data_o = s0_data_i;
                         end
                         slave_1: begin
-                            s1_req_o = m0_req_i;
                             s1_we_o = m0_we_i;
                             s1_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
                             s1_data_o = m0_data_i;
-                            m0_ack_o = s1_ack_i;
                             m0_data_o = s1_data_i;
                         end
                         slave_2: begin
-                            s2_req_o = m0_req_i;
                             s2_we_o = m0_we_i;
                             s2_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
                             s2_data_o = m0_data_i;
-                            m0_ack_o = s2_ack_i;
                             m0_data_o = s2_data_i;
                         end
                         slave_3: begin
-                            s3_req_o = m0_req_i;
                             s3_we_o = m0_we_i;
                             s3_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
                             s3_data_o = m0_data_i;
-                            m0_ack_o = s3_ack_i;
                             m0_data_o = s3_data_i;
                         end
                         slave_4: begin
-                            s4_req_o = m0_req_i;
                             s4_we_o = m0_we_i;
                             s4_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
                             s4_data_o = m0_data_i;
-                            m0_ack_o = s4_ack_i;
                             m0_data_o = s4_data_i;
                         end
                         slave_5: begin
-                            s5_req_o = m0_req_i;
                             s5_we_o = m0_we_i;
                             s5_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
                             s5_data_o = m0_data_i;
-                            m0_ack_o = s5_ack_i;
                             m0_data_o = s5_data_i;
                         end
                         default: begin
@@ -283,51 +235,39 @@ module rib(
                 grant1: begin
                     case (m1_addr_i[31:28])
                         slave_0: begin
-                            s0_req_o = m1_req_i;
                             s0_we_o = m1_we_i;
                             s0_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
                             s0_data_o = m1_data_i;
-                            m1_ack_o = s0_ack_i;
                             m1_data_o = s0_data_i;
                         end
                         slave_1: begin
-                            s1_req_o = m1_req_i;
                             s1_we_o = m1_we_i;
                             s1_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
                             s1_data_o = m1_data_i;
-                            m1_ack_o = s1_ack_i;
                             m1_data_o = s1_data_i;
                         end
                         slave_2: begin
-                            s2_req_o = m1_req_i;
                             s2_we_o = m1_we_i;
                             s2_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
                             s2_data_o = m1_data_i;
-                            m1_ack_o = s2_ack_i;
                             m1_data_o = s2_data_i;
                         end
                         slave_3: begin
-                            s3_req_o = m1_req_i;
                             s3_we_o = m1_we_i;
                             s3_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
                             s3_data_o = m1_data_i;
-                            m1_ack_o = s3_ack_i;
                             m1_data_o = s3_data_i;
                         end
                         slave_4: begin
-                            s4_req_o = m1_req_i;
                             s4_we_o = m1_we_i;
                             s4_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
                             s4_data_o = m1_data_i;
-                            m1_ack_o = s4_ack_i;
                             m1_data_o = s4_data_i;
                         end
                         slave_5: begin
-                            s5_req_o = m1_req_i;
                             s5_we_o = m1_we_i;
                             s5_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
                             s5_data_o = m1_data_i;
-                            m1_ack_o = s5_ack_i;
                             m1_data_o = s5_data_i;
                         end
                         default: begin
@@ -338,51 +278,39 @@ module rib(
                 grant2: begin
                     case (m2_addr_i[31:28])
                         slave_0: begin
-                            s0_req_o = m2_req_i;
                             s0_we_o = m2_we_i;
                             s0_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
                             s0_data_o = m2_data_i;
-                            m2_ack_o = s0_ack_i;
                             m2_data_o = s0_data_i;
                         end
                         slave_1: begin
-                            s1_req_o = m2_req_i;
                             s1_we_o = m2_we_i;
                             s1_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
                             s1_data_o = m2_data_i;
-                            m2_ack_o = s1_ack_i;
                             m2_data_o = s1_data_i;
                         end
                         slave_2: begin
-                            s2_req_o = m2_req_i;
                             s2_we_o = m2_we_i;
                             s2_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
                             s2_data_o = m2_data_i;
-                            m2_ack_o = s2_ack_i;
                             m2_data_o = s2_data_i;
                         end
                         slave_3: begin
-                            s3_req_o = m2_req_i;
                             s3_we_o = m2_we_i;
                             s3_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
                             s3_data_o = m2_data_i;
-                            m2_ack_o = s3_ack_i;
                             m2_data_o = s3_data_i;
                         end
                         slave_4: begin
-                            s4_req_o = m2_req_i;
                             s4_we_o = m2_we_i;
                             s4_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
                             s4_data_o = m2_data_i;
-                            m2_ack_o = s4_ack_i;
                             m2_data_o = s4_data_i;
                         end
                         slave_5: begin
-                            s5_req_o = m2_req_i;
                             s5_we_o = m2_we_i;
                             s5_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
                             s5_data_o = m2_data_i;
-                            m2_ack_o = s5_ack_i;
                             m2_data_o = s5_data_i;
                         end
                         default: begin
@@ -393,51 +321,39 @@ module rib(
                 grant3: begin
                     case (m3_addr_i[31:28])
                         slave_0: begin
-                            s0_req_o = m3_req_i;
                             s0_we_o = m3_we_i;
                             s0_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
                             s0_data_o = m3_data_i;
-                            m3_ack_o = s0_ack_i;
                             m3_data_o = s0_data_i;
                         end
                         slave_1: begin
-                            s1_req_o = m3_req_i;
                             s1_we_o = m3_we_i;
                             s1_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
                             s1_data_o = m3_data_i;
-                            m3_ack_o = s1_ack_i;
                             m3_data_o = s1_data_i;
                         end
                         slave_2: begin
-                            s2_req_o = m3_req_i;
                             s2_we_o = m3_we_i;
                             s2_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
                             s2_data_o = m3_data_i;
-                            m3_ack_o = s2_ack_i;
                             m3_data_o = s2_data_i;
                         end
                         slave_3: begin
-                            s3_req_o = m3_req_i;
                             s3_we_o = m3_we_i;
                             s3_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
                             s3_data_o = m3_data_i;
-                            m3_ack_o = s3_ack_i;
                             m3_data_o = s3_data_i;
                         end
                         slave_4: begin
-                            s4_req_o = m3_req_i;
                             s4_we_o = m3_we_i;
                             s4_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
                             s4_data_o = m3_data_i;
-                            m3_ack_o = s4_ack_i;
                             m3_data_o = s4_data_i;
                         end
                         slave_5: begin
-                            s5_req_o = m3_req_i;
                             s5_we_o = m3_we_i;
                             s5_addr_o = {{4'h0}, {m3_addr_i[27:0]}};
                             s5_data_o = m3_data_i;
-                            m3_ack_o = s5_ack_i;
                             m3_data_o = s5_data_i;
                         end
                         default: begin
diff --git a/rtl/perips/gpio.v b/rtl/perips/gpio.v
index 4c8c5da..608c315 100644
--- a/rtl/perips/gpio.v
+++ b/rtl/perips/gpio.v
@@ -22,12 +22,10 @@ module gpio(
 	input wire rst,
 
     input wire we_i,
-    input wire req_i,
     input wire[31:0] addr_i,
     input wire[31:0] data_i,
 
     output reg[31:0] data_o,
-    output reg ack_o,
 
     input wire[1:0] io_pin_i,
     output wire[31:0] reg_ctrl,
diff --git a/rtl/perips/ram.v b/rtl/perips/ram.v
index d03e8b8..bb3d32c 100644
--- a/rtl/perips/ram.v
+++ b/rtl/perips/ram.v
@@ -25,10 +25,8 @@ module ram(
     input wire we_i,                   // write enable
     input wire[`MemAddrBus] addr_i,    // addr
     input wire[`MemBus] data_i,
-    input wire req_i,
 
-    output reg[`MemBus] data_o,        // read data
-    output reg ack_o
+    output reg[`MemBus] data_o         // read data
 
     );
 
@@ -36,12 +34,8 @@ module ram(
 
 
     always @ (posedge clk) begin
-        if (rst == `RstEnable) begin
-            ack_o <= `RIB_ACK;
-        end else begin
-            if (we_i == `WriteEnable) begin
-                _ram[addr_i[31:2]] <= data_i;
-            end
+        if (we_i == `WriteEnable) begin
+            _ram[addr_i[31:2]] <= data_i;
         end
     end
 
diff --git a/rtl/perips/rom.v b/rtl/perips/rom.v
index 4654529..d934eec 100644
--- a/rtl/perips/rom.v
+++ b/rtl/perips/rom.v
@@ -25,10 +25,8 @@ module rom(
     input wire we_i,                   // write enable
     input wire[`MemAddrBus] addr_i,    // addr
     input wire[`MemBus] data_i,
-    input wire req_i,
 
-    output reg[`MemBus] data_o,        // read data
-    output reg ack_o
+    output reg[`MemBus] data_o         // read data
 
     );
 
@@ -36,12 +34,8 @@ module rom(
 
 
     always @ (posedge clk) begin
-        if (rst == `RstEnable) begin
-            ack_o <= `RIB_ACK;
-        end else begin
-            if (we_i == `WriteEnable) begin
-                _rom[addr_i[31:2]] <= data_i;
-            end
+        if (we_i == `WriteEnable) begin
+            _rom[addr_i[31:2]] <= data_i;
         end
     end
 
diff --git a/rtl/perips/spi.v b/rtl/perips/spi.v
index 6a394e3..8f0f83e 100644
--- a/rtl/perips/spi.v
+++ b/rtl/perips/spi.v
@@ -24,10 +24,8 @@ module spi(
     input wire[31:0] data_i,
     input wire[31:0] addr_i,
     input wire we_i,
-    input wire req_i,
 
     output reg[31:0] data_o,
-    output reg ack_o,
 
     output reg spi_mosi,             // spi控制器输出、spi设备输入信号
     input wire spi_miso,             // spi控制器输入、spi设备输出信号
diff --git a/rtl/perips/timer.v b/rtl/perips/timer.v
index a81c28a..201134f 100644
--- a/rtl/perips/timer.v
+++ b/rtl/perips/timer.v
@@ -26,11 +26,9 @@ module timer(
     input wire[31:0] data_i,
     input wire[31:0] addr_i,
     input wire we_i,
-    input wire req_i,
 
     output reg[31:0] data_o,
-    output wire int_sig_o,
-    output reg ack_o
+    output wire int_sig_o
 
     );
 
diff --git a/rtl/perips/uart.v b/rtl/perips/uart.v
index e3ada87..628bbcc 100644
--- a/rtl/perips/uart.v
+++ b/rtl/perips/uart.v
@@ -22,12 +22,10 @@ module uart(
 	input wire rst,
 
     input wire we_i,
-    input wire req_i,
     input wire[31:0] addr_i,
     input wire[31:0] data_i,
 
     output reg[31:0] data_o,
-    output reg ack_o,
 	output wire tx_pin,
     input wire rx_pin
 
diff --git a/rtl/soc/tinyriscv_soc_top.v b/rtl/soc/tinyriscv_soc_top.v
index 3cc5109..4ed1f86 100644
--- a/rtl/soc/tinyriscv_soc_top.v
+++ b/rtl/soc/tinyriscv_soc_top.v
@@ -50,7 +50,6 @@ module tinyriscv_soc_top(
     wire[`MemAddrBus] m0_addr_i;
     wire[`MemBus] m0_data_i;
     wire[`MemBus] m0_data_o;
-    wire m0_ack_o;
     wire m0_req_i;
     wire m0_we_i;
 
@@ -58,7 +57,6 @@ module tinyriscv_soc_top(
     wire[`MemAddrBus] m1_addr_i;
     wire[`MemBus] m1_data_i;
     wire[`MemBus] m1_data_o;
-    wire m1_ack_o;
     wire m1_req_i;
     wire m1_we_i;
 
@@ -66,7 +64,6 @@ module tinyriscv_soc_top(
     wire[`MemAddrBus] m2_addr_i;
     wire[`MemBus] m2_data_i;
     wire[`MemBus] m2_data_o;
-    wire m2_ack_o;
     wire m2_req_i;
     wire m2_we_i;
 
@@ -74,7 +71,6 @@ module tinyriscv_soc_top(
     wire[`MemAddrBus] m3_addr_i;
     wire[`MemBus] m3_data_i;
     wire[`MemBus] m3_data_o;
-    wire m3_ack_o;
     wire m3_req_i;
     wire m3_we_i;
 
@@ -82,48 +78,36 @@ module tinyriscv_soc_top(
     wire[`MemAddrBus] s0_addr_o;
     wire[`MemBus] s0_data_o;
     wire[`MemBus] s0_data_i;
-    wire s0_ack_i;
-    wire s0_req_o;
     wire s0_we_o;
 
     // slave 1 interface
     wire[`MemAddrBus] s1_addr_o;
     wire[`MemBus] s1_data_o;
     wire[`MemBus] s1_data_i;
-    wire s1_ack_i;
-    wire s1_req_o;
     wire s1_we_o;
 
     // slave 2 interface
     wire[`MemAddrBus] s2_addr_o;
     wire[`MemBus] s2_data_o;
     wire[`MemBus] s2_data_i;
-    wire s2_ack_i;
-    wire s2_req_o;
     wire s2_we_o;
 
     // slave 3 interface
     wire[`MemAddrBus] s3_addr_o;
     wire[`MemBus] s3_data_o;
     wire[`MemBus] s3_data_i;
-    wire s3_ack_i;
-    wire s3_req_o;
     wire s3_we_o;
 
     // slave 4 interface
     wire[`MemAddrBus] s4_addr_o;
     wire[`MemBus] s4_data_o;
     wire[`MemBus] s4_data_i;
-    wire s4_ack_i;
-    wire s4_req_o;
     wire s4_we_o;
 
     // slave 5 interface
     wire[`MemAddrBus] s5_addr_o;
     wire[`MemBus] s5_data_o;
     wire[`MemBus] s5_data_i;
-    wire s5_ack_i;
-    wire s5_req_o;
     wire s5_we_o;
 
     // rib
@@ -199,9 +183,7 @@ module tinyriscv_soc_top(
         .we_i(s0_we_o),
         .addr_i(s0_addr_o),
         .data_i(s0_data_o),
-        .req_i(s0_req_o),
-        .data_o(s0_data_i),
-        .ack_o(s0_ack_i)
+        .data_o(s0_data_i)
     );
 
     // ram模块例化
@@ -211,9 +193,7 @@ module tinyriscv_soc_top(
         .we_i(s1_we_o),
         .addr_i(s1_addr_o),
         .data_i(s1_data_o),
-        .req_i(s1_req_o),
-        .data_o(s1_data_i),
-        .ack_o(s1_ack_i)
+        .data_o(s1_data_i)
     );
 
     // timer模块例化
@@ -224,9 +204,7 @@ module tinyriscv_soc_top(
         .addr_i(s2_addr_o),
         .we_i(s2_we_o),
         .data_o(s2_data_i),
-        .int_sig_o(timer0_int),
-        .req_i(s2_req_o),
-        .ack_o(s2_ack_i)
+        .int_sig_o(timer0_int)
     );
 
     // uart模块例化
@@ -234,11 +212,9 @@ module tinyriscv_soc_top(
         .clk(clk),
         .rst(rst),
         .we_i(s3_we_o),
-        .req_i(s3_req_o),
         .addr_i(s3_addr_o),
         .data_i(s3_data_o),
         .data_o(s3_data_i),
-        .ack_o(s3_ack_i),
         .tx_pin(uart_tx_pin),
         .rx_pin(uart_rx_pin)
     );
@@ -255,11 +231,9 @@ module tinyriscv_soc_top(
         .clk(clk),
         .rst(rst),
         .we_i(s4_we_o),
-        .req_i(s4_req_o),
         .addr_i(s4_addr_o),
         .data_i(s4_data_o),
         .data_o(s4_data_i),
-        .ack_o(s4_ack_i),
         .io_pin_i(io_in),
         .reg_ctrl(gpio_ctrl),
         .reg_data(gpio_data)
@@ -272,9 +246,7 @@ module tinyriscv_soc_top(
         .data_i(s5_data_o),
         .addr_i(s5_addr_o),
         .we_i(s5_we_o),
-        .req_i(s5_req_o),
         .data_o(s5_data_i),
-        .ack_o(s5_ack_i),
         .spi_mosi(spi_mosi),
         .spi_miso(spi_miso),
         .spi_ss(spi_ss),
@@ -290,7 +262,6 @@ module tinyriscv_soc_top(
         .m0_addr_i(m0_addr_i),
         .m0_data_i(m0_data_i),
         .m0_data_o(m0_data_o),
-        .m0_ack_o(m0_ack_o),
         .m0_req_i(m0_req_i),
         .m0_we_i(m0_we_i),
 
@@ -298,7 +269,6 @@ module tinyriscv_soc_top(
         .m1_addr_i(m1_addr_i),
         .m1_data_i(`ZeroWord),
         .m1_data_o(m1_data_o),
-        .m1_ack_o(m1_ack_o),
         .m1_req_i(`RIB_REQ),
         .m1_we_i(`WriteDisable),
 
@@ -306,7 +276,6 @@ module tinyriscv_soc_top(
         .m2_addr_i(m2_addr_i),
         .m2_data_i(m2_data_i),
         .m2_data_o(m2_data_o),
-        .m2_ack_o(m2_ack_o),
         .m2_req_i(m2_req_i),
         .m2_we_i(m2_we_i),
 
@@ -314,7 +283,6 @@ module tinyriscv_soc_top(
         .m3_addr_i(m3_addr_i),
         .m3_data_i(m3_data_i),
         .m3_data_o(m3_data_o),
-        .m3_ack_o(m3_ack_o),
         .m3_req_i(m3_req_i),
         .m3_we_i(m3_we_i),
 
@@ -322,48 +290,36 @@ module tinyriscv_soc_top(
         .s0_addr_o(s0_addr_o),
         .s0_data_o(s0_data_o),
         .s0_data_i(s0_data_i),
-        .s0_ack_i(s0_ack_i),
-        .s0_req_o(s0_req_o),
         .s0_we_o(s0_we_o),
 
         // slave 1 interface
         .s1_addr_o(s1_addr_o),
         .s1_data_o(s1_data_o),
         .s1_data_i(s1_data_i),
-        .s1_ack_i(s1_ack_i),
-        .s1_req_o(s1_req_o),
         .s1_we_o(s1_we_o),
 
         // slave 2 interface
         .s2_addr_o(s2_addr_o),
         .s2_data_o(s2_data_o),
         .s2_data_i(s2_data_i),
-        .s2_ack_i(s2_ack_i),
-        .s2_req_o(s2_req_o),
         .s2_we_o(s2_we_o),
 
         // slave 3 interface
         .s3_addr_o(s3_addr_o),
         .s3_data_o(s3_data_o),
         .s3_data_i(s3_data_i),
-        .s3_ack_i(s3_ack_i),
-        .s3_req_o(s3_req_o),
         .s3_we_o(s3_we_o),
 
         // slave 4 interface
         .s4_addr_o(s4_addr_o),
         .s4_data_o(s4_data_o),
         .s4_data_i(s4_data_i),
-        .s4_ack_i(s4_ack_i),
-        .s4_req_o(s4_req_o),
         .s4_we_o(s4_we_o),
 
         // slave 5 interface
         .s5_addr_o(s5_addr_o),
         .s5_data_o(s5_data_o),
         .s5_data_i(s5_data_i),
-        .s5_ack_i(s5_ack_i),
-        .s5_req_o(s5_req_o),
         .s5_we_o(s5_we_o),
 
         .hold_flag_o(rib_hold_flag_o)