sdk:bsp: adapte to new rvic
Signed-off-by: liangkangnan <liangkangnan@163.com>pull/4/head
liangkangnan
parent
d4b670217a
commit
12467d1554
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@ -1,30 +1,114 @@
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#ifndef _RVIC_H_
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#define _RVIC_H_
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#define RVIC_BASE (0xD0000000)
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#define RVIC_IE (RVIC_BASE + (0x00))
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#define RVIC_IP (RVIC_BASE + (0x04))
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#define RVIC_PRIO0 (RVIC_BASE + (0x08))
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#define RVIC_PRIO1 (RVIC_BASE + (0x0C))
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#define RVIC_PRIO2 (RVIC_BASE + (0x10))
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#define RVIC_PRIO3 (RVIC_BASE + (0x14))
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#define RVIC_PRIO4 (RVIC_BASE + (0x18))
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#define RVIC_PRIO5 (RVIC_BASE + (0x1C))
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#define RVIC_PRIO6 (RVIC_BASE + (0x20))
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#define RVIC_PRIO7 (RVIC_BASE + (0x24))
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#define RVIC_ID (RVIC_BASE + (0x28))
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#define RVIC_REG(addr) (*((volatile uint32_t *)addr))
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typedef struct {
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volatile uint32_t prio[8];
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} rvic_prio_t;
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#define RVIC_PRIO ((rvic_prio_t *)0xD0000008)
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void rvic_irq_enable(uint32_t id);
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void rvic_irq_disable(uint32_t id);
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void rvic_clear_irq_pending(uint32_t id);
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void rvic_set_irq_prio_level(uint32_t id, uint8_t level);
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#endif
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// Generated register defines for rvic
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// Copyright information found in source file:
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// Copyright lowRISC contributors.
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// Licensing information found in source file:
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef _RVIC_REG_DEFS_
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#define _RVIC_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define RVIC_PARAM_REG_WIDTH 32
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#define RVIC_BASE (0xD0000000)
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#define RVIC_REG(addr) (*((volatile uint32_t *)(RVIC_BASE + addr)))
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#define RVIC_PRIO_REG_NUM (8)
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typedef struct {
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volatile uint32_t prio[RVIC_PRIO_REG_NUM];
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} rvic_prio_t;
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#define RVIC_PRIO ((rvic_prio_t *)(RVIC_BASE + RVIC_PRIORITY0_REG_OFFSET))
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typedef enum {
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RVIC_INT_ID_0 = 0,
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RVIC_INT_ID_1,
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RVIC_INT_ID_2,
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RVIC_INT_ID_3,
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RVIC_INT_ID_4,
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RVIC_INT_ID_5,
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RVIC_INT_ID_6,
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RVIC_INT_ID_7,
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RVIC_INT_ID_8,
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RVIC_INT_ID_9,
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RVIC_INT_ID_10,
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RVIC_INT_ID_11,
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RVIC_INT_ID_12,
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RVIC_INT_ID_13,
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RVIC_INT_ID_14,
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RVIC_INT_ID_15,
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RVIC_INT_ID_16,
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RVIC_INT_ID_17,
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RVIC_INT_ID_18,
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RVIC_INT_ID_19,
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RVIC_INT_ID_20,
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RVIC_INT_ID_21,
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RVIC_INT_ID_22,
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RVIC_INT_ID_23,
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RVIC_INT_ID_24,
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RVIC_INT_ID_25,
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RVIC_INT_ID_26,
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RVIC_INT_ID_27,
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RVIC_INT_ID_28,
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RVIC_INT_ID_29,
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RVIC_INT_ID_30,
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RVIC_INT_ID_31,
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} rvic_int_id_e;
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void rvic_irq_enable(rvic_int_id_e id);
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void rvic_irq_disable(rvic_int_id_e id);
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void rvic_clear_irq_pending(rvic_int_id_e id);
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void rvic_set_irq_prio_level(rvic_int_id_e id, uint8_t level);
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// RVIC interrupt enable register
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#define RVIC_ENABLE_REG_OFFSET 0x0
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#define RVIC_ENABLE_REG_RESVAL 0x0
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// RVIC interrupt pending register
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#define RVIC_PENDING_REG_OFFSET 0x4
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#define RVIC_PENDING_REG_RESVAL 0x0
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// RVIC interrupt priority0 register
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#define RVIC_PRIORITY0_REG_OFFSET 0x8
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#define RVIC_PRIORITY0_REG_RESVAL 0x0
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// RVIC interrupt priority1 register
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#define RVIC_PRIORITY1_REG_OFFSET 0xc
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#define RVIC_PRIORITY1_REG_RESVAL 0x0
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// RVIC interrupt priority2 register
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#define RVIC_PRIORITY2_REG_OFFSET 0x10
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#define RVIC_PRIORITY2_REG_RESVAL 0x0
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// RVIC interrupt priority3 register
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#define RVIC_PRIORITY3_REG_OFFSET 0x14
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#define RVIC_PRIORITY3_REG_RESVAL 0x0
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// RVIC interrupt priority4 register
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#define RVIC_PRIORITY4_REG_OFFSET 0x18
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#define RVIC_PRIORITY4_REG_RESVAL 0x0
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// RVIC interrupt priority5 register
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#define RVIC_PRIORITY5_REG_OFFSET 0x1c
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#define RVIC_PRIORITY5_REG_RESVAL 0x0
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// RVIC interrupt priority6 register
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#define RVIC_PRIORITY6_REG_OFFSET 0x20
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#define RVIC_PRIORITY6_REG_RESVAL 0x0
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// RVIC interrupt priority7 register
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#define RVIC_PRIORITY7_REG_OFFSET 0x24
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#define RVIC_PRIORITY7_REG_RESVAL 0x0
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _RVIC_REG_DEFS_
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// End generated register defines for rvic
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@ -3,22 +3,22 @@
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#include "../../bsp/include/rvic.h"
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void rvic_irq_enable(uint32_t id)
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void rvic_irq_enable(rvic_int_id_e id)
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{
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RVIC_REG(RVIC_IE) |= 1 << id;
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RVIC_REG(RVIC_ENABLE_REG_OFFSET) |= 1 << id;
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}
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void rvic_irq_disable(uint32_t id)
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void rvic_irq_disable(rvic_int_id_e id)
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{
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RVIC_REG(RVIC_IE) &= ~(1 << id);
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RVIC_REG(RVIC_ENABLE_REG_OFFSET) &= ~(1 << id);
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}
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void rvic_clear_irq_pending(uint32_t id)
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void rvic_clear_irq_pending(rvic_int_id_e id)
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{
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RVIC_REG(RVIC_IP) |= 1 << id;
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RVIC_REG(RVIC_PENDING_REG_OFFSET) |= 1 << id;
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}
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void rvic_set_irq_prio_level(uint32_t id, uint8_t level)
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void rvic_set_irq_prio_level(rvic_int_id_e id, uint8_t level)
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{
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uint8_t reg;
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uint8_t index;
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