diff --git a/sim/compliance_test/compliance_test.py b/sim/compliance_test/compliance_test.py
index 22502a4..d8ce2c3 100644
--- a/sim/compliance_test/compliance_test.py
+++ b/sim/compliance_test/compliance_test.py
@@ -41,6 +41,7 @@ iverilog_cmd.append(r'..\..\rtl\perips\gpio.v')
 iverilog_cmd.append(r'..\..\rtl\debug\jtag_dm.v')
 iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v')
 iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v')
+iverilog_cmd.append(r'..\..\rtl\debug\uart_debug.v')
 # ..\rtl\soc
 iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v')
 
diff --git a/sim/sim_default_nowave.bat b/sim/sim_default_nowave.bat
index 0f6270b..3300b53 100644
--- a/sim/sim_default_nowave.bat
+++ b/sim/sim_default_nowave.bat
@@ -1,2 +1,2 @@
-iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v
+iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v
 vvp out.vvp
diff --git a/sim/sim_new_nowave.bat b/sim/sim_new_nowave.bat
index 3908ef3..193dadc 100644
--- a/sim/sim_new_nowave.bat
+++ b/sim/sim_new_nowave.bat
@@ -1,3 +1,3 @@
 ..\tools\BinToMem_CLI.exe %1 %2
-iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v
+iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v
 vvp out.vvp