rtl: add sync_fifo module
Signed-off-by: liangkangnan <liangkangnan@163.com>pull/4/head
liangkangnan
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96d6976c44
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2db9e7dbb9
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@ -50,3 +50,4 @@
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../rtl/utils/gen_dff.sv
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../rtl/utils/gen_ram.sv
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../rtl/utils/cdc_2phase.sv
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../rtl/utils/sync_fifo.sv
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@ -0,0 +1,138 @@
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// Copyright 2018 ETH Zurich and University of Bologna.
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// Copyright and related rights are licensed under the Solderpad Hardware
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// License, Version 0.51 (the "License"); you may not use this file except in
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// compliance with the License. You may obtain a copy of the License at
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// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
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// or agreed to in writing, software, hardware and materials distributed under
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// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
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// CONDITIONS OF ANY KIND, either express or implied. See the License for the
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// specific language governing permissions and limitations under the License.
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// Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
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module sync_fifo #(
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parameter bit FALL_THROUGH = 1'b0, // fifo is in fall-through mode
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parameter int unsigned DATA_WIDTH = 32, // default data width if the fifo is of type logic
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parameter int unsigned DEPTH = 8, // depth can be arbitrary from 0 to 2**32
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parameter type dtype = logic [DATA_WIDTH-1:0],
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// DO NOT OVERWRITE THIS PARAMETER
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parameter int unsigned ADDR_DEPTH = (DEPTH > 1) ? $clog2(DEPTH) : 1
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)(
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input logic clk_i, // Clock
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input logic rst_ni, // Asynchronous reset active low
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input logic flush_i, // flush the queue
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input logic testmode_i, // test_mode to bypass clock gating
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// status flags
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output logic full_o, // queue is full
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output logic empty_o, // queue is empty
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output logic [ADDR_DEPTH-1:0] usage_o, // fill pointer
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// as long as the queue is not full we can push new data
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input dtype data_i, // data to push into the queue
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input logic push_i, // data is valid and can be pushed to the queue
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// as long as the queue is not empty we can pop new elements
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output dtype data_o, // output data
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input logic pop_i // pop head from queue
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);
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// local parameter
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// FIFO depth - handle the case of pass-through, synthesizer will do constant propagation
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localparam int unsigned FifoDepth = (DEPTH > 0) ? DEPTH : 1;
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// clock gating control
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logic gate_clock;
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// pointer to the read and write section of the queue
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logic [ADDR_DEPTH - 1:0] read_pointer_n, read_pointer_q, write_pointer_n, write_pointer_q;
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// keep a counter to keep track of the current queue status
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// this integer will be truncated by the synthesis tool
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logic [ADDR_DEPTH:0] status_cnt_n, status_cnt_q;
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// actual memory
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dtype [FifoDepth - 1:0] mem_n, mem_q;
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assign usage_o = status_cnt_q[ADDR_DEPTH-1:0];
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if (DEPTH == 0) begin : gen_pass_through
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assign empty_o = ~push_i;
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assign full_o = ~pop_i;
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end else begin : gen_fifo
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assign full_o = (status_cnt_q == FifoDepth[ADDR_DEPTH:0]);
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assign empty_o = (status_cnt_q == 0) & ~(FALL_THROUGH & push_i);
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end
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// status flags
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// read and write queue logic
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always_comb begin : read_write_comb
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// default assignment
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read_pointer_n = read_pointer_q;
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write_pointer_n = write_pointer_q;
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status_cnt_n = status_cnt_q;
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data_o = (DEPTH == 0) ? data_i : mem_q[read_pointer_q];
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mem_n = mem_q;
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gate_clock = 1'b1;
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// push a new element to the queue
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if (push_i && ~full_o) begin
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// push the data onto the queue
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mem_n[write_pointer_q] = data_i;
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// un-gate the clock, we want to write something
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gate_clock = 1'b0;
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// increment the write counter
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if (write_pointer_q == FifoDepth[ADDR_DEPTH-1:0] - 1)
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write_pointer_n = '0;
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else
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write_pointer_n = write_pointer_q + 1;
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// increment the overall counter
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status_cnt_n = status_cnt_q + 1;
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end
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if (pop_i && ~empty_o) begin
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// read from the queue is a default assignment
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// but increment the read pointer...
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if (read_pointer_n == FifoDepth[ADDR_DEPTH-1:0] - 1)
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read_pointer_n = '0;
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else
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read_pointer_n = read_pointer_q + 1;
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// ... and decrement the overall count
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status_cnt_n = status_cnt_q - 1;
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end
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// keep the count pointer stable if we push and pop at the same time
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if (push_i && pop_i && ~full_o && ~empty_o)
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status_cnt_n = status_cnt_q;
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// FIFO is in pass through mode -> do not change the pointers
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if (FALL_THROUGH && (status_cnt_q == 0) && push_i) begin
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data_o = data_i;
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if (pop_i) begin
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status_cnt_n = status_cnt_q;
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read_pointer_n = read_pointer_q;
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write_pointer_n = write_pointer_q;
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end
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end
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end
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// sequential process
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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read_pointer_q <= '0;
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write_pointer_q <= '0;
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status_cnt_q <= '0;
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end else begin
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if (flush_i) begin
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read_pointer_q <= '0;
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write_pointer_q <= '0;
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status_cnt_q <= '0;
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end else begin
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read_pointer_q <= read_pointer_n;
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write_pointer_q <= write_pointer_n;
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status_cnt_q <= status_cnt_n;
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end
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if(~rst_ni) begin
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mem_q <= '0;
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end else if (!gate_clock) begin
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mem_q <= mem_n;
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end
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end
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endmodule
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