rtl: add config for branch predictor

Signed-off-by: liangkangnan <liangkangnan@163.com>

rtl/core/exu.sv

@@ -17,8 +17,9 @@
 `include "defines.sv"
 
 // 执行模块
-module exu(
-
+module exu #(
+    parameter bit          BranchPredictor      = 1'b1
+    )(
     input wire clk,                         // 时钟
     input wire rst_n,                       // 复位
 
@@ -373,10 +374,16 @@ module exu(
 
     assign reg_we_o = commit_reg_we_o & (~int_stall_i);
 
-                       // jal
-    wire prdt_taken = ((~bjp_op_jalr_o) & bjp_op_jump_o) |
-                       // bxx & imm[31]
-                      (req_bjp_o & (~bjp_op_jump_o) & dec_imm_i[31]);
+    wire prdt_taken;
+
+    if (BranchPredictor) begin: g_branch_predictor
+                            // jal
+        assign prdt_taken = ((~bjp_op_jalr_o) & bjp_op_jump_o) |
+                            // bxx & imm[31]
+                            (req_bjp_o & (~bjp_op_jump_o) & dec_imm_i[31]);
+    end else begin: g_no_branch_predictor
+        assign prdt_taken = 1'b0;
+    end
 
     // bxx分支预测错误
     wire prdt_taken_error = prdt_taken & (~bjp_cmp_res_o) & req_bjp_o & (~bjp_op_jump_o);

rtl/core/ifu.sv

@@ -17,25 +17,29 @@
 `include "defines.sv"
 
 // 取指模块
-module ifu(
+module ifu #(
+    parameter bit          BranchPredictor      = 1'b1
+    )(
 
-    input wire clk,
-    input wire rst_n,
+    input wire                      clk,
+    input wire                      rst_n,
 
-    input wire flush_i,                        // 跳转标志
-    input wire[31:0] flush_addr_i,             // 跳转地址
-    input wire[`STALL_WIDTH-1:0] stall_i,      // 流水线暂停标志
-    input wire jtag_halt_i,
-    output wire[31:0] inst_o,
-    output wire[31:0] pc_o,
-    output wire inst_valid_o,
+    input wire                      flush_i,      // 冲刷标志
+    input wire[31:0]                flush_addr_i, // 冲刷地址
+    input wire[`STALL_WIDTH-1:0]    stall_i,      // 流水线暂停标志
 
-    output wire instr_req_o,
-    input wire instr_gnt_i,
-    input wire instr_rvalid_i,
-    output wire[31:0] instr_addr_o,
-    input wire[31:0] instr_rdata_i,
-    input wire instr_err_i
+    // to ifu_idu
+    output wire[31:0]               inst_o,
+    output wire[31:0]               pc_o,
+    output wire                     inst_valid_o,
+
+    // 指令总线信号
+    output wire                     instr_req_o,
+    input  wire                     instr_gnt_i,
+    input  wire                     instr_rvalid_i,
+    output wire[31:0]               instr_addr_o,
+    input  wire[31:0]               instr_rdata_i,
+    input  wire                     instr_err_i
 
     );
 
@@ -109,14 +113,19 @@ module ifu(
     assign instr_addr_o = {fetch_addr_d[31:2], 2'b00};
     assign pc_o = fetch_addr_q;
 
-    bpu u_bpu(
-        .clk(clk),
-        .rst_n(rst_n),
-        .inst_i(instr_rdata_i),
-        .inst_valid_i(inst_valid),
-        .pc_i(fetch_addr_q),
-        .prdt_taken_o(prdt_taken),
-        .prdt_addr_o(prdt_addr)
-    );
+    if (BranchPredictor) begin: g_branch_predictor
+        bpu u_bpu(
+            .clk(clk),
+            .rst_n(rst_n),
+            .inst_i(instr_rdata_i),
+            .inst_valid_i(inst_valid),
+            .pc_i(fetch_addr_q),
+            .prdt_taken_o(prdt_taken),
+            .prdt_addr_o(prdt_addr)
+        );
+    end else begin: g_no_branch_predictor
+        assign prdt_taken = 1'b0;
+        assign prdt_addr = 32'h0;
+    end
 
 endmodule

rtl/core/tinyriscv_core.sv

@@ -19,7 +19,8 @@
 // tinyriscv处理器核顶层模块
 module tinyriscv_core #(
     parameter int unsigned DEBUG_HALT_ADDR      = 32'h10000800,
-    parameter int unsigned DEBUG_EXCEPTION_ADDR = 32'h10000808
+    parameter int unsigned DEBUG_EXCEPTION_ADDR = 32'h10000808,
+    parameter bit          BranchPredictor      = 1'b1
     )(
 
     input wire clk,
@@ -147,7 +148,9 @@ module tinyriscv_core #(
     wire clint_int_assert_o;
 
 
-    ifu u_ifu(
+    ifu #(
+        .BranchPredictor(BranchPredictor)
+    ) u_ifu (
         .clk(clk),
         .rst_n(rst_n),
         .flush_addr_i(ctrl_flush_addr_o),
@@ -272,7 +275,9 @@ module tinyriscv_core #(
         .rd_we_o(ie_rd_we_o)
     );
 
-    exu u_exu(
+    exu #(
+        .BranchPredictor(BranchPredictor)
+    ) u_exu (
         .clk(clk),
         .rst_n(rst_n),
         .reg1_rdata_i(ie_rs1_rdata_o),