From 38c22452187b8a4381b41dccdeacc1d8adddef43 Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Wed, 27 May 2020 23:17:05 +0800 Subject: [PATCH] sim: remove tb file to tb dir Signed-off-by: liangkangnan --- sim/sim_default_nowave.bat | 2 +- sim/sim_new_nowave.bat | 2 +- tb/compliance_test/tinyriscv_soc_tb.v | 520 ++++++++++++++++++++++++++ {sim => tb}/tinyriscv_soc_tb.v | 0 4 files changed, 522 insertions(+), 2 deletions(-) create mode 100644 tb/compliance_test/tinyriscv_soc_tb.v rename {sim => tb}/tinyriscv_soc_tb.v (100%) diff --git a/sim/sim_default_nowave.bat b/sim/sim_default_nowave.bat index fc893f2..c9284f1 100644 --- a/sim/sim_default_nowave.bat +++ b/sim/sim_default_nowave.bat @@ -1,2 +1,2 @@ -iverilog -s tinyriscv_soc_tb -o out.vvp -I ..\rtl\core tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart_tx.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v +iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart_tx.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v vvp out.vvp diff --git a/sim/sim_new_nowave.bat b/sim/sim_new_nowave.bat index 864e3ea..5a88311 100644 --- a/sim/sim_new_nowave.bat +++ b/sim/sim_new_nowave.bat @@ -1,3 +1,3 @@ ..\tools\BinToMem_CLI.exe %1 %2 -iverilog -s tinyriscv_soc_tb -o out.vvp -I ..\rtl\core tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart_tx.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v +iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\perips\timer.v ..\rtl\perips\uart_tx.v ..\rtl\perips\gpio.v ..\rtl\soc\tinyriscv_soc_top.v vvp out.vvp diff --git a/tb/compliance_test/tinyriscv_soc_tb.v b/tb/compliance_test/tinyriscv_soc_tb.v new file mode 100644 index 0000000..2377561 --- /dev/null +++ b/tb/compliance_test/tinyriscv_soc_tb.v @@ -0,0 +1,520 @@ +`timescale 1 ns / 1 ps + +`include "defines.v" + + +`define TEST_PROG 1 +//`define TEST_JTAG 1 + + +// testbench module +module tinyriscv_soc_tb; + + reg clk; + reg rst; + + + always #10 clk = ~clk; // 50MHz + + wire[`RegBus] x3 = tinyriscv_soc_top_0.u_tinyriscv.u_regs.regs[3]; + wire[`RegBus] x26 = tinyriscv_soc_top_0.u_tinyriscv.u_regs.regs[26]; + wire[`RegBus] x27 = tinyriscv_soc_top_0.u_tinyriscv.u_regs.regs[27]; + + wire[31:0] ex_end_flag = tinyriscv_soc_top_0.u_ram._ram[4]; + wire[31:0] begin_signature = tinyriscv_soc_top_0.u_ram._ram[2]; + wire[31:0] end_signature = tinyriscv_soc_top_0.u_ram._ram[3]; + + integer r; + integer fd; + +`ifdef TEST_JTAG + reg TCK; + reg TMS; + reg TDI; + wire TDO; + + integer i; + reg[39:0] shift_reg; + reg in; + wire[39:0] req_data = tinyriscv_soc_top_0.u_jtag_top.u_jtag_driver.dtm_req_data; + wire[4:0] ir_reg = tinyriscv_soc_top_0.u_jtag_top.u_jtag_driver.ir_reg; + wire dtm_req_valid = tinyriscv_soc_top_0.u_jtag_top.u_jtag_driver.dtm_req_valid; + wire[31:0] dmstatus = tinyriscv_soc_top_0.u_jtag_top.u_jtag_dm.dmstatus; +`endif + + initial begin + clk = 0; + rst = `RstEnable; +`ifdef TEST_JTAG + TCK = 1; + TMS = 1; + TDI = 1; +`endif + $display("test running..."); + #40 + rst = `RstDisable; + #200 +/* +`ifdef TEST_PROG + wait(x26 == 32'b1) // wait sim end, when x26 == 1 + #100 + if (x27 == 32'b1) begin + $display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~"); + $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); + $display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~"); + $display("~~~~~~~~~ # # # # # # ~~~~~~~~~"); + $display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~"); + $display("~~~~~~~~~ ##### ###### # #~~~~~~~~~"); + $display("~~~~~~~~~ # # # # # # #~~~~~~~~~"); + $display("~~~~~~~~~ # # # #### #### ~~~~~~~~~"); + $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); + end else begin + $display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~"); + $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); + $display("~~~~~~~~~~###### ## # # ~~~~~~~~~~"); + $display("~~~~~~~~~~# # # # # ~~~~~~~~~~"); + $display("~~~~~~~~~~##### # # # # ~~~~~~~~~~"); + $display("~~~~~~~~~~# ###### # # ~~~~~~~~~~"); + $display("~~~~~~~~~~# # # # # ~~~~~~~~~~"); + $display("~~~~~~~~~~# # # # ######~~~~~~~~~~"); + $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); + $display("fail testnum = %2d", x3); + for (r = 0; r < 32; r = r + 1) + $display("x%2d = 0x%x", r, tinyriscv_soc_top_0.u_tinyriscv.u_regs.regs[r]); + end +`endif +*/ + + wait(ex_end_flag == 32'h1); // wait sim end + + fd = $fopen(`OUTPUT); // OUTPUT的值在命令行里定义 + for (r = begin_signature; r < end_signature; r = r + 4) begin + $fdisplay(fd, "%x", tinyriscv_soc_top_0.u_rom._rom[r[31:2]]); + end + $fclose(fd); + +`ifdef TEST_JTAG + // reset + for (i = 0; i < 8; i++) begin + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + end + + // IR + shift_reg = 40'b10001; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SELECT-DR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SELECT-IR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // CAPTURE-IR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SHIFT-IR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SHIFT-IR & EXIT1-IR + for (i = 5; i > 0; i--) begin + if (shift_reg[0] == 1'b1) + TDI = 1'b1; + else + TDI = 1'b0; + + if (i == 1) + TMS = 1; + + TCK = 0; + #100 + in = TDO; + TCK = 1; + #100 + TCK = 0; + + shift_reg = {{(35){1'b0}}, in, shift_reg[4:1]}; + end + + // PAUSE-IR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // EXIT2-IR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // UPDATE-IR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // dmi write + shift_reg = {6'h10, {(32){1'b0}}, 2'b10}; + + // SELECT-DR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // CAPTURE-DR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SHIFT-DR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SHIFT-DR & EXIT1-DR + for (i = 40; i > 0; i--) begin + if (shift_reg[0] == 1'b1) + TDI = 1'b1; + else + TDI = 1'b0; + + if (i == 1) + TMS = 1; + + TCK = 0; + #100 + in = TDO; + TCK = 1; + #100 + TCK = 0; + + shift_reg = {in, shift_reg[39:1]}; + end + + // PAUSE-DR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // EXIT2-DR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // UPDATE-DR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + $display("ir_reg = 0x%x", ir_reg); + $display("dtm_req_valid = %d", dtm_req_valid); + $display("req_data = 0x%x", req_data); + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + $display("dmstatus = 0x%x", dmstatus); + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SELECT-DR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // dmi read + shift_reg = {6'h11, {(32){1'b0}}, 2'b01}; + + // CAPTURE-DR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SHIFT-DR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SHIFT-DR & EXIT1-DR + for (i = 40; i > 0; i--) begin + if (shift_reg[0] == 1'b1) + TDI = 1'b1; + else + TDI = 1'b0; + + if (i == 1) + TMS = 1; + + TCK = 0; + #100 + in = TDO; + TCK = 1; + #100 + TCK = 0; + + shift_reg = {in, shift_reg[39:1]}; + end + + // PAUSE-DR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // EXIT2-DR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // UPDATE-DR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // IDLE + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SELECT-DR + TMS = 1; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // dmi read + shift_reg = {6'h11, {(32){1'b0}}, 2'b00}; + + // CAPTURE-DR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SHIFT-DR + TMS = 0; + TCK = 0; + #100 + TCK = 1; + #100 + TCK = 0; + + // SHIFT-DR & EXIT1-DR + for (i = 40; i > 0; i--) begin + if (shift_reg[0] == 1'b1) + TDI = 1'b1; + else + TDI = 1'b0; + + if (i == 1) + TMS = 1; + + TCK = 0; + #100 + in = TDO; + TCK = 1; + #100 + TCK = 0; + + shift_reg = {in, shift_reg[39:1]}; + end + + #100 + + $display("shift_reg = 0x%x", shift_reg[33:2]); +`endif + + $finish; + end + + // sim timeout + initial begin + #500000 + $display("Time Out."); + $finish; + end + + // read mem data + initial begin + $readmemh ("inst.data", tinyriscv_soc_top_0.u_rom._rom); + end + + // generate wave file, used by gtkwave + initial begin + $dumpfile("tinyriscv_soc_tb.vcd"); + $dumpvars(0, tinyriscv_soc_tb); + end + + tinyriscv_soc_top tinyriscv_soc_top_0( + .clk(clk), + .rst(rst)/* + .jtag_TCK(TCK), + .jtag_TMS(TMS), + .jtag_TDI(TDI), + .jtag_TDO(TDO)*/ + ); + +endmodule diff --git a/sim/tinyriscv_soc_tb.v b/tb/tinyriscv_soc_tb.v similarity index 100% rename from sim/tinyriscv_soc_tb.v rename to tb/tinyriscv_soc_tb.v