tests: example: support sync interrupt handle

Signed-off-by: liangkangnan <liangkangnan@163.com>

tests/example/common.mk

@@ -16,6 +16,7 @@ all: $(TARGET)
 ASM_SRCS += $(COMMON_DIR)/start.S
 ASM_SRCS += $(COMMON_DIR)/trap_entry.S
 C_SRCS += $(COMMON_DIR)/init.c
+C_SRCS += $(COMMON_DIR)/trap_handler.c
 C_SRCS += $(COMMON_DIR)/lib/utils.c
 C_SRCS += $(COMMON_DIR)/lib/xprintf.c
 C_SRCS += $(COMMON_DIR)/lib/uart.c

tests/example/init.c

@@ -5,14 +5,6 @@
 
 extern void trap_entry();
 
-extern void timer0_irq_handler() __attribute__((weak));
-
-
-void trap_handler(uint32_t mcause)
-{
-    // we have only timer0 interrupt here
-    timer0_irq_handler();
-}
 
 void _init()
 {

tests/example/trap_entry.S

@@ -45,8 +45,19 @@ trap_entry:
     STORE x31, 31*REGBYTES(sp)
 
     csrr a0, mcause
-    call trap_handler
+    csrr a1, mepc
+test_if_asynchronous:
+	srli a2, a0, 31		                /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
+	beq a2, x0, handle_synchronous		/* Branch past interrupt handing if not asynchronous. */
 
+    call trap_handler
+    j asynchronous_return
+
+handle_synchronous:
+    addi a1, a1, 4
+    csrw mepc, a1
+
+asynchronous_return:
     LOAD x1, 1*REGBYTES(sp)
     LOAD x2, 2*REGBYTES(sp)
     LOAD x3, 3*REGBYTES(sp)

tests/example/trap_handler.c

@@ -0,0 +1,11 @@
+#include <stdint.h>
+
+
+extern void timer0_irq_handler() __attribute__((weak));
+
+
+void trap_handler(uint32_t mcause, uint32_t mepc)
+{
+    // we have only timer0 interrupt here
+    timer0_irq_handler();
+}