rtl: utils: add full handshake CDC source
Signed-off-by: liangkangnan <liangkangnan@163.com>pull/1/head
liangkangnan
parent
386ba909ba
commit
4876225f60
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@ -0,0 +1,128 @@
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/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// 数据接收端模块
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// 跨时钟域传输，全(四次)握手协议
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// req = 1
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// ack_o = 1
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// req = 0
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// ack_o = 0
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module full_handshake_rx #(
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parameter DW = 32)( // RX要接收数据的位宽
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input wire clk, // RX端时钟信号
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input wire rst_n, // RX端复位信号
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// from tx
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input wire req_i, // TX端请求信号
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input wire[DW-1:0] req_data_i, // TX端输入数据
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// to tx
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output wire ack_o, // RX端应答TX端信号
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// to rx
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output wire[DW-1:0] recv_data_o,// RX端接收到的数据
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output wire recv_rdy_o // RX端是否接收到数据信号
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);
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localparam STATE_IDLE = 2'b01;
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localparam STATE_DEASSERT = 2'b10;
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reg[1:0] state;
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reg[1:0] state_next;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= STATE_IDLE;
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end else begin
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state <= state_next;
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end
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end
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always @ (*) begin
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case (state)
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// 等待TX请求信号req=1
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STATE_IDLE: begin
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if (req == 1'b1) begin
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state_next = STATE_DEASSERT;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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// 等待req=0
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STATE_DEASSERT: begin
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if (req) begin
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state_next = STATE_DEASSERT;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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default: begin
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state_next = STATE_IDLE;
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end
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endcase
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end
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reg req_d;
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reg req;
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// 将请求信号打两拍进行同步
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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req_d <= 1'b0;
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req <= 1'b0;
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end else begin
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req_d <= req_i;
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req <= req_d;
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end
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end
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reg[DW-1:0] recv_data;
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reg recv_rdy;
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reg ack;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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ack <= 1'b0;
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recv_rdy <= 1'b0;
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recv_data <= {(DW){1'b0}};
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end else begin
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case (state)
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STATE_IDLE: begin
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if (req == 1'b1) begin
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ack <= 1'b1;
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recv_rdy <= 1'b1; // 这个信号只会持续一个时钟
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recv_data <= req_data_i; // 这个信号只会持续一个时钟
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end
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end
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STATE_DEASSERT: begin
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recv_rdy <= 1'b0;
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recv_data <= {(DW){1'b0}};
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// req撤销后ack也撤销
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if (req == 1'b0) begin
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ack <= 1'b0;
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end
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end
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endcase
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end
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end
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assign ack_o = ack;
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assign recv_rdy_o = recv_rdy;
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assign recv_data_o = recv_data;
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endmodule
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@ -0,0 +1,147 @@
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/*
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Copyright 2020 Blue Liang, liangkangnan@163.com
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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// 数据发送端模块
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// 跨时钟域传输，全(四次)握手协议
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// req_o = 1
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// ack = 1
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// req_o = 0
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// ack = 0
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module full_handshake_tx #(
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parameter DW = 32)( // TX要发送数据的位宽
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input wire clk, // TX端时钟信号
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input wire rst_n, // TX端复位信号
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// from rx
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input wire ack_i, // RX端应答信号
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// from tx
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input wire req_i, // TX端请求信号，只需持续一个时钟
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input wire[DW-1:0] req_data_i, // TX端要发送的数据，只需持续一个时钟
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// to tx
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output wire idle_o, // TX端是否空闲信号，空闲才能发数据
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// to rx
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output wire req_o, // TX端请求信号
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output wire[DW-1:0] req_data_o // TX端要发送的数据
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);
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localparam STATE_IDLE = 3'b001;
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localparam STATE_ASSERT = 3'b010;
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localparam STATE_DEASSERT = 3'b100;
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reg[2:0] state;
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reg[2:0] state_next;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= STATE_IDLE;
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end else begin
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state <= state_next;
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end
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end
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always @ (*) begin
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case (state)
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STATE_IDLE: begin
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if (req_i == 1'b1) begin
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state_next = STATE_ASSERT;
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end else begin
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state_next = STATE_IDLE;
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end
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end
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// 等待ack=1
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STATE_ASSERT: begin
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if (!ack) begin
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state_next = STATE_ASSERT;
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end else begin
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state_next = STATE_DEASSERT;
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end
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end
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// 等待ack=0
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STATE_DEASSERT: begin
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if (!ack) begin
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state_next = STATE_IDLE;
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end else begin
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state_next = STATE_DEASSERT;
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end
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end
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default: begin
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state_next = STATE_IDLE;
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end
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endcase
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end
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reg ack_d;
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reg ack;
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// 将应答信号打两拍进行同步
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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ack_d <= 1'b0;
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ack <= 1'b0;
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end else begin
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ack_d <= ack_i;
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ack <= ack_d;
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end
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end
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reg req;
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reg[DW-1:0] req_data;
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reg idle;
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always @ (posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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idle <= 1'b1;
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req <= 1'b0;
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req_data <= {(DW){1'b0}};
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end else begin
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case (state)
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// 锁存TX请求数据，在收到ack之前一直保持有效
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STATE_IDLE: begin
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if (req_i == 1'b1) begin
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idle <= 1'b0;
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req <= req_i;
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req_data <= req_data_i;
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end else begin
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idle <= 1'b1;
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req <= 1'b0;
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end
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end
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// 收到RX的ack之后撤销TX请求
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STATE_ASSERT: begin
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if (ack == 1'b1) begin
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req <= 1'b0;
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req_data <= {(DW){1'b0}};
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end
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end
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STATE_DEASSERT: begin
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if (!ack) begin
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idle <= 1'b1;
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end
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end
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endcase
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end
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end
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assign idle_o = idle;
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assign req_o = req;
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assign req_data_o = req_data;
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endmodule
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@ -1,2 +1,2 @@
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iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\utils\gen_dff.v ..\rtl\utils\gen_buf.v ..\rtl\soc\tinyriscv_soc_top.v
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iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\utils\gen_dff.v ..\rtl\utils\gen_buf.v ..\rtl\utils\full_handshake_rx.v ..\rtl\utils\full_handshake_tx.v ..\rtl\soc\tinyriscv_soc_top.v
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vvp out.vvp
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@ -1,3 +1,3 @@
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..\tools\BinToMem_CLI.exe %1 %2
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iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\utils\gen_dff.v ..\rtl\utils\gen_buf.v ..\rtl\soc\tinyriscv_soc_top.v
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iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\utils\gen_dff.v ..\rtl\utils\gen_buf.v ..\rtl\utils\full_handshake_rx.v ..\rtl\utils\full_handshake_tx.v ..\rtl\soc\tinyriscv_soc_top.v
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vvp out.vvp
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