fpga: xilinx: cmod_a7: add bin.tcl and mcs.tcl

Signed-off-by: liangkangnan <liangkangnan@163.com>

fpga/xilinx/cmod_a7/Makefile

@@ -1,22 +1,30 @@
-VIVADO_BASE := /home/ubuntu/Xilinx/Vivado/2018.1/bin
-VIVADO := $(VIVADO_BASE)/vivado
-
-VIVADOFLAGS := \
-	-nojournal -mode batch \
-	-source scripts/init.tcl
-
-.PHONY: synth
-synth:
-	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl
-
-.PHONY: impl
-impl:
-	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl
-
-.PHONY: bit
-bit:
-	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit_stream.tcl -source scripts/report.tcl
-
-.PHONY: clean
-clean::
-	rm -rf .Xil .ip_user_files *.log *.jou out usage_statistics_webtalk.xml usage_statistics_webtalk.html
+VIVADO_BASE := /home/ubuntu/Xilinx/Vivado/2018.1/bin
+VIVADO := $(VIVADO_BASE)/vivado
+
+VIVADOFLAGS := \
+	-nojournal -mode batch \
+	-source scripts/init.tcl
+
+.PHONY: synth
+synth:
+	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl
+
+.PHONY: impl
+impl:
+	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl
+
+.PHONY: bit
+bit:
+	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit.tcl -source scripts/report.tcl
+
+.PHONY: bin
+bin:
+	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit.tcl -source scripts/bin.tcl -source scripts/report.tcl
+
+.PHONY: mcs
+mcs:
+	$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit.tcl -source scripts/mcs.tcl -source scripts/report.tcl
+
+.PHONY: clean
+clean::
+	rm -rf .Xil .ip_user_files *.log *.jou out usage_statistics_webtalk.xml usage_statistics_webtalk.html

fpga/xilinx/cmod_a7/scripts/bin.tcl

@@ -0,0 +1 @@
+write_cfgmem  -format bin -size 4 -interface SPIx4 -loadbit {up 0x00000000 "out/tinyriscv_soc_top.bit" } -force -file "out/tinyriscv_soc_top.bin"

fpga/xilinx/cmod_a7/scripts/bit.tcl

@@ -1 +1 @@
-write_bitstream -force [file join $outdir "${top_module}.bit"]
+write_bitstream -force [file join $outdir "${top_module}.bit"]

fpga/xilinx/cmod_a7/scripts/init.tcl

@@ -41,6 +41,3 @@ add_files -norecurse -fileset constrs_1 [glob -directory $constrsdir {*.xdc}]
 
 # 创建输出目录
 file mkdir $outdir
-
-# 综合
-synth_design -top $top_module

fpga/xilinx/cmod_a7/scripts/mcs.tcl

@@ -0,0 +1 @@
+write_cfgmem  -format mcs -size 4 -interface SPIx4 -loadbit {up 0x00000000 "out/tinyriscv_soc_top.bit" } -force -file "out/tinyriscv_soc_top.mcs"