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fpga: xilinx: cmod_a7: add bin.tcl and mcs.tcl 

Signed-off-by: liangkangnan <liangkangnan@163.com>
verilator
liangkangnan 2022-08-12 19:33:49 +08:00
parent 4c16dfb254
commit 490c52054b
5 changed files with 33 additions and 26 deletions
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10
fpga/xilinx/cmod_a7/Makefile
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@ -15,7 +15,15 @@ impl:
.PHONY: bit
bit:
$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit_stream.tcl -source scripts/report.tcl
$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit.tcl -source scripts/report.tcl
.PHONY: bin
bin:
$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit.tcl -source scripts/bin.tcl -source scripts/report.tcl
.PHONY: mcs
mcs:
$(VIVADO) $(VIVADOFLAGS) -source scripts/synth.tcl -source scripts/impl.tcl -source scripts/bit.tcl -source scripts/mcs.tcl -source scripts/report.tcl
.PHONY: clean
clean::

1
fpga/xilinx/cmod_a7/scripts/bin.tcl Normal file
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@ -0,0 +1 @@
write_cfgmem -format bin -size 4 -interface SPIx4 -loadbit {up 0x00000000 "out/tinyriscv_soc_top.bit" } -force -file "out/tinyriscv_soc_top.bin"

0
fpga/xilinx/cmod_a7/scripts/bit_stream.tcl → fpga/xilinx/cmod_a7/scripts/bit.tcl
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3
fpga/xilinx/cmod_a7/scripts/init.tcl
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@ -41,6 +41,3 @@ add_files -norecurse -fileset constrs_1 [glob -directory $constrsdir {*.xdc}]
# 创建输出目录
file mkdir $outdir
# 综合
synth_design -top $top_module

1
fpga/xilinx/cmod_a7/scripts/mcs.tcl
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@ -0,0 +1 @@
write_cfgmem -format mcs -size 4 -interface SPIx4 -loadbit {up 0x00000000 "out/tinyriscv_soc_top.bit" } -force -file "out/tinyriscv_soc_top.mcs"