From 519ef32ae7f75bc8675fb7198788e163eefd3218 Mon Sep 17 00:00:00 2001 From: liangkangnan Date: Fri, 10 Sep 2021 09:56:21 +0800 Subject: [PATCH] sdk: adapt to more perips Signed-off-by: liangkangnan --- sdk/bsp/bsp.mk | 2 + sdk/bsp/include/gpio.h | 78 ++++++------ sdk/bsp/include/i2c.h | 5 +- sdk/bsp/include/pinmux.h | 201 ++++++++++++++++++++++++++++++ sdk/bsp/include/timer.h | 116 +++++++++-------- sdk/bsp/include/uart.h | 8 +- sdk/bsp/lib/gpio.c | 12 +- sdk/bsp/lib/pinmux.c | 100 +++++++++++++++ sdk/bsp/trap_entry.S | 60 +++++++++ sdk/examples/gpio/main.c | 37 ++++-- sdk/examples/hello_world/main.c | 4 +- sdk/examples/i2c_master/main.c | 5 + sdk/examples/uart_loopback/main.c | 4 +- 13 files changed, 517 insertions(+), 115 deletions(-) create mode 100644 sdk/bsp/include/pinmux.h create mode 100644 sdk/bsp/lib/pinmux.c diff --git a/sdk/bsp/bsp.mk b/sdk/bsp/bsp.mk index b3f66a1..1b1f772 100644 --- a/sdk/bsp/bsp.mk +++ b/sdk/bsp/bsp.mk @@ -26,6 +26,8 @@ C_SRCS += $(BSP_DIR)/lib/timer.c C_SRCS += $(BSP_DIR)/lib/gpio.c C_SRCS += $(BSP_DIR)/lib/rvic.c C_SRCS += $(BSP_DIR)/lib/i2c.c +C_SRCS += $(BSP_DIR)/lib/spi.c +C_SRCS += $(BSP_DIR)/lib/pinmux.c LINKER_SCRIPT := $(BSP_DIR)/link.lds diff --git a/sdk/bsp/include/gpio.h b/sdk/bsp/include/gpio.h index ab9a1c4..7b74c5b 100644 --- a/sdk/bsp/include/gpio.h +++ b/sdk/bsp/include/gpio.h @@ -16,7 +16,7 @@ extern "C" { // Register width #define GPIO_PARAM_REG_WIDTH 32 -#define GPIO_BASE_ADDR (0x30000000) +#define GPIO_BASE_ADDR (0x03000000) #define GPIO_REG(offset) (*((volatile uint32_t *)(GPIO_BASE_ADDR + offset))) typedef enum { @@ -41,44 +41,16 @@ typedef enum { GPIO5, GPIO6, GPIO7, + GPIO8, + GPIO9, + GPIO10, + GPIO11, + GPIO12, + GPIO13, + GPIO14, + GPIO15, } gpio_e; -// gpio mode register -#define GPIO_MODE_REG_OFFSET 0x0 -#define GPIO_MODE_REG_RESVAL 0x0 -#define GPIO_MODE_GPIO_MASK 0xffff -#define GPIO_MODE_GPIO_OFFSET 0 -#define GPIO_MODE_GPIO_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_MODE_GPIO_MASK, .index = GPIO_MODE_GPIO_OFFSET }) - -// gpio interrupt register -#define GPIO_INTR_REG_OFFSET 0x4 -#define GPIO_INTR_REG_RESVAL 0x0 -#define GPIO_INTR_GPIO_INT_MASK 0xffff -#define GPIO_INTR_GPIO_INT_OFFSET 0 -#define GPIO_INTR_GPIO_INT_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_INTR_GPIO_INT_MASK, .index = GPIO_INTR_GPIO_INT_OFFSET }) -#define GPIO_INTR_GPIO_PENDING_MASK 0xff -#define GPIO_INTR_GPIO_PENDING_OFFSET 16 -#define GPIO_INTR_GPIO_PENDING_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_INTR_GPIO_PENDING_MASK, .index = GPIO_INTR_GPIO_PENDING_OFFSET }) - -// gpio data register -#define GPIO_DATA_REG_OFFSET 0x8 -#define GPIO_DATA_REG_RESVAL 0x0 -#define GPIO_DATA_GPIO_MASK 0xff -#define GPIO_DATA_GPIO_OFFSET 0 -#define GPIO_DATA_GPIO_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_DATA_GPIO_MASK, .index = GPIO_DATA_GPIO_OFFSET }) - -// gpio input filter enable register -#define GPIO_FILTER_REG_OFFSET 0xc -#define GPIO_FILTER_REG_RESVAL 0x0 -#define GPIO_FILTER_GPIO_MASK 0xff -#define GPIO_FILTER_GPIO_OFFSET 0 -#define GPIO_FILTER_GPIO_FIELD \ - ((bitfield_field32_t) { .mask = GPIO_FILTER_GPIO_MASK, .index = GPIO_FILTER_GPIO_OFFSET }) - void gpio_set_mode(gpio_e gpio, gpio_mode_e mode); uint8_t gpio_get_input_data(gpio_e gpio); void gpio_set_output_data(gpio_e gpio, uint8_t data); @@ -88,6 +60,38 @@ void gpio_set_interrupt_mode(gpio_e gpio, gpio_intr_mode_e mode); void gpio_clear_intr_pending(gpio_e gpio); uint8_t gpio_get_intr_pending(gpio_e gpio); +// gpio input/output mode register +#define GPIO_IO_MODE_REG_OFFSET 0x0 +#define GPIO_IO_MODE_REG_RESVAL 0x0 + +// gpio interrupt mode register +#define GPIO_INT_MODE_REG_OFFSET 0x4 +#define GPIO_INT_MODE_REG_RESVAL 0x0 + +// gpio interrupt pending register +#define GPIO_INT_PENDING_REG_OFFSET 0x8 +#define GPIO_INT_PENDING_REG_RESVAL 0x0 +#define GPIO_INT_PENDING_GPIO_INT_PENDING_MASK 0xffff +#define GPIO_INT_PENDING_GPIO_INT_PENDING_OFFSET 0 +#define GPIO_INT_PENDING_GPIO_INT_PENDING_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_INT_PENDING_GPIO_INT_PENDING_MASK, .index = GPIO_INT_PENDING_GPIO_INT_PENDING_OFFSET }) + +// gpio data register +#define GPIO_DATA_REG_OFFSET 0xc +#define GPIO_DATA_REG_RESVAL 0x0 +#define GPIO_DATA_DATA_MASK 0xffff +#define GPIO_DATA_DATA_OFFSET 0 +#define GPIO_DATA_DATA_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_DATA_DATA_MASK, .index = GPIO_DATA_DATA_OFFSET }) + +// gpio input filter enable register +#define GPIO_FILTER_REG_OFFSET 0x10 +#define GPIO_FILTER_REG_RESVAL 0x0 +#define GPIO_FILTER_FILTER_MASK 0xffff +#define GPIO_FILTER_FILTER_OFFSET 0 +#define GPIO_FILTER_FILTER_FIELD \ + ((bitfield_field32_t) { .mask = GPIO_FILTER_FILTER_MASK, .index = GPIO_FILTER_FILTER_OFFSET }) + #ifdef __cplusplus } // extern "C" #endif diff --git a/sdk/bsp/include/i2c.h b/sdk/bsp/include/i2c.h index f6248b7..ea5d1ff 100644 --- a/sdk/bsp/include/i2c.h +++ b/sdk/bsp/include/i2c.h @@ -16,9 +16,12 @@ extern "C" { // Register width #define I2C_PARAM_REG_WIDTH 32 -#define I2C0_BASE_ADDR (0x60000000) +#define I2C0_BASE_ADDR (0x06000000) #define I2C0_REG(offset) (*((volatile uint32_t *)(I2C0_BASE_ADDR + offset))) +#define I2C1_BASE_ADDR (0x0B000000) +#define I2C1_REG(offset) (*((volatile uint32_t *)(I2C1_BASE_ADDR + offset))) + typedef enum { I2C_MODE_MASTER = 0, I2C_MODE_SLAVE diff --git a/sdk/bsp/include/pinmux.h b/sdk/bsp/include/pinmux.h new file mode 100644 index 0000000..aa9f807 --- /dev/null +++ b/sdk/bsp/include/pinmux.h @@ -0,0 +1,201 @@ +// Generated register defines for pinmux + +// Copyright information found in source file: +// Copyright lowRISC contributors. + +// Licensing information found in source file: +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef _PINMUX_REG_DEFS_ +#define _PINMUX_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Register width +#define PINMUX_PARAM_REG_WIDTH 32 + +#define PINMUX_BASE_ADDR (0x08000000) +#define PINMUX_REG(offset) (*((volatile uint32_t *)(PINMUX_BASE_ADDR + offset))) + +typedef enum { + IO0_GPIO0 = 0x0, + IO0_UART0_TX, + IO0_UART0_RX, +} pinmux_io0_e; + +typedef enum { + IO1_GPIO1 = 0x0, + IO1_UART1_TX, + IO1_UART1_RX, +} pinmux_io1_e; + +typedef enum { + IO2_GPIO2 = 0x0, + IO2_UART2_TX, + IO2_UART2_RX, +} pinmux_io2_e; + +typedef enum { + IO3_GPIO3 = 0x0, + IO3_UART0_TX, + IO3_UART0_RX, +} pinmux_io3_e; + +typedef enum { + IO4_GPIO4 = 0x0, + IO4_UART1_TX, + IO4_UART1_RX, +} pinmux_io4_e; + +typedef enum { + IO5_GPIO5 = 0x0, + IO5_UART2_TX, + IO5_UART2_RX, +} pinmux_io5_e; + +typedef enum { + IO6_GPIO6 = 0x0, + IO6_I2C0_SCL, + IO6_I2C0_SDA, +} pinmux_io6_e; + +typedef enum { + IO7_GPIO7 = 0x0, + IO7_I2C1_SCL, + IO7_I2C1_SDA, +} pinmux_io7_e; + +typedef enum { + IO8_GPIO8 = 0x0, + IO8_I2C0_SCL, + IO8_I2C0_SDA, +} pinmux_io8_e; + +typedef enum { + IO9_GPIO9 = 0x0, + IO9_I2C1_SCL, + IO9_I2C1_SDA, +} pinmux_io9_e; + +typedef enum { + IO10_GPIO10 = 0x0, + IO10_SPI_CLK, +} pinmux_io10_e; + +typedef enum { + IO11_GPIO11 = 0x0, + IO11_SPI_SS, +} pinmux_io11_e; + +typedef enum { + IO12_GPIO12 = 0x0, + IO12_SPI_DQ0, +} pinmux_io12_e; + +typedef enum { + IO13_GPIO13 = 0x0, + IO13_SPI_DQ1, +} pinmux_io13_e; + +typedef enum { + IO14_GPIO14 = 0x0, + IO14_SPI_DQ2, +} pinmux_io14_e; + +typedef enum { + IO15_GPIO15 = 0x0, + IO15_SPI_DQ3, +} pinmux_io15_e; + +void pinmux_set_io0_func(pinmux_io0_e func); +void pinmux_set_io1_func(pinmux_io1_e func); +void pinmux_set_io2_func(pinmux_io2_e func); +void pinmux_set_io3_func(pinmux_io3_e func); +void pinmux_set_io4_func(pinmux_io4_e func); +void pinmux_set_io5_func(pinmux_io5_e func); +void pinmux_set_io6_func(pinmux_io6_e func); +void pinmux_set_io7_func(pinmux_io7_e func); +void pinmux_set_io8_func(pinmux_io8_e func); +void pinmux_set_io9_func(pinmux_io9_e func); +void pinmux_set_io10_func(pinmux_io10_e func); +void pinmux_set_io11_func(pinmux_io11_e func); +void pinmux_set_io12_func(pinmux_io12_e func); +void pinmux_set_io13_func(pinmux_io13_e func); +void pinmux_set_io14_func(pinmux_io14_e func); +void pinmux_set_io15_func(pinmux_io15_e func); + +// Pinmux control register +#define PINMUX_CTRL_REG_OFFSET 0x0 +#define PINMUX_CTRL_REG_RESVAL 0x0 +#define PINMUX_CTRL_IO0_MUX_MASK 0x3 +#define PINMUX_CTRL_IO0_MUX_OFFSET 0 +#define PINMUX_CTRL_IO0_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO0_MUX_MASK, .index = PINMUX_CTRL_IO0_MUX_OFFSET }) +#define PINMUX_CTRL_IO1_MUX_MASK 0x3 +#define PINMUX_CTRL_IO1_MUX_OFFSET 2 +#define PINMUX_CTRL_IO1_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO1_MUX_MASK, .index = PINMUX_CTRL_IO1_MUX_OFFSET }) +#define PINMUX_CTRL_IO2_MUX_MASK 0x3 +#define PINMUX_CTRL_IO2_MUX_OFFSET 4 +#define PINMUX_CTRL_IO2_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO2_MUX_MASK, .index = PINMUX_CTRL_IO2_MUX_OFFSET }) +#define PINMUX_CTRL_IO3_MUX_MASK 0x3 +#define PINMUX_CTRL_IO3_MUX_OFFSET 6 +#define PINMUX_CTRL_IO3_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO3_MUX_MASK, .index = PINMUX_CTRL_IO3_MUX_OFFSET }) +#define PINMUX_CTRL_IO4_MUX_MASK 0x3 +#define PINMUX_CTRL_IO4_MUX_OFFSET 8 +#define PINMUX_CTRL_IO4_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO4_MUX_MASK, .index = PINMUX_CTRL_IO4_MUX_OFFSET }) +#define PINMUX_CTRL_IO5_MUX_MASK 0x3 +#define PINMUX_CTRL_IO5_MUX_OFFSET 10 +#define PINMUX_CTRL_IO5_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO5_MUX_MASK, .index = PINMUX_CTRL_IO5_MUX_OFFSET }) +#define PINMUX_CTRL_IO6_MUX_MASK 0x3 +#define PINMUX_CTRL_IO6_MUX_OFFSET 12 +#define PINMUX_CTRL_IO6_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO6_MUX_MASK, .index = PINMUX_CTRL_IO6_MUX_OFFSET }) +#define PINMUX_CTRL_IO7_MUX_MASK 0x3 +#define PINMUX_CTRL_IO7_MUX_OFFSET 14 +#define PINMUX_CTRL_IO7_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO7_MUX_MASK, .index = PINMUX_CTRL_IO7_MUX_OFFSET }) +#define PINMUX_CTRL_IO8_MUX_MASK 0x3 +#define PINMUX_CTRL_IO8_MUX_OFFSET 16 +#define PINMUX_CTRL_IO8_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO8_MUX_MASK, .index = PINMUX_CTRL_IO8_MUX_OFFSET }) +#define PINMUX_CTRL_IO9_MUX_MASK 0x3 +#define PINMUX_CTRL_IO9_MUX_OFFSET 18 +#define PINMUX_CTRL_IO9_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO9_MUX_MASK, .index = PINMUX_CTRL_IO9_MUX_OFFSET }) +#define PINMUX_CTRL_IO10_MUX_MASK 0x3 +#define PINMUX_CTRL_IO10_MUX_OFFSET 20 +#define PINMUX_CTRL_IO10_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO10_MUX_MASK, .index = PINMUX_CTRL_IO10_MUX_OFFSET }) +#define PINMUX_CTRL_IO11_MUX_MASK 0x3 +#define PINMUX_CTRL_IO11_MUX_OFFSET 22 +#define PINMUX_CTRL_IO11_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO11_MUX_MASK, .index = PINMUX_CTRL_IO11_MUX_OFFSET }) +#define PINMUX_CTRL_IO12_MUX_MASK 0x3 +#define PINMUX_CTRL_IO12_MUX_OFFSET 24 +#define PINMUX_CTRL_IO12_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO12_MUX_MASK, .index = PINMUX_CTRL_IO12_MUX_OFFSET }) +#define PINMUX_CTRL_IO13_MUX_MASK 0x3 +#define PINMUX_CTRL_IO13_MUX_OFFSET 26 +#define PINMUX_CTRL_IO13_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO13_MUX_MASK, .index = PINMUX_CTRL_IO13_MUX_OFFSET }) +#define PINMUX_CTRL_IO14_MUX_MASK 0x3 +#define PINMUX_CTRL_IO14_MUX_OFFSET 28 +#define PINMUX_CTRL_IO14_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO14_MUX_MASK, .index = PINMUX_CTRL_IO14_MUX_OFFSET }) +#define PINMUX_CTRL_IO15_MUX_MASK 0x3 +#define PINMUX_CTRL_IO15_MUX_OFFSET 30 +#define PINMUX_CTRL_IO15_MUX_FIELD \ + ((bitfield_field32_t) { .mask = PINMUX_CTRL_IO15_MUX_MASK, .index = PINMUX_CTRL_IO15_MUX_OFFSET }) + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _PINMUX_REG_DEFS_ +// End generated register defines for pinmux \ No newline at end of file diff --git a/sdk/bsp/include/timer.h b/sdk/bsp/include/timer.h index 1e3cad6..3aaf5a1 100644 --- a/sdk/bsp/include/timer.h +++ b/sdk/bsp/include/timer.h @@ -1,56 +1,62 @@ -// Generated register defines for timer - -// Copyright information found in source file: -// Copyright lowRISC contributors. - -// Licensing information found in source file: -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -#ifndef _TIMER_REG_DEFS_ -#define _TIMER_REG_DEFS_ - -#ifdef __cplusplus -extern "C" { -#endif -// Register width -#define TIMER_PARAM_REG_WIDTH 32 - -#define TIMER0_BASE_ADDR (0x40000000) -#define TIMER0_REG(offset) (*((volatile uint32_t *)(TIMER0_BASE_ADDR + offset))) - -// Timer control register -#define TIMER_CTRL_REG_OFFSET 0x0 -#define TIMER_CTRL_REG_RESVAL 0x0 -#define TIMER_CTRL_EN_BIT 0 -#define TIMER_CTRL_INT_EN_BIT 1 -#define TIMER_CTRL_INT_PENDING_BIT 2 -#define TIMER_CTRL_MODE_BIT 3 -#define TIMER_CTRL_CLK_DIV_MASK 0xffffff -#define TIMER_CTRL_CLK_DIV_OFFSET 8 -#define TIMER_CTRL_CLK_DIV_FIELD \ - ((bitfield_field32_t) { .mask = TIMER_CTRL_CLK_DIV_MASK, .index = TIMER_CTRL_CLK_DIV_OFFSET }) - -// Timer expired value register -#define TIMER_VALUE_REG_OFFSET 0x4 -#define TIMER_VALUE_REG_RESVAL 0x0 - -// Timer current count register -#define TIMER_COUNT_REG_OFFSET 0x8 -#define TIMER_COUNT_REG_RESVAL 0x0 - -void timer0_start(uint8_t en); -void timer0_set_value(uint32_t val); -void timer0_set_int_enable(uint8_t en); -void timer0_clear_int_pending(); -uint8_t timer0_get_int_pending(); -uint32_t timer0_get_current_count(); -void timer0_set_mode_auto_reload(); -void timer0_set_mode_ontshot(); -void timer0_set_div(uint32_t div); - -#ifdef __cplusplus -} // extern "C" -#endif -#endif // _TIMER_REG_DEFS_ +// Generated register defines for timer + +// Copyright information found in source file: +// Copyright lowRISC contributors. + +// Licensing information found in source file: +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +#ifndef _TIMER_REG_DEFS_ +#define _TIMER_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Register width +#define TIMER_PARAM_REG_WIDTH 32 + +#define TIMER0_BASE_ADDR (0x04000000) +#define TIMER0_REG(offset) (*((volatile uint32_t *)(TIMER0_BASE_ADDR + offset))) + +#define TIMER1_BASE_ADDR (0x0C000000) +#define TIMER1_REG(offset) (*((volatile uint32_t *)(TIMER1_BASE_ADDR + offset))) + +#define TIMER2_BASE_ADDR (0x0D000000) +#define TIMER2_REG(offset) (*((volatile uint32_t *)(TIMER2_BASE_ADDR + offset))) + +// Timer control register +#define TIMER_CTRL_REG_OFFSET 0x0 +#define TIMER_CTRL_REG_RESVAL 0x0 +#define TIMER_CTRL_EN_BIT 0 +#define TIMER_CTRL_INT_EN_BIT 1 +#define TIMER_CTRL_INT_PENDING_BIT 2 +#define TIMER_CTRL_MODE_BIT 3 +#define TIMER_CTRL_CLK_DIV_MASK 0xffffff +#define TIMER_CTRL_CLK_DIV_OFFSET 8 +#define TIMER_CTRL_CLK_DIV_FIELD \ + ((bitfield_field32_t) { .mask = TIMER_CTRL_CLK_DIV_MASK, .index = TIMER_CTRL_CLK_DIV_OFFSET }) + +// Timer expired value register +#define TIMER_VALUE_REG_OFFSET 0x4 +#define TIMER_VALUE_REG_RESVAL 0x0 + +// Timer current count register +#define TIMER_COUNT_REG_OFFSET 0x8 +#define TIMER_COUNT_REG_RESVAL 0x0 + +void timer0_start(uint8_t en); +void timer0_set_value(uint32_t val); +void timer0_set_int_enable(uint8_t en); +void timer0_clear_int_pending(); +uint8_t timer0_get_int_pending(); +uint32_t timer0_get_current_count(); +void timer0_set_mode_auto_reload(); +void timer0_set_mode_ontshot(); +void timer0_set_div(uint32_t div); + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _TIMER_REG_DEFS_ // End generated register defines for timer \ No newline at end of file diff --git a/sdk/bsp/include/uart.h b/sdk/bsp/include/uart.h index d1dfd03..6f0bbca 100644 --- a/sdk/bsp/include/uart.h +++ b/sdk/bsp/include/uart.h @@ -7,9 +7,15 @@ extern "C" { // Register width #define UART_PARAM_REG_WIDTH 32 -#define UART0_BASE_ADDR (0x50000000) +#define UART0_BASE_ADDR (0x05000000) #define UART0_REG(offset) (*((volatile uint32_t *)(UART0_BASE_ADDR + offset))) +#define UART1_BASE_ADDR (0x09000000) +#define UART1_REG(offset) (*((volatile uint32_t *)(UART1_BASE_ADDR + offset))) + +#define UART2_BASE_ADDR (0x0A000000) +#define UART2_REG(offset) (*((volatile uint32_t *)(UART2_BASE_ADDR + offset))) + // UART control register #define UART_CTRL_REG_OFFSET 0x0 #define UART_CTRL_REG_RESVAL 0xd90000 diff --git a/sdk/bsp/lib/gpio.c b/sdk/bsp/lib/gpio.c index c3c6ea8..54b3394 100644 --- a/sdk/bsp/lib/gpio.c +++ b/sdk/bsp/lib/gpio.c @@ -5,8 +5,8 @@ void gpio_set_mode(gpio_e gpio, gpio_mode_e mode) { - GPIO_REG(GPIO_MODE_REG_OFFSET) &= ~(0x3 << (gpio << 1)); - GPIO_REG(GPIO_MODE_REG_OFFSET) |= ((uint8_t)mode) << (gpio << 1); + GPIO_REG(GPIO_IO_MODE_REG_OFFSET) &= ~(0x3 << (gpio << 1)); + GPIO_REG(GPIO_IO_MODE_REG_OFFSET) |= ((uint8_t)mode) << (gpio << 1); } uint8_t gpio_get_input_data(gpio_e gpio) @@ -40,18 +40,18 @@ void gpio_set_input_filter_enable(gpio_e gpio, uint8_t en) void gpio_set_interrupt_mode(gpio_e gpio, gpio_intr_mode_e mode) { - GPIO_REG(GPIO_INTR_REG_OFFSET) &= ~(0x3 << (gpio << 1)); - GPIO_REG(GPIO_INTR_REG_OFFSET) |= ((uint8_t)mode) << (gpio << 1); + GPIO_REG(GPIO_INT_MODE_REG_OFFSET) &= ~(0x3 << (gpio << 1)); + GPIO_REG(GPIO_INT_MODE_REG_OFFSET) |= ((uint8_t)mode) << (gpio << 1); } void gpio_clear_intr_pending(gpio_e gpio) { - GPIO_REG(GPIO_INTR_REG_OFFSET) |= 1 << (gpio + 16); + GPIO_REG(GPIO_INT_PENDING_REG_OFFSET) |= 1 << gpio; } uint8_t gpio_get_intr_pending(gpio_e gpio) { - if (GPIO_REG(GPIO_INTR_REG_OFFSET) & (1 << (gpio + 16))) + if (GPIO_REG(GPIO_INT_PENDING_REG_OFFSET) & (1 << gpio)) return 1; else return 0; diff --git a/sdk/bsp/lib/pinmux.c b/sdk/bsp/lib/pinmux.c new file mode 100644 index 0000000..742cb53 --- /dev/null +++ b/sdk/bsp/lib/pinmux.c @@ -0,0 +1,100 @@ +#include + +#include "../include/pinmux.h" + + +void pinmux_set_io0_func(pinmux_io0_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO0_MUX_MASK << PINMUX_CTRL_IO0_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO0_MUX_OFFSET; +} + +void pinmux_set_io1_func(pinmux_io1_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO1_MUX_MASK << PINMUX_CTRL_IO1_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO1_MUX_OFFSET; +} + +void pinmux_set_io2_func(pinmux_io2_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO2_MUX_MASK << PINMUX_CTRL_IO2_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO2_MUX_OFFSET; +} + +void pinmux_set_io3_func(pinmux_io3_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO3_MUX_MASK << PINMUX_CTRL_IO3_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO3_MUX_OFFSET; +} + +void pinmux_set_io4_func(pinmux_io4_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO4_MUX_MASK << PINMUX_CTRL_IO4_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO4_MUX_OFFSET; +} + +void pinmux_set_io5_func(pinmux_io5_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO5_MUX_MASK << PINMUX_CTRL_IO5_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO5_MUX_OFFSET; +} + +void pinmux_set_io6_func(pinmux_io6_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO6_MUX_MASK << PINMUX_CTRL_IO6_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO6_MUX_OFFSET; +} + +void pinmux_set_io7_func(pinmux_io7_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO7_MUX_MASK << PINMUX_CTRL_IO7_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO7_MUX_OFFSET; +} + +void pinmux_set_io8_func(pinmux_io8_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO8_MUX_MASK << PINMUX_CTRL_IO8_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO8_MUX_OFFSET; +} + +void pinmux_set_io9_func(pinmux_io9_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO9_MUX_MASK << PINMUX_CTRL_IO9_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO9_MUX_OFFSET; +} + +void pinmux_set_io10_func(pinmux_io10_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO10_MUX_MASK << PINMUX_CTRL_IO10_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO10_MUX_OFFSET; +} + +void pinmux_set_io11_func(pinmux_io11_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO11_MUX_MASK << PINMUX_CTRL_IO11_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO11_MUX_OFFSET; +} + +void pinmux_set_io12_func(pinmux_io12_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO12_MUX_MASK << PINMUX_CTRL_IO12_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO12_MUX_OFFSET; +} + +void pinmux_set_io13_func(pinmux_io13_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO13_MUX_MASK << PINMUX_CTRL_IO13_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO13_MUX_OFFSET; +} + +void pinmux_set_io14_func(pinmux_io14_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO14_MUX_MASK << PINMUX_CTRL_IO14_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO14_MUX_OFFSET; +} + +void pinmux_set_io15_func(pinmux_io15_e func) +{ + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) &= ~(PINMUX_CTRL_IO15_MUX_MASK << PINMUX_CTRL_IO15_MUX_OFFSET); + PINMUX_REG(PINMUX_CTRL_REG_OFFSET) |= func << PINMUX_CTRL_IO15_MUX_OFFSET; +} diff --git a/sdk/bsp/trap_entry.S b/sdk/bsp/trap_entry.S index f56e79c..6b9ae02 100644 --- a/sdk/bsp/trap_entry.S +++ b/sdk/bsp/trap_entry.S @@ -21,6 +21,18 @@ vector_table: .word gpio0_irq_handler .word gpio1_irq_handler .word i2c0_irq_handler + .word spi0_irq_handler + .word gpio2_4_irq_handler + .word gpio5_7_irq_handler + .word gpio8_irq_handler + .word gpio9_irq_handler + .word gpio10_12_irq_handler + .word gpio13_15_irq_handler + .word uart1_irq_handler + .word uart2_irq_handler + .word i2c1_irq_handler + .word timer1_irq_handler + .word timer2_irq_handler /* add your ISR here */ .weak illegal_instruction_handler @@ -35,6 +47,18 @@ vector_table: .weak gpio0_irq_handler .weak gpio1_irq_handler .weak i2c0_irq_handler +.weak spi0_irq_handler +.weak gpio2_4_irq_handler +.weak gpio5_7_irq_handler +.weak gpio8_irq_handler +.weak gpio9_irq_handler +.weak gpio10_12_irq_handler +.weak gpio13_15_irq_handler +.weak uart1_irq_handler +.weak uart2_irq_handler +.weak i2c1_irq_handler +.weak timer1_irq_handler +.weak timer2_irq_handler handle_exception_unknown: j handle_exception_unknown @@ -78,6 +102,42 @@ gpio1_irq_handler: i2c0_irq_handler: j i2c0_irq_handler +spi0_irq_handler: + j spi0_irq_handler + +gpio2_4_irq_handler: + j gpio2_4_irq_handler + +gpio5_7_irq_handler: + j gpio5_7_irq_handler + +gpio8_irq_handler: + j gpio8_irq_handler + +gpio9_irq_handler: + j gpio9_irq_handler + +gpio10_12_irq_handler: + j gpio10_12_irq_handler + +gpio13_15_irq_handler: + j gpio13_15_irq_handler + +uart1_irq_handler: + j uart1_irq_handler + +uart2_irq_handler: + j uart2_irq_handler + +i2c1_irq_handler: + j i2c1_irq_handler + +timer1_irq_handler: + j timer1_irq_handler + +timer2_irq_handler: + j timer2_irq_handler + /* 异常和中断总入口 */ trap_entry: addi sp, sp, -32*17 diff --git a/sdk/examples/gpio/main.c b/sdk/examples/gpio/main.c index 38212ab..ff49474 100644 --- a/sdk/examples/gpio/main.c +++ b/sdk/examples/gpio/main.c @@ -3,28 +3,39 @@ #include "../../bsp/include/gpio.h" #include "../../bsp/include/utils.h" #include "../../bsp/include/rvic.h" +#include "../../bsp/include/pinmux.h" int main() { - gpio_set_mode(GPIO0, GPIO_MODE_OUTPUT); // gpio0输出模式 - gpio_set_mode(GPIO1, GPIO_MODE_INPUT); // gpio1输入模式 - gpio_set_interrupt_mode(GPIO1, GPIO_INTR_DOUBLE_EDGE); - rvic_irq_enable(3); - rvic_set_irq_prio_level(3, 1); + // IO7用作GPIO7 + pinmux_set_io7_func(IO7_GPIO7); + // IO9用作GPIO9 + pinmux_set_io9_func(IO9_GPIO9); + // gpio7输出模式 + gpio_set_mode(GPIO7, GPIO_MODE_OUTPUT); + // gpio9输入模式 + gpio_set_mode(GPIO9, GPIO_MODE_INPUT); + // gpio9双沿中断模式 + gpio_set_interrupt_mode(GPIO9, GPIO_INTR_DOUBLE_EDGE); + // 使能RVIC中断 + rvic_irq_enable(RVIC_INT_ID_9); + // gpio9中断优先级为1 + rvic_set_irq_prio_level(RVIC_INT_ID_9, 1); + // 使能全局中断 global_irq_enable(); while (1); } -void gpio1_irq_handler() +void gpio9_irq_handler() { - gpio_clear_intr_pending(GPIO1); - rvic_clear_irq_pending(3); + gpio_clear_intr_pending(GPIO9); + rvic_clear_irq_pending(RVIC_INT_ID_9); - // 如果GPIO1输入高 - if (gpio_get_input_data(GPIO1)) - gpio_set_output_data(GPIO0, 1); // GPIO0输出高 - // 如果GPIO1输入低 + // 如果GPIO9输入高 + if (gpio_get_input_data(GPIO9)) + gpio_set_output_data(GPIO7, 1); // GPIO7输出高 + // 如果GPIO9输入低 else - gpio_set_output_data(GPIO0, 0); // GPIO0输出低 + gpio_set_output_data(GPIO7, 0); // GPIO7输出低 } diff --git a/sdk/examples/hello_world/main.c b/sdk/examples/hello_world/main.c index 86314fc..7a10fc3 100644 --- a/sdk/examples/hello_world/main.c +++ b/sdk/examples/hello_world/main.c @@ -3,7 +3,7 @@ #include "../../bsp/include/sim_ctrl.h" #include "../../bsp/include/uart.h" #include "../../bsp/include/xprintf.h" - +#include "../../bsp/include/pinmux.h" int main() @@ -12,6 +12,8 @@ int main() sim_ctrl_init(); #else uart0_init(uart0_putc); + pinmux_set_io0_func(IO0_UART0_TX); + pinmux_set_io3_func(IO3_UART0_RX); #endif xprintf("hello world\n"); diff --git a/sdk/examples/i2c_master/main.c b/sdk/examples/i2c_master/main.c index 6f0725b..f07ebd0 100644 --- a/sdk/examples/i2c_master/main.c +++ b/sdk/examples/i2c_master/main.c @@ -5,6 +5,7 @@ #include "../../bsp/include/xprintf.h" #include "../../bsp/include/utils.h" #include "../../bsp/include/rvic.h" +#include "../../bsp/include/pinmux.h" #define SLAVE_ADDR (0xA0) @@ -38,6 +39,10 @@ int main() uint8_t data, i; uart0_init(uart0_putc); + pinmux_set_io0_func(IO0_UART0_TX); + pinmux_set_io3_func(IO3_UART0_RX); + pinmux_set_io6_func(IO6_I2C0_SCL); + pinmux_set_io8_func(IO8_I2C0_SDA); i2c0_set_clk(0x7D); // 200KHZ i2c0_set_mode(I2C_MODE_MASTER); diff --git a/sdk/examples/uart_loopback/main.c b/sdk/examples/uart_loopback/main.c index a7adc3d..e687771 100644 --- a/sdk/examples/uart_loopback/main.c +++ b/sdk/examples/uart_loopback/main.c @@ -2,12 +2,14 @@ #include "../../bsp/include/uart.h" #include "../../bsp/include/xprintf.h" - +#include "../../bsp/include/pinmux.h" int main() { uart0_init(uart0_putc); + pinmux_set_io0_func(IO0_UART0_TX); + pinmux_set_io3_func(IO3_UART0_RX); while (1) { // loopback