diff --git a/rtl/top/tinyriscv_soc_top.sv b/rtl/top/tinyriscv_soc_top.sv
index 8816c3e..e519074 100644
--- a/rtl/top/tinyriscv_soc_top.sv
+++ b/rtl/top/tinyriscv_soc_top.sv
@@ -219,7 +219,7 @@ module tinyriscv_soc_top(
 
 `ifdef VERILATOR
     sim_jtag #(
-        .TICK_DELAY(1),
+        .TICK_DELAY(10),
         .PORT(9999)
     ) u_sim_jtag (
         .clock                ( clk                  ),
diff --git a/sim/jtag_compliance_test.cfg b/sim/jtag_compliance_test.cfg
index 9de9b41..9b7b5f6 100644
--- a/sim/jtag_compliance_test.cfg
+++ b/sim/jtag_compliance_test.cfg
@@ -1,30 +1,31 @@
-debug_level 2
-adapter_khz     10000
-
-interface remote_bitbang
-remote_bitbang_host localhost
-
-remote_bitbang_port 9999
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6f
-
-foreach t [jtag names] {
-    puts [format "TAP: %s\n" $t]
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-
-riscv set_reset_timeout_sec 2000
-riscv set_command_timeout_sec 2000
-
-# prefer to use sba for system bus access
-riscv set_prefer_sba on
-
-# dump jtag chain
-scan_chain
-
-init
-riscv test_compliance
-shutdown
+debug_level 2
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host localhost
+
+remote_bitbang_port 9999
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6f
+
+foreach t [jtag names] {
+    puts [format "TAP: %s\n" $t]
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_reset_timeout_sec 2000
+riscv set_command_timeout_sec 2000
+
+# prefer to use sba for system bus access
+riscv set_prefer_sba on
+riscv set_enable_virt2phys off
+
+# dump jtag chain
+scan_chain
+
+init
+riscv test_compliance
+shutdown
diff --git a/sim/jtag_debug.cfg b/sim/jtag_debug.cfg
index 2ae4020..7db2cf8 100644
--- a/sim/jtag_debug.cfg
+++ b/sim/jtag_debug.cfg
@@ -1,31 +1,32 @@
-debug_level 2
-adapter_khz     10000
-
-interface remote_bitbang
-remote_bitbang_host localhost
-
-remote_bitbang_port 9999
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6f
-
-foreach t [jtag names] {
-    puts [format "TAP: %s\n" $t]
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-
-riscv set_reset_timeout_sec 2000
-riscv set_command_timeout_sec 2000
-
-# prefer to use sba for system bus access
-riscv set_prefer_sba on
-
-# dump jtag chain
-scan_chain
-
-init
-
-halt
-echo "Ready for Remote Connections"
+debug_level 2
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host localhost
+
+remote_bitbang_port 9999
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1e200a6f
+
+foreach t [jtag names] {
+    puts [format "TAP: %s\n" $t]
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_reset_timeout_sec 2000
+riscv set_command_timeout_sec 2000
+
+# prefer to use sba for system bus access
+riscv set_prefer_sba on
+riscv set_enable_virt2phys off
+
+# dump jtag chain
+scan_chain
+
+init
+
+halt
+echo "Ready for Remote Connections"
diff --git a/sim/tb_top_verilator.cpp b/sim/tb_top_verilator.cpp
index 047e90d..0edc63f 100644
--- a/sim/tb_top_verilator.cpp
+++ b/sim/tb_top_verilator.cpp
@@ -1,21 +1,3 @@
-// Copyright 2018 Robert Balas <balasr@student.ethz.ch>
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-
-// Top level wrapper for a verilator RI5CY testbench
-// Contributor: Robert Balas <balasr@student.ethz.ch>
-
 #include "svdpi.h"
 #include "Vtb_top_verilator__Dpi.h"
 #include "Vtb_top_verilator.h"
@@ -30,7 +12,6 @@
 #include <cstdint>
 #include <cerrno>
 
-//void dump_memory();
 double sc_time_stamp();
 
 static vluint64_t t = 0;
@@ -42,36 +23,35 @@ int main(int argc, char **argv, char **env)
     Verilated::traceEverOn(true);
     top = new Vtb_top_verilator();
 
-    //svSetScope(svGetScopeFromName(
-    //    "TOP.tb_top_verilator.u_ram.ram"));
-    //Verilated::scopesDump();
-
 #ifdef VCD_TRACE
     VerilatedVcdC *tfp = new VerilatedVcdC;
     top->trace(tfp, 99);
     tfp->open("verilator_tb.vcd");
 #endif
+
     top->clk_i          = 0;
     top->rst_ni         = 0;
 
     top->eval();
-    //dump_memory();
 
     while (!Verilated::gotFinish()) {
         if (t > 40)
             top->rst_ni = 1;
+
         top->clk_i = !top->clk_i;
         top->eval();
+
 #ifdef VCD_TRACE
         tfp->dump(t);
 #endif
+
         t += 5;
-        //if (t > 2000)
-        //    break;
     }
+
 #ifdef VCD_TRACE
     tfp->close();
 #endif
+
     delete top;
     exit(0);
 }
@@ -80,28 +60,3 @@ double sc_time_stamp()
 {
     return t;
 }
-/*
-void dump_memory()
-{
-    errno = 0;
-    std::ofstream mem_file;
-    svLogicVecVal addr = {0};
-
-    mem_file.exceptions(std::ofstream::failbit | std::ofstream::badbit);
-    try {
-        mem_file.open("memory_dump.bin");
-        for (size_t i = 0; i < 1048576; i++) {
-            addr.aval    = i;
-            uint32_t val = read_byte(&addr);
-            mem_file << std::setfill('0') << std::setw(2) << std::hex << val
-                     << std::endl;
-        }
-        mem_file.close();
-
-        std::cout << "finished dumping memory" << std::endl;
-
-    } catch (std::ofstream::failure e) {
-        std::cerr << "exception opening/reading/closing file memory_dump.bin\n";
-    }
-}
-*/