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rtl: core: fix data related for csr regs 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-06-05 22:22:49 +08:00
parent 0256674146
commit 5b888bd483
2 changed files with 75 additions and 52 deletions
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22
rtl/core/csr_reg.v
View File

@ -54,6 +54,7 @@ module csr_reg(
reg[`RegBus] mepc; reg[`RegBus] mepc;
reg[`RegBus] mie; reg[`RegBus] mie;
reg[`RegBus] mstatus; reg[`RegBus] mstatus;
reg[`RegBus] mscratch;
assign global_int_en_o = (mstatus[3] == 1'b1)? `True: `False; assign global_int_en_o = (mstatus[3] == 1'b1)? `True: `False;
@ -82,6 +83,7 @@ module csr_reg(
mepc <= `ZeroWord; mepc <= `ZeroWord;
mie <= `ZeroWord; mie <= `ZeroWord;
mstatus <= `ZeroWord; mstatus <= `ZeroWord;
mscratch <= `ZeroWord;
end else begin end else begin
// 优先响应ex模块的写操作 // 优先响应ex模块的写操作
if (we_i == `WriteEnable) begin if (we_i == `WriteEnable) begin
@ -101,6 +103,9 @@ module csr_reg(
`CSR_MSTATUS: begin `CSR_MSTATUS: begin
mstatus <= data_i; mstatus <= data_i;
end end
`CSR_MSCRATCH: begin
mscratch <= data_i;
end
default: begin default: begin
end end
@ -123,6 +128,9 @@ module csr_reg(
`CSR_MSTATUS: begin `CSR_MSTATUS: begin
mstatus <= clint_data_i; mstatus <= clint_data_i;
end end
`CSR_MSCRATCH: begin
mscratch <= clint_data_i;
end
default: begin default: begin
end end
@ -136,6 +144,9 @@ module csr_reg(
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
data_o = `ZeroWord; data_o = `ZeroWord;
end else begin
if ((waddr_i[11:0] == raddr_i[11:0]) && (we_i == `WriteEnable)) begin
data_o = data_i;
end else begin end else begin
case (raddr_i[11:0]) case (raddr_i[11:0])
`CSR_CYCLE: begin `CSR_CYCLE: begin
@ -159,18 +170,25 @@ module csr_reg(
`CSR_MSTATUS: begin `CSR_MSTATUS: begin
data_o = mstatus; data_o = mstatus;
end end
`CSR_MSCRATCH: begin
data_o = mscratch;
end
default: begin default: begin
data_o = `ZeroWord; data_o = `ZeroWord;
end end
endcase endcase
end end
end end
end
// read reg // read reg
// clint模块读CSR寄存器 // clint模块读CSR寄存器
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
clint_data_o = `ZeroWord; clint_data_o = `ZeroWord;
end else begin
if ((clint_waddr_i[11:0] == clint_raddr_i[11:0]) && (clint_we_i == `WriteEnable)) begin
clint_data_o = clint_data_i;
end else begin end else begin
case (clint_raddr_i[11:0]) case (clint_raddr_i[11:0])
`CSR_CYCLE: begin `CSR_CYCLE: begin
@ -194,11 +212,15 @@ module csr_reg(
`CSR_MSTATUS: begin `CSR_MSTATUS: begin
clint_data_o = mstatus; clint_data_o = mstatus;
end end
`CSR_MSCRATCH: begin
clint_data_o = mscratch;
end
default: begin default: begin
clint_data_o = `ZeroWord; clint_data_o = `ZeroWord;
end end
endcase endcase
end end
end end
end
endmodule endmodule

1
rtl/core/defines.v
View File

@ -143,6 +143,7 @@
`define CSR_MEPC 12'h341 `define CSR_MEPC 12'h341
`define CSR_MIE 12'h304 `define CSR_MIE 12'h304
`define CSR_MSTATUS 12'h300 `define CSR_MSTATUS 12'h300
`define CSR_MSCRATCH 12'h340
`define RomNum 4096 // rom depth(how many words) `define RomNum 4096 // rom depth(how many words)