diff --git a/sdk/bsp/bsp.mk b/sdk/bsp/bsp.mk
index 409a5f4..9d5832e 100644
--- a/sdk/bsp/bsp.mk
+++ b/sdk/bsp/bsp.mk
@@ -1,58 +1,57 @@
-RISCV_TOOLS_PATH := /opt/riscv/bin
-RISCV_TOOLS_PREFIX := riscv32-unknown-elf-
-
-RISCV_GCC     := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)gcc)
-RISCV_AS      := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)as)
-RISCV_GXX     := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)g++)
-RISCV_OBJDUMP := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)objdump)
-RISCV_GDB     := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)gdb)
-RISCV_AR      := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)ar)
-RISCV_OBJCOPY := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)objcopy)
-RISCV_READELF := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)readelf)
-
-BIN_TO_MEM    := $(BSP_DIR)/../../tools/BinToMem.py
-
-.PHONY: all
-all: $(TARGET)
-
-ASM_SRCS += $(BSP_DIR)/start.S
-ASM_SRCS += $(BSP_DIR)/trap_entry.S
-C_SRCS += $(BSP_DIR)/init.c
-C_SRCS += $(BSP_DIR)/trap_handler.c
-C_SRCS += $(BSP_DIR)/lib/utils.c
-C_SRCS += $(BSP_DIR)/lib/xprintf.c
-C_SRCS += $(BSP_DIR)/lib/uart.c
-
-LINKER_SCRIPT := $(BSP_DIR)/link.lds
-
-INCLUDES += -I$(BSP_DIR)
-
-LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles -Wl,--gc-sections -Wl,--check-sections
-
-ASM_OBJS := $(ASM_SRCS:.S=.o)
-C_OBJS := $(C_SRCS:.c=.o)
-
-LINK_OBJS += $(ASM_OBJS) $(C_OBJS)
-LINK_DEPS += $(LINKER_SCRIPT)
-
-CLEAN_OBJS += $(TARGET) $(LINK_OBJS) $(TARGET).dump $(TARGET).bin $(TARGET).hex $(TARGET).mem
-
-CFLAGS += -march=$(RISCV_ARCH)
-CFLAGS += -mabi=$(RISCV_ABI)
-CFLAGS += -mcmodel=$(RISCV_MCMODEL) -ffunction-sections -fdata-sections -fno-builtin-printf -fno-builtin-malloc
-
-$(TARGET): $(LINK_OBJS) $(LINK_DEPS) Makefile
-	$(RISCV_GCC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS)
-	$(RISCV_OBJCOPY) -O binary $@ $@.bin
-	$(RISCV_OBJDUMP) --disassemble-all $@ > $@.dump
-	$(BIN_TO_MEM) $@.bin $@.mem
-
-$(ASM_OBJS): %.o: %.S
-	$(RISCV_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
-
-$(C_OBJS): %.o: %.c
-	$(RISCV_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
-
-.PHONY: clean
-clean:
-	rm -f $(CLEAN_OBJS)
+RISCV_TOOLS_PATH := /opt/riscv/bin
+RISCV_TOOLS_PREFIX := riscv32-unknown-elf-
+
+RISCV_GCC     := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)gcc)
+RISCV_AS      := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)as)
+RISCV_GXX     := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)g++)
+RISCV_OBJDUMP := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)objdump)
+RISCV_GDB     := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)gdb)
+RISCV_AR      := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)ar)
+RISCV_OBJCOPY := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)objcopy)
+RISCV_READELF := $(abspath $(RISCV_TOOLS_PATH)/$(RISCV_TOOLS_PREFIX)readelf)
+
+BIN_TO_MEM    := $(BSP_DIR)/../../tools/BinToMem.py
+
+.PHONY: all
+all: $(TARGET)
+
+ASM_SRCS += $(BSP_DIR)/crt0.S
+ASM_SRCS += $(BSP_DIR)/vector_table.S
+
+C_SRCS += $(BSP_DIR)/lib/utils.c
+C_SRCS += $(BSP_DIR)/lib/xprintf.c
+C_SRCS += $(BSP_DIR)/lib/uart.c
+
+LINKER_SCRIPT := $(BSP_DIR)/link.lds
+
+INCLUDES += -I$(BSP_DIR)
+
+LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles -Wl,--gc-sections -Wl,--check-sections
+
+ASM_OBJS := $(ASM_SRCS:.S=.o)
+C_OBJS := $(C_SRCS:.c=.o)
+
+LINK_OBJS += $(ASM_OBJS) $(C_OBJS)
+LINK_DEPS += $(LINKER_SCRIPT)
+
+CLEAN_OBJS += $(TARGET) $(LINK_OBJS) $(TARGET).dump $(TARGET).bin $(TARGET).hex $(TARGET).mem
+
+CFLAGS += -march=$(RISCV_ARCH)
+CFLAGS += -mabi=$(RISCV_ABI)
+CFLAGS += -mcmodel=$(RISCV_MCMODEL) -ffunction-sections -fdata-sections -fno-builtin-printf -fno-builtin-malloc
+
+$(TARGET): $(LINK_OBJS) $(LINK_DEPS) Makefile
+	$(RISCV_GCC) $(CFLAGS) $(INCLUDES) $(LINK_OBJS) -o $@ $(LDFLAGS)
+	$(RISCV_OBJCOPY) -O binary $@ $@.bin
+	$(RISCV_OBJDUMP) --disassemble-all $@ > $@.dump
+	$(BIN_TO_MEM) $@.bin $@.mem
+
+$(ASM_OBJS): %.o: %.S
+	$(RISCV_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
+
+$(C_OBJS): %.o: %.c
+	$(RISCV_GCC) $(CFLAGS) $(INCLUDES) -c -o $@ $<
+
+.PHONY: clean
+clean:
+	rm -f $(CLEAN_OBJS)
diff --git a/sdk/bsp/start.S b/sdk/bsp/crt0.S
similarity index 77%
rename from sdk/bsp/start.S
rename to sdk/bsp/crt0.S
index c27c10d..adaf944 100644
--- a/sdk/bsp/start.S
+++ b/sdk/bsp/crt0.S
@@ -1,49 +1,53 @@
-
-    .section .init;
-    .globl _start;
-    .type _start,@function
-
-
-_start:
-.option push
-.option norelax
-	la gp, __global_pointer$
-.option pop
-	la sp, _sp
-#ifdef SIMULATION
-    li x26, 0x00
-    li x27, 0x00
-#endif
-
-	/* Load data section */
-	la a0, _data_lma
-	la a1, _data
-	la a2, _edata
-	bgeu a1, a2, 2f
-1:
-	lw t0, (a0)
-	sw t0, (a1)
-	addi a0, a0, 4
-	addi a1, a1, 4
-	bltu a1, a2, 1b
-2:
-
-	/* Clear bss section */
-	la a0, __bss_start
-	la a1, _end
-	bgeu a0, a1, 2f
-1:
-	sw zero, (a0)
-	addi a0, a0, 4
-	bltu a0, a1, 1b
-2:
-
-    call _init
-    call main
-
-#ifdef SIMULATION
-    li x26, 0x01
-#endif
-
-loop:
-    j loop
+    .section .init;
+    .globl _start;
+    .type _start,@function
+
+
+_start:
+.option push
+.option norelax
+	la gp, __global_pointer$
+.option pop
+	la sp, _sp
+#ifdef SIMULATION
+    li x26, 0x00
+    li x27, 0x00
+#endif
+
+	/* Load data section */
+	la a0, _data_lma
+	la a1, _data
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+
+	/* Clear bss section */
+	la a0, __bss_start
+	la a1, _end
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+
+    /* set exception and interrupt vector table */
+    la a0, vector_table
+    csrw mtvec, a0
+
+    li a0, 0
+    li a1, 0
+    call main
+
+#ifdef SIMULATION
+    li x26, 0x01
+#endif
+
+loop:
+    j loop
diff --git a/sdk/bsp/init.c b/sdk/bsp/init.c
deleted file mode 100644
index 931dddd..0000000
--- a/sdk/bsp/init.c
+++ /dev/null
@@ -1,16 +0,0 @@
-#include <stdint.h>
-
-#include "include/utils.h"
-
-
-extern void trap_entry();
-
-
-void _init()
-{
-    // 设置中断入口函数
-    write_csr(mtvec, &trap_entry);
-    // 使能CPU全局中断
-    // MIE = 1, MPIE = 1, MPP = 11
-    write_csr(mstatus, 0x1888);
-}
diff --git a/sdk/bsp/trap_entry.S b/sdk/bsp/trap_entry.S
deleted file mode 100644
index f19f3a3..0000000
--- a/sdk/bsp/trap_entry.S
+++ /dev/null
@@ -1,109 +0,0 @@
-#define REGBYTES  4
-#define STORE     sw
-#define LOAD      lw
-
-
-    .section      .text.entry	
-    .align 2
-    .global trap_entry
-trap_entry:
-
-    addi sp, sp, -32*REGBYTES
-
-    STORE x1, 1*REGBYTES(sp)
-    STORE x2, 2*REGBYTES(sp)
-    STORE x3, 3*REGBYTES(sp)
-    STORE x4, 4*REGBYTES(sp)
-    STORE x5, 5*REGBYTES(sp)
-    STORE x6, 6*REGBYTES(sp)
-    STORE x7, 7*REGBYTES(sp)
-    STORE x8, 8*REGBYTES(sp)
-    STORE x9, 9*REGBYTES(sp)
-    STORE x10, 10*REGBYTES(sp)
-    STORE x11, 11*REGBYTES(sp)
-    STORE x12, 12*REGBYTES(sp)
-    STORE x13, 13*REGBYTES(sp)
-    STORE x14, 14*REGBYTES(sp)
-    STORE x15, 15*REGBYTES(sp)
-    STORE x16, 16*REGBYTES(sp)
-    STORE x17, 17*REGBYTES(sp)
-    STORE x18, 18*REGBYTES(sp)
-    STORE x19, 19*REGBYTES(sp)
-    STORE x20, 20*REGBYTES(sp)
-    STORE x21, 21*REGBYTES(sp)
-    STORE x22, 22*REGBYTES(sp)
-    STORE x23, 23*REGBYTES(sp)
-    STORE x24, 24*REGBYTES(sp)
-    STORE x25, 25*REGBYTES(sp)
-#ifndef SIMULATION
-    STORE x26, 26*REGBYTES(sp)
-    STORE x27, 27*REGBYTES(sp)
-#endif
-    STORE x28, 28*REGBYTES(sp)
-    STORE x29, 29*REGBYTES(sp)
-    STORE x30, 30*REGBYTES(sp)
-    STORE x31, 31*REGBYTES(sp)
-
-    csrr a0, mcause
-    csrr a1, mepc
-test_if_asynchronous:
-	srli a2, a0, 31		                /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
-	beq a2, x0, handle_synchronous		/* Branch past interrupt handing if not asynchronous. */
-
-    call interrupt_handler
-    j asynchronous_return
-
-handle_synchronous:
-    call exception_handler
-    addi a1, a1, 4
-    csrw mepc, a1
-
-asynchronous_return:
-    LOAD x1, 1*REGBYTES(sp)
-    LOAD x2, 2*REGBYTES(sp)
-    LOAD x3, 3*REGBYTES(sp)
-    LOAD x4, 4*REGBYTES(sp)
-    LOAD x5, 5*REGBYTES(sp)
-    LOAD x6, 6*REGBYTES(sp)
-    LOAD x7, 7*REGBYTES(sp)
-    LOAD x8, 8*REGBYTES(sp)
-    LOAD x9, 9*REGBYTES(sp)
-    LOAD x10, 10*REGBYTES(sp)
-    LOAD x11, 11*REGBYTES(sp)
-    LOAD x12, 12*REGBYTES(sp)
-    LOAD x13, 13*REGBYTES(sp)
-    LOAD x14, 14*REGBYTES(sp)
-    LOAD x15, 15*REGBYTES(sp)
-    LOAD x16, 16*REGBYTES(sp)
-    LOAD x17, 17*REGBYTES(sp)
-    LOAD x18, 18*REGBYTES(sp)
-    LOAD x19, 19*REGBYTES(sp)
-    LOAD x20, 20*REGBYTES(sp)
-    LOAD x21, 21*REGBYTES(sp)
-    LOAD x22, 22*REGBYTES(sp)
-    LOAD x23, 23*REGBYTES(sp)
-    LOAD x24, 24*REGBYTES(sp)
-    LOAD x25, 25*REGBYTES(sp)
-#ifndef SIMULATION
-    LOAD x26, 26*REGBYTES(sp)
-    LOAD x27, 27*REGBYTES(sp)
-#endif
-    LOAD x28, 28*REGBYTES(sp)
-    LOAD x29, 29*REGBYTES(sp)
-    LOAD x30, 30*REGBYTES(sp)
-    LOAD x31, 31*REGBYTES(sp)
-
-    addi sp, sp, 32*REGBYTES
-
-    mret
-
-
-.weak interrupt_handler
-interrupt_handler:
-1:
-    j 1b
-
-.weak exception_handler
-exception_handler:
-2:
-    j 2b
diff --git a/sdk/bsp/trap_handler.c b/sdk/bsp/trap_handler.c
deleted file mode 100644
index d74a119..0000000
--- a/sdk/bsp/trap_handler.c
+++ /dev/null
@@ -1,18 +0,0 @@
-#include <stdint.h>
-
-#include "./include/trap_code.h"
-
-extern void timer0_irq_handler() __attribute__((weak));
-
-
-void interrupt_handler(uint32_t mcause, uint32_t mepc)
-{
-    // we have only timer0 interrupt here
-    timer0_irq_handler();
-}
-
-void exception_handler(uint32_t mcause, uint32_t mepc)
-{
-    if ((mcause != TRAP_BREAKPOINT) && (mcause != TRAP_ECALL_M))
-        while (1);
-}
diff --git a/sdk/bsp/vector_table.S b/sdk/bsp/vector_table.S
new file mode 100644
index 0000000..d4d3345
--- /dev/null
+++ b/sdk/bsp/vector_table.S
@@ -0,0 +1,91 @@
+
+    .section      .text.vector
+    .align 2
+    .global vector_table
+vector_table:
+    .org 0x00
+    jal x0, illegal_instruction_handler
+    jal x0, instruction_addr_misaligned_handler
+    jal x0, ecall_handler
+    jal x0, ebreak_handler
+    jal x0, load_misaligned_handler
+    jal x0, store_misaligned_handler
+    jal x0, handle_exception_unknown
+    jal x0, handle_exception_unknown
+    jal x0, external_irq_handler
+    jal x0, software_irq_handler
+    jal x0, timer_irq_handler
+    jal x0, fast_irq0_handler
+    jal x0, fast_irq1_handler
+    jal x0, fast_irq2_handler
+    jal x0, fast_irq3_handler
+    jal x0, fast_irq4_handler
+    .rept 10
+    jal x0, fast_irq_handler
+    .endr
+
+
+.weak illegal_instruction_handler
+.weak instruction_addr_misaligned_handler
+.weak ecall_handler
+.weak ebreak_handler
+.weak load_misaligned_handler
+.weak store_misaligned_handler
+.weak handle_exception_unknown
+.weak external_irq_handler
+.weak software_irq_handler
+.weak timer_irq_handler
+.weak fast_irq0_handler
+.weak fast_irq1_handler
+.weak fast_irq2_handler
+.weak fast_irq3_handler
+.weak fast_irq4_handler
+.weak fast_irq_handler
+
+handle_exception_unknown:
+    j handle_exception_unknown
+
+illegal_instruction_handler:
+    j illegal_instruction_handler
+
+instruction_addr_misaligned_handler:
+    j instruction_addr_misaligned_handler
+
+ecall_handler:
+    j ecall_handler
+
+ebreak_handler:
+    j ebreak_handler
+
+load_misaligned_handler:
+    j load_misaligned_handler
+
+store_misaligned_handler:
+    j store_misaligned_handler
+
+external_irq_handler:
+    j external_irq_handler
+
+software_irq_handler:
+    j software_irq_handler
+
+timer_irq_handler:
+    j timer_irq_handler
+
+fast_irq0_handler:
+    j fast_irq0_handler
+
+fast_irq1_handler:
+    j fast_irq1_handler
+
+fast_irq2_handler:
+    j fast_irq2_handler
+
+fast_irq3_handler:
+    j fast_irq3_handler
+
+fast_irq4_handler:
+    j fast_irq4_handler
+
+fast_irq_handler:
+    j fast_irq_handler