diff --git a/README.md b/README.md
index 161e690..16c58aa 100644
--- a/README.md
+++ b/README.md
@@ -32,7 +32,7 @@
 
 **tests**：该目录包含测试程序源码，其中example目录为C语言程序例程源码，isa目录为RV32指令测试源码；
 
-**tools**：该目录包含编译汇编和C语言程序所需GNU工具链和将二进制文件转成仿真所需的mem格式文件的工具BinToMem，还有通过串口下载程序的脚本。BinToMem\_CLI.exe需要在cmd窗口下执行，BinToMem\_GUI.exe提供图形界面，双击即可运行；
+**tools**：该目录包含编译汇编和C语言程序所需GNU工具链和将二进制文件转成仿真所需的mem格式文件的脚本，还有通过串口下载程序的脚本。
 
 **pic**：存放图片；
 
@@ -54,7 +54,7 @@ tinyriscv目前外挂了6个外设，每个外设的空间大小为256MB，地
 
 ![tinyriscv跑分](./pic/tinyriscv_coremark.png)
 
-可知，tinyriscv的跑分成绩为2.4。此成绩是基于指令在rom存储和数据在ram存储的情况下得出的，如果指令和数据都在ram的话跑分上3.0问题应该不大。
+可知，tinyriscv的跑分成绩为2.4。
 
 选了几款其他MCU的跑分结果如下图所示：
 
@@ -64,9 +64,9 @@ tinyriscv目前外挂了6个外设，每个外设的空间大小为256MB，地
 
 # 4.如何使用
 
-本项目运行在windows平台，编译仿真工具使用的是iverilog和vpp，波形查看工具使用的是gtkwave。
+本项目可以运行在Windows和Linux平台(macOS平台理论上也是可以的)，编译仿真工具使用的是iverilog和vpp，波形查看工具使用的是gtkwave。
 
-## 4.1安装环境
+## 4.1Windows平台环境搭建
 
 在使用之前需要安装以下工具：
 
@@ -88,15 +88,56 @@ tinyriscv目前外挂了6个外设，每个外设的空间大小为256MB，地
 
 到[python官网](https://www.python.org/)下载win版本的python，注意要下载python3版本的。网速慢的同学可以通过百度网盘下载(链接: https://pan.baidu.com/s/1gNC8L5dZTsN6E5TJD2rmnQ 提取码: 3b4t)，或者通过微云下载[https://share.weiyun.com/XwzSQHND](https://share.weiyun.com/XwzSQHND)。安装完后将python添加到环境变量里。
 
-5. 下载代码
+5. 下载tinyriscv代码
 
-使用git clone命令下载，不要使用zip方式下载，否则有些文件会有格式问题。
+**使用git clone命令下载，不要使用zip方式下载**，否则有些文件会有格式问题。
 
 `git clone https://gitee.com/liangkangnan/tinyriscv.git`
 
-## 4.2运行指令测试程序
+## 4.2Linux平台环境搭建
 
-### 4.2.1 运行旧的指令测试程序
+这里以Ubuntu系统为例进行说明。
+
+1. 下载iverilog源码
+
+`git clone https://github.com/steveicarus/iverilog.git`
+
+2. 切换到v11分支(必须用V11或以上的版本)
+
+`git checkout v11-branch`
+
+3. 安装依赖
+
+`sudo apt-get install autoconf gperf flex bison build-essential`
+
+4. 编译、安装iverilog和vvp
+
+```
+sh autoconf.sh
+./configure
+make
+make install
+```
+
+5. 创建python软链接
+
+`sudo ln -s /usr/bin/python3.8 /usr/bin/python`
+
+其中/usr/bin/python3.8对应你实际安装的python版本。
+
+6. 安装gtkwave
+
+`sudo apt-get install gtkwave`
+
+**注意：**如果使用其他版本的GNU工具链，可以自行修改tests/example/common.mk文件里的这几行内容：
+
+![toolchain](./pic/toolchain.png)
+
+## 4.3运行指令测试程序
+
+这里以Windows平台为例进行说明，Linux平台是类似的。
+
+### 4.3.1 运行旧的指令测试程序
 
 旧的指令测试程序属于比较早的指令兼容性测试方法，虽然目前RISC-V官方已经不更新了，但仍然是一个比较好的测试参考。
 
@@ -104,7 +145,7 @@ tinyriscv目前外挂了6个外设，每个外设的空间大小为256MB，地
 
 打开CMD窗口，进入到sim目录，执行以下命令：
 
-```sim_new_nowave.bat ..\tests\isa\generated\rv32ui-p-add.bin inst.data```
+```python .\sim_new_nowave.py ..\tests\isa\generated\rv32ui-p-add.bin inst.data```
 
 如果运行成功的话就可以看到"PASS"的打印。其他指令使用方法类似。
 
@@ -116,7 +157,7 @@ tinyriscv目前外挂了6个外设，每个外设的空间大小为256MB，地
 
 `python .\test_all_isa.py`
 
-### 4.2.2运行新的指令测试程序
+### 4.3.2运行新的指令测试程序
 
 新的指令兼容性([riscv-compliance](https://github.com/riscv/riscv-compliance))测试项相对于旧的指令兼容性测试项来说对指令的测试更加严谨，可以精确到每一条指令的运行结果，而且RISC-V官方一直在更新。
 
@@ -124,13 +165,13 @@ tinyriscv目前外挂了6个外设，每个外设的空间大小为256MB，地
 
 打开CMD窗口，进入到sim/compliance_test目录，执行以下命令：
 
-`python compliance_test.py ..\..\tests\riscv-compliance\build_generated\rv32i\I-ADD-01.elf.bin inst.data`
+`python .\compliance_test.py ..\..\tests\riscv-compliance\build_generated\rv32i\I-ADD-01.elf.bin inst.data`
 
 如果运行成功的话就可以看到"PASS"的打印。其他指令使用方法类似。
 
 ![new_test_output](./pic/new_test_output.png)
 
-## 4.3运行C语言程序
+## 4.4运行C语言程序
 
 C语言程序例程位于tests\example目录里。
 
@@ -142,7 +183,7 @@ C语言程序例程位于tests\example目录里。
 
 编译成功之后，进入到sim目录，执行以下命令开始测试：
 
-` .\sim_new_nowave.bat ..\tests\example\simple\simple.bin inst.data`
+` python .\sim_new_nowave.py ..\tests\example\simple\simple.bin inst.data`
 
 # 5.移植到FPGA
 
@@ -157,6 +198,8 @@ C语言程序例程位于tests\example目录里。
 
 # 7.更新记录
 
+2020-10-25：支持Linux平台；
+
 2020-07-04：支持通过UART烧写固件；
 
 2020-05-27：增加新的指令兼容性(riscv-compliance)测试项。
diff --git a/pic/new_test_output.png b/pic/new_test_output.png
index b041c61..ace91ff 100644
Binary files a/pic/new_test_output.png and b/pic/new_test_output.png differ
diff --git a/pic/test_output.png b/pic/test_output.png
index c0889c2..d9194b9 100644
Binary files a/pic/test_output.png and b/pic/test_output.png differ
diff --git a/pic/toolchain.png b/pic/toolchain.png
new file mode 100644
index 0000000..4b289db
Binary files /dev/null and b/pic/toolchain.png differ
diff --git a/sim/README.md b/sim/README.md
index 842b6fe..a3edbea 100644
--- a/sim/README.md
+++ b/sim/README.md
@@ -1,22 +1,40 @@
-# sim_new_nowave.bat
+# compile_rtl.py
+
+编译rtl代码。
+
+使用方法：
+
+`python compile_rtl.py [rtl目录相对路径]`
+
+比如：
+
+`python compile_rtl.py ..`
+
+# sim_new_nowave.py
 
 对指定的bin文件(重新生成inst.data文件)进行测试。
 
 使用方法：
 
-`sim_new_nowave.bat ..\tests\isa\generated\rv32ui-p-add.bin inst.data`
+windows系统下：
 
-# sim_default_nowave.bat
+`python sim_new_nowave.py ..\tests\isa\generated\rv32ui-p-add.bin inst.data`
+
+Linux系统下：
+
+`python sim_new_nowave.py ../tests/isa/generated/rv32ui-p-add.bin inst.data`
+
+# sim_default_nowave.py
 
 对已经存在的inst.data文件进行测试。
 
 使用方法：
 
-`sim_default_nowave.bat`
+`python sim_default_nowave.py`
 
 # test_all_isa.py
 
-一次性测试所有指令。
+一次性测试../tests/isa/generated目录下的所有指令。
 
 使用方法：
 
diff --git a/sim/compile_rtl.py b/sim/compile_rtl.py
new file mode 100644
index 0000000..3686eac
--- /dev/null
+++ b/sim/compile_rtl.py
@@ -0,0 +1,68 @@
+import sys
+import filecmp
+import subprocess
+import sys
+import os
+
+
+# 主函数
+def main():
+    rtl_dir = sys.argv[1]
+
+    if rtl_dir != r'..':
+        tb_file = r'/tb/compliance_test/tinyriscv_soc_tb.v'
+    else:
+        tb_file = r'/tb/tinyriscv_soc_tb.v'
+
+    # iverilog程序
+    iverilog_cmd = ['iverilog']
+    # 顶层模块
+    #iverilog_cmd += ['-s', r'tinyriscv_soc_tb']
+    # 编译生成文件
+    iverilog_cmd += ['-o', r'out.vvp']
+    # 头文件(defines.v)路径
+    iverilog_cmd += ['-I', rtl_dir + r'/rtl/core']
+    # 宏定义，仿真输出文件
+    iverilog_cmd += ['-D', r'OUTPUT="signature.output"']
+    # testbench文件
+    iverilog_cmd.append(rtl_dir + tb_file)
+    # ../rtl/core
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/clint.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/csr_reg.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/ctrl.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/defines.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/div.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/ex.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/id.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/id_ex.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/if_id.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/pc_reg.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/regs.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/rib.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/core/tinyriscv.v')
+    # ../rtl/perips
+    iverilog_cmd.append(rtl_dir + r'/rtl/perips/ram.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/perips/rom.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/perips/timer.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/perips/uart.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/perips/gpio.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/perips/spi.v')
+    # ../rtl/debug
+    iverilog_cmd.append(rtl_dir + r'/rtl/debug/jtag_dm.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/debug/jtag_driver.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/debug/jtag_top.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/debug/uart_debug.v')
+    # ../rtl/soc
+    iverilog_cmd.append(rtl_dir + r'/rtl/soc/tinyriscv_soc_top.v')
+    # ../rtl/utils
+    iverilog_cmd.append(rtl_dir + r'/rtl/utils/full_handshake_rx.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/utils/full_handshake_tx.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/utils/gen_buf.v')
+    iverilog_cmd.append(rtl_dir + r'/rtl/utils/gen_dff.v')
+
+    # 编译
+    process = subprocess.Popen(iverilog_cmd)
+    process.wait(timeout=5)
+
+if __name__ == '__main__':
+    sys.exit(main())
diff --git a/sim/compliance_test/README.md b/sim/compliance_test/README.md
index e5dc50a..2ff6b19 100644
--- a/sim/compliance_test/README.md
+++ b/sim/compliance_test/README.md
@@ -2,4 +2,10 @@
 
 使用方法：
 
-`python compliance_test.py ..\..\tests\riscv-compliance\build_generated\rv32i\I-ADD-01.elf.bin inst.data`
\ No newline at end of file
+Windows系统下：
+
+`python compliance_test.py ..\..\tests\riscv-compliance\build_generated\rv32i\I-ADD-01.elf.bin inst.data`
+
+Linux系统下：
+
+`python compliance_test.py ../../tests/riscv-compliance/build_generated/rv32i/I-ADD-01.elf.bin inst.data`
\ No newline at end of file
diff --git a/sim/compliance_test/compliance_test.py b/sim/compliance_test/compliance_test.py
index ad7cfa5..01c679e 100644
--- a/sim/compliance_test/compliance_test.py
+++ b/sim/compliance_test/compliance_test.py
@@ -1,57 +1,10 @@
+import sys
 import filecmp
 import subprocess
 import sys
 import os
 
 
-# iverilog程序
-iverilog_cmd = ['iverilog']
-# 顶层模块
-#iverilog_cmd += ['-s', r'tinyriscv_soc_tb']
-# 编译生成文件
-iverilog_cmd += ['-o', r'out.vvp']
-# 头文件(defines.v)路径
-iverilog_cmd += ['-I', r'..\..\rtl\core']
-# 宏定义，仿真输出文件
-iverilog_cmd += ['-D', r'OUTPUT="signature.output"']
-# testbench文件
-iverilog_cmd.append(r'..\..\tb\compliance_test\tinyriscv_soc_tb.v')
-# ..\rtl\core
-iverilog_cmd.append(r'..\..\rtl\core\defines.v')
-iverilog_cmd.append(r'..\..\rtl\core\ex.v')
-iverilog_cmd.append(r'..\..\rtl\core\id.v')
-iverilog_cmd.append(r'..\..\rtl\core\tinyriscv.v')
-iverilog_cmd.append(r'..\..\rtl\core\pc_reg.v')
-iverilog_cmd.append(r'..\..\rtl\core\id_ex.v')
-iverilog_cmd.append(r'..\..\rtl\core\ctrl.v')
-iverilog_cmd.append(r'..\..\rtl\core\regs.v')
-iverilog_cmd.append(r'..\..\rtl\core\if_id.v')
-iverilog_cmd.append(r'..\..\rtl\core\div.v')
-iverilog_cmd.append(r'..\..\rtl\core\rib.v')
-iverilog_cmd.append(r'..\..\rtl\core\clint.v')
-iverilog_cmd.append(r'..\..\rtl\core\csr_reg.v')
-# ..\rtl\perips
-iverilog_cmd.append(r'..\..\rtl\perips\ram.v')
-iverilog_cmd.append(r'..\..\rtl\perips\rom.v')
-iverilog_cmd.append(r'..\..\rtl\perips\spi.v')
-iverilog_cmd.append(r'..\..\rtl\perips\timer.v')
-iverilog_cmd.append(r'..\..\rtl\perips\uart.v')
-iverilog_cmd.append(r'..\..\rtl\perips\gpio.v')
-# ..\rtl\debug
-iverilog_cmd.append(r'..\..\rtl\debug\jtag_dm.v')
-iverilog_cmd.append(r'..\..\rtl\debug\jtag_driver.v')
-iverilog_cmd.append(r'..\..\rtl\debug\jtag_top.v')
-iverilog_cmd.append(r'..\..\rtl\debug\uart_debug.v')
-# ..rtl\utils
-iverilog_cmd.append(r'..\..\rtl\utils\full_handshake_rx.v')
-iverilog_cmd.append(r'..\..\rtl\utils\full_handshake_tx.v')
-iverilog_cmd.append(r'..\..\rtl\utils\gen_buf.v')
-iverilog_cmd.append(r'..\..\rtl\utils\gen_dff.v')
-# ..\rtl\soc
-iverilog_cmd.append(r'..\..\rtl\soc\tinyriscv_soc_top.v')
-
-
-
 # 找出path目录下的所有reference_output文件
 def list_ref_files(path):
     files = []
@@ -74,13 +27,13 @@ def get_reference_file(bin_file):
 
     files = []
     if (bin_file.find('rv32im') != -1):
-        files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32im\references')
+        files = list_ref_files(r'../../tests/riscv-compliance/riscv-test-suite/rv32im/references')
     elif (bin_file.find('rv32i') != -1):
-        files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32i\references')
+        files = list_ref_files(r'../../tests/riscv-compliance/riscv-test-suite/rv32i/references')
     elif (bin_file.find('rv32Zicsr') != -1):
-        files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32Zicsr\references')
+        files = list_ref_files(r'../../tests/riscv-compliance/riscv-test-suite/rv32Zicsr/references')
     elif (bin_file.find('rv32Zifencei') != -1):
-        files = list_ref_files(r'..\..\tests\riscv-compliance\riscv-test-suite\rv32Zifencei\references')
+        files = list_ref_files(r'../../tests/riscv-compliance/riscv-test-suite/rv32Zifencei/references')
     else:
         return None
 
@@ -96,17 +49,14 @@ def main():
     #print(sys.argv[0] + ' ' + sys.argv[1] + ' ' + sys.argv[2])
 
     # 1.将bin文件转成mem文件
-    bin_to_mem_cmd = [r'..\..\tools\BinToMem_CLI.exe']
-    bin_to_mem_cmd.append(sys.argv[1])
-    bin_to_mem_cmd.append(sys.argv[2])
-    process = subprocess.Popen(bin_to_mem_cmd, stdout=subprocess.PIPE, stderr=subprocess.PIPE)
-    process.wait(timeout=5)
+    cmd = r'python ../../tools/BinToMem_CLI.py' + ' ' + sys.argv[1] + ' ' + sys.argv[2]
+    f = os.popen(cmd)
+    f.close()
 
     # 2.编译rtl文件
-    logfile = open('complie.log', 'w')
-    process = subprocess.Popen(iverilog_cmd, stdout=logfile, stderr=logfile)
-    process.wait(timeout=5)
-    logfile.close()
+    cmd = r'python ../compile_rtl.py' + r' ../..'
+    f = os.popen(cmd)
+    f.close()
 
     # 3.运行
     logfile = open('run.log', 'w')
@@ -121,7 +71,7 @@ def main():
     if (ref_file != None):
         # 如果文件大小不一致，直接报fail
         if (os.path.getsize('signature.output') != os.path.getsize(ref_file)):
-            print('!!! FAIL !!!')
+            print('!!! FAIL, size != !!!')
             return
         f1 = open('signature.output')
         f2 = open(ref_file)
@@ -131,7 +81,7 @@ def main():
         for line in f2.readlines():
             # 只要有一行内容不一样就报fail
             if (f1_lines[i] != line):
-                print('!!! FAIL !!!')
+                print('!!! FAIL, content != !!!')
                 f1.close()
                 f2.close()
                 return
@@ -142,6 +92,5 @@ def main():
     else:
         print('No ref file found, please check result by yourself.')
 
-
 if __name__ == '__main__':
     sys.exit(main())
diff --git a/sim/sim_default_nowave.bat b/sim/sim_default_nowave.bat
deleted file mode 100644
index 6407954..0000000
--- a/sim/sim_default_nowave.bat
+++ /dev/null
@@ -1,2 +0,0 @@
-iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\utils\gen_dff.v ..\rtl\utils\gen_buf.v ..\rtl\utils\full_handshake_rx.v ..\rtl\utils\full_handshake_tx.v ..\rtl\soc\tinyriscv_soc_top.v
-vvp out.vvp
diff --git a/sim/sim_default_nowave.py b/sim/sim_default_nowave.py
new file mode 100644
index 0000000..b0bc422
--- /dev/null
+++ b/sim/sim_default_nowave.py
@@ -0,0 +1,28 @@
+import sys
+import filecmp
+import subprocess
+import sys
+import os
+
+
+# 主函数
+def main():
+    #print(sys.argv[0] + ' ' + sys.argv[1] + ' ' + sys.argv[2])
+
+    # 1.编译rtl文件
+    cmd = r'python compile_rtl.py' + r' ..'
+    f = os.popen(cmd)
+    f.close()
+
+    # 2.运行
+    vvp_cmd = [r'vvp']
+    vvp_cmd.append(r'out.vvp')
+    process = subprocess.Popen(vvp_cmd)
+    try:
+        process.wait(timeout=10)
+    except subprocess.TimeoutExpired:
+        print('!!!Fail, vvp exec timeout!!!')
+
+
+if __name__ == '__main__':
+    sys.exit(main())
diff --git a/sim/sim_new_nowave.bat b/sim/sim_new_nowave.bat
deleted file mode 100644
index 23c562b..0000000
--- a/sim/sim_new_nowave.bat
+++ /dev/null
@@ -1,3 +0,0 @@
-..\tools\BinToMem_CLI.exe %1 %2
-iverilog -o out.vvp -I ..\rtl\core ..\tb\tinyriscv_soc_tb.v ..\rtl\core\defines.v ..\rtl\core\ex.v ..\rtl\core\id.v ..\rtl\core\tinyriscv.v ..\rtl\core\pc_reg.v ..\rtl\core\id_ex.v ..\rtl\core\ctrl.v ..\rtl\core\regs.v ..\rtl\perips\ram.v ..\rtl\perips\rom.v ..\rtl\perips\spi.v ..\rtl\core\if_id.v ..\rtl\core\div.v ..\rtl\core\rib.v ..\rtl\core\clint.v ..\rtl\core\csr_reg.v ..\rtl\debug\jtag_dm.v ..\rtl\debug\jtag_driver.v ..\rtl\debug\jtag_top.v ..\rtl\debug\uart_debug.v ..\rtl\perips\timer.v ..\rtl\perips\uart.v ..\rtl\perips\gpio.v ..\rtl\utils\gen_dff.v ..\rtl\utils\gen_buf.v ..\rtl\utils\full_handshake_rx.v ..\rtl\utils\full_handshake_tx.v ..\rtl\soc\tinyriscv_soc_top.v
-vvp out.vvp
diff --git a/sim/sim_new_nowave.py b/sim/sim_new_nowave.py
new file mode 100644
index 0000000..83885cd
--- /dev/null
+++ b/sim/sim_new_nowave.py
@@ -0,0 +1,33 @@
+import sys
+import filecmp
+import subprocess
+import sys
+import os
+
+
+# 主函数
+def main():
+    #print(sys.argv[0] + ' ' + sys.argv[1] + ' ' + sys.argv[2])
+
+    # 1.将bin文件转成mem文件
+    cmd = r'python ../tools/BinToMem_CLI.py' + ' ' + sys.argv[1] + ' ' + sys.argv[2]
+    f = os.popen(cmd)
+    f.close()
+
+    # 2.编译rtl文件
+    cmd = r'python compile_rtl.py' + r' ..'
+    f = os.popen(cmd)
+    f.close()
+
+    # 3.运行
+    vvp_cmd = [r'vvp']
+    vvp_cmd.append(r'out.vvp')
+    process = subprocess.Popen(vvp_cmd)
+    try:
+        process.wait(timeout=20)
+    except subprocess.TimeoutExpired:
+        print('!!!Fail, vvp exec timeout!!!')
+
+
+if __name__ == '__main__':
+    sys.exit(main())
diff --git a/sim/test_all_isa.py b/sim/test_all_isa.py
index ccacf81..2f811f6 100644
--- a/sim/test_all_isa.py
+++ b/sim/test_all_isa.py
@@ -1,4 +1,7 @@
 import os
+import subprocess
+import sys
+
 
 # 找出path目录下的所有bin文件
 def list_binfiles(path):
@@ -12,25 +15,29 @@ def list_binfiles(path):
 
     return files
 
+# 主函数
+def main():
+    bin_files = list_binfiles(r'../tests/isa/generated')
 
-files = list_binfiles('..\\tests\\isa\\generated')
+    anyfail = False
+
+    # 对每一个bin文件进行测试
+    for file in bin_files:
+        #print(file)
+        cmd = r'python sim_new_nowave.py' + ' ' + file + ' ' + 'inst.data'
+        f = os.popen(cmd)
+        r = f.read()
+        f.close()
+        if (r.find('TEST_PASS') != -1):
+            print(file + '    PASS')
+        else:
+            print(file + '    !!!FAIL!!!')
+            anyfail = True
+            break
+
+    if (anyfail == False):
+        print('Congratulation, All PASS...')
 
 
-anyfail = False
-
-# 对每一个bin文件进行测试
-for file in files:
-    #print(file)
-    cmd = '.\\sim_new_nowave.bat ' + file + ' inst.data'
-    f = os.popen(cmd)
-    r = f.read()
-    f.close()
-    if (r.find('TEST_PASS') != -1):
-        print(file + '    PASS')
-    else:
-        print(file + '    !!!FAIL!!!')
-        anyfail = True
-        break
-
-if (anyfail == False):
-    print('Congratulation, All PASS...')
+if __name__ == '__main__':
+    sys.exit(main())
diff --git a/tools/.gitignore b/tools/.gitignore
index 01bf5d9..54994ec 100644
--- a/tools/.gitignore
+++ b/tools/.gitignore
@@ -3,4 +3,5 @@
 *.ko
 *.obj
 
+__pycache__
 gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64
\ No newline at end of file
diff --git a/tools/BinToMem_CLI.exe b/tools/BinToMem_CLI.exe
deleted file mode 100644
index ac002bb..0000000
Binary files a/tools/BinToMem_CLI.exe and /dev/null differ
diff --git a/tools/BinToMem_GUI.exe b/tools/BinToMem_GUI.exe
deleted file mode 100644
index f479f97..0000000
Binary files a/tools/BinToMem_GUI.exe and /dev/null differ