diff --git a/sdk/examples/timer/Makefile b/sdk/examples/timer/Makefile
index 7a522ae..b68f70f 100644
--- a/sdk/examples/timer/Makefile
+++ b/sdk/examples/timer/Makefile
@@ -6,7 +6,7 @@ RISCV_MCMODEL := medlow
 TARGET = timer
 
 
-#CFLAGS += -DSIMULATION
+CFLAGS += -DSIMULATION
 #CFLAGS += -Os
 #ASM_SRCS +=
 #LDFLAGS +=
diff --git a/sdk/examples/timer/main.c b/sdk/examples/timer/main.c
index 6fa3cd8..12a922e 100644
--- a/sdk/examples/timer/main.c
+++ b/sdk/examples/timer/main.c
@@ -17,6 +17,7 @@ int main()
     timer0_clear_int_pending();
     timer0_set_int_enable(1);
     timer0_set_mode_auto_reload();
+    rvic_set_irq_prio_level(0, 1);
     global_irq_enable();
     rvic_irq_enable(0);
     timer0_start(1);
@@ -37,6 +38,7 @@ int main()
     timer0_clear_int_pending();
     timer0_set_int_enable(1);
     timer0_set_mode_auto_reload();
+    rvic_set_irq_prio_level(0, 1);
     global_irq_enable();
     rvic_irq_enable(0);
     timer0_start(1);