parent
ad5adcb843
commit
79f83c1ad4
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@ -6,7 +6,7 @@ RISCV_MCMODEL := medlow
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TARGET = timer
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TARGET = timer
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#CFLAGS += -DSIMULATION
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CFLAGS += -DSIMULATION
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#CFLAGS += -Os
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#CFLAGS += -Os
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#ASM_SRCS +=
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#ASM_SRCS +=
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#LDFLAGS +=
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#LDFLAGS +=
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@ -17,6 +17,7 @@ int main()
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timer0_clear_int_pending();
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timer0_clear_int_pending();
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timer0_set_int_enable(1);
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timer0_set_int_enable(1);
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timer0_set_mode_auto_reload();
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timer0_set_mode_auto_reload();
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rvic_set_irq_prio_level(0, 1);
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global_irq_enable();
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global_irq_enable();
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rvic_irq_enable(0);
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rvic_irq_enable(0);
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timer0_start(1);
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timer0_start(1);
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@ -37,6 +38,7 @@ int main()
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timer0_clear_int_pending();
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timer0_clear_int_pending();
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timer0_set_int_enable(1);
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timer0_set_int_enable(1);
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timer0_set_mode_auto_reload();
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timer0_set_mode_auto_reload();
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rvic_set_irq_prio_level(0, 1);
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global_irq_enable();
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global_irq_enable();
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rvic_irq_enable(0);
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rvic_irq_enable(0);
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timer0_start(1);
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timer0_start(1);
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