diff --git a/rtl/core/clint.v b/rtl/core/clint.v index d93966a..fca6af1 100644 --- a/rtl/core/clint.v +++ b/rtl/core/clint.v @@ -83,16 +83,16 @@ module clint( // ÖжÏÖÙ²ÃÂß¼­ always @ (*) begin if (rst == `RstEnable) begin - int_state <= S_INT_IDLE; + int_state = S_INT_IDLE; end else begin if (inst_i == `INST_ECALL) begin - int_state <= S_INT_SYNC_ASSERT; + int_state = S_INT_SYNC_ASSERT; end else if (int_flag_i != `INT_NONE && global_int_en_i == `True) begin - int_state <= S_INT_ASYNC_ASSERT; + int_state = S_INT_ASYNC_ASSERT; end else if (inst_i == `INST_MRET) begin - int_state <= S_INT_MRET; + int_state = S_INT_MRET; end else begin - int_state <= S_INT_IDLE; + int_state = S_INT_IDLE; end end end diff --git a/rtl/core/csr_reg.v b/rtl/core/csr_reg.v index 8cc5b64..1c41503 100644 --- a/rtl/core/csr_reg.v +++ b/rtl/core/csr_reg.v @@ -135,32 +135,32 @@ module csr_reg( // ex模å—读CSR寄存器 always @ (*) begin if (rst == `RstEnable) begin - data_o <= `ZeroWord; + data_o = `ZeroWord; end else begin case (raddr_i[11:0]) `CSR_CYCLE: begin - data_o <= cycle[31:0]; + data_o = cycle[31:0]; end `CSR_CYCLEH: begin - data_o <= cycle[63:32]; + data_o = cycle[63:32]; end `CSR_MTVEC: begin - data_o <= mtvec; + data_o = mtvec; end `CSR_MCAUSE: begin - data_o <= mcause; + data_o = mcause; end `CSR_MEPC: begin - data_o <= mepc; + data_o = mepc; end `CSR_MIE: begin - data_o <= mie; + data_o = mie; end `CSR_MSTATUS: begin - data_o <= mstatus; + data_o = mstatus; end default: begin - data_o <= `ZeroWord; + data_o = `ZeroWord; end endcase end diff --git a/rtl/core/ctrl.v b/rtl/core/ctrl.v index 9a2aaad..4abdc49 100644 --- a/rtl/core/ctrl.v +++ b/rtl/core/ctrl.v @@ -47,26 +47,26 @@ module ctrl( always @ (*) begin if (rst == `RstEnable) begin - hold_flag_o <= `Hold_None; - jump_flag_o <= `JumpDisable; - jump_addr_o <= `ZeroWord; + hold_flag_o = `Hold_None; + jump_flag_o = `JumpDisable; + jump_addr_o = `ZeroWord; end else begin - jump_addr_o <= jump_addr_i; - jump_flag_o <= jump_flag_i; + jump_addr_o = jump_addr_i; + jump_flag_o = jump_flag_i; // 默认ä¸æš‚åœ - hold_flag_o <= `Hold_None; + hold_flag_o = `Hold_None; // 按优先级处ç†ä¸åŒæ¨¡å—的请求 if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable || hold_flag_clint_i == `HoldEnable) begin // æš‚åœæ•´æ¡æµæ°´çº¿ - hold_flag_o <= `Hold_Id; + hold_flag_o = `Hold_Id; end else if (hold_flag_rib_i == `HoldEnable) begin // æš‚åœPC，å³å–指地å€ä¸å˜ - hold_flag_o <= `Hold_Pc; + hold_flag_o = `Hold_Pc; end else if (jtag_halt_flag_i == `HoldEnable) begin // æš‚åœæ•´æ¡æµæ°´çº¿ - hold_flag_o <= `Hold_Id; + hold_flag_o = `Hold_Id; end else begin - hold_flag_o <= `Hold_None; + hold_flag_o = `Hold_None; end end end diff --git a/rtl/core/ex.v b/rtl/core/ex.v index 713dc94..8093206 100644 --- a/rtl/core/ex.v +++ b/rtl/core/ex.v @@ -145,35 +145,31 @@ module ex( // 处ç†ä¹˜æ³•æŒ‡ä»¤ always @ (*) begin if (rst == `RstEnable) begin - mul_op1 <= `ZeroWord; - mul_op2 <= `ZeroWord; + mul_op1 = `ZeroWord; + mul_op2 = `ZeroWord; end else begin if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin case (funct3) - `INST_MUL: begin - mul_op1 <= reg1_rdata_i; - mul_op2 <= reg2_rdata_i; - end - `INST_MULHU: begin - mul_op1 <= reg1_rdata_i; - mul_op2 <= reg2_rdata_i; + `INST_MUL, `INST_MULHU: begin + mul_op1 = reg1_rdata_i; + mul_op2 = reg2_rdata_i; end `INST_MULHSU: begin - mul_op1 <= (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i; - mul_op2 <= reg2_rdata_i; + mul_op1 = (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i; + mul_op2 = reg2_rdata_i; end `INST_MULH: begin - mul_op1 <= (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i; - mul_op2 <= (reg2_rdata_i[31] == 1'b1)? (~reg2_rdata_i + 1): reg2_rdata_i; + mul_op1 = (reg1_rdata_i[31] == 1'b1)? (~reg1_rdata_i + 1): reg1_rdata_i; + mul_op2 = (reg2_rdata_i[31] == 1'b1)? (~reg2_rdata_i + 1): reg2_rdata_i; end default: begin - mul_op1 <= reg1_rdata_i; - mul_op2 <= reg2_rdata_i; + mul_op1 = reg1_rdata_i; + mul_op2 = reg2_rdata_i; end endcase end else begin - mul_op1 <= reg1_rdata_i; - mul_op2 <= reg2_rdata_i; + mul_op1 = reg1_rdata_i; + mul_op2 = reg2_rdata_i; end end end @@ -181,256 +177,239 @@ module ex( // 处ç†é™¤æ³•æŒ‡ä»¤ always @ (*) begin if (rst == `RstEnable) begin - div_dividend_o <= `ZeroWord; - div_divisor_o <= `ZeroWord; - div_op_o <= 3'b0; - div_reg_waddr_o <= `ZeroWord; - div_waddr <= `ZeroWord; - div_hold_flag <= `HoldDisable; - div_we <= `WriteDisable; - div_wdata <= `ZeroWord; - div_start <= `DivStop; - div_jump_flag <= `JumpDisable; - div_jump_addr <= `ZeroWord; + div_dividend_o = `ZeroWord; + div_divisor_o = `ZeroWord; + div_op_o = 3'b0; + div_reg_waddr_o = `ZeroWord; + div_waddr = `ZeroWord; + div_hold_flag = `HoldDisable; + div_we = `WriteDisable; + div_wdata = `ZeroWord; + div_start = `DivStop; + div_jump_flag = `JumpDisable; + div_jump_addr = `ZeroWord; end else begin - div_dividend_o <= reg1_rdata_i; - div_divisor_o <= reg2_rdata_i; - div_op_o <= funct3; - div_reg_waddr_o <= reg_waddr_i; + div_dividend_o = reg1_rdata_i; + div_divisor_o = reg2_rdata_i; + div_op_o = funct3; + div_reg_waddr_o = reg_waddr_i; if ((opcode == `INST_TYPE_R_M) && (funct7 == 7'b0000001)) begin - div_we <= `WriteDisable; - div_wdata <= `ZeroWord; - div_waddr <= `ZeroWord; + div_we = `WriteDisable; + div_wdata = `ZeroWord; + div_waddr = `ZeroWord; case (funct3) - `INST_DIV: begin - div_start <= `DivStart; - div_jump_flag <= `JumpEnable; - div_hold_flag <= `HoldEnable; - div_jump_addr <= inst_addr_i + 4'h4; - end - `INST_DIVU: begin - div_start <= `DivStart; - div_jump_flag <= `JumpEnable; - div_hold_flag <= `HoldEnable; - div_jump_addr <= inst_addr_i + 4'h4; - end - `INST_REM: begin - div_start <= `DivStart; - div_jump_flag <= `JumpEnable; - div_hold_flag <= `HoldEnable; - div_jump_addr <= inst_addr_i + 4'h4; - end - `INST_REMU: begin - div_start <= `DivStart; - div_jump_flag <= `JumpEnable; - div_hold_flag <= `HoldEnable; - div_jump_addr <= inst_addr_i + 4'h4; + `INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin + div_start = `DivStart; + div_jump_flag = `JumpEnable; + div_hold_flag = `HoldEnable; + div_jump_addr = inst_addr_i + 4'h4; end default: begin - div_start <= `DivStop; - div_jump_flag <= `JumpDisable; - div_hold_flag <= `HoldDisable; - div_jump_addr <= `ZeroWord; + div_start = `DivStop; + div_jump_flag = `JumpDisable; + div_hold_flag = `HoldDisable; + div_jump_addr = `ZeroWord; end endcase end else begin - div_jump_flag <= `JumpDisable; - div_jump_addr <= `ZeroWord; + div_jump_flag = `JumpDisable; + div_jump_addr = `ZeroWord; if (div_busy_i == `True) begin - div_start <= `DivStart; - div_we <= `WriteDisable; - div_wdata <= `ZeroWord; - div_waddr <= `ZeroWord; - div_hold_flag <= `HoldEnable; + div_start = `DivStart; + div_we = `WriteDisable; + div_wdata = `ZeroWord; + div_waddr = `ZeroWord; + div_hold_flag = `HoldEnable; end else begin - div_start <= `DivStop; - div_hold_flag <= `HoldDisable; + div_start = `DivStop; + div_hold_flag = `HoldDisable; if (div_ready_i == `DivResultReady) begin case (div_op_i) - `INST_DIV: begin - div_wdata <= div_result_i[31:0]; - div_waddr <= div_reg_waddr_i; - div_we <= `WriteEnable; + `INST_DIV, `INST_DIVU: begin + div_wdata = div_result_i[31:0]; + div_waddr = div_reg_waddr_i; + div_we = `WriteEnable; end - `INST_DIVU: begin - div_wdata <= div_result_i[31:0]; - div_waddr <= div_reg_waddr_i; - div_we <= `WriteEnable; - end - `INST_REM: begin - div_wdata <= div_result_i[63:32]; - div_waddr <= div_reg_waddr_i; - div_we <= `WriteEnable; - end - `INST_REMU: begin - div_wdata <= div_result_i[63:32]; - div_waddr <= div_reg_waddr_i; - div_we <= `WriteEnable; + `INST_REM, `INST_REMU: begin + div_wdata = div_result_i[63:32]; + div_waddr = div_reg_waddr_i; + div_we = `WriteEnable; end default: begin - div_wdata <= `ZeroWord; - div_waddr <= `ZeroWord; - div_we <= `WriteDisable; + div_wdata = `ZeroWord; + div_waddr = `ZeroWord; + div_we = `WriteDisable; end endcase end else begin - div_we <= `WriteDisable; - div_wdata <= `ZeroWord; - div_waddr <= `ZeroWord; + div_we = `WriteDisable; + div_wdata = `ZeroWord; + div_waddr = `ZeroWord; end end end end end + // 执行 always @ (*) begin if (rst == `RstEnable) begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - mem_req <= `RIB_NREQ; - reg_wdata <= `ZeroWord; - reg_we <= `WriteDisable; - reg_waddr <= `ZeroReg; - csr_wdata_o <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_req = `RIB_NREQ; + reg_wdata = `ZeroWord; + reg_we = `WriteDisable; + reg_waddr = `ZeroReg; + csr_wdata_o = `ZeroWord; end else begin - reg_we <= reg_we_i; - reg_waddr <= reg_waddr_i; - mem_req <= `RIB_NREQ; - csr_wdata_o <= `ZeroWord; + reg_we = reg_we_i; + reg_waddr = reg_waddr_i; + mem_req = `RIB_NREQ; + csr_wdata_o = `ZeroWord; case (opcode) `INST_TYPE_I: begin case (funct3) `INST_ADDI: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; end `INST_SLTI: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin - if (reg1_rdata_i < sign_extend_tmp) begin - reg_wdata <= 32'h00000001; - end else begin - reg_wdata <= 32'h00000000; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + case ({reg1_rdata_i[31], sign_extend_tmp[31]}) + 2'b11: begin + if (reg1_rdata_i < sign_extend_tmp) begin + reg_wdata = 32'h00000001; + end else begin + reg_wdata = 32'h00000000; + end end - end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin - reg_wdata <= 32'h00000001; - end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin - reg_wdata <= 32'h00000000; - end else begin - if (reg1_rdata_i < sign_extend_tmp) begin - reg_wdata <= 32'h00000001; - end else begin - reg_wdata <= 32'h00000000; + 2'b10: begin + reg_wdata = 32'h00000001; end - end + 2'b01: begin + reg_wdata = 32'h00000000; + end + default: begin + if (reg1_rdata_i < sign_extend_tmp) begin + reg_wdata = 32'h00000001; + end else begin + reg_wdata = 32'h00000000; + end + end + endcase end `INST_SLTIU: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin - if (reg1_rdata_i < sign_extend_tmp) begin - reg_wdata <= 32'h00000001; - end else begin - reg_wdata <= 32'h00000000; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + case ({reg1_rdata_i[31], sign_extend_tmp[31]}) + 2'b11: begin + if (reg1_rdata_i < sign_extend_tmp) begin + reg_wdata = 32'h00000001; + end else begin + reg_wdata = 32'h00000000; + end end - end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin - reg_wdata <= 32'h00000000; - end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin - reg_wdata <= 32'h00000001; - end else begin - if (reg1_rdata_i < sign_extend_tmp) begin - reg_wdata <= 32'h00000001; - end else begin - reg_wdata <= 32'h00000000; + 2'b10: begin + reg_wdata = 32'h00000000; end - end + 2'b01: begin + reg_wdata = 32'h00000001; + end + default: begin + if (reg1_rdata_i < sign_extend_tmp) begin + reg_wdata = 32'h00000001; + end else begin + reg_wdata = 32'h00000000; + end + end + endcase end `INST_XORI: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= reg1_rdata_i ^ {{20{inst_i[31]}}, inst_i[31:20]}; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i ^ {{20{inst_i[31]}}, inst_i[31:20]}; end `INST_ORI: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= reg1_rdata_i | {{20{inst_i[31]}}, inst_i[31:20]}; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i | {{20{inst_i[31]}}, inst_i[31:20]}; end `INST_ANDI: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= reg1_rdata_i & {{20{inst_i[31]}}, inst_i[31:20]}; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i & {{20{inst_i[31]}}, inst_i[31:20]}; end `INST_SLLI: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= reg1_rdata_i << shift_bits; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i << shift_bits; end `INST_SRI: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; if (inst_i[30] == 1'b1) begin - reg_wdata <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, shift_bits})) | (reg1_rdata_i >> shift_bits); + reg_wdata = ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, shift_bits})) | (reg1_rdata_i >> shift_bits); end else begin - reg_wdata <= reg1_rdata_i >> shift_bits; + reg_wdata = reg1_rdata_i >> shift_bits; end end default: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end endcase end @@ -438,641 +417,691 @@ module ex( if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin case (funct3) `INST_ADD_SUB: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; if (inst_i[30] == 1'b0) begin - reg_wdata <= reg1_rdata_i + reg2_rdata_i; + reg_wdata = reg1_rdata_i + reg2_rdata_i; end else begin - reg_wdata <= reg1_rdata_i - reg2_rdata_i; + reg_wdata = reg1_rdata_i - reg2_rdata_i; end end `INST_SLL: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= reg1_rdata_i << reg2_rdata_i[4:0]; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i << reg2_rdata_i[4:0]; end `INST_SLT: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin - if (reg1_rdata_i < reg2_rdata_i) begin - reg_wdata <= 32'h00000001; - end else begin - reg_wdata <= 32'h00000000; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + case ({reg1_rdata_i[31], reg2_rdata_i[31]}) + 2'b11: begin + if (reg1_rdata_i < reg2_rdata_i) begin + reg_wdata = 32'h00000001; + end else begin + reg_wdata = 32'h00000000; + end end - end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin - reg_wdata <= 32'h00000001; - end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin - reg_wdata <= 32'h00000000; - end else begin - if (reg1_rdata_i < reg2_rdata_i) begin - reg_wdata <= 32'h00000001; - end else begin - reg_wdata <= 32'h00000000; + 2'b10: begin + reg_wdata = 32'h00000001; end - end + 2'b01: begin + reg_wdata = 32'h00000000; + end + default: begin + if (reg1_rdata_i < reg2_rdata_i) begin + reg_wdata = 32'h00000001; + end else begin + reg_wdata = 32'h00000000; + end + end + endcase end `INST_SLTU: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin - if (reg1_rdata_i < reg2_rdata_i) begin - reg_wdata <= 32'h00000001; - end else begin - reg_wdata <= 32'h00000000; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + case ({reg1_rdata_i[31], reg2_rdata_i[31]}) + 2'b11: begin + if (reg1_rdata_i < reg2_rdata_i) begin + reg_wdata = 32'h00000001; + end else begin + reg_wdata = 32'h00000000; + end end - end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin - reg_wdata <= 32'h00000000; - end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin - reg_wdata <= 32'h00000001; - end else begin - if (reg1_rdata_i < reg2_rdata_i) begin - reg_wdata <= 32'h00000001; - end else begin - reg_wdata <= 32'h00000000; + 2'b10: begin + reg_wdata = 32'h00000000; end - end + 2'b01: begin + reg_wdata = 32'h00000001; + end + default: begin + if (reg1_rdata_i < reg2_rdata_i) begin + reg_wdata = 32'h00000001; + end else begin + reg_wdata = 32'h00000000; + end + end + endcase end `INST_XOR: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= reg1_rdata_i ^ reg2_rdata_i; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i ^ reg2_rdata_i; end `INST_SR: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; if (inst_i[30] == 1'b1) begin - reg_wdata <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]); + reg_wdata = ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]); end else begin - reg_wdata <= reg1_rdata_i >> reg2_rdata_i[4:0]; + reg_wdata = reg1_rdata_i >> reg2_rdata_i[4:0]; end end `INST_OR: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= reg1_rdata_i | reg2_rdata_i; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i | reg2_rdata_i; end `INST_AND: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= reg1_rdata_i & reg2_rdata_i; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = reg1_rdata_i & reg2_rdata_i; end default: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end endcase end else if (funct7 == 7'b0000001) begin case (funct3) `INST_MUL: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= mul_temp[31:0]; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = mul_temp[31:0]; end `INST_MULHU: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= mul_temp[63:32]; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = mul_temp[63:32]; end `INST_MULH: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - if ((reg1_rdata_i[31] == 1'b0) && (reg2_rdata_i[31] == 1'b0)) begin - reg_wdata <= mul_temp[63:32]; - end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b1)) begin - reg_wdata <= mul_temp[63:32]; - end else if ((reg1_rdata_i[31] == 1'b1) && (reg2_rdata_i[31] == 1'b0)) begin - reg_wdata <= mul_temp_invert[63:32]; - end else begin - reg_wdata <= mul_temp_invert[63:32]; - end + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + case ({reg1_rdata_i[31], reg2_rdata_i[31]}) + 2'b00: begin + reg_wdata = mul_temp[63:32]; + end + 2'b11: begin + reg_wdata = mul_temp[63:32]; + end + 2'b10: begin + reg_wdata = mul_temp_invert[63:32]; + end + default: begin + reg_wdata = mul_temp_invert[63:32]; + end + endcase end `INST_MULHSU: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; if (reg1_rdata_i[31] == 1'b1) begin - reg_wdata <= mul_temp_invert[63:32]; + reg_wdata = mul_temp_invert[63:32]; end else begin - reg_wdata <= mul_temp[63:32]; + reg_wdata = mul_temp[63:32]; end end default: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end endcase end else begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end end `INST_TYPE_L: begin case (funct3) `INST_LB: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; - if (mem_raddr_index == 2'b0) begin - reg_wdata <= {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]}; - end else if (mem_raddr_index == 2'b01) begin - reg_wdata <= {{24{mem_rdata_i[15]}}, mem_rdata_i[15:8]}; - end else if (mem_raddr_index == 2'b10) begin - reg_wdata <= {{24{mem_rdata_i[23]}}, mem_rdata_i[23:16]}; - end else begin - reg_wdata <= {{24{mem_rdata_i[31]}}, mem_rdata_i[31:24]}; - end + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_raddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + case (mem_raddr_index) + 2'b00: begin + reg_wdata = {{24{mem_rdata_i[7]}}, mem_rdata_i[7:0]}; + end + 2'b01: begin + reg_wdata = {{24{mem_rdata_i[15]}}, mem_rdata_i[15:8]}; + end + 2'b10: begin + reg_wdata = {{24{mem_rdata_i[23]}}, mem_rdata_i[23:16]}; + end + default: begin + reg_wdata = {{24{mem_rdata_i[31]}}, mem_rdata_i[31:24]}; + end + endcase end `INST_LH: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_raddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; if (mem_raddr_index == 2'b0) begin - reg_wdata <= {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]}; + reg_wdata = {{16{mem_rdata_i[15]}}, mem_rdata_i[15:0]}; end else begin - reg_wdata <= {{16{mem_rdata_i[31]}}, mem_rdata_i[31:16]}; + reg_wdata = {{16{mem_rdata_i[31]}}, mem_rdata_i[31:16]}; end end `INST_LW: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; - reg_wdata <= mem_rdata_i; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_raddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + reg_wdata = mem_rdata_i; end `INST_LBU: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; - if (mem_raddr_index == 2'b0) begin - reg_wdata <= {24'h0, mem_rdata_i[7:0]}; - end else if (mem_raddr_index == 2'b01) begin - reg_wdata <= {24'h0, mem_rdata_i[15:8]}; - end else if (mem_raddr_index == 2'b10) begin - reg_wdata <= {24'h0, mem_rdata_i[23:16]}; - end else begin - reg_wdata <= {24'h0, mem_rdata_i[31:24]}; - end + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_raddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + case (mem_raddr_index) + 2'b00: begin + reg_wdata = {24'h0, mem_rdata_i[7:0]}; + end + 2'b01: begin + reg_wdata = {24'h0, mem_rdata_i[15:8]}; + end + 2'b10: begin + reg_wdata = {24'h0, mem_rdata_i[23:16]}; + end + default: begin + reg_wdata = {24'h0, mem_rdata_i[31:24]}; + end + endcase end `INST_LHU: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + mem_raddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; if (mem_raddr_index == 2'b0) begin - reg_wdata <= {16'h0, mem_rdata_i[15:0]}; + reg_wdata = {16'h0, mem_rdata_i[15:0]}; end else begin - reg_wdata <= {16'h0, mem_rdata_i[31:16]}; + reg_wdata = {16'h0, mem_rdata_i[31:16]}; end end default: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end endcase end `INST_TYPE_S: begin case (funct3) `INST_SB: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - reg_wdata <= `ZeroWord; - mem_we <= `WriteEnable; - mem_req <= `RIB_REQ; - mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; - mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; - if (mem_waddr_index == 2'b00) begin - mem_wdata_o <= {mem_rdata_i[31:8], reg2_rdata_i[7:0]}; - end else if (mem_waddr_index == 2'b01) begin - mem_wdata_o <= {mem_rdata_i[31:16], reg2_rdata_i[7:0], mem_rdata_i[7:0]}; - end else if (mem_waddr_index == 2'b10) begin - mem_wdata_o <= {mem_rdata_i[31:24], reg2_rdata_i[7:0], mem_rdata_i[15:0]}; - end else begin - mem_wdata_o <= {reg2_rdata_i[7:0], mem_rdata_i[23:0]}; - end + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + reg_wdata = `ZeroWord; + mem_we = `WriteEnable; + mem_req = `RIB_REQ; + mem_waddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + mem_raddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + case (mem_waddr_index) + 2'b00: begin + mem_wdata_o = {mem_rdata_i[31:8], reg2_rdata_i[7:0]}; + end + 2'b01: begin + mem_wdata_o = {mem_rdata_i[31:16], reg2_rdata_i[7:0], mem_rdata_i[7:0]}; + end + 2'b10: begin + mem_wdata_o = {mem_rdata_i[31:24], reg2_rdata_i[7:0], mem_rdata_i[15:0]}; + end + default: begin + mem_wdata_o = {reg2_rdata_i[7:0], mem_rdata_i[23:0]}; + end + endcase end `INST_SH: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - reg_wdata <= `ZeroWord; - mem_we <= `WriteEnable; - mem_req <= `RIB_REQ; - mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; - mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + reg_wdata = `ZeroWord; + mem_we = `WriteEnable; + mem_req = `RIB_REQ; + mem_waddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + mem_raddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; if (mem_waddr_index == 2'b00) begin - mem_wdata_o <= {mem_rdata_i[31:16], reg2_rdata_i[15:0]}; + mem_wdata_o = {mem_rdata_i[31:16], reg2_rdata_i[15:0]}; end else begin - mem_wdata_o <= {reg2_rdata_i[15:0], mem_rdata_i[15:0]}; + mem_wdata_o = {reg2_rdata_i[15:0], mem_rdata_i[15:0]}; end end `INST_SW: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - reg_wdata <= `ZeroWord; - mem_we <= `WriteEnable; - mem_req <= `RIB_REQ; - mem_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; - mem_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; - mem_wdata_o <= reg2_rdata_i; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + reg_wdata = `ZeroWord; + mem_we = `WriteEnable; + mem_req = `RIB_REQ; + mem_waddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + mem_raddr_o = reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + mem_wdata_o = reg2_rdata_i; end default: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end endcase end `INST_TYPE_B: begin case (funct3) `INST_BEQ: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; if (reg1_rdata_i == reg2_rdata_i) begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end else begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; end end `INST_BNE: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; if (reg1_rdata_i != reg2_rdata_i) begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end else begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; end end `INST_BLT: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; - if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; - end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin - if (reg1_rdata_i >= reg2_rdata_i) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + case ({reg1_rdata_i[31], reg2_rdata_i[31]}) + 2'b10: begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end - end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin - if (reg1_rdata_i >= reg2_rdata_i) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + 2'b11: begin + if (reg1_rdata_i >= reg2_rdata_i) begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end else begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end end - end else begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end + 2'b00: begin + if (reg1_rdata_i >= reg2_rdata_i) begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end else begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end + default: begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end + endcase end `INST_BGE: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; - if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; - end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin - if (reg1_rdata_i < reg2_rdata_i) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + case ({reg1_rdata_i[31], reg2_rdata_i[31]}) + 2'b01: begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; end - end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin - if (reg1_rdata_i < reg2_rdata_i) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + 2'b11: begin + if (reg1_rdata_i < reg2_rdata_i) begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end else begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end end - end else begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end + 2'b00: begin + if (reg1_rdata_i < reg2_rdata_i) begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end else begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end + default: begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end + endcase end `INST_BLTU: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; - if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin - if (reg1_rdata_i >= reg2_rdata_i) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + case ({reg1_rdata_i[31], reg2_rdata_i[31]}) + 2'b10: begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; end - end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin - if (reg1_rdata_i >= reg2_rdata_i) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + 2'b11: begin + if (reg1_rdata_i >= reg2_rdata_i) begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end else begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end end - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; - end + 2'b00: begin + if (reg1_rdata_i >= reg2_rdata_i) begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end else begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end + default: begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + endcase end `INST_BGEU: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; - if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin - if (reg1_rdata_i < reg2_rdata_i) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + case ({reg1_rdata_i[31], reg2_rdata_i[31]}) + 2'b01: begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; end - end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin - if (reg1_rdata_i < reg2_rdata_i) begin - jump_flag <= `JumpDisable; - jump_addr <= `ZeroWord; - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + 2'b11: begin + if (reg1_rdata_i < reg2_rdata_i) begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end else begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end end - end else begin - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; - end + 2'b00: begin + if (reg1_rdata_i < reg2_rdata_i) begin + jump_flag = `JumpDisable; + jump_addr = `ZeroWord; + end else begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end + default: begin + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + endcase end default: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end endcase end `INST_JAL: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0}; - reg_wdata <= inst_addr_i + 4'h4; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0}; + reg_wdata = inst_addr_i + 4'h4; end `INST_JALR: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - jump_flag <= `JumpEnable; - jump_addr <= (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe); - reg_wdata <= inst_addr_i + 4'h4; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + jump_flag = `JumpEnable; + jump_addr = (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe); + reg_wdata = inst_addr_i + 4'h4; end `INST_LUI: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - jump_addr <= `ZeroWord; - jump_flag <= `JumpDisable; - reg_wdata <= {inst_i[31:12], 12'b0}; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + jump_addr = `ZeroWord; + jump_flag = `JumpDisable; + reg_wdata = {inst_i[31:12], 12'b0}; end `INST_AUIPC: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - jump_addr <= `ZeroWord; - jump_flag <= `JumpDisable; - reg_wdata <= {inst_i[31:12], 12'b0} + inst_addr_i; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + jump_addr = `ZeroWord; + jump_flag = `JumpDisable; + reg_wdata = {inst_i[31:12], 12'b0} + inst_addr_i; end `INST_NOP: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end `INST_FENCE: begin - hold_flag <= `HoldDisable; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; - jump_flag <= `JumpEnable; - jump_addr <= inst_addr_i + 4'h4; + hold_flag = `HoldDisable; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; + jump_flag = `JumpEnable; + jump_addr = inst_addr_i + 4'h4; end `INST_CSR: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; case (funct3) `INST_CSRRW: begin - csr_wdata_o <= reg1_rdata_i; - reg_wdata <= csr_rdata_i; + csr_wdata_o = reg1_rdata_i; + reg_wdata = csr_rdata_i; end `INST_CSRRS: begin - csr_wdata_o <= reg1_rdata_i | csr_rdata_i; - reg_wdata <= csr_rdata_i; + csr_wdata_o = reg1_rdata_i | csr_rdata_i; + reg_wdata = csr_rdata_i; end `INST_CSRRC: begin - csr_wdata_o <= csr_rdata_i & (~reg1_rdata_i); - reg_wdata <= csr_rdata_i; + csr_wdata_o = csr_rdata_i & (~reg1_rdata_i); + reg_wdata = csr_rdata_i; end `INST_CSRRWI: begin - csr_wdata_o <= {27'h0, uimm}; - reg_wdata <= csr_rdata_i; + csr_wdata_o = {27'h0, uimm}; + reg_wdata = csr_rdata_i; end `INST_CSRRSI: begin - csr_wdata_o <= {27'h0, uimm} | csr_rdata_i; - reg_wdata <= csr_rdata_i; + csr_wdata_o = {27'h0, uimm} | csr_rdata_i; + reg_wdata = csr_rdata_i; end `INST_CSRRCI: begin - csr_wdata_o <= (~{27'h0, uimm}) & csr_rdata_i; - reg_wdata <= csr_rdata_i; + csr_wdata_o = (~{27'h0, uimm}) & csr_rdata_i; + reg_wdata = csr_rdata_i; end default: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end endcase end default: begin - jump_flag <= `JumpDisable; - hold_flag <= `HoldDisable; - jump_addr <= `ZeroWord; - mem_wdata_o <= `ZeroWord; - mem_raddr_o <= `ZeroWord; - mem_waddr_o <= `ZeroWord; - mem_we <= `WriteDisable; - reg_wdata <= `ZeroWord; + jump_flag = `JumpDisable; + hold_flag = `HoldDisable; + jump_addr = `ZeroWord; + mem_wdata_o = `ZeroWord; + mem_raddr_o = `ZeroWord; + mem_waddr_o = `ZeroWord; + mem_we = `WriteDisable; + reg_wdata = `ZeroWord; end endcase end diff --git a/rtl/core/id.v b/rtl/core/id.v index 34876c3..b47b99d 100644 --- a/rtl/core/id.v +++ b/rtl/core/id.v @@ -73,433 +73,213 @@ module id( always @ (*) begin if (rst == `RstEnable) begin - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; - csr_raddr_o <= `ZeroWord; - inst_o <= `INST_NOP; - inst_addr_o <= `ZeroWord; - reg1_rdata_o <= `ZeroWord; - reg2_rdata_o <= `ZeroWord; - csr_rdata_o <= `ZeroWord; - reg_we_o <= `WriteDisable; - csr_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - csr_waddr_o <= `ZeroWord; - mem_req <= `RIB_NREQ; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + csr_raddr_o = `ZeroWord; + inst_o = `INST_NOP; + inst_addr_o = `ZeroWord; + reg1_rdata_o = `ZeroWord; + reg2_rdata_o = `ZeroWord; + csr_rdata_o = `ZeroWord; + reg_we_o = `WriteDisable; + csr_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + csr_waddr_o = `ZeroWord; + mem_req = `RIB_NREQ; end else begin - inst_o <= inst_i; - inst_addr_o <= inst_addr_i; - reg1_rdata_o <= reg1_rdata_i; - reg2_rdata_o <= reg2_rdata_i; - csr_rdata_o <= csr_rdata_i; - mem_req <= `RIB_NREQ; - csr_raddr_o <= `ZeroWord; - csr_waddr_o <= `ZeroWord; - csr_we_o <= `WriteDisable; + inst_o = inst_i; + inst_addr_o = inst_addr_i; + reg1_rdata_o = reg1_rdata_i; + reg2_rdata_o = reg2_rdata_i; + csr_rdata_o = csr_rdata_i; + mem_req = `RIB_NREQ; + csr_raddr_o = `ZeroWord; + csr_waddr_o = `ZeroWord; + csr_we_o = `WriteDisable; case (opcode) `INST_TYPE_I: begin case (funct3) - `INST_ADDI: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - end - `INST_SLTI: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - end - `INST_SLTIU: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - end - `INST_XORI: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - end - `INST_ORI: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - end - `INST_ANDI: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - end - `INST_SLLI: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - end - `INST_SRI: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; + `INST_ADDI, `INST_SLTI, `INST_SLTIU, `INST_XORI, `INST_ORI, `INST_ANDI, `INST_SLLI, `INST_SRI: begin + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = rs1; + reg2_raddr_o = `ZeroReg; end default: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end endcase end `INST_TYPE_R_M: begin if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin case (funct3) - `INST_ADD_SUB: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_SLL: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_SLT: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_SLTU: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_XOR: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_SR: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_OR: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_AND: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; + `INST_ADD_SUB, `INST_SLL, `INST_SLT, `INST_SLTU, `INST_XOR, `INST_SR, `INST_OR, `INST_AND: begin + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = rs1; + reg2_raddr_o = rs2; end default: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end endcase end else if (funct7 == 7'b0000001) begin case (funct3) - `INST_MUL: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; + `INST_MUL, `INST_MULHU, `INST_MULH, `INST_MULHSU: begin + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = rs1; + reg2_raddr_o = rs2; end - `INST_MULHU: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_MULH: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_MULHSU: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_DIV: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_DIVU: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_REM: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - end - `INST_REMU: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= rd; - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; + `INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin + reg_we_o = `WriteDisable; + reg_waddr_o = rd; + reg1_raddr_o = rs1; + reg2_raddr_o = rs2; end default: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end endcase end else begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end end `INST_TYPE_L: begin case (funct3) - `INST_LB: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - mem_req <= `RIB_REQ; - end - `INST_LH: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - mem_req <= `RIB_REQ; - end - `INST_LW: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - mem_req <= `RIB_REQ; - end - `INST_LBU: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - mem_req <= `RIB_REQ; - end - `INST_LHU: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - mem_req <= `RIB_REQ; + `INST_LB, `INST_LH, `INST_LW, `INST_LBU, `INST_LHU: begin + reg1_raddr_o = rs1; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + mem_req = `RIB_REQ; end default: begin - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; end endcase end `INST_TYPE_S: begin case (funct3) - `INST_SB: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - mem_req <= `RIB_REQ; - end - `INST_SH: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - mem_req <= `RIB_REQ; - end - `INST_SW: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - mem_req <= `RIB_REQ; + `INST_SB, `INST_SW, `INST_SH: begin + reg1_raddr_o = rs1; + reg2_raddr_o = rs2; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + mem_req = `RIB_REQ; end default: begin - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; end endcase end `INST_TYPE_B: begin case (funct3) - `INST_BEQ: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - end - `INST_BNE: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - end - `INST_BLT: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - end - `INST_BGE: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroWord; - end - `INST_BLTU: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - end - `INST_BGEU: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= rs2; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; + `INST_BEQ, `INST_BNE, `INST_BLT, `INST_BGE, `INST_BLTU, `INST_BGEU: begin + reg1_raddr_o = rs1; + reg2_raddr_o = rs2; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; end default: begin - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; end endcase end `INST_JAL: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end `INST_JALR: begin - reg_we_o <= `WriteEnable; - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - reg_waddr_o <= rd; + reg_we_o = `WriteEnable; + reg1_raddr_o = rs1; + reg2_raddr_o = `ZeroReg; + reg_waddr_o = rd; end `INST_LUI: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end `INST_AUIPC: begin - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end `INST_NOP: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end `INST_FENCE: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end `INST_CSR: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; - csr_raddr_o <= {20'h0, inst_i[31:20]}; - csr_waddr_o <= {20'h0, inst_i[31:20]}; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + csr_raddr_o = {20'h0, inst_i[31:20]}; + csr_waddr_o = {20'h0, inst_i[31:20]}; case (funct3) - `INST_CSRRW: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - csr_we_o <= `WriteEnable; + `INST_CSRRW, `INST_CSRRS, `INST_CSRRC: begin + reg1_raddr_o = rs1; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + csr_we_o = `WriteEnable; end - `INST_CSRRS: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - csr_we_o <= `WriteEnable; - end - `INST_CSRRC: begin - reg1_raddr_o <= rs1; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - csr_we_o <= `WriteEnable; - end - `INST_CSRRWI: begin - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - csr_we_o <= `WriteEnable; - end - `INST_CSRRSI: begin - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - csr_we_o <= `WriteEnable; - end - `INST_CSRRCI: begin - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; - reg_we_o <= `WriteEnable; - reg_waddr_o <= rd; - csr_we_o <= `WriteEnable; + `INST_CSRRWI, `INST_CSRRSI, `INST_CSRRCI: begin + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + reg_we_o = `WriteEnable; + reg_waddr_o = rd; + csr_we_o = `WriteEnable; end default: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; - csr_we_o <= `WriteDisable; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; + csr_we_o = `WriteDisable; end endcase end default: begin - reg_we_o <= `WriteDisable; - reg_waddr_o <= `ZeroReg; - reg1_raddr_o <= `ZeroReg; - reg2_raddr_o <= `ZeroReg; + reg_we_o = `WriteDisable; + reg_waddr_o = `ZeroReg; + reg1_raddr_o = `ZeroReg; + reg2_raddr_o = `ZeroReg; end endcase end diff --git a/rtl/core/rib.v b/rtl/core/rib.v index 9679876..1b784b0 100644 --- a/rtl/core/rib.v +++ b/rtl/core/rib.v @@ -128,49 +128,49 @@ module rib( // 优先级由高到低：主设备0，主设备2，主设备1 always @ (*) begin if (rst == `RstEnable) begin - next_grant <= grant1; - hold_flag_o <= `HoldDisable; + next_grant = grant1; + hold_flag_o = `HoldDisable; end else begin case (grant) grant0: begin if (req[0]) begin - next_grant <= grant0; - hold_flag_o <= `HoldEnable; + next_grant = grant0; + hold_flag_o = `HoldEnable; end else if (req[2]) begin - next_grant <= grant2; - hold_flag_o <= `HoldEnable; + next_grant = grant2; + hold_flag_o = `HoldEnable; end else begin - next_grant <= grant1; - hold_flag_o <= `HoldDisable; + next_grant = grant1; + hold_flag_o = `HoldDisable; end end grant1: begin if (req[0]) begin - next_grant <= grant0; - hold_flag_o <= `HoldEnable; + next_grant = grant0; + hold_flag_o = `HoldEnable; end else if (req[2]) begin - next_grant <= grant2; - hold_flag_o <= `HoldEnable; + next_grant = grant2; + hold_flag_o = `HoldEnable; end else begin - next_grant <= grant1; - hold_flag_o <= `HoldDisable; + next_grant = grant1; + hold_flag_o = `HoldDisable; end end grant2: begin if (req[0]) begin - next_grant <= grant0; - hold_flag_o <= `HoldEnable; + next_grant = grant0; + hold_flag_o = `HoldEnable; end else if (req[2]) begin - next_grant <= grant2; - hold_flag_o <= `HoldEnable; + next_grant = grant2; + hold_flag_o = `HoldEnable; end else begin - next_grant <= grant1; - hold_flag_o <= `HoldDisable; + next_grant = grant1; + hold_flag_o = `HoldDisable; end end default: begin - next_grant <= grant1; - hold_flag_o <= `HoldDisable; + next_grant = grant1; + hold_flag_o = `HoldDisable; end endcase end @@ -179,104 +179,104 @@ module rib( // æ ¹æ®æŽˆæƒç»“果，选择(访问)对应的从设备 always @ (*) begin if (rst == `RstEnable) begin - m0_ack_o <= `RIB_NACK; - m1_ack_o <= `RIB_NACK; - m2_ack_o <= `RIB_NACK; - m0_data_o <= `ZeroWord; - m1_data_o <= `INST_NOP; - m2_data_o <= `ZeroWord; + m0_ack_o = `RIB_NACK; + m1_ack_o = `RIB_NACK; + m2_ack_o = `RIB_NACK; + m0_data_o = `ZeroWord; + m1_data_o = `INST_NOP; + m2_data_o = `ZeroWord; - s0_addr_o <= `ZeroWord; - s1_addr_o <= `ZeroWord; - s2_addr_o <= `ZeroWord; - s3_addr_o <= `ZeroWord; - s4_addr_o <= `ZeroWord; - s0_data_o <= `ZeroWord; - s1_data_o <= `ZeroWord; - s2_data_o <= `ZeroWord; - s3_data_o <= `ZeroWord; - s4_data_o <= `ZeroWord; - s0_req_o <= `RIB_NREQ; - s1_req_o <= `RIB_NREQ; - s2_req_o <= `RIB_NREQ; - s3_req_o <= `RIB_NREQ; - s4_req_o <= `RIB_NREQ; - s0_we_o <= `WriteDisable; - s1_we_o <= `WriteDisable; - s2_we_o <= `WriteDisable; - s3_we_o <= `WriteDisable; - s4_we_o <= `WriteDisable; + s0_addr_o = `ZeroWord; + s1_addr_o = `ZeroWord; + s2_addr_o = `ZeroWord; + s3_addr_o = `ZeroWord; + s4_addr_o = `ZeroWord; + s0_data_o = `ZeroWord; + s1_data_o = `ZeroWord; + s2_data_o = `ZeroWord; + s3_data_o = `ZeroWord; + s4_data_o = `ZeroWord; + s0_req_o = `RIB_NREQ; + s1_req_o = `RIB_NREQ; + s2_req_o = `RIB_NREQ; + s3_req_o = `RIB_NREQ; + s4_req_o = `RIB_NREQ; + s0_we_o = `WriteDisable; + s1_we_o = `WriteDisable; + s2_we_o = `WriteDisable; + s3_we_o = `WriteDisable; + s4_we_o = `WriteDisable; end else begin - m0_ack_o <= `RIB_NACK; - m1_ack_o <= `RIB_NACK; - m2_ack_o <= `RIB_NACK; - m0_data_o <= `ZeroWord; - m1_data_o <= `INST_NOP; - m2_data_o <= `ZeroWord; + m0_ack_o = `RIB_NACK; + m1_ack_o = `RIB_NACK; + m2_ack_o = `RIB_NACK; + m0_data_o = `ZeroWord; + m1_data_o = `INST_NOP; + m2_data_o = `ZeroWord; - s0_addr_o <= `ZeroWord; - s1_addr_o <= `ZeroWord; - s2_addr_o <= `ZeroWord; - s3_addr_o <= `ZeroWord; - s4_addr_o <= `ZeroWord; - s0_data_o <= `ZeroWord; - s1_data_o <= `ZeroWord; - s2_data_o <= `ZeroWord; - s3_data_o <= `ZeroWord; - s4_data_o <= `ZeroWord; - s0_req_o <= `RIB_NREQ; - s1_req_o <= `RIB_NREQ; - s2_req_o <= `RIB_NREQ; - s3_req_o <= `RIB_NREQ; - s4_req_o <= `RIB_NREQ; - s0_we_o <= `WriteDisable; - s1_we_o <= `WriteDisable; - s2_we_o <= `WriteDisable; - s3_we_o <= `WriteDisable; - s4_we_o <= `WriteDisable; + s0_addr_o = `ZeroWord; + s1_addr_o = `ZeroWord; + s2_addr_o = `ZeroWord; + s3_addr_o = `ZeroWord; + s4_addr_o = `ZeroWord; + s0_data_o = `ZeroWord; + s1_data_o = `ZeroWord; + s2_data_o = `ZeroWord; + s3_data_o = `ZeroWord; + s4_data_o = `ZeroWord; + s0_req_o = `RIB_NREQ; + s1_req_o = `RIB_NREQ; + s2_req_o = `RIB_NREQ; + s3_req_o = `RIB_NREQ; + s4_req_o = `RIB_NREQ; + s0_we_o = `WriteDisable; + s1_we_o = `WriteDisable; + s2_we_o = `WriteDisable; + s3_we_o = `WriteDisable; + s4_we_o = `WriteDisable; case (grant) grant0: begin case (m0_addr_i[31:28]) slave_0: begin - s0_req_o <= m0_req_i; - s0_we_o <= m0_we_i; - s0_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; - s0_data_o <= m0_data_i; - m0_ack_o <= s0_ack_i; - m0_data_o <= s0_data_i; + s0_req_o = m0_req_i; + s0_we_o = m0_we_i; + s0_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s0_data_o = m0_data_i; + m0_ack_o = s0_ack_i; + m0_data_o = s0_data_i; end slave_1: begin - s1_req_o <= m0_req_i; - s1_we_o <= m0_we_i; - s1_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; - s1_data_o <= m0_data_i; - m0_ack_o <= s1_ack_i; - m0_data_o <= s1_data_i; + s1_req_o = m0_req_i; + s1_we_o = m0_we_i; + s1_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s1_data_o = m0_data_i; + m0_ack_o = s1_ack_i; + m0_data_o = s1_data_i; end slave_2: begin - s2_req_o <= m0_req_i; - s2_we_o <= m0_we_i; - s2_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; - s2_data_o <= m0_data_i; - m0_ack_o <= s2_ack_i; - m0_data_o <= s2_data_i; + s2_req_o = m0_req_i; + s2_we_o = m0_we_i; + s2_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s2_data_o = m0_data_i; + m0_ack_o = s2_ack_i; + m0_data_o = s2_data_i; end slave_3: begin - s3_req_o <= m0_req_i; - s3_we_o <= m0_we_i; - s3_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; - s3_data_o <= m0_data_i; - m0_ack_o <= s3_ack_i; - m0_data_o <= s3_data_i; + s3_req_o = m0_req_i; + s3_we_o = m0_we_i; + s3_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s3_data_o = m0_data_i; + m0_ack_o = s3_ack_i; + m0_data_o = s3_data_i; end slave_4: begin - s4_req_o <= m0_req_i; - s4_we_o <= m0_we_i; - s4_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; - s4_data_o <= m0_data_i; - m0_ack_o <= s4_ack_i; - m0_data_o <= s4_data_i; + s4_req_o = m0_req_i; + s4_we_o = m0_we_i; + s4_addr_o = {{4'h0}, {m0_addr_i[27:0]}}; + s4_data_o = m0_data_i; + m0_ack_o = s4_ack_i; + m0_data_o = s4_data_i; end default: begin @@ -286,44 +286,44 @@ module rib( grant1: begin case (m1_addr_i[31:28]) slave_0: begin - s0_req_o <= m1_req_i; - s0_we_o <= m1_we_i; - s0_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; - s0_data_o <= m1_data_i; - m1_ack_o <= s0_ack_i; - m1_data_o <= s0_data_i; + s0_req_o = m1_req_i; + s0_we_o = m1_we_i; + s0_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s0_data_o = m1_data_i; + m1_ack_o = s0_ack_i; + m1_data_o = s0_data_i; end slave_1: begin - s1_req_o <= m1_req_i; - s1_we_o <= m1_we_i; - s1_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; - s1_data_o <= m1_data_i; - m1_ack_o <= s1_ack_i; - m1_data_o <= s1_data_i; + s1_req_o = m1_req_i; + s1_we_o = m1_we_i; + s1_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s1_data_o = m1_data_i; + m1_ack_o = s1_ack_i; + m1_data_o = s1_data_i; end slave_2: begin - s2_req_o <= m1_req_i; - s2_we_o <= m1_we_i; - s2_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; - s2_data_o <= m1_data_i; - m1_ack_o <= s2_ack_i; - m1_data_o <= s2_data_i; + s2_req_o = m1_req_i; + s2_we_o = m1_we_i; + s2_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s2_data_o = m1_data_i; + m1_ack_o = s2_ack_i; + m1_data_o = s2_data_i; end slave_3: begin - s3_req_o <= m1_req_i; - s3_we_o <= m1_we_i; - s3_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; - s3_data_o <= m1_data_i; - m1_ack_o <= s3_ack_i; - m1_data_o <= s3_data_i; + s3_req_o = m1_req_i; + s3_we_o = m1_we_i; + s3_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s3_data_o = m1_data_i; + m1_ack_o = s3_ack_i; + m1_data_o = s3_data_i; end slave_4: begin - s4_req_o <= m1_req_i; - s4_we_o <= m1_we_i; - s4_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; - s4_data_o <= m1_data_i; - m1_ack_o <= s4_ack_i; - m1_data_o <= s4_data_i; + s4_req_o = m1_req_i; + s4_we_o = m1_we_i; + s4_addr_o = {{4'h0}, {m1_addr_i[27:0]}}; + s4_data_o = m1_data_i; + m1_ack_o = s4_ack_i; + m1_data_o = s4_data_i; end default: begin @@ -333,44 +333,44 @@ module rib( grant2: begin case (m2_addr_i[31:28]) slave_0: begin - s0_req_o <= m2_req_i; - s0_we_o <= m2_we_i; - s0_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; - s0_data_o <= m2_data_i; - m2_ack_o <= s0_ack_i; - m2_data_o <= s0_data_i; + s0_req_o = m2_req_i; + s0_we_o = m2_we_i; + s0_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s0_data_o = m2_data_i; + m2_ack_o = s0_ack_i; + m2_data_o = s0_data_i; end slave_1: begin - s1_req_o <= m2_req_i; - s1_we_o <= m2_we_i; - s1_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; - s1_data_o <= m2_data_i; - m2_ack_o <= s1_ack_i; - m2_data_o <= s1_data_i; + s1_req_o = m2_req_i; + s1_we_o = m2_we_i; + s1_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s1_data_o = m2_data_i; + m2_ack_o = s1_ack_i; + m2_data_o = s1_data_i; end slave_2: begin - s2_req_o <= m2_req_i; - s2_we_o <= m2_we_i; - s2_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; - s2_data_o <= m2_data_i; - m2_ack_o <= s2_ack_i; - m2_data_o <= s2_data_i; + s2_req_o = m2_req_i; + s2_we_o = m2_we_i; + s2_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s2_data_o = m2_data_i; + m2_ack_o = s2_ack_i; + m2_data_o = s2_data_i; end slave_3: begin - s3_req_o <= m2_req_i; - s3_we_o <= m2_we_i; - s3_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; - s3_data_o <= m2_data_i; - m2_ack_o <= s3_ack_i; - m2_data_o <= s3_data_i; + s3_req_o = m2_req_i; + s3_we_o = m2_we_i; + s3_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s3_data_o = m2_data_i; + m2_ack_o = s3_ack_i; + m2_data_o = s3_data_i; end slave_4: begin - s4_req_o <= m2_req_i; - s4_we_o <= m2_we_i; - s4_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; - s4_data_o <= m2_data_i; - m2_ack_o <= s4_ack_i; - m2_data_o <= s4_data_i; + s4_req_o = m2_req_i; + s4_we_o = m2_we_i; + s4_addr_o = {{4'h0}, {m2_addr_i[27:0]}}; + s4_data_o = m2_data_i; + m2_ack_o = s4_ack_i; + m2_data_o = s4_data_i; end default: begin