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use = instead of <= in combination logic 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-05-02 11:58:44 +08:00
parent 043bc23f8a
commit 837af2c977
6 changed files with 1055 additions and 1246 deletions
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10
rtl/core/clint.v
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@ -83,16 +83,16 @@ module clint(
// 中断仲裁逻辑 // 中断仲裁逻辑
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
int_state <= S_INT_IDLE; int_state = S_INT_IDLE;
end else begin end else begin
if (inst_i == `INST_ECALL) begin if (inst_i == `INST_ECALL) begin
int_state <= S_INT_SYNC_ASSERT; int_state = S_INT_SYNC_ASSERT;
end else if (int_flag_i != `INT_NONE && global_int_en_i == `True) begin end else if (int_flag_i != `INT_NONE && global_int_en_i == `True) begin
int_state <= S_INT_ASYNC_ASSERT; int_state = S_INT_ASYNC_ASSERT;
end else if (inst_i == `INST_MRET) begin end else if (inst_i == `INST_MRET) begin
int_state <= S_INT_MRET; int_state = S_INT_MRET;
end else begin end else begin
int_state <= S_INT_IDLE; int_state = S_INT_IDLE;
end end
end end
end end

18
rtl/core/csr_reg.v
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@ -135,32 +135,32 @@ module csr_reg(
// ex模块读CSR寄存器 // ex模块读CSR寄存器
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
data_o <= `ZeroWord; data_o = `ZeroWord;
end else begin end else begin
case (raddr_i[11:0]) case (raddr_i[11:0])
`CSR_CYCLE: begin `CSR_CYCLE: begin
data_o <= cycle[31:0]; data_o = cycle[31:0];
end end
`CSR_CYCLEH: begin `CSR_CYCLEH: begin
data_o <= cycle[63:32]; data_o = cycle[63:32];
end end
`CSR_MTVEC: begin `CSR_MTVEC: begin
data_o <= mtvec; data_o = mtvec;
end end
`CSR_MCAUSE: begin `CSR_MCAUSE: begin
data_o <= mcause; data_o = mcause;
end end
`CSR_MEPC: begin `CSR_MEPC: begin
data_o <= mepc; data_o = mepc;
end end
`CSR_MIE: begin `CSR_MIE: begin
data_o <= mie; data_o = mie;
end end
`CSR_MSTATUS: begin `CSR_MSTATUS: begin
data_o <= mstatus; data_o = mstatus;
end end
default: begin default: begin
data_o <= `ZeroWord; data_o = `ZeroWord;
end end
endcase endcase
end end

20
rtl/core/ctrl.v
View File

@ -47,26 +47,26 @@ module ctrl(
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
hold_flag_o <= `Hold_None; hold_flag_o = `Hold_None;
jump_flag_o <= `JumpDisable; jump_flag_o = `JumpDisable;
jump_addr_o <= `ZeroWord; jump_addr_o = `ZeroWord;
end else begin end else begin
jump_addr_o <= jump_addr_i; jump_addr_o = jump_addr_i;
jump_flag_o <= jump_flag_i; jump_flag_o = jump_flag_i;
// 默认不暂停 // 默认不暂停
hold_flag_o <= `Hold_None; hold_flag_o = `Hold_None;
// 按优先级处理不同模块的请求 // 按优先级处理不同模块的请求
if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable || hold_flag_clint_i == `HoldEnable) begin if (jump_flag_i == `JumpEnable || hold_flag_ex_i == `HoldEnable || hold_flag_clint_i == `HoldEnable) begin
// 暂停整条流水线 // 暂停整条流水线
hold_flag_o <= `Hold_Id; hold_flag_o = `Hold_Id;
end else if (hold_flag_rib_i == `HoldEnable) begin end else if (hold_flag_rib_i == `HoldEnable) begin
// 暂停PC，即取指地址不变 // 暂停PC，即取指地址不变
hold_flag_o <= `Hold_Pc; hold_flag_o = `Hold_Pc;
end else if (jtag_halt_flag_i == `HoldEnable) begin end else if (jtag_halt_flag_i == `HoldEnable) begin
// 暂停整条流水线 // 暂停整条流水线
hold_flag_o <= `Hold_Id; hold_flag_o = `Hold_Id;
end else begin end else begin
hold_flag_o <= `Hold_None; hold_flag_o = `Hold_None;
end end
end end
end end

1429
rtl/core/ex.v
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File diff suppressed because it is too large Load Diff

496
rtl/core/id.v
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@ -73,433 +73,213 @@ module id(
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
csr_raddr_o <= `ZeroWord; csr_raddr_o = `ZeroWord;
inst_o <= `INST_NOP; inst_o = `INST_NOP;
inst_addr_o <= `ZeroWord; inst_addr_o = `ZeroWord;
reg1_rdata_o <= `ZeroWord; reg1_rdata_o = `ZeroWord;
reg2_rdata_o <= `ZeroWord; reg2_rdata_o = `ZeroWord;
csr_rdata_o <= `ZeroWord; csr_rdata_o = `ZeroWord;
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
csr_we_o <= `WriteDisable; csr_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
csr_waddr_o <= `ZeroWord; csr_waddr_o = `ZeroWord;
mem_req <= `RIB_NREQ; mem_req = `RIB_NREQ;
end else begin end else begin
inst_o <= inst_i; inst_o = inst_i;
inst_addr_o <= inst_addr_i; inst_addr_o = inst_addr_i;
reg1_rdata_o <= reg1_rdata_i; reg1_rdata_o = reg1_rdata_i;
reg2_rdata_o <= reg2_rdata_i; reg2_rdata_o = reg2_rdata_i;
csr_rdata_o <= csr_rdata_i; csr_rdata_o = csr_rdata_i;
mem_req <= `RIB_NREQ; mem_req = `RIB_NREQ;
csr_raddr_o <= `ZeroWord; csr_raddr_o = `ZeroWord;
csr_waddr_o <= `ZeroWord; csr_waddr_o = `ZeroWord;
csr_we_o <= `WriteDisable; csr_we_o = `WriteDisable;
case (opcode) case (opcode)
`INST_TYPE_I: begin `INST_TYPE_I: begin
case (funct3) case (funct3)
`INST_ADDI: begin `INST_ADDI, `INST_SLTI, `INST_SLTIU, `INST_XORI, `INST_ORI, `INST_ANDI, `INST_SLLI, `INST_SRI: begin
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o = rd;
reg1_raddr_o <= rs1; reg1_raddr_o = rs1;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end
`INST_SLTI: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
end
`INST_SLTIU: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
end
`INST_XORI: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
end
`INST_ORI: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
end
`INST_ANDI: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
end
`INST_SLLI: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
end
`INST_SRI: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
endcase endcase
end end
`INST_TYPE_R_M: begin `INST_TYPE_R_M: begin
if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin if ((funct7 == 7'b0000000) || (funct7 == 7'b0100000)) begin
case (funct3) case (funct3)
`INST_ADD_SUB: begin `INST_ADD_SUB, `INST_SLL, `INST_SLT, `INST_SLTU, `INST_XOR, `INST_SR, `INST_OR, `INST_AND: begin
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o = rd;
reg1_raddr_o <= rs1; reg1_raddr_o = rs1;
reg2_raddr_o <= rs2; reg2_raddr_o = rs2;
end
`INST_SLL: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_SLT: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_SLTU: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_XOR: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_SR: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_OR: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_AND: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
endcase endcase
end else if (funct7 == 7'b0000001) begin end else if (funct7 == 7'b0000001) begin
case (funct3) case (funct3)
`INST_MUL: begin `INST_MUL, `INST_MULHU, `INST_MULH, `INST_MULHSU: begin
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o = rd;
reg1_raddr_o <= rs1; reg1_raddr_o = rs1;
reg2_raddr_o <= rs2; reg2_raddr_o = rs2;
end end
`INST_MULHU: begin `INST_DIV, `INST_DIVU, `INST_REM, `INST_REMU: begin
reg_we_o <= `WriteEnable; reg_we_o = `WriteDisable;
reg_waddr_o <= rd; reg_waddr_o = rd;
reg1_raddr_o <= rs1; reg1_raddr_o = rs1;
reg2_raddr_o <= rs2; reg2_raddr_o = rs2;
end
`INST_MULH: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_MULHSU: begin
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_DIV: begin
reg_we_o <= `WriteDisable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_DIVU: begin
reg_we_o <= `WriteDisable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_REM: begin
reg_we_o <= `WriteDisable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end
`INST_REMU: begin
reg_we_o <= `WriteDisable;
reg_waddr_o <= rd;
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
endcase endcase
end else begin end else begin
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
end end
`INST_TYPE_L: begin `INST_TYPE_L: begin
case (funct3) case (funct3)
`INST_LB: begin `INST_LB, `INST_LH, `INST_LW, `INST_LBU, `INST_LHU: begin
reg1_raddr_o <= rs1; reg1_raddr_o = rs1;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o = rd;
mem_req <= `RIB_REQ; mem_req = `RIB_REQ;
end
`INST_LH: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
mem_req <= `RIB_REQ;
end
`INST_LW: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
mem_req <= `RIB_REQ;
end
`INST_LBU: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
mem_req <= `RIB_REQ;
end
`INST_LHU: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
mem_req <= `RIB_REQ;
end end
default: begin default: begin
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
end end
endcase endcase
end end
`INST_TYPE_S: begin `INST_TYPE_S: begin
case (funct3) case (funct3)
`INST_SB: begin `INST_SB, `INST_SW, `INST_SH: begin
reg1_raddr_o <= rs1; reg1_raddr_o = rs1;
reg2_raddr_o <= rs2; reg2_raddr_o = rs2;
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
mem_req <= `RIB_REQ; mem_req = `RIB_REQ;
end
`INST_SH: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroReg;
mem_req <= `RIB_REQ;
end
`INST_SW: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroReg;
mem_req <= `RIB_REQ;
end end
default: begin default: begin
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
end end
endcase endcase
end end
`INST_TYPE_B: begin `INST_TYPE_B: begin
case (funct3) case (funct3)
`INST_BEQ: begin `INST_BEQ, `INST_BNE, `INST_BLT, `INST_BGE, `INST_BLTU, `INST_BGEU: begin
reg1_raddr_o <= rs1; reg1_raddr_o = rs1;
reg2_raddr_o <= rs2; reg2_raddr_o = rs2;
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
end
`INST_BNE: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroReg;
end
`INST_BLT: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroReg;
end
`INST_BGE: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroWord;
end
`INST_BLTU: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroReg;
end
`INST_BGEU: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= rs2;
reg_we_o <= `WriteDisable;
reg_waddr_o <= `ZeroReg;
end end
default: begin default: begin
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
end end
endcase endcase
end end
`INST_JAL: begin `INST_JAL: begin
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o = rd;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
`INST_JALR: begin `INST_JALR: begin
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg1_raddr_o <= rs1; reg1_raddr_o = rs1;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
reg_waddr_o <= rd; reg_waddr_o = rd;
end end
`INST_LUI: begin `INST_LUI: begin
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o = rd;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
`INST_AUIPC: begin `INST_AUIPC: begin
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o = rd;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
`INST_NOP: begin `INST_NOP: begin
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
`INST_FENCE: begin `INST_FENCE: begin
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
`INST_CSR: begin `INST_CSR: begin
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
csr_raddr_o <= {20'h0, inst_i[31:20]}; csr_raddr_o = {20'h0, inst_i[31:20]};
csr_waddr_o <= {20'h0, inst_i[31:20]}; csr_waddr_o = {20'h0, inst_i[31:20]};
case (funct3) case (funct3)
`INST_CSRRW: begin `INST_CSRRW, `INST_CSRRS, `INST_CSRRC: begin
reg1_raddr_o <= rs1; reg1_raddr_o = rs1;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o = rd;
csr_we_o <= `WriteEnable; csr_we_o = `WriteEnable;
end end
`INST_CSRRS: begin `INST_CSRRWI, `INST_CSRRSI, `INST_CSRRCI: begin
reg1_raddr_o <= rs1; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
reg_we_o <= `WriteEnable; reg_we_o = `WriteEnable;
reg_waddr_o <= rd; reg_waddr_o = rd;
csr_we_o <= `WriteEnable; csr_we_o = `WriteEnable;
end
`INST_CSRRC: begin
reg1_raddr_o <= rs1;
reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
csr_we_o <= `WriteEnable;
end
`INST_CSRRWI: begin
reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
csr_we_o <= `WriteEnable;
end
`INST_CSRRSI: begin
reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
csr_we_o <= `WriteEnable;
end
`INST_CSRRCI: begin
reg1_raddr_o <= `ZeroReg;
reg2_raddr_o <= `ZeroReg;
reg_we_o <= `WriteEnable;
reg_waddr_o <= rd;
csr_we_o <= `WriteEnable;
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
csr_we_o <= `WriteDisable; csr_we_o = `WriteDisable;
end end
endcase endcase
end end
default: begin default: begin
reg_we_o <= `WriteDisable; reg_we_o = `WriteDisable;
reg_waddr_o <= `ZeroReg; reg_waddr_o = `ZeroReg;
reg1_raddr_o <= `ZeroReg; reg1_raddr_o = `ZeroReg;
reg2_raddr_o <= `ZeroReg; reg2_raddr_o = `ZeroReg;
end end
endcase endcase
end end

328
rtl/core/rib.v
View File

@ -128,49 +128,49 @@ module rib(
// 优先级由高到低：主设备0，主设备2，主设备1 // 优先级由高到低：主设备0，主设备2，主设备1
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
next_grant <= grant1; next_grant = grant1;
hold_flag_o <= `HoldDisable; hold_flag_o = `HoldDisable;
end else begin end else begin
case (grant) case (grant)
grant0: begin grant0: begin
if (req[0]) begin if (req[0]) begin
next_grant <= grant0; next_grant = grant0;
hold_flag_o <= `HoldEnable; hold_flag_o = `HoldEnable;
end else if (req[2]) begin end else if (req[2]) begin
next_grant <= grant2; next_grant = grant2;
hold_flag_o <= `HoldEnable; hold_flag_o = `HoldEnable;
end else begin end else begin
next_grant <= grant1; next_grant = grant1;
hold_flag_o <= `HoldDisable; hold_flag_o = `HoldDisable;
end end
end end
grant1: begin grant1: begin
if (req[0]) begin if (req[0]) begin
next_grant <= grant0; next_grant = grant0;
hold_flag_o <= `HoldEnable; hold_flag_o = `HoldEnable;
end else if (req[2]) begin end else if (req[2]) begin
next_grant <= grant2; next_grant = grant2;
hold_flag_o <= `HoldEnable; hold_flag_o = `HoldEnable;
end else begin end else begin
next_grant <= grant1; next_grant = grant1;
hold_flag_o <= `HoldDisable; hold_flag_o = `HoldDisable;
end end
end end
grant2: begin grant2: begin
if (req[0]) begin if (req[0]) begin
next_grant <= grant0; next_grant = grant0;
hold_flag_o <= `HoldEnable; hold_flag_o = `HoldEnable;
end else if (req[2]) begin end else if (req[2]) begin
next_grant <= grant2; next_grant = grant2;
hold_flag_o <= `HoldEnable; hold_flag_o = `HoldEnable;
end else begin end else begin
next_grant <= grant1; next_grant = grant1;
hold_flag_o <= `HoldDisable; hold_flag_o = `HoldDisable;
end end
end end
default: begin default: begin
next_grant <= grant1; next_grant = grant1;
hold_flag_o <= `HoldDisable; hold_flag_o = `HoldDisable;
end end
endcase endcase
end end
@ -179,104 +179,104 @@ module rib(
// 根据授权结果，选择(访问)对应的从设备 // 根据授权结果，选择(访问)对应的从设备
always @ (*) begin always @ (*) begin
if (rst == `RstEnable) begin if (rst == `RstEnable) begin
m0_ack_o <= `RIB_NACK; m0_ack_o = `RIB_NACK;
m1_ack_o <= `RIB_NACK; m1_ack_o = `RIB_NACK;
m2_ack_o <= `RIB_NACK; m2_ack_o = `RIB_NACK;
m0_data_o <= `ZeroWord; m0_data_o = `ZeroWord;
m1_data_o <= `INST_NOP; m1_data_o = `INST_NOP;
m2_data_o <= `ZeroWord; m2_data_o = `ZeroWord;
s0_addr_o <= `ZeroWord; s0_addr_o = `ZeroWord;
s1_addr_o <= `ZeroWord; s1_addr_o = `ZeroWord;
s2_addr_o <= `ZeroWord; s2_addr_o = `ZeroWord;
s3_addr_o <= `ZeroWord; s3_addr_o = `ZeroWord;
s4_addr_o <= `ZeroWord; s4_addr_o = `ZeroWord;
s0_data_o <= `ZeroWord; s0_data_o = `ZeroWord;
s1_data_o <= `ZeroWord; s1_data_o = `ZeroWord;
s2_data_o <= `ZeroWord; s2_data_o = `ZeroWord;
s3_data_o <= `ZeroWord; s3_data_o = `ZeroWord;
s4_data_o <= `ZeroWord; s4_data_o = `ZeroWord;
s0_req_o <= `RIB_NREQ; s0_req_o = `RIB_NREQ;
s1_req_o <= `RIB_NREQ; s1_req_o = `RIB_NREQ;
s2_req_o <= `RIB_NREQ; s2_req_o = `RIB_NREQ;
s3_req_o <= `RIB_NREQ; s3_req_o = `RIB_NREQ;
s4_req_o <= `RIB_NREQ; s4_req_o = `RIB_NREQ;
s0_we_o <= `WriteDisable; s0_we_o = `WriteDisable;
s1_we_o <= `WriteDisable; s1_we_o = `WriteDisable;
s2_we_o <= `WriteDisable; s2_we_o = `WriteDisable;
s3_we_o <= `WriteDisable; s3_we_o = `WriteDisable;
s4_we_o <= `WriteDisable; s4_we_o = `WriteDisable;
end else begin end else begin
m0_ack_o <= `RIB_NACK; m0_ack_o = `RIB_NACK;
m1_ack_o <= `RIB_NACK; m1_ack_o = `RIB_NACK;
m2_ack_o <= `RIB_NACK; m2_ack_o = `RIB_NACK;
m0_data_o <= `ZeroWord; m0_data_o = `ZeroWord;
m1_data_o <= `INST_NOP; m1_data_o = `INST_NOP;
m2_data_o <= `ZeroWord; m2_data_o = `ZeroWord;
s0_addr_o <= `ZeroWord; s0_addr_o = `ZeroWord;
s1_addr_o <= `ZeroWord; s1_addr_o = `ZeroWord;
s2_addr_o <= `ZeroWord; s2_addr_o = `ZeroWord;
s3_addr_o <= `ZeroWord; s3_addr_o = `ZeroWord;
s4_addr_o <= `ZeroWord; s4_addr_o = `ZeroWord;
s0_data_o <= `ZeroWord; s0_data_o = `ZeroWord;
s1_data_o <= `ZeroWord; s1_data_o = `ZeroWord;
s2_data_o <= `ZeroWord; s2_data_o = `ZeroWord;
s3_data_o <= `ZeroWord; s3_data_o = `ZeroWord;
s4_data_o <= `ZeroWord; s4_data_o = `ZeroWord;
s0_req_o <= `RIB_NREQ; s0_req_o = `RIB_NREQ;
s1_req_o <= `RIB_NREQ; s1_req_o = `RIB_NREQ;
s2_req_o <= `RIB_NREQ; s2_req_o = `RIB_NREQ;
s3_req_o <= `RIB_NREQ; s3_req_o = `RIB_NREQ;
s4_req_o <= `RIB_NREQ; s4_req_o = `RIB_NREQ;
s0_we_o <= `WriteDisable; s0_we_o = `WriteDisable;
s1_we_o <= `WriteDisable; s1_we_o = `WriteDisable;
s2_we_o <= `WriteDisable; s2_we_o = `WriteDisable;
s3_we_o <= `WriteDisable; s3_we_o = `WriteDisable;
s4_we_o <= `WriteDisable; s4_we_o = `WriteDisable;
case (grant) case (grant)
grant0: begin grant0: begin
case (m0_addr_i[31:28]) case (m0_addr_i[31:28])
slave_0: begin slave_0: begin
s0_req_o <= m0_req_i; s0_req_o = m0_req_i;
s0_we_o <= m0_we_i; s0_we_o = m0_we_i;
s0_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; s0_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s0_data_o <= m0_data_i; s0_data_o = m0_data_i;
m0_ack_o <= s0_ack_i; m0_ack_o = s0_ack_i;
m0_data_o <= s0_data_i; m0_data_o = s0_data_i;
end end
slave_1: begin slave_1: begin
s1_req_o <= m0_req_i; s1_req_o = m0_req_i;
s1_we_o <= m0_we_i; s1_we_o = m0_we_i;
s1_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; s1_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s1_data_o <= m0_data_i; s1_data_o = m0_data_i;
m0_ack_o <= s1_ack_i; m0_ack_o = s1_ack_i;
m0_data_o <= s1_data_i; m0_data_o = s1_data_i;
end end
slave_2: begin slave_2: begin
s2_req_o <= m0_req_i; s2_req_o = m0_req_i;
s2_we_o <= m0_we_i; s2_we_o = m0_we_i;
s2_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; s2_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s2_data_o <= m0_data_i; s2_data_o = m0_data_i;
m0_ack_o <= s2_ack_i; m0_ack_o = s2_ack_i;
m0_data_o <= s2_data_i; m0_data_o = s2_data_i;
end end
slave_3: begin slave_3: begin
s3_req_o <= m0_req_i; s3_req_o = m0_req_i;
s3_we_o <= m0_we_i; s3_we_o = m0_we_i;
s3_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; s3_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s3_data_o <= m0_data_i; s3_data_o = m0_data_i;
m0_ack_o <= s3_ack_i; m0_ack_o = s3_ack_i;
m0_data_o <= s3_data_i; m0_data_o = s3_data_i;
end end
slave_4: begin slave_4: begin
s4_req_o <= m0_req_i; s4_req_o = m0_req_i;
s4_we_o <= m0_we_i; s4_we_o = m0_we_i;
s4_addr_o <= {{4'h0}, {m0_addr_i[27:0]}}; s4_addr_o = {{4'h0}, {m0_addr_i[27:0]}};
s4_data_o <= m0_data_i; s4_data_o = m0_data_i;
m0_ack_o <= s4_ack_i; m0_ack_o = s4_ack_i;
m0_data_o <= s4_data_i; m0_data_o = s4_data_i;
end end
default: begin default: begin
@ -286,44 +286,44 @@ module rib(
grant1: begin grant1: begin
case (m1_addr_i[31:28]) case (m1_addr_i[31:28])
slave_0: begin slave_0: begin
s0_req_o <= m1_req_i; s0_req_o = m1_req_i;
s0_we_o <= m1_we_i; s0_we_o = m1_we_i;
s0_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; s0_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
s0_data_o <= m1_data_i; s0_data_o = m1_data_i;
m1_ack_o <= s0_ack_i; m1_ack_o = s0_ack_i;
m1_data_o <= s0_data_i; m1_data_o = s0_data_i;
end end
slave_1: begin slave_1: begin
s1_req_o <= m1_req_i; s1_req_o = m1_req_i;
s1_we_o <= m1_we_i; s1_we_o = m1_we_i;
s1_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; s1_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
s1_data_o <= m1_data_i; s1_data_o = m1_data_i;
m1_ack_o <= s1_ack_i; m1_ack_o = s1_ack_i;
m1_data_o <= s1_data_i; m1_data_o = s1_data_i;
end end
slave_2: begin slave_2: begin
s2_req_o <= m1_req_i; s2_req_o = m1_req_i;
s2_we_o <= m1_we_i; s2_we_o = m1_we_i;
s2_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; s2_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
s2_data_o <= m1_data_i; s2_data_o = m1_data_i;
m1_ack_o <= s2_ack_i; m1_ack_o = s2_ack_i;
m1_data_o <= s2_data_i; m1_data_o = s2_data_i;
end end
slave_3: begin slave_3: begin
s3_req_o <= m1_req_i; s3_req_o = m1_req_i;
s3_we_o <= m1_we_i; s3_we_o = m1_we_i;
s3_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; s3_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
s3_data_o <= m1_data_i; s3_data_o = m1_data_i;
m1_ack_o <= s3_ack_i; m1_ack_o = s3_ack_i;
m1_data_o <= s3_data_i; m1_data_o = s3_data_i;
end end
slave_4: begin slave_4: begin
s4_req_o <= m1_req_i; s4_req_o = m1_req_i;
s4_we_o <= m1_we_i; s4_we_o = m1_we_i;
s4_addr_o <= {{4'h0}, {m1_addr_i[27:0]}}; s4_addr_o = {{4'h0}, {m1_addr_i[27:0]}};
s4_data_o <= m1_data_i; s4_data_o = m1_data_i;
m1_ack_o <= s4_ack_i; m1_ack_o = s4_ack_i;
m1_data_o <= s4_data_i; m1_data_o = s4_data_i;
end end
default: begin default: begin
@ -333,44 +333,44 @@ module rib(
grant2: begin grant2: begin
case (m2_addr_i[31:28]) case (m2_addr_i[31:28])
slave_0: begin slave_0: begin
s0_req_o <= m2_req_i; s0_req_o = m2_req_i;
s0_we_o <= m2_we_i; s0_we_o = m2_we_i;
s0_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; s0_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s0_data_o <= m2_data_i; s0_data_o = m2_data_i;
m2_ack_o <= s0_ack_i; m2_ack_o = s0_ack_i;
m2_data_o <= s0_data_i; m2_data_o = s0_data_i;
end end
slave_1: begin slave_1: begin
s1_req_o <= m2_req_i; s1_req_o = m2_req_i;
s1_we_o <= m2_we_i; s1_we_o = m2_we_i;
s1_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; s1_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s1_data_o <= m2_data_i; s1_data_o = m2_data_i;
m2_ack_o <= s1_ack_i; m2_ack_o = s1_ack_i;
m2_data_o <= s1_data_i; m2_data_o = s1_data_i;
end end
slave_2: begin slave_2: begin
s2_req_o <= m2_req_i; s2_req_o = m2_req_i;
s2_we_o <= m2_we_i; s2_we_o = m2_we_i;
s2_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; s2_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s2_data_o <= m2_data_i; s2_data_o = m2_data_i;
m2_ack_o <= s2_ack_i; m2_ack_o = s2_ack_i;
m2_data_o <= s2_data_i; m2_data_o = s2_data_i;
end end
slave_3: begin slave_3: begin
s3_req_o <= m2_req_i; s3_req_o = m2_req_i;
s3_we_o <= m2_we_i; s3_we_o = m2_we_i;
s3_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; s3_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s3_data_o <= m2_data_i; s3_data_o = m2_data_i;
m2_ack_o <= s3_ack_i; m2_ack_o = s3_ack_i;
m2_data_o <= s3_data_i; m2_data_o = s3_data_i;
end end
slave_4: begin slave_4: begin
s4_req_o <= m2_req_i; s4_req_o = m2_req_i;
s4_we_o <= m2_we_i; s4_we_o = m2_we_i;
s4_addr_o <= {{4'h0}, {m2_addr_i[27:0]}}; s4_addr_o = {{4'h0}, {m2_addr_i[27:0]}};
s4_data_o <= m2_data_i; s4_data_o = m2_data_i;
m2_ack_o <= s4_ack_i; m2_ack_o = s4_ack_i;
m2_data_o <= s4_data_i; m2_data_o = s4_data_i;
end end
default: begin default: begin