rtl: add gen_buf.v

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head
liangkangnan 2020-09-12 14:14:59 +08:00
parent b57bfe7736
commit 8468303ba7
1 changed files with 46 additions and 0 deletions

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rtl/utils/gen_buf.v Normal file
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/*
Copyright 2020 Blue Liang, liangkangnan@163.com
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
// DP
module gen_ticks_sync #(
parameter DP = 2,
parameter DW = 32)(
input wire rst,
input wire clk,
input wire[DW-1:0] din,
output wire[DW-1:0] dout
);
wire[DW-1:0] sync_dat[DP-1:0];
genvar i;
generate
for (i = 0; i < DP; i = i + 1) begin
if (i == 0) begin
gen_rst_0_dff #(DW) rst_0_dff(clk, rst, din, sync_dat[0]);
end else begin
gen_rst_0_dff #(DW) rst_0_dff(clk, rst, sync_dat[i-1], sync_dat[i]);
end
end
endgenerate
assign dout = sync_dat[DP-1];
endmodule