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add interrupt support and example 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/1/head v1.1
liangkangnan 2020-03-08 15:09:30 +08:00
parent c7c9193982
commit 8b51737477
30 changed files with 84899 additions and 78766 deletions
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1
rtl/core/defines.v
View File

@ -89,6 +89,7 @@
`define INST_LUI 7'b0110111
`define INST_AUIPC 7'b0010111
`define INST_NOP 32'h00000001
`define INST_MRET 32'h30200073
`define INST_FENCE 7'b0001111

31
rtl/core/ex.v
View File

@ -40,6 +40,9 @@ module ex (
input wire div_ready_i,
input wire[`DoubleRegBus] div_result_i,
// from perips
input wire int_sig_i,
// to sram
output reg[`SramBus] sram_wdata_o, // ram write data
output reg[`SramAddrBus] sram_raddr_o, // ram read addr
@ -59,6 +62,10 @@ module ex (
output wire hold_flag_o,
output reg[`RegBus] hold_addr_o,
// to pc_reg
output reg int_flag_o,
output reg[`RegBus] int_addr_o,
// to pc_reg
output reg jump_flag_o, // if jump or not flag
output reg[`RegBus] jump_addr_o // jump dest addr
@ -83,6 +90,8 @@ module ex (
wire[2:0] funct3;
wire[6:0] funct7;
wire[4:0] rd;
reg[`SramAddrBus] saved_addr;
reg in_interrupt_context;
assign opcode = inst_i[6:0];
assign funct3 = inst_i[14:12];
@ -107,6 +116,28 @@ module ex (
assign hold_flag_o = (div_starting == `DivStop) ? `HoldDisable : `HoldEnable;
// handle interrupt signal
always @ (*) begin
if (rst == `RstEnable) begin
int_flag_o <= 1'b0;
in_interrupt_context <= 1'b0;
saved_addr <= `ZeroWord;
end else if (int_sig_i == 1'b1 && in_interrupt_context == 1'b0) begin
int_flag_o <= 1'b1;
int_addr_o <= 32'h4;
saved_addr <= inst_addr_i + 4'h4;
in_interrupt_context <= 1'b1;
end else begin
if (inst_i == `INST_MRET) begin
int_flag_o <= 1'b1;
int_addr_o <= saved_addr;
in_interrupt_context <= 1'b0;
end else if (inst_i == `INST_NOP) begin
int_flag_o <= 1'b0;
end
end
end
always @ (*) begin
if (rst == `RstEnable) begin
sram_raddr_o <= `ZeroWord;

6
rtl/core/id.v
View File

@ -25,6 +25,7 @@ module id (
input wire[`SramAddrBus] inst_addr_i, // inst addr
input wire jump_flag_ex_i,
input wire hold_flag_ex_i,
input wire int_flag_ex_i,
input wire halt_flag_dm_i,
// to regs
@ -68,6 +69,11 @@ module id (
sram_we_o <= `WriteDisable;
reg_we_o <= `WriteDisable;
inst_o <= `INST_NOP;
end else if (int_flag_ex_i == 1'b1 && inst_i != `INST_NOP) begin
inst_valid_o <= `InstValid;
sram_we_o <= `WriteDisable;
reg_we_o <= `WriteDisable;
inst_o <= `INST_NOP;
end else if (jump_flag_ex_i == `JumpEnable && inst_i != `INST_NOP) begin
inst_valid_o <= `InstValid;
sram_we_o <= `WriteDisable;

4
rtl/core/if_id.v
View File

@ -27,6 +27,7 @@ module if_id (
input wire jump_flag_ex_i,
input wire hold_flag_ex_i,
input wire int_flag_ex_i,
input wire dm_halt_req_i,
output reg[`SramBus] inst_o,
@ -41,6 +42,9 @@ module if_id (
end else if (dm_halt_req_i == 1'b1) begin
inst_o <= `INST_NOP;
inst_addr_o <= `ZeroWord;
end else if (int_flag_ex_i == 1'b1) begin
inst_o <= `INST_NOP;
inst_addr_o <= `ZeroWord;
end else if (jump_flag_ex_i == `JumpEnable) begin
inst_o <= `INST_NOP;
inst_addr_o <= `ZeroWord;

6
rtl/core/pc_reg.v
View File

@ -28,6 +28,9 @@ module pc_reg (
input wire hold_flag_ex_i,
input wire[`RegBus] hold_addr_ex_i,
input wire int_flag_ex_i,
input wire[`RegBus] int_addr_ex_i,
input wire dm_halt_req_i,
input wire dm_reset_req_i,
@ -44,6 +47,9 @@ module pc_reg (
offset <= `ZeroWord;
end else if (dm_halt_req_i == 1'b1) begin
pc_o <= offset;
end else if (int_flag_ex_i == 1'b1) begin
pc_o <= int_addr_ex_i;
offset <= int_addr_ex_i + 4'h4;
end else if (jump_flag_ex_i == `JumpEnable) begin
pc_o <= jump_addr_ex_i;
offset <= jump_addr_ex_i + 4'h4;

13
rtl/core/sim_ram.v
View File

@ -38,13 +38,18 @@ module sim_ram (
input wire ex_re_i, // ex read enable
input wire[`SramAddrBus] ex_raddr_i, // ex read addr
output reg[`SramBus] ex_rdata_o // ex read data
output reg[`SramBus] ex_rdata_o, // ex read data
output wire we_o,
input wire[`SramBus] rdata_i
);
reg[`SramBus] ram[0:`SramMemNum - 1];
reg[`SramBus] rom[0:`SramMemNum - 1];
assign we_o = (waddr_i >= 32'h10000000) ? 1'b1 : 1'b0;
// ex write mem
always @ (posedge clk) begin
if (rst == `RstDisable) begin
@ -85,7 +90,11 @@ module sim_ram (
if (rst == `RstEnable) begin
ex_rdata_o <= `ZeroWord;
end else if (ex_re_i == `ReadEnable) begin
ex_rdata_o <= ram[ex_raddr_i[13:2]];
if (ex_raddr_i < 32'h10000000) begin
ex_rdata_o <= ram[ex_raddr_i[13:2]];
end else begin
ex_rdata_o <= rdata_i;
end
end else begin
ex_rdata_o <= `ZeroWord;
end

31
rtl/core/tinyriscv_core.v
View File

@ -63,6 +63,8 @@ module tinyriscv_core (
wire[`SramAddrBus] ex_sram_waddr_o;
wire ex_jump_flag_o;
wire[`RegBus] ex_jump_addr_o;
wire ex_int_flag_o;
wire[`RegBus] ex_int_addr_o;
wire[`RegBus] ex_div_dividend_o;
wire[`RegBus] ex_div_divisor_o;
wire ex_div_start_o;
@ -79,11 +81,16 @@ module tinyriscv_core (
wire[`SramBus] ram_pc_rdata_o;
wire[`SramBus] ram_ex_rdata_o;
wire[`SramBus] ram_dm_rdata_o;
wire ram_we_o;
// div
wire[`DoubleRegBus] div_result_o;
wire div_ready_o;
// timer
wire timer_int_o;
wire[`SramBus] timer_rdata_o;
// jtag
wire jtag_halt_req;
wire jtag_reset_req;
@ -135,7 +142,9 @@ module tinyriscv_core (
.pc_rdata_o(ram_pc_rdata_o),
.ex_re_i(id_sram_re_o),
.ex_raddr_i(ex_sram_raddr_o),
.ex_rdata_o(ram_ex_rdata_o)
.ex_rdata_o(ram_ex_rdata_o),
.we_o(ram_we_o),
.rdata_i(timer_rdata_o)
);
pc_reg u_pc_reg(
@ -145,6 +154,8 @@ module tinyriscv_core (
.re_o(pc_re_o),
.hold_flag_ex_i(ex_hold_flag_o),
.hold_addr_ex_i(ex_hold_addr_o),
.int_flag_ex_i(ex_int_flag_o),
.int_addr_ex_i(ex_int_addr_o),
.dm_halt_req_i(jtag_halt_req),
.dm_reset_req_i(jtag_reset_req),
.jump_flag_ex_i(ex_jump_flag_o),
@ -174,6 +185,7 @@ module tinyriscv_core (
.inst_addr_o(if_inst_addr_o),
.jump_flag_ex_i(ex_jump_flag_o),
.hold_flag_ex_i(ex_hold_flag_o),
.int_flag_ex_i(ex_int_flag_o),
.dm_halt_req_i(jtag_halt_req)
);
@ -185,6 +197,7 @@ module tinyriscv_core (
.inst_addr_i(if_inst_addr_o),
.jump_flag_ex_i(ex_jump_flag_o),
.hold_flag_ex_i(ex_hold_flag_o),
.int_flag_ex_i(ex_int_flag_o),
.halt_flag_dm_i(jtag_halt_req),
.reg1_re_o(id_reg1_re_o),
.reg1_raddr_o(id_reg1_raddr_o),
@ -223,7 +236,10 @@ module tinyriscv_core (
.hold_flag_o(ex_hold_flag_o),
.hold_addr_o(ex_hold_addr_o),
.jump_flag_o(ex_jump_flag_o),
.jump_addr_o(ex_jump_addr_o)
.jump_addr_o(ex_jump_addr_o),
.int_sig_i(timer_int_o),
.int_flag_o(ex_int_flag_o),
.int_addr_o(ex_int_addr_o)
);
div u_div(
@ -254,4 +270,15 @@ module tinyriscv_core (
.reset_req(jtag_reset_req)
);
timer u_timer(
.clk(clk),
.rst(rst),
.wdata(ex_sram_wdata_o),
.waddr(ex_sram_waddr_o),
.raddr(ex_sram_raddr_o),
.rdata(timer_rdata_o),
.we(ram_we_o),
.int_sig(timer_int_o)
);
endmodule

7
sim/inst.data
View File

@ -1,9 +1,14 @@
0080006f
01c0006f
10000113
00000d13
00000d93
04c000ef
058000ef
00100d13
0000006f
00000097
000000e7
00008067
ff010113
00812623
01010413

15601
sim/out.vvp
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File diff suppressed because one or more lines are too long

2
sim/tinyriscv_core_tb.v
View File

@ -478,7 +478,7 @@ module tinyriscv_core_tb;
// sim timeout
initial begin
#5000000
#500000
$display("Time Out.");
$finish;
end

147446
sim/tinyriscv_core_tb.vcd
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File diff suppressed because it is too large Load Diff

BIN
tests/example/example.bin
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Binary file not shown.

96
tests/example/example.dump
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@ -1,96 +0,0 @@
example: file format elf32-littleriscv
Disassembly of section .text:
00000000 <_reset>:
0: 10000113 li sp,256
4: 00000d13 li s10,0
8: 00000d93 li s11,0
c: 04c000ef jal ra,58 <main>
10: 00100d13 li s10,1
00000014 <loop>:
14: 0000006f j 14 <loop>
00000018 <set_test_pass>:
18: ff010113 addi sp,sp,-16
1c: 00812623 sw s0,12(sp)
20: 01010413 addi s0,sp,16
24: 00100d93 li s11,1
28: 00000013 nop
2c: 00c12403 lw s0,12(sp)
30: 01010113 addi sp,sp,16
34: 00008067 ret
00000038 <set_test_fail>:
38: ff010113 addi sp,sp,-16
3c: 00812623 sw s0,12(sp)
40: 01010413 addi s0,sp,16
44: 00000d93 li s11,0
48: 00000013 nop
4c: 00c12403 lw s0,12(sp)
50: 01010113 addi sp,sp,16
54: 00008067 ret
00000058 <main>:
58: fe010113 addi sp,sp,-32
5c: 00112e23 sw ra,28(sp)
60: 00812c23 sw s0,24(sp)
64: 02010413 addi s0,sp,32
68: fe042423 sw zero,-24(s0)
6c: fe042623 sw zero,-20(s0)
70: 0200006f j 90 <main+0x38>
74: fe842703 lw a4,-24(s0)
78: fec42783 lw a5,-20(s0)
7c: 00f707b3 add a5,a4,a5
80: fef42423 sw a5,-24(s0)
84: fec42783 lw a5,-20(s0)
88: 00178793 addi a5,a5,1
8c: fef42623 sw a5,-20(s0)
90: fec42703 lw a4,-20(s0)
94: 06400793 li a5,100
98: fce7dee3 bge a5,a4,74 <main+0x1c>
9c: fe842703 lw a4,-24(s0)
a0: 000017b7 lui a5,0x1
a4: 3ba78793 addi a5,a5,954 # 13ba <_end+0x12ba>
a8: 00f71663 bne a4,a5,b4 <main+0x5c>
ac: f6dff0ef jal ra,18 <set_test_pass>
b0: 0080006f j b8 <main+0x60>
b4: f85ff0ef jal ra,38 <set_test_fail>
b8: 00000793 li a5,0
bc: 00078513 mv a0,a5
c0: 01c12083 lw ra,28(sp)
c4: 01812403 lw s0,24(sp)
c8: 02010113 addi sp,sp,32
cc: 00008067 ret
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19
c: 2055 jal b0 <main+0x58>
e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4)
14: 2065 jal bc <main+0x64>
16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0)
1e: 626d lui tp,0x1b
20: 6465 lui s0,0x19
22: 6564 flw fs1,76(a0)
24: 2064 fld fs1,192(s0)
26: 2c434347 0x2c434347
2a: 3620 fld fs0,104(a2)
2c: 2d34 fld fa3,88(a0)
2e: 6962 flw fs2,24(sp)
30: 2974 fld fa3,208(a0)
32: 3820 fld fs0,112(s0)
34: 322e fld ft4,232(sp)
36: 302e fld ft0,232(sp)
...

15
tests/example/reset.S
View File

@ -1,15 +0,0 @@
.section .text;
.align 2;
.globl _reset;
_reset:
la sp, _sp
li x26, 0x00
li x27, 0x00
call main
li x26, 0x01
loop:
j loop

8
tests/example/Makefile → tests/example/simple/Makefile
View File

@ -2,7 +2,7 @@
RISCV_ARCH := rv32i
RISCV_ABI := ilp32
RISCV_PATH := ../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/
RISCV_PATH := ../../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/
CFLAGS += -march=$(RISCV_ARCH)
CFLAGS += -mabi=$(RISCV_ABI)
@ -20,6 +20,6 @@ RISCV_READELF := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-readelf)
.PHONY: all
all:
$(RISCV_GCC) $(CFLAGS) reset.S main.c -Tlink.ld -o example
$(RISCV_OBJCOPY) -O binary example example.bin
$(RISCV_OBJDUMP) --disassemble-all example > example.dump
$(RISCV_GCC) $(CFLAGS) start.S main.c -Tlink.ld -o simple
$(RISCV_OBJCOPY) -O binary simple simple.bin
$(RISCV_OBJDUMP) --disassemble-all simple > simple.dump

0
tests/example/README.md → tests/example/simple/README.md
View File

2
tests/example/link.ld → tests/example/simple/link.ld
View File

@ -1,5 +1,5 @@
OUTPUT_ARCH( "riscv" )
ENTRY(_reset)
ENTRY(_start)
SECTIONS
{

0
tests/example/main.c → tests/example/simple/main.c
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BIN
tests/example/example → tests/example/simple/simple
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Binary file not shown.

BIN
tests/example/simple/simple.bin Normal file
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Binary file not shown.

105
tests/example/simple/simple.dump Normal file
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@ -0,0 +1,105 @@
simple: file format elf32-littleriscv
Disassembly of section .text:
00000000 <_start>:
0: 0080006f j 8 <_reset_handler>
4: 01c0006f j 20 <_timer_handler>
00000008 <_reset_handler>:
8: 10000113 li sp,256
c: 00000d13 li s10,0
10: 00000d93 li s11,0
14: 058000ef jal ra,6c <main>
18: 00100d13 li s10,1
0000001c <loop>:
1c: 0000006f j 1c <loop>
00000020 <_timer_handler>:
20: 00000097 auipc ra,0x0
24: 000000e7 jalr zero # 0 <_start>
28: 00008067 ret
0000002c <set_test_pass>:
2c: ff010113 addi sp,sp,-16
30: 00812623 sw s0,12(sp)
34: 01010413 addi s0,sp,16
38: 00100d93 li s11,1
3c: 00000013 nop
40: 00c12403 lw s0,12(sp)
44: 01010113 addi sp,sp,16
48: 00008067 ret
0000004c <set_test_fail>:
4c: ff010113 addi sp,sp,-16
50: 00812623 sw s0,12(sp)
54: 01010413 addi s0,sp,16
58: 00000d93 li s11,0
5c: 00000013 nop
60: 00c12403 lw s0,12(sp)
64: 01010113 addi sp,sp,16
68: 00008067 ret
0000006c <main>:
6c: fe010113 addi sp,sp,-32
70: 00112e23 sw ra,28(sp)
74: 00812c23 sw s0,24(sp)
78: 02010413 addi s0,sp,32
7c: fe042423 sw zero,-24(s0)
80: fe042623 sw zero,-20(s0)
84: 0200006f j a4 <main+0x38>
88: fe842703 lw a4,-24(s0)
8c: fec42783 lw a5,-20(s0)
90: 00f707b3 add a5,a4,a5
94: fef42423 sw a5,-24(s0)
98: fec42783 lw a5,-20(s0)
9c: 00178793 addi a5,a5,1
a0: fef42623 sw a5,-20(s0)
a4: fec42703 lw a4,-20(s0)
a8: 06400793 li a5,100
ac: fce7dee3 bge a5,a4,88 <main+0x1c>
b0: fe842703 lw a4,-24(s0)
b4: 000017b7 lui a5,0x1
b8: 3ba78793 addi a5,a5,954 # 13ba <_end+0x12ba>
bc: 00f71663 bne a4,a5,c8 <main+0x5c>
c0: f6dff0ef jal ra,2c <set_test_pass>
c4: 0080006f j cc <main+0x60>
c8: f85ff0ef jal ra,4c <set_test_fail>
cc: 00000793 li a5,0
d0: 00078513 mv a0,a5
d4: 01c12083 lw ra,28(sp)
d8: 01812403 lw s0,24(sp)
dc: 02010113 addi sp,sp,32
e0: 00008067 ret
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19
c: 2055 jal b0 <main+0x44>
e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4)
14: 2065 jal bc <main+0x50>
16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0)
1e: 626d lui tp,0x1b
20: 6465 lui s0,0x19
22: 6564 flw fs1,76(a0)
24: 2064 fld fs1,192(s0)
26: 2c434347 0x2c434347
2a: 3620 fld fs0,104(a2)
2c: 2d34 fld fa3,88(a0)
2e: 6962 flw fs2,24(sp)
30: 2974 fld fa3,208(a0)
32: 3820 fld fs0,112(s0)
34: 322e fld ft4,232(sp)
36: 302e fld ft0,232(sp)
...

26
tests/example/simple/start.S Normal file
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@ -0,0 +1,26 @@
.section .text;
.align 2;
.globl _start;
.weak TIMER_IRQHandler
_start:
j _reset_handler
j _timer_handler
_reset_handler:
la sp, _sp
li x26, 0x00
li x27, 0x00
call main
li x26, 0x01
loop:
j loop
_timer_handler:
call TIMER_IRQHandler
ret

25
tests/example/timer_int/Makefile Normal file
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@ -0,0 +1,25 @@
RISCV_ARCH := rv32i
RISCV_ABI := ilp32
RISCV_PATH := ../../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/
CFLAGS += -march=$(RISCV_ARCH)
CFLAGS += -mabi=$(RISCV_ABI)
CFLAGS += -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
RISCV_AS := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-as)
RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
RISCV_OBJCOPY := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objcopy)
RISCV_READELF := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-readelf)
.PHONY: all
all:
$(RISCV_GCC) $(CFLAGS) start.S main.c -Tlink.ld -o timer_int
$(RISCV_OBJCOPY) -O binary timer_int timer_int.bin
$(RISCV_OBJDUMP) --disassemble-all timer_int > timer_int.dump

1
tests/example/timer_int/README.md Normal file
View File

@ -0,0 +1 @@
a simple c program which can run on tinyriscv.

25
tests/example/timer_int/link.ld Normal file
View File

@ -0,0 +1,25 @@
OUTPUT_ARCH( "riscv" )
ENTRY(_start)
SECTIONS
{
__stack_size = 0x1000;
. = 0x00000000;
.text : { *(.text) }
PROVIDE( _data_start = . );
.data ALIGN(0x1000) : { *(.data) }
. = ALIGN(4);
PROVIDE( _data_end = . );
PROVIDE( _bss_start = . );
.bss : { *(.bss) }
PROVIDE( _bss_end = . );
PROVIDE(_stack_begin = .);
. = __stack_size;
PROVIDE( _sp = . );
PROVIDE(_stack_end = .);
_end = .;
}

52
tests/example/timer_int/main.c Normal file
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@ -0,0 +1,52 @@
#include <stdint.h>
// Timer regs
#define TIMER_BASE (0x10000000)
#define TIMER_CTRL (TIMER_BASE + (0x00))
#define TIMER_COUNT (TIMER_BASE + (0x04))
#define TIMER_VALUE (TIMER_BASE + (0x08))
#define TIMER_REG(addr) (*((volatile uint32_t *)addr))
static uint32_t ms_count;
static void set_test_pass()
{
asm("li x27, 0x01");
}
static void set_test_fail()
{
asm("li x27, 0x00");
}
int main()
{
ms_count = 0;
TIMER_REG(TIMER_VALUE) = 500; // 10us period
TIMER_REG(TIMER_CTRL) = 0x07; // enable interrupt and start timer
while (1) {
if (ms_count == 5) {
TIMER_REG(TIMER_CTRL) = 0x00;
ms_count = 0;
// TODO: do something
set_test_pass();
break;
}
}
return 0;
}
void TIMER_IRQHandler()
{
TIMER_REG(TIMER_CTRL) = 0x07; // clear int pending
ms_count++;
}

30
tests/example/timer_int/start.S Normal file
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#define REGBYTES 4
#define STORE sw
#define LOAD lw
.section .text;
.align 2;
.globl _start;
.weak TIMER_IRQHandler
_start:
j _reset_handler
j _timer_handler
_reset_handler:
la sp, _sp
li x26, 0x00
li x27, 0x00
call main
li x26, 0x01
loop:
j loop
_timer_handler:
call TIMER_IRQHandler
mret

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tests/example/timer_int/timer_int Normal file
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tests/example/timer_int/timer_int.bin Normal file
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tests/example/timer_int/timer_int.dump Normal file
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timer_int: file format elf32-littleriscv
Disassembly of section .text:
00000000 <_start>:
0: 0080006f j 8 <_reset_handler>
4: 0200006f j 24 <_timer_handler>
00000008 <_reset_handler>:
8: 00001117 auipc sp,0x1
c: ff810113 addi sp,sp,-8 # 1000 <__stack_size>
10: 00000d13 li s10,0
14: 00000d93 li s11,0
18: 054000ef jal ra,6c <main>
1c: 00100d13 li s10,1
00000020 <loop>:
20: 0000006f j 20 <loop>
00000024 <_timer_handler>:
24: 0c8000ef jal ra,ec <TIMER_IRQHandler>
28: 30200073 mret
0000002c <set_test_pass>:
2c: ff010113 addi sp,sp,-16
30: 00812623 sw s0,12(sp)
34: 01010413 addi s0,sp,16
38: 00100d93 li s11,1
3c: 00000013 nop
40: 00c12403 lw s0,12(sp)
44: 01010113 addi sp,sp,16
48: 00008067 ret
0000004c <set_test_fail>:
4c: ff010113 addi sp,sp,-16
50: 00812623 sw s0,12(sp)
54: 01010413 addi s0,sp,16
58: 00000d93 li s11,0
5c: 00000013 nop
60: 00c12403 lw s0,12(sp)
64: 01010113 addi sp,sp,16
68: 00008067 ret
0000006c <main>:
6c: ff010113 addi sp,sp,-16
70: 00112623 sw ra,12(sp)
74: 00812423 sw s0,8(sp)
78: 01010413 addi s0,sp,16
7c: 00001797 auipc a5,0x1
80: f8478793 addi a5,a5,-124 # 1000 <__stack_size>
84: 0007a023 sw zero,0(a5)
88: 100007b7 lui a5,0x10000
8c: 00878793 addi a5,a5,8 # 10000008 <__stack_size+0xffff008>
90: 1f400713 li a4,500
94: 00e7a023 sw a4,0(a5)
98: 100007b7 lui a5,0x10000
9c: 00700713 li a4,7
a0: 00e7a023 sw a4,0(a5) # 10000000 <__stack_size+0xffff000>
a4: 00001797 auipc a5,0x1
a8: f5c78793 addi a5,a5,-164 # 1000 <__stack_size>
ac: 0007a703 lw a4,0(a5)
b0: 00500793 li a5,5
b4: fef718e3 bne a4,a5,a4 <main+0x38>
b8: 100007b7 lui a5,0x10000
bc: 0007a023 sw zero,0(a5) # 10000000 <__stack_size+0xffff000>
c0: 00001797 auipc a5,0x1
c4: f4078793 addi a5,a5,-192 # 1000 <__stack_size>
c8: 0007a023 sw zero,0(a5)
cc: f61ff0ef jal ra,2c <set_test_pass>
d0: 00000013 nop
d4: 00000793 li a5,0
d8: 00078513 mv a0,a5
dc: 00c12083 lw ra,12(sp)
e0: 00812403 lw s0,8(sp)
e4: 01010113 addi sp,sp,16
e8: 00008067 ret
000000ec <TIMER_IRQHandler>:
ec: ff010113 addi sp,sp,-16
f0: 00812623 sw s0,12(sp)
f4: 01010413 addi s0,sp,16
f8: 100007b7 lui a5,0x10000
fc: 00700713 li a4,7
100: 00e7a023 sw a4,0(a5) # 10000000 <__stack_size+0xffff000>
104: 00001797 auipc a5,0x1
108: efc78793 addi a5,a5,-260 # 1000 <__stack_size>
10c: 0007a783 lw a5,0(a5)
110: 00178713 addi a4,a5,1
114: 00001797 auipc a5,0x1
118: eec78793 addi a5,a5,-276 # 1000 <__stack_size>
11c: 00e7a023 sw a4,0(a5)
120: 00000013 nop
124: 00c12403 lw s0,12(sp)
128: 01010113 addi sp,sp,16
12c: 00008067 ret
Disassembly of section .bss:
00001000 <_end>:
1000: 0000 unimp
...
Disassembly of section .comment:
00000000 <.comment>:
0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm
4: 2820 fld fs0,80(s0)
6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm
a: 434d li t1,19
c: 2055 jal b0 <main+0x44>
e: 6345 lui t1,0x11
10: 696c flw fa1,84(a0)
12: 7370 flw fa2,100(a4)
14: 2065 jal bc <main+0x50>
16: 4952 lw s2,20(sp)
18: 562d4353 0x562d4353
1c: 4520 lw s0,72(a0)
1e: 626d lui tp,0x1b
20: 6465 lui s0,0x19
22: 6564 flw fs1,76(a0)
24: 2064 fld fs1,192(s0)
26: 2c434347 0x2c434347
2a: 3620 fld fs0,104(a2)
2c: 2d34 fld fa3,88(a0)
2e: 6962 flw fs2,24(sp)
30: 2974 fld fa3,208(a0)
32: 3820 fld fs0,112(s0)
34: 322e fld ft4,232(sp)
36: 302e fld ft0,232(sp)
...