rtl: div: timing optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>pull/1/head
liangkangnan
parent
90f57951e4
commit
8c3d7ac932
366
rtl/core/div.v
366
rtl/core/div.v
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@ -40,166 +40,336 @@ module div(
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);
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// 状态定义
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localparam STATE_IDLE = 4'b0001;
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localparam STATE_START = 4'b0010;
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localparam STATE_INVERT = 4'b0100;
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localparam STATE_END = 4'b1000;
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localparam STATE_IDLE = 5'b00001;
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localparam STATE_START = 5'b00010;
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localparam STATE_CALC = 5'b00100;
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localparam STATE_INVERT = 5'b01000;
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localparam STATE_END = 5'b10000;
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reg[`RegBus] dividend_temp;
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reg[`RegBus] divisor_temp;
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reg[3:0] state;
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reg[4:0] state;
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reg[4:0] next_state;
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reg[`RegBus] dividend_r;
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reg[`RegBus] divisor_r;
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reg[2:0] op_r;
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reg[31:0] count;
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reg[`RegBus] div_result;
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reg[`RegBus] div_remain;
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reg[`RegBus] minuend;
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reg invert_result;
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reg inst_div;
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reg inst_divu;
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wire[31:0] dividend_invert = -dividend_i;
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wire[31:0] divisor_invert = -divisor_i;
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wire[31:0] minuend_sub_res = minuend - divisor_temp;
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wire minuend_ge_divisor = minuend >= divisor_temp;
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wire[31:0] dividend_invert = (-dividend_r);
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wire[31:0] divisor_invert = (-divisor_r);
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wire[31:0] minuend_sub_res = (minuend - divisor_r);
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wire minuend_ge_divisor = (minuend >= divisor_r);
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wire op_div = (op_i == `INST_DIV);
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wire op_divu = (op_i == `INST_DIVU);
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wire op_rem = (op_i == `INST_REM);
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wire op_remu = (op_i == `INST_REMU);
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wire op_div = (op_r == `INST_DIV);
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wire op_divu = (op_r == `INST_DIVU);
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wire op_rem = (op_r == `INST_REM);
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wire op_remu = (op_r == `INST_REMU);
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wire is_divisor_zero = (divisor_r == `ZeroWord);
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// 状态机实现
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// 当前状态切换
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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state <= STATE_IDLE;
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ready_o <= `DivResultNotReady;
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result_o <= `ZeroWord;
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div_result <= `ZeroWord;
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div_remain <= `ZeroWord;
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reg_waddr_o <= `ZeroWord;
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dividend_temp <= `ZeroWord;
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divisor_temp <= `ZeroWord;
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minuend <= `ZeroWord;
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count <= `ZeroWord;
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invert_result <= 1'b0;
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busy_o <= `False;
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inst_div <= 1'b0;
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inst_divu <= 1'b0;
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end else begin
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state <= next_state;
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end
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end
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// 下一个状态切换
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always @ (*) begin
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if (start_i == `DivStart) begin
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case (state)
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STATE_IDLE: begin
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next_state = STATE_START;
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end
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STATE_START: begin
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if (is_divisor_zero) begin
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next_state = STATE_IDLE;
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end else begin
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next_state = STATE_CALC;
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end
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end
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STATE_CALC: begin
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if (count == `ZeroWord) begin
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next_state = STATE_INVERT;
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end else begin
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next_state = STATE_CALC;
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end
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end
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STATE_INVERT: begin
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next_state = STATE_END;
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end
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STATE_END: begin
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next_state = STATE_IDLE;
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end
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default: begin
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next_state = STATE_IDLE;
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end
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endcase
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end else begin
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next_state = STATE_IDLE;
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end
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end
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// 具体操作
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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op_r <= 3'h0;
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end else begin
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if (start_i == `DivStart && state == STATE_IDLE) begin
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op_r <= op_i;
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end
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end
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end
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// 运算完后要写的寄存器地址
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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reg_waddr_o <= `ZeroReg;
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end else begin
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if (start_i == `DivStart && state == STATE_IDLE) begin
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reg_waddr_o <= reg_waddr_i;
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end
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end
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end
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// 被除数
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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dividend_r <= `ZeroWord;
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end else begin
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case (state)
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STATE_IDLE: begin
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busy_o <= `False;
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if (start_i == `DivStart) begin
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reg_waddr_o <= reg_waddr_i;
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inst_div <= op_div;
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inst_divu <= op_divu;
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dividend_r <= dividend_i;
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end
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end
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STATE_START: begin
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// 除数不为0
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if (!is_divisor_zero) begin
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// DIV和REM这两条指令是有符号数运算
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if ((op_div | op_rem) & dividend_r[31]) begin
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// 被除数求补码
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dividend_r <= dividend_invert;
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end
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end
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end
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STATE_CALC: begin
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if (|count) begin
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dividend_r <= {dividend_r[30:0], 1'b0};
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end
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end
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endcase
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end
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end
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// 除数
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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divisor_r <= `ZeroWord;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (start_i == `DivStart) begin
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divisor_r <= divisor_i;
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end
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end
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STATE_START: begin
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// 除数不为0
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if (!is_divisor_zero) begin
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// DIV和REM这两条指令是有符号数运算
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if ((op_div | op_rem) & divisor_r[31]) begin
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// 除数求补码
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divisor_r <= divisor_invert;
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end
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end
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end
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endcase
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end
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end
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// 运算结束
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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ready_o <= `DivResultNotReady;
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end else begin
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case (state)
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STATE_IDLE: begin
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ready_o <= `DivResultNotReady;
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end
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STATE_START: begin
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// 除数为0
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if (divisor_i == `ZeroWord) begin
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if (is_divisor_zero) begin
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ready_o <= `DivResultReady;
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end
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end
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STATE_END: begin
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ready_o <= `DivResultReady;
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end
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endcase
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end
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end
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// 最终结果
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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result_o <= `ZeroWord;
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end else begin
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case (state)
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STATE_IDLE: begin
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result_o <= `ZeroWord;
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end
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STATE_START: begin
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// 除数为0
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if (is_divisor_zero) begin
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if (op_div | op_divu) begin
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result_o <= 32'hffffffff;
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end else begin
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result_o <= dividend_i;
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result_o <= dividend_r;
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end
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end
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end
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STATE_END: begin
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if (op_div | op_divu) begin
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result_o <= div_result;
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end else begin
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result_o <= div_remain;
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end
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end
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endcase
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end
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end
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// bit计数
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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count <= `ZeroWord;
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end else begin
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case (state)
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STATE_START: begin
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// 除数不为0
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end else begin
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if (!is_divisor_zero) begin
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count <= 32'h80000000;
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state <= STATE_START;
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// DIV和REM这两条指令是有符号数运算
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if ((op_div) || (op_rem)) begin
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// 被除数求补码
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if (dividend_i[31] == 1'b1) begin
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dividend_temp <= dividend_invert;
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minuend <= dividend_invert[31];
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end else begin
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dividend_temp <= dividend_i;
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minuend <= dividend_i[31];
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end
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// 除数求补码
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if (divisor_i[31] == 1'b1) begin
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divisor_temp <= divisor_invert;
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end else begin
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divisor_temp <= divisor_i;
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end
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end else begin
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dividend_temp <= dividend_i;
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minuend <= dividend_i[31];
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divisor_temp <= divisor_i;
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STATE_CALC: begin
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if (|count) begin
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count <= {1'b0, count[31:1]};
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end
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end
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endcase
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end
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end
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// 结果是否取补码
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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invert_result <= 1'b0;
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end else begin
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case (state)
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STATE_START: begin
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// 除数不为0
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if (!is_divisor_zero) begin
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// 运算结束后是否要对结果取补码
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if (((op_div) && (dividend_i[31] ^ divisor_i[31] == 1'b1))
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|| ((op_rem) && (dividend_i[31] == 1'b1))) begin
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if (((op_div) && (dividend_r[31] ^ divisor_r[31] == 1'b1))
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|| ((op_rem) && (dividend_r[31] == 1'b1))) begin
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invert_result <= 1'b1;
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end else begin
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invert_result <= 1'b0;
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end
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end
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end else begin
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ready_o <= `DivResultNotReady;
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result_o <= `ZeroWord;
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end
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endcase
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end
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end
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// 被减数
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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minuend <= `ZeroWord;
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end else begin
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case (state)
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STATE_START: begin
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busy_o <= `True;
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if (start_i == `DivStart) begin
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div_result <= {div_result[30:0], minuend_ge_divisor};
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// 除数不为0
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if (!is_divisor_zero) begin
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// DIV和REM这两条指令是有符号数运算
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if ((op_div | op_rem) & dividend_r[31]) begin
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minuend <= dividend_invert[31];
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end else begin
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minuend <= dividend_r[31];
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end
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end
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end
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STATE_CALC: begin
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if (|count) begin
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if (minuend_ge_divisor) begin
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minuend <= {minuend_sub_res[30:0], dividend_temp[31]};
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minuend <= {minuend_sub_res[30:0], dividend_r[31]};
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end else begin
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minuend <= {minuend[30:0], dividend_temp[31]};
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minuend <= {minuend[30:0], dividend_r[31]};
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end
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count <= {1'b0, count[31:1]};
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dividend_temp <= {dividend_temp[30:0], 1'b0};
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end
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end
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endcase
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end
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end
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// 商
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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div_result <= `ZeroWord;
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end else begin
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state <= STATE_INVERT;
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case (state)
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STATE_CALC: begin
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div_result <= {div_result[30:0], minuend_ge_divisor};
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end
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STATE_INVERT: begin
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if (invert_result == 1'b1) begin
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div_result <= -div_result;
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end
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end
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endcase
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end
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end
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// 余数
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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div_remain <= `ZeroWord;
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end else begin
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case (state)
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STATE_CALC: begin
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if (count == `ZeroWord) begin
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if (minuend_ge_divisor) begin
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div_remain <= minuend_sub_res;
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end else begin
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div_remain <= minuend;
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end
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end
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end else begin
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ready_o <= `DivResultNotReady;
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result_o <= `ZeroWord;
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state <= STATE_IDLE;
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end
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end
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STATE_INVERT: begin
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busy_o <= `True;
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if (start_i == `DivStart) begin
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if (invert_result == 1'b1) begin
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div_result <= -div_result;
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div_remain <= -div_remain;
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end
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state <= STATE_END;
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end else begin
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ready_o <= `DivResultNotReady;
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result_o <= `ZeroWord;
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state <= STATE_IDLE;
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end
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endcase
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end
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end
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STATE_END: begin
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// busy信号要比ready信号提前一个时钟撤销
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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busy_o <= `False;
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if (start_i == `DivStart) begin
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ready_o <= `DivResultReady;
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if (inst_div | inst_divu) begin
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result_o <= div_result;
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end else begin
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result_o <= div_remain;
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case (state)
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STATE_CALC, STATE_INVERT: begin
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busy_o <= `True;
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end
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state <= STATE_IDLE;
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end else begin
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state <= STATE_IDLE;
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result_o <= `ZeroWord;
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ready_o <= `DivResultNotReady;
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default: begin
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busy_o <= `False;
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end
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end
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endcase
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end
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end
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@ -14,7 +14,7 @@
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limitations under the License.
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*/
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// 带默认值和控制信号的流水线触发器
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module gen_pipe_dff #(
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parameter DW = 32)(
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@ -41,3 +41,109 @@ module gen_pipe_dff #(
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assign qout = qout_r;
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endmodule
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// 复位后输出为0的触发器
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module gen_rst_0_dff #(
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parameter DW = 32)(
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input wire clk,
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input wire rst,
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input wire[DW-1:0] din,
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output wire[DW-1:0] qout
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);
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reg[DW-1:0] qout_r;
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always @ (posedge clk) begin
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if (!rst) begin
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qout_r <= {DW{1'b0}};
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end else begin
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qout_r <= din;
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end
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end
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assign qout = qout_r;
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endmodule
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// 复位后输出为1的触发器
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module gen_rst_1_dff #(
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parameter DW = 32)(
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input wire clk,
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input wire rst,
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input wire[DW-1:0] din,
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output wire[DW-1:0] qout
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);
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reg[DW-1:0] qout_r;
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always @ (posedge clk) begin
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if (!rst) begin
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qout_r <= {DW{1'b1}};
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end else begin
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qout_r <= din;
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end
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end
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assign qout = qout_r;
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endmodule
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// 复位后输出为默认值的触发器
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module gen_rst_def_dff #(
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parameter DW = 32)(
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input wire clk,
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input wire rst,
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input wire[DW-1:0] def_val,
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input wire[DW-1:0] din,
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output wire[DW-1:0] qout
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);
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reg[DW-1:0] qout_r;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (!rst) begin
|
||||
qout_r <= def_val;
|
||||
end else begin
|
||||
qout_r <= din;
|
||||
end
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
|
||||
// 带使能端、复位后输出为0的触发器
|
||||
module gen_en_dff #(
|
||||
parameter DW = 32)(
|
||||
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
input wire en,
|
||||
input wire[DW-1:0] din,
|
||||
output wire[DW-1:0] qout
|
||||
|
||||
);
|
||||
|
||||
reg[DW-1:0] qout_r;
|
||||
|
||||
always @ (posedge clk) begin
|
||||
if (!rst) begin
|
||||
qout_r <= {DW{1'b0}};
|
||||
end else if (en == 1'b1) begin
|
||||
qout_r <= din;
|
||||
end
|
||||
end
|
||||
|
||||
assign qout = qout_r;
|
||||
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Reference in New Issue