sim: add dump wave enable by softwave

Signed-off-by: liangkangnan <liangkangnan@163.com>

rtl/top/tinyriscv_soc_top.sv

@@ -36,6 +36,10 @@ module tinyriscv_soc_top #(
 
     inout wire[1:0] gpio_pins,      // GPIO引脚，1bit代表一个GPIO
 
+`ifdef VERILATOR
+    output wire dump_wave_en_o,     // dump wave使能
+`endif
+
     input wire jtag_TCK_pin,        // JTAG TCK引脚
     input wire jtag_TMS_pin,        // JTAG TMS引脚
     input wire jtag_TDI_pin,        // JTAG TDI引脚
@@ -315,6 +319,7 @@ module tinyriscv_soc_top #(
     sim_ctrl u_sim_ctrl(
         .clk_i  (clk),
         .rst_ni (ndmreset_n),
+        .dump_wave_en_o(dump_wave_en_o),
         .req_i  (),
         .gnt_o  (),
         .addr_i (slave_addr[SimCtrl]),

sim/sim_ctrl.sv

@@ -16,11 +16,14 @@
 
 `define REG_CTRL  0
 `define REG_PRINT 4
+`define REG_DUMP  8
 
 module sim_ctrl(
     input  logic       clk_i,
     input  logic       rst_ni,
 
+    output logic       dump_wave_en_o,
+
     input  logic       req_i,
     output logic       gnt_o,
     input  logic[31:0] addr_i,
@@ -39,7 +42,7 @@ module sim_ctrl(
 
     always_ff @ (posedge clk_i or negedge rst_ni) begin
         if (!rst_ni) begin
-
+            dump_wave_en_o <= 1'b0;
         end else begin
             if (we_i) begin
                 case (reg_addr)
@@ -55,6 +58,16 @@ module sim_ctrl(
                             $display("%c", wdata_i[7:0]);
                         end
                     end
+
+                    `REG_DUMP: begin
+                        if (be_i[0] & wdata_i[0]) begin
+                            dump_wave_en_o <= 1'b1;
+                        end else if (be_i[0] & (!wdata_i[0])) begin
+                            dump_wave_en_o <= 1'b0;
+                        end
+                    end
+
+                    default: ;
                 endcase
             end
         end

sim/tb_top_verilator.cpp

@@ -42,6 +42,7 @@ int main(int argc, char **argv, char **env)
         top->eval();
 
 #ifdef VCD_TRACE
+        if (top->dump_wave_en_o)
             tfp->dump(t);
 #endif
 

sim/tb_top_verilator.sv

@@ -24,7 +24,8 @@ module tb_top_verilator #(
 
     ) (
        input wire  clk_i,
-       input wire  rst_ni
+       input wire  rst_ni,
+       output wire dump_wave_en_o
     );
 
     wire halted;
@@ -106,6 +107,7 @@ module tb_top_verilator #(
     ) u_tinyriscv_soc_top (
         .clk_50m_i(clk_i),
         .rst_ext_ni(rst_ni),
+        .dump_wave_en_o(dump_wave_en_o),
         .halted_ind_pin(halted)
     );