parent
af74c11db8
commit
9420b85796
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@ -29,6 +29,12 @@
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`define ChipDisable 1'b0
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`define JumpEnable 1'b1
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`define JumpDisable 1'b0
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`define DivResultNotReady 1'b0
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`define DivResultReady 1'b1
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`define DivStart 1'b1
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`define DivStop 1'b0
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`define HoldEnable 1'b1
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`define HoldDisable 1'b0
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// I type inst
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`define INST_TYPE_I 7'b0010011
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@ -71,6 +77,10 @@
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`define INST_MULH 3'b001
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`define INST_MULHSU 3'b010
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`define INST_MULHU 3'b011
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`define INST_DIV 3'b100
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`define INST_DIVU 3'b101
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`define INST_REM 3'b110
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`define INST_REMU 3'b111
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// J type inst
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`define INST_JAL 7'b1101111
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@ -0,0 +1,131 @@
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`include "defines.v"
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module div (
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input wire clk,
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input wire rst,
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input wire[`RegBus] dividend_i,
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input wire[`RegBus] divisor_i,
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input wire start_i,
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output reg[`DoubleRegBus] result_o,
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output reg ready_o
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);
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parameter STATE_IDLE = 0;
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parameter STATE_START = 1;
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parameter STATE_REVERT = 2;
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parameter STATE_END = 3;
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reg[`RegBus] dividend_temp;
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reg[`RegBus] divisor_temp;
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reg[1:0] state;
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reg[6:0] count;
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reg[`RegBus] div_result;
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reg[`RegBus] div_remain;
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reg[`RegBus] minuend;
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reg[`RegBus] divisor_zero_result;
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always @ (posedge clk) begin
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if (rst == `RstEnable) begin
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state <= STATE_IDLE;
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ready_o <= `DivResultNotReady;
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result_o <= {`ZeroWord, `ZeroWord};
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div_result <= `ZeroWord;
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div_remain <= `ZeroWord;
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divisor_zero_result <= ~32'b00000001 + 1'b1;
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end else begin
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case (state)
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STATE_IDLE: begin
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if (start_i == `DivStart) begin
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if (divisor_i == `ZeroWord) begin
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ready_o <= `DivResultReady;
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result_o <= {`ZeroWord, divisor_zero_result};
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end else begin
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count <= 7'd31;
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state <= STATE_START;
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if (dividend_i[31] == 1'b1) begin
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dividend_temp <= ~dividend_i + 1;
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minuend <= ((~dividend_i + 1) >> 7'd31) & 1'b1;
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end else begin
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dividend_temp <= dividend_i;
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minuend <= (dividend_i >> 7'd31) & 1'b1;
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end
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if (divisor_i[31] == 1'b1) begin
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divisor_temp <= ~divisor_i + 1;
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end else begin
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divisor_temp <= divisor_i;
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end
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div_result <= `ZeroWord;
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div_remain <= `ZeroWord;
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end
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end else begin
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ready_o <= `DivResultNotReady;
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result_o <= {`ZeroWord, `ZeroWord};
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end
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end
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STATE_START: begin
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if (start_i == `DivStart) begin
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if (count >= 7'd1) begin
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if (minuend >= divisor_temp) begin
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div_result <= (div_result << 1'b1) | 1'b1;
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minuend <= ((minuend - divisor_temp) << 1'b1) | ((dividend_temp >> (count - 1'b1)) & 1'b1);
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end else begin
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div_result <= (div_result << 1'b1) | 1'b0;
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minuend <= (minuend << 1'b1) | ((dividend_temp >> (count - 1'b1)) & 1'b1);
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end
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count <= count - 1'b1;
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end else begin
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state <= STATE_REVERT;
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if (minuend >= divisor_temp) begin
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div_result <= (div_result << 1'b1) | 1'b1;
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div_remain <= minuend - divisor_temp;
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end else begin
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div_result <= (div_result << 1'b1) | 1'b0;
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div_remain <= minuend;
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end
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end
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end else begin
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ready_o <= `DivResultReady;
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result_o <= {`ZeroWord, `ZeroWord};
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state <= STATE_IDLE;
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end
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end
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STATE_REVERT: begin
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if (start_i == `DivStart) begin
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if (dividend_i[31] ^ divisor_i[31] == 1'b1) begin
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div_result <= ~div_result + 1'b1;
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end
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if (((dividend_i[31] == 1'b1) && (div_remain >= 0)) || ((dividend_i[31] == 1'b0) && (div_remain < 0))) begin
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div_remain <= ~div_remain + 1'b1;
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end
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state <= STATE_END;
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end else begin
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ready_o <= `DivResultReady;
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result_o <= {`ZeroWord, `ZeroWord};
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state <= STATE_IDLE;
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end
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end
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STATE_END: begin
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if (start_i == `DivStart) begin
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ready_o <= `DivResultReady;
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result_o <= {div_remain, div_result};
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end else begin
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state <= STATE_IDLE;
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ready_o <= `DivResultNotReady;
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end
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end
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endcase
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end
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end
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endmodule
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132
rtl/ex.v
132
rtl/ex.v
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@ -26,6 +26,8 @@ module ex (
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input wire[`SramBus] inst_i, // inst content
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input wire inst_valid_i,
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input wire[`SramAddrBus] inst_addr_i, // inst addr
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input wire reg_we_i,
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input wire[`RegAddrBus] reg_waddr_i,
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// from regs
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input wire[`RegBus] reg1_rdata_i, // reg1 read data
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@ -34,6 +36,10 @@ module ex (
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// from sram
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input wire[`SramBus] sram_rdata_i, // ram read data
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// from div
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input wire div_ready_i,
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input wire[`DoubleRegBus] div_result_i,
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// to sram
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output reg[`SramBus] sram_wdata_o, // ram write data
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output reg[`SramAddrBus] sram_raddr_o, // ram read addr
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@ -41,6 +47,17 @@ module ex (
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// to regs
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output reg[`RegBus] reg_wdata_o, // reg write data
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output reg reg_we_o, // reg write enable
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output reg[`RegAddrBus] reg_waddr_o, // reg write addr
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// to div
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output reg[`RegBus] div_dividend_o,
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output reg[`RegBus] div_divisor_o,
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output reg div_start_o,
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// to pc_reg
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output reg hold_flag_o,
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output reg[`RegBus] hold_addr_o,
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// to pc_reg
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output reg jump_flag_o, // if jump or not flag
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@ -59,10 +76,16 @@ module ex (
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wire[`DoubleRegBus] mulhsu_temp_invert;
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wire[`RegBus] op1_mul;
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wire[`RegBus] op2_mul;
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reg div_starting;
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reg is_jumping;
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reg div_reg_we;
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reg[4:0] div_rd_reg;
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reg[2:0] div_funct3;
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wire[6:0] opcode = inst_i[6:0];
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wire[2:0] funct3 = inst_i[14:12];
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wire[6:0] funct7 = inst_i[31:25];
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wire[4:0] rd = inst_i[11:7];
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assign sign_extend_tmp = {{20{inst_i[31]}}, inst_i[31:20]};
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assign shift_bits = inst_i[24:20];
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if (rst == `RstEnable) begin
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sram_raddr_o <= `ZeroWord;
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jump_flag_o <= `JumpDisable;
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hold_flag_o <= `HoldDisable;
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sram_raddr_index <= 2'b0;
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sram_waddr_index <= 2'b0;
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div_starting <= `DivStop;
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is_jumping <= `False;
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div_reg_we <= `WriteDisable;
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div_start_o <= `DivStop;
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end
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end
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always @ (*) begin
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if (inst_valid_i == `InstValid) begin
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div_dividend_o <= reg1_rdata_i;
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div_divisor_o <= reg2_rdata_i;
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end
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always @ (*) begin
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reg_we_o <= reg_we_i | div_reg_we;
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end
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always @ (*) begin
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if ((is_jumping == `False) && (div_starting == `DivStart)) begin
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if (div_ready_i == `DivResultReady) begin
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case (div_funct3)
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`INST_DIV: begin
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div_reg_we <= `WriteEnable;
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reg_waddr_o <= div_rd_reg;
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reg_wdata_o <= div_result_i[31:0];
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div_starting <= `DivStop;
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div_start_o <= `DivStop;
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hold_flag_o <= `HoldDisable;
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end
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`INST_DIVU: begin
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div_reg_we <= `WriteEnable;
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reg_waddr_o <= div_rd_reg;
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reg_wdata_o <= div_result_i[31:0];
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div_starting <= `DivStop;
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div_start_o <= `DivStop;
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hold_flag_o <= `HoldDisable;
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end
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`INST_REM: begin
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div_reg_we <= `WriteEnable;
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reg_waddr_o <= div_rd_reg;
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reg_wdata_o <= div_result_i[63:32];
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div_starting <= `DivStop;
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div_start_o <= `DivStop;
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hold_flag_o <= `HoldDisable;
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end
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`INST_REMU: begin
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div_reg_we <= `WriteEnable;
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reg_waddr_o <= div_rd_reg;
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reg_wdata_o <= div_result_i[63:32];
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div_starting <= `DivStop;
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div_start_o <= `DivStop;
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hold_flag_o <= `HoldDisable;
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end
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endcase
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end
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end else if (inst_valid_i == `InstValid) begin
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div_reg_we <= `WriteDisable;
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reg_waddr_o <= reg_waddr_i;
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case (opcode)
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`INST_TYPE_I: begin
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case (funct3)
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reg_wdata_o <= mulhsu_temp[63:32];
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end
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end
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`INST_DIV: begin
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jump_flag_o <= `JumpDisable;
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hold_flag_o <= `HoldEnable;
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div_start_o <= `DivStart;
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div_starting <= `DivStart;
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div_rd_reg <= rd;
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div_funct3 <= funct3;
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hold_addr_o <= inst_addr_i + 4'h4;
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end
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`INST_DIVU: begin
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jump_flag_o <= `JumpDisable;
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hold_flag_o <= `HoldEnable;
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div_start_o <= `DivStart;
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div_starting <= `DivStart;
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div_rd_reg <= rd;
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div_funct3 <= funct3;
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hold_addr_o <= inst_addr_i + 4'h4;
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end
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`INST_REM: begin
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jump_flag_o <= `JumpDisable;
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hold_flag_o <= `HoldEnable;
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div_start_o <= `DivStart;
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div_starting <= `DivStart;
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div_rd_reg <= rd;
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div_funct3 <= funct3;
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hold_addr_o <= inst_addr_i + 4'h4;
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end
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`INST_REMU: begin
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jump_flag_o <= `JumpDisable;
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hold_flag_o <= `HoldEnable;
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div_start_o <= `DivStart;
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div_starting <= `DivStart;
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div_rd_reg <= rd;
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div_funct3 <= funct3;
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hold_addr_o <= inst_addr_i + 4'h4;
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end
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endcase
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end
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end
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@ -323,6 +435,7 @@ module ex (
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`INST_BEQ: begin
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if (reg1_rdata_i == reg2_rdata_i) begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end else begin
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jump_flag_o <= `JumpDisable;
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@ -331,6 +444,7 @@ module ex (
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`INST_BNE: begin
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if (reg1_rdata_i != reg2_rdata_i) begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end else begin
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jump_flag_o <= `JumpDisable;
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@ -339,12 +453,14 @@ module ex (
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`INST_BLT: begin
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if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
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if (reg1_rdata_i >= reg2_rdata_i) begin
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jump_flag_o <= `JumpDisable;
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end else begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end
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end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
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@ -352,6 +468,7 @@ module ex (
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jump_flag_o <= `JumpDisable;
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end else begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end
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end else begin
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@ -361,12 +478,14 @@ module ex (
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`INST_BGE: begin
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if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
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if (reg1_rdata_i < reg2_rdata_i) begin
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jump_flag_o <= `JumpDisable;
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end else begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end
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end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
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@ -374,6 +493,7 @@ module ex (
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jump_flag_o <= `JumpDisable;
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end else begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end
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end else begin
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@ -388,6 +508,7 @@ module ex (
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jump_flag_o <= `JumpDisable;
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end else begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end
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end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
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@ -395,10 +516,12 @@ module ex (
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jump_flag_o <= `JumpDisable;
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end else begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end
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end else begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end
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end
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@ -410,6 +533,7 @@ module ex (
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jump_flag_o <= `JumpDisable;
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end else begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end
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end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
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@ -417,10 +541,12 @@ module ex (
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jump_flag_o <= `JumpDisable;
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end else begin
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jump_flag_o <= `JumpEnable;
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is_jumping <= `True;
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jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
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end
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end else begin
|
||||
jump_flag_o <= `JumpEnable;
|
||||
is_jumping <= `True;
|
||||
jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
|
||||
end
|
||||
end
|
||||
|
@ -428,11 +554,13 @@ module ex (
|
|||
end
|
||||
`INST_JAL: begin
|
||||
jump_flag_o <= `JumpEnable;
|
||||
is_jumping <= `True;
|
||||
jump_addr_o <= inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
|
||||
reg_wdata_o <= inst_addr_i + 4'h4;
|
||||
end
|
||||
`INST_JALR: begin
|
||||
jump_flag_o <= `JumpEnable;
|
||||
is_jumping <= `True;
|
||||
jump_addr_o <= (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe);
|
||||
reg_wdata_o <= inst_addr_i + 4'h4;
|
||||
end
|
||||
|
@ -446,9 +574,11 @@ module ex (
|
|||
end
|
||||
`INST_NOP: begin
|
||||
jump_flag_o <= `JumpDisable;
|
||||
is_jumping <= `False;
|
||||
end
|
||||
`INST_FENCE: begin
|
||||
jump_flag_o <= `JumpEnable;
|
||||
is_jumping <= `True;
|
||||
jump_addr_o <= inst_addr_i + 4'h4;
|
||||
end
|
||||
default: begin
|
||||
|
|
46
rtl/id.v
46
rtl/id.v
|
@ -24,6 +24,7 @@ module id (
|
|||
input wire[`SramBus] inst_i, // inst content
|
||||
input wire[`SramAddrBus] inst_addr_i, // inst addr
|
||||
input wire jump_flag_ex_i,
|
||||
input wire hold_flag_ex_i,
|
||||
|
||||
// to regs
|
||||
output reg reg1_re_o, // reg1 read enable
|
||||
|
@ -66,6 +67,11 @@ module id (
|
|||
sram_we_o <= `WriteDisable;
|
||||
reg_we_o <= `WriteDisable;
|
||||
inst_o <= `INST_NOP;
|
||||
end else if (hold_flag_ex_i == `HoldEnable) begin
|
||||
inst_valid_o <= `InstValid;
|
||||
sram_we_o <= `WriteDisable;
|
||||
reg_we_o <= `WriteDisable;
|
||||
inst_o <= `INST_NOP;
|
||||
end else begin
|
||||
inst_o <= inst_i;
|
||||
inst_addr_o <= inst_addr_i;
|
||||
|
@ -271,6 +277,46 @@ module id (
|
|||
reg2_raddr_o <= rs2;
|
||||
sram_we_o <= `WriteDisable;
|
||||
end
|
||||
`INST_DIV: begin
|
||||
inst_valid_o <= `InstValid;
|
||||
reg_we_o <= `WriteDisable;
|
||||
reg_waddr_o <= rd;
|
||||
reg1_re_o <= `ReadEnable;
|
||||
reg1_raddr_o <= rs1;
|
||||
reg2_re_o <= `ReadEnable;
|
||||
reg2_raddr_o <= rs2;
|
||||
sram_we_o <= `WriteDisable;
|
||||
end
|
||||
`INST_DIVU: begin
|
||||
inst_valid_o <= `InstValid;
|
||||
reg_we_o <= `WriteDisable;
|
||||
reg_waddr_o <= rd;
|
||||
reg1_re_o <= `ReadEnable;
|
||||
reg1_raddr_o <= rs1;
|
||||
reg2_re_o <= `ReadEnable;
|
||||
reg2_raddr_o <= rs2;
|
||||
sram_we_o <= `WriteDisable;
|
||||
end
|
||||
`INST_REM: begin
|
||||
inst_valid_o <= `InstValid;
|
||||
reg_we_o <= `WriteDisable;
|
||||
reg_waddr_o <= rd;
|
||||
reg1_re_o <= `ReadEnable;
|
||||
reg1_raddr_o <= rs1;
|
||||
reg2_re_o <= `ReadEnable;
|
||||
reg2_raddr_o <= rs2;
|
||||
sram_we_o <= `WriteDisable;
|
||||
end
|
||||
`INST_REMU: begin
|
||||
inst_valid_o <= `InstValid;
|
||||
reg_we_o <= `WriteDisable;
|
||||
reg_waddr_o <= rd;
|
||||
reg1_re_o <= `ReadEnable;
|
||||
reg1_raddr_o <= rs1;
|
||||
reg2_re_o <= `ReadEnable;
|
||||
reg2_raddr_o <= rs2;
|
||||
sram_we_o <= `WriteDisable;
|
||||
end
|
||||
default: begin
|
||||
inst_valid_o <= `InstInvalid;
|
||||
end
|
||||
|
|
|
@ -26,6 +26,7 @@ module if_id (
|
|||
input wire[`SramAddrBus] inst_addr_i, // inst addr
|
||||
|
||||
input wire jump_flag_ex_i,
|
||||
input wire hold_flag_ex_i,
|
||||
|
||||
output reg[`SramBus] inst_o,
|
||||
output reg[`SramAddrBus] inst_addr_o
|
||||
|
@ -39,6 +40,9 @@ module if_id (
|
|||
end else if (jump_flag_ex_i == `JumpEnable) begin
|
||||
inst_o <= `INST_NOP;
|
||||
inst_addr_o <= `ZeroWord;
|
||||
end else if (hold_flag_ex_i == `HoldEnable) begin
|
||||
inst_o <= `INST_NOP;
|
||||
inst_addr_o <= `ZeroWord;
|
||||
end else begin
|
||||
inst_o <= inst_i;
|
||||
inst_addr_o <= inst_addr_i;
|
||||
|
|
|
@ -53,6 +53,13 @@ module openriscv_core (
|
|||
wire[`SramAddrBus] ex_sram_waddr_o;
|
||||
wire ex_jump_flag_o;
|
||||
wire[`RegBus] ex_jump_addr_o;
|
||||
wire[`RegBus] ex_div_dividend_o;
|
||||
wire[`RegBus] ex_div_divisor_o;
|
||||
wire ex_div_start_o;
|
||||
wire ex_hold_flag_o;
|
||||
wire[`RegBus] ex_hold_addr_o;
|
||||
wire ex_reg_we_o;
|
||||
wire[`RegAddrBus] ex_reg_waddr_o;
|
||||
|
||||
// regs
|
||||
wire[`RegBus] regs_rdata1_o;
|
||||
|
@ -62,6 +69,10 @@ module openriscv_core (
|
|||
wire[`SramBus] ram_pc_rdata_o;
|
||||
wire[`SramBus] ram_ex_rdata_o;
|
||||
|
||||
// div
|
||||
wire[`DoubleRegBus] div_result_o;
|
||||
wire div_ready_o;
|
||||
|
||||
sim_ram u_sim_ram(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
@ -81,6 +92,8 @@ module openriscv_core (
|
|||
.rst(rst),
|
||||
.pc_o(pc_pc_o),
|
||||
.re_o(pc_re_o),
|
||||
.hold_flag_ex_i(ex_hold_flag_o),
|
||||
.hold_addr_ex_i(ex_hold_addr_o),
|
||||
.jump_flag_ex_i(ex_jump_flag_o),
|
||||
.jump_addr_ex_i(ex_jump_addr_o)
|
||||
);
|
||||
|
@ -88,8 +101,8 @@ module openriscv_core (
|
|||
regs u_regs(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.we(id_reg_we_o),
|
||||
.waddr(id_reg_waddr_o),
|
||||
.we(ex_reg_we_o),
|
||||
.waddr(ex_reg_waddr_o),
|
||||
.wdata(ex_reg_wdata_o),
|
||||
.re1(id_reg1_re_o),
|
||||
.raddr1(id_reg1_raddr_o),
|
||||
|
@ -106,7 +119,8 @@ module openriscv_core (
|
|||
.inst_addr_i(pc_pc_o),
|
||||
.inst_o(if_inst_o),
|
||||
.inst_addr_o(if_inst_addr_o),
|
||||
.jump_flag_ex_i(ex_jump_flag_o)
|
||||
.jump_flag_ex_i(ex_jump_flag_o),
|
||||
.hold_flag_ex_i(ex_hold_flag_o)
|
||||
);
|
||||
|
||||
id u_id(
|
||||
|
@ -116,6 +130,7 @@ module openriscv_core (
|
|||
.inst_addr_o(id_inst_addr_o),
|
||||
.inst_addr_i(if_inst_addr_o),
|
||||
.jump_flag_ex_i(ex_jump_flag_o),
|
||||
.hold_flag_ex_i(ex_hold_flag_o),
|
||||
.reg1_re_o(id_reg1_re_o),
|
||||
.reg1_raddr_o(id_reg1_raddr_o),
|
||||
.reg2_re_o(id_reg2_re_o),
|
||||
|
@ -134,15 +149,36 @@ module openriscv_core (
|
|||
.inst_i(id_inst_o),
|
||||
.inst_addr_i(id_inst_addr_o),
|
||||
.inst_valid_i(id_inst_valid_o),
|
||||
.reg_we_i(id_reg_we_o),
|
||||
.reg_waddr_i(id_reg_waddr_o),
|
||||
.reg1_rdata_i(regs_rdata1_o),
|
||||
.reg2_rdata_i(regs_rdata2_o),
|
||||
.reg_wdata_o(ex_reg_wdata_o),
|
||||
.reg_we_o(ex_reg_we_o),
|
||||
.reg_waddr_o(ex_reg_waddr_o),
|
||||
.sram_rdata_i(ram_ex_rdata_o),
|
||||
.sram_wdata_o(ex_sram_wdata_o),
|
||||
.sram_raddr_o(ex_sram_raddr_o),
|
||||
.sram_waddr_o(ex_sram_waddr_o),
|
||||
.div_dividend_o(ex_div_dividend_o),
|
||||
.div_divisor_o(ex_div_divisor_o),
|
||||
.div_ready_i(div_ready_o),
|
||||
.div_result_i(div_result_o),
|
||||
.div_start_o(ex_div_start_o),
|
||||
.hold_flag_o(ex_hold_flag_o),
|
||||
.hold_addr_o(ex_hold_addr_o),
|
||||
.jump_flag_o(ex_jump_flag_o),
|
||||
.jump_addr_o(ex_jump_addr_o)
|
||||
);
|
||||
|
||||
div u_div(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.dividend_i(ex_div_dividend_o),
|
||||
.divisor_i(ex_div_divisor_o),
|
||||
.start_i(ex_div_start_o),
|
||||
.result_o(div_result_o),
|
||||
.ready_o(div_ready_o)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
|
|
@ -25,6 +25,9 @@ module pc_reg (
|
|||
input wire jump_flag_ex_i,
|
||||
input wire[`RegBus] jump_addr_ex_i,
|
||||
|
||||
input wire hold_flag_ex_i,
|
||||
input wire[`RegBus] hold_addr_ex_i,
|
||||
|
||||
output reg[`SramAddrBus] pc_o,
|
||||
output reg re_o
|
||||
|
||||
|
@ -39,6 +42,9 @@ module pc_reg (
|
|||
end else if (jump_flag_ex_i == `JumpEnable) begin
|
||||
pc_o <= jump_addr_ex_i;
|
||||
offset <= jump_addr_ex_i + 4'h4;
|
||||
end else if (hold_flag_ex_i == `HoldEnable) begin
|
||||
pc_o <= hold_addr_ex_i;
|
||||
offset <= hold_addr_ex_i;
|
||||
end else begin
|
||||
pc_o <= offset;
|
||||
offset <= offset + 4'h4;
|
||||
|
|
|
@ -53,7 +53,7 @@ module openriscv_core_tb;
|
|||
|
||||
// sim timeout
|
||||
initial begin
|
||||
#100000
|
||||
#5000000
|
||||
$display("Time Out.");
|
||||
$finish;
|
||||
end
|
||||
|
|
|
@ -1,2 +1,2 @@
|
|||
iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v
|
||||
iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v ..\rtl\div.v
|
||||
vvp out.vvp
|
||||
|
|
|
@ -1,3 +1,3 @@
|
|||
..\tools\BinToMem_CLI.exe %1 %2
|
||||
iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v
|
||||
iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v ..\rtl\div.v
|
||||
vvp out.vvp
|
||||
|
|
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,105 @@
|
|||
|
||||
generated/rv32um-p-div: file format elf32-littleriscv
|
||||
|
||||
|
||||
Disassembly of section .text.init:
|
||||
|
||||
00000000 <_start>:
|
||||
0: 00000d13 li s10,0
|
||||
4: 00000d93 li s11,0
|
||||
|
||||
00000008 <test_2>:
|
||||
8: 01400093 li ra,20
|
||||
c: 00600113 li sp,6
|
||||
10: 0220cf33 div t5,ra,sp
|
||||
14: 00300e93 li t4,3
|
||||
18: 00200193 li gp,2
|
||||
1c: 0ddf1463 bne t5,t4,e4 <fail>
|
||||
|
||||
00000020 <test_3>:
|
||||
20: fec00093 li ra,-20
|
||||
24: 00600113 li sp,6
|
||||
28: 0220cf33 div t5,ra,sp
|
||||
2c: ffd00e93 li t4,-3
|
||||
30: 00300193 li gp,3
|
||||
34: 0bdf1863 bne t5,t4,e4 <fail>
|
||||
|
||||
00000038 <test_4>:
|
||||
38: 01400093 li ra,20
|
||||
3c: ffa00113 li sp,-6
|
||||
40: 0220cf33 div t5,ra,sp
|
||||
44: ffd00e93 li t4,-3
|
||||
48: 00400193 li gp,4
|
||||
4c: 09df1c63 bne t5,t4,e4 <fail>
|
||||
|
||||
00000050 <test_5>:
|
||||
50: fec00093 li ra,-20
|
||||
54: ffa00113 li sp,-6
|
||||
58: 0220cf33 div t5,ra,sp
|
||||
5c: 00300e93 li t4,3
|
||||
60: 00500193 li gp,5
|
||||
64: 09df1063 bne t5,t4,e4 <fail>
|
||||
|
||||
00000068 <test_6>:
|
||||
68: 00000093 li ra,0
|
||||
6c: 00100113 li sp,1
|
||||
70: 0220cf33 div t5,ra,sp
|
||||
74: 00000e93 li t4,0
|
||||
78: 00600193 li gp,6
|
||||
7c: 07df1463 bne t5,t4,e4 <fail>
|
||||
|
||||
00000080 <test_7>:
|
||||
80: 00000093 li ra,0
|
||||
84: fff00113 li sp,-1
|
||||
88: 0220cf33 div t5,ra,sp
|
||||
8c: 00000e93 li t4,0
|
||||
90: 00700193 li gp,7
|
||||
94: 05df1863 bne t5,t4,e4 <fail>
|
||||
|
||||
00000098 <test_8>:
|
||||
98: 00000093 li ra,0
|
||||
9c: 00000113 li sp,0
|
||||
a0: 0220cf33 div t5,ra,sp
|
||||
a4: fff00e93 li t4,-1
|
||||
a8: 00800193 li gp,8
|
||||
ac: 03df1c63 bne t5,t4,e4 <fail>
|
||||
|
||||
000000b0 <test_9>:
|
||||
b0: 00100093 li ra,1
|
||||
b4: 00000113 li sp,0
|
||||
b8: 0220cf33 div t5,ra,sp
|
||||
bc: fff00e93 li t4,-1
|
||||
c0: 00900193 li gp,9
|
||||
c4: 03df1063 bne t5,t4,e4 <fail>
|
||||
|
||||
000000c8 <test_10>:
|
||||
c8: 00000093 li ra,0
|
||||
cc: 00000113 li sp,0
|
||||
d0: 0220cf33 div t5,ra,sp
|
||||
d4: fff00e93 li t4,-1
|
||||
d8: 00a00193 li gp,10
|
||||
dc: 01df1463 bne t5,t4,e4 <fail>
|
||||
e0: 00301863 bne zero,gp,f0 <pass>
|
||||
|
||||
000000e4 <fail>:
|
||||
e4: 00100d13 li s10,1
|
||||
e8: 00000d93 li s11,0
|
||||
|
||||
000000ec <loop_fail>:
|
||||
ec: 0000006f j ec <loop_fail>
|
||||
|
||||
000000f0 <pass>:
|
||||
f0: 00100d13 li s10,1
|
||||
f4: 00100d93 li s11,1
|
||||
|
||||
000000f8 <loop_pass>:
|
||||
f8: 0000006f j f8 <loop_pass>
|
||||
...
|
||||
|
||||
Disassembly of section .tohost:
|
||||
|
||||
00000140 <tohost>:
|
||||
...
|
||||
|
||||
00000180 <fromhost>:
|
||||
...
|
|
@ -0,0 +1,24 @@
|
|||
@00000000
|
||||
13 0D 00 00 93 0D 00 00 93 00 40 01 13 01 60 00
|
||||
33 CF 20 02 93 0E 30 00 93 01 20 00 63 14 DF 0D
|
||||
93 00 C0 FE 13 01 60 00 33 CF 20 02 93 0E D0 FF
|
||||
93 01 30 00 63 18 DF 0B 93 00 40 01 13 01 A0 FF
|
||||
33 CF 20 02 93 0E D0 FF 93 01 40 00 63 1C DF 09
|
||||
93 00 C0 FE 13 01 A0 FF 33 CF 20 02 93 0E 30 00
|
||||
93 01 50 00 63 10 DF 09 93 00 00 00 13 01 10 00
|
||||
33 CF 20 02 93 0E 00 00 93 01 60 00 63 14 DF 07
|
||||
93 00 00 00 13 01 F0 FF 33 CF 20 02 93 0E 00 00
|
||||
93 01 70 00 63 18 DF 05 93 00 00 00 13 01 00 00
|
||||
33 CF 20 02 93 0E F0 FF 93 01 80 00 63 1C DF 03
|
||||
93 00 10 00 13 01 00 00 33 CF 20 02 93 0E F0 FF
|
||||
93 01 90 00 63 10 DF 03 93 00 00 00 13 01 00 00
|
||||
33 CF 20 02 93 0E F0 FF 93 01 A0 00 63 14 DF 01
|
||||
63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00
|
||||
13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00
|
||||
00 00 00 00
|
||||
@00000140
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,107 @@
|
|||
|
||||
generated/rv32um-p-divu: file format elf32-littleriscv
|
||||
|
||||
|
||||
Disassembly of section .text.init:
|
||||
|
||||
00000000 <_start>:
|
||||
0: 00000d13 li s10,0
|
||||
4: 00000d93 li s11,0
|
||||
|
||||
00000008 <test_2>:
|
||||
8: 01400093 li ra,20
|
||||
c: 00600113 li sp,6
|
||||
10: 0220df33 divu t5,ra,sp
|
||||
14: 00300e93 li t4,3
|
||||
18: 00200193 li gp,2
|
||||
1c: 0ddf1663 bne t5,t4,e8 <fail>
|
||||
|
||||
00000020 <test_3>:
|
||||
20: fec00093 li ra,-20
|
||||
24: 00600113 li sp,6
|
||||
28: 0220df33 divu t5,ra,sp
|
||||
2c: 2aaabeb7 lui t4,0x2aaab
|
||||
30: aa7e8e93 addi t4,t4,-1369 # 2aaaaaa7 <begin_signature+0x2aaa9aa7>
|
||||
34: 00300193 li gp,3
|
||||
38: 0bdf1863 bne t5,t4,e8 <fail>
|
||||
|
||||
0000003c <test_4>:
|
||||
3c: 01400093 li ra,20
|
||||
40: ffa00113 li sp,-6
|
||||
44: 0220df33 divu t5,ra,sp
|
||||
48: 00000e93 li t4,0
|
||||
4c: 00400193 li gp,4
|
||||
50: 09df1c63 bne t5,t4,e8 <fail>
|
||||
|
||||
00000054 <test_5>:
|
||||
54: fec00093 li ra,-20
|
||||
58: ffa00113 li sp,-6
|
||||
5c: 0220df33 divu t5,ra,sp
|
||||
60: 00000e93 li t4,0
|
||||
64: 00500193 li gp,5
|
||||
68: 09df1063 bne t5,t4,e8 <fail>
|
||||
|
||||
0000006c <test_6>:
|
||||
6c: 800000b7 lui ra,0x80000
|
||||
70: 00100113 li sp,1
|
||||
74: 0220df33 divu t5,ra,sp
|
||||
78: 80000eb7 lui t4,0x80000
|
||||
7c: 00600193 li gp,6
|
||||
80: 07df1463 bne t5,t4,e8 <fail>
|
||||
|
||||
00000084 <test_7>:
|
||||
84: 800000b7 lui ra,0x80000
|
||||
88: fff00113 li sp,-1
|
||||
8c: 0220df33 divu t5,ra,sp
|
||||
90: 00000e93 li t4,0
|
||||
94: 00700193 li gp,7
|
||||
98: 05df1863 bne t5,t4,e8 <fail>
|
||||
|
||||
0000009c <test_8>:
|
||||
9c: 800000b7 lui ra,0x80000
|
||||
a0: 00000113 li sp,0
|
||||
a4: 0220df33 divu t5,ra,sp
|
||||
a8: fff00e93 li t4,-1
|
||||
ac: 00800193 li gp,8
|
||||
b0: 03df1c63 bne t5,t4,e8 <fail>
|
||||
|
||||
000000b4 <test_9>:
|
||||
b4: 00100093 li ra,1
|
||||
b8: 00000113 li sp,0
|
||||
bc: 0220df33 divu t5,ra,sp
|
||||
c0: fff00e93 li t4,-1
|
||||
c4: 00900193 li gp,9
|
||||
c8: 03df1063 bne t5,t4,e8 <fail>
|
||||
|
||||
000000cc <test_10>:
|
||||
cc: 00000093 li ra,0
|
||||
d0: 00000113 li sp,0
|
||||
d4: 0220df33 divu t5,ra,sp
|
||||
d8: fff00e93 li t4,-1
|
||||
dc: 00a00193 li gp,10
|
||||
e0: 01df1463 bne t5,t4,e8 <fail>
|
||||
e4: 00301863 bne zero,gp,f4 <pass>
|
||||
|
||||
000000e8 <fail>:
|
||||
e8: 00100d13 li s10,1
|
||||
ec: 00000d93 li s11,0
|
||||
|
||||
000000f0 <loop_fail>:
|
||||
f0: 0000006f j f0 <loop_fail>
|
||||
|
||||
000000f4 <pass>:
|
||||
f4: 00100d13 li s10,1
|
||||
f8: 00100d93 li s11,1
|
||||
|
||||
000000fc <loop_pass>:
|
||||
fc: 0000006f j fc <loop_pass>
|
||||
100: 0000 unimp
|
||||
...
|
||||
|
||||
Disassembly of section .tohost:
|
||||
|
||||
00000140 <tohost>:
|
||||
...
|
||||
|
||||
00000180 <fromhost>:
|
||||
...
|
|
@ -0,0 +1,24 @@
|
|||
@00000000
|
||||
13 0D 00 00 93 0D 00 00 93 00 40 01 13 01 60 00
|
||||
33 DF 20 02 93 0E 30 00 93 01 20 00 63 16 DF 0D
|
||||
93 00 C0 FE 13 01 60 00 33 DF 20 02 B7 BE AA 2A
|
||||
93 8E 7E AA 93 01 30 00 63 18 DF 0B 93 00 40 01
|
||||
13 01 A0 FF 33 DF 20 02 93 0E 00 00 93 01 40 00
|
||||
63 1C DF 09 93 00 C0 FE 13 01 A0 FF 33 DF 20 02
|
||||
93 0E 00 00 93 01 50 00 63 10 DF 09 B7 00 00 80
|
||||
13 01 10 00 33 DF 20 02 B7 0E 00 80 93 01 60 00
|
||||
63 14 DF 07 B7 00 00 80 13 01 F0 FF 33 DF 20 02
|
||||
93 0E 00 00 93 01 70 00 63 18 DF 05 B7 00 00 80
|
||||
13 01 00 00 33 DF 20 02 93 0E F0 FF 93 01 80 00
|
||||
63 1C DF 03 93 00 10 00 13 01 00 00 33 DF 20 02
|
||||
93 0E F0 FF 93 01 90 00 63 10 DF 03 93 00 00 00
|
||||
13 01 00 00 33 DF 20 02 93 0E F0 FF 93 01 A0 00
|
||||
63 14 DF 01 63 18 30 00 13 0D 10 00 93 0D 00 00
|
||||
6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00
|
||||
00 00 00 00
|
||||
@00000140
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,105 @@
|
|||
|
||||
generated/rv32um-p-rem: file format elf32-littleriscv
|
||||
|
||||
|
||||
Disassembly of section .text.init:
|
||||
|
||||
00000000 <_start>:
|
||||
0: 00000d13 li s10,0
|
||||
4: 00000d93 li s11,0
|
||||
|
||||
00000008 <test_2>:
|
||||
8: 01400093 li ra,20
|
||||
c: 00600113 li sp,6
|
||||
10: 0220ef33 rem t5,ra,sp
|
||||
14: 00200e93 li t4,2
|
||||
18: 00200193 li gp,2
|
||||
1c: 0ddf1463 bne t5,t4,e4 <fail>
|
||||
|
||||
00000020 <test_3>:
|
||||
20: fec00093 li ra,-20
|
||||
24: 00600113 li sp,6
|
||||
28: 0220ef33 rem t5,ra,sp
|
||||
2c: ffe00e93 li t4,-2
|
||||
30: 00300193 li gp,3
|
||||
34: 0bdf1863 bne t5,t4,e4 <fail>
|
||||
|
||||
00000038 <test_4>:
|
||||
38: 01400093 li ra,20
|
||||
3c: ffa00113 li sp,-6
|
||||
40: 0220ef33 rem t5,ra,sp
|
||||
44: 00200e93 li t4,2
|
||||
48: 00400193 li gp,4
|
||||
4c: 09df1c63 bne t5,t4,e4 <fail>
|
||||
|
||||
00000050 <test_5>:
|
||||
50: fec00093 li ra,-20
|
||||
54: ffa00113 li sp,-6
|
||||
58: 0220ef33 rem t5,ra,sp
|
||||
5c: ffe00e93 li t4,-2
|
||||
60: 00500193 li gp,5
|
||||
64: 09df1063 bne t5,t4,e4 <fail>
|
||||
|
||||
00000068 <test_6>:
|
||||
68: 00000093 li ra,0
|
||||
6c: 00100113 li sp,1
|
||||
70: 0220ef33 rem t5,ra,sp
|
||||
74: 00000e93 li t4,0
|
||||
78: 00600193 li gp,6
|
||||
7c: 07df1463 bne t5,t4,e4 <fail>
|
||||
|
||||
00000080 <test_7>:
|
||||
80: 00000093 li ra,0
|
||||
84: fff00113 li sp,-1
|
||||
88: 0220ef33 rem t5,ra,sp
|
||||
8c: 00000e93 li t4,0
|
||||
90: 00700193 li gp,7
|
||||
94: 05df1863 bne t5,t4,e4 <fail>
|
||||
|
||||
00000098 <test_8>:
|
||||
98: 00000093 li ra,0
|
||||
9c: 00000113 li sp,0
|
||||
a0: 0220ef33 rem t5,ra,sp
|
||||
a4: 00000e93 li t4,0
|
||||
a8: 00800193 li gp,8
|
||||
ac: 03df1c63 bne t5,t4,e4 <fail>
|
||||
|
||||
000000b0 <test_9>:
|
||||
b0: 00100093 li ra,1
|
||||
b4: 00000113 li sp,0
|
||||
b8: 0220ef33 rem t5,ra,sp
|
||||
bc: 00100e93 li t4,1
|
||||
c0: 00900193 li gp,9
|
||||
c4: 03df1063 bne t5,t4,e4 <fail>
|
||||
|
||||
000000c8 <test_10>:
|
||||
c8: 00000093 li ra,0
|
||||
cc: 00000113 li sp,0
|
||||
d0: 0220ef33 rem t5,ra,sp
|
||||
d4: 00000e93 li t4,0
|
||||
d8: 00a00193 li gp,10
|
||||
dc: 01df1463 bne t5,t4,e4 <fail>
|
||||
e0: 00301863 bne zero,gp,f0 <pass>
|
||||
|
||||
000000e4 <fail>:
|
||||
e4: 00100d13 li s10,1
|
||||
e8: 00000d93 li s11,0
|
||||
|
||||
000000ec <loop_fail>:
|
||||
ec: 0000006f j ec <loop_fail>
|
||||
|
||||
000000f0 <pass>:
|
||||
f0: 00100d13 li s10,1
|
||||
f4: 00100d93 li s11,1
|
||||
|
||||
000000f8 <loop_pass>:
|
||||
f8: 0000006f j f8 <loop_pass>
|
||||
...
|
||||
|
||||
Disassembly of section .tohost:
|
||||
|
||||
00000140 <tohost>:
|
||||
...
|
||||
|
||||
00000180 <fromhost>:
|
||||
...
|
|
@ -0,0 +1,24 @@
|
|||
@00000000
|
||||
13 0D 00 00 93 0D 00 00 93 00 40 01 13 01 60 00
|
||||
33 EF 20 02 93 0E 20 00 93 01 20 00 63 14 DF 0D
|
||||
93 00 C0 FE 13 01 60 00 33 EF 20 02 93 0E E0 FF
|
||||
93 01 30 00 63 18 DF 0B 93 00 40 01 13 01 A0 FF
|
||||
33 EF 20 02 93 0E 20 00 93 01 40 00 63 1C DF 09
|
||||
93 00 C0 FE 13 01 A0 FF 33 EF 20 02 93 0E E0 FF
|
||||
93 01 50 00 63 10 DF 09 93 00 00 00 13 01 10 00
|
||||
33 EF 20 02 93 0E 00 00 93 01 60 00 63 14 DF 07
|
||||
93 00 00 00 13 01 F0 FF 33 EF 20 02 93 0E 00 00
|
||||
93 01 70 00 63 18 DF 05 93 00 00 00 13 01 00 00
|
||||
33 EF 20 02 93 0E 00 00 93 01 80 00 63 1C DF 03
|
||||
93 00 10 00 13 01 00 00 33 EF 20 02 93 0E 10 00
|
||||
93 01 90 00 63 10 DF 03 93 00 00 00 13 01 00 00
|
||||
33 EF 20 02 93 0E 00 00 93 01 A0 00 63 14 DF 01
|
||||
63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00
|
||||
13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00
|
||||
00 00 00 00
|
||||
@00000140
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
Binary file not shown.
Binary file not shown.
|
@ -0,0 +1,105 @@
|
|||
|
||||
generated/rv32um-p-remu: file format elf32-littleriscv
|
||||
|
||||
|
||||
Disassembly of section .text.init:
|
||||
|
||||
00000000 <_start>:
|
||||
0: 00000d13 li s10,0
|
||||
4: 00000d93 li s11,0
|
||||
|
||||
00000008 <test_2>:
|
||||
8: 01400093 li ra,20
|
||||
c: 00600113 li sp,6
|
||||
10: 0220ff33 remu t5,ra,sp
|
||||
14: 00200e93 li t4,2
|
||||
18: 00200193 li gp,2
|
||||
1c: 0ddf1463 bne t5,t4,e4 <fail>
|
||||
|
||||
00000020 <test_3>:
|
||||
20: fec00093 li ra,-20
|
||||
24: 00600113 li sp,6
|
||||
28: 0220ff33 remu t5,ra,sp
|
||||
2c: 00200e93 li t4,2
|
||||
30: 00300193 li gp,3
|
||||
34: 0bdf1863 bne t5,t4,e4 <fail>
|
||||
|
||||
00000038 <test_4>:
|
||||
38: 01400093 li ra,20
|
||||
3c: ffa00113 li sp,-6
|
||||
40: 0220ff33 remu t5,ra,sp
|
||||
44: 01400e93 li t4,20
|
||||
48: 00400193 li gp,4
|
||||
4c: 09df1c63 bne t5,t4,e4 <fail>
|
||||
|
||||
00000050 <test_5>:
|
||||
50: fec00093 li ra,-20
|
||||
54: ffa00113 li sp,-6
|
||||
58: 0220ff33 remu t5,ra,sp
|
||||
5c: fec00e93 li t4,-20
|
||||
60: 00500193 li gp,5
|
||||
64: 09df1063 bne t5,t4,e4 <fail>
|
||||
|
||||
00000068 <test_6>:
|
||||
68: 00000093 li ra,0
|
||||
6c: 00100113 li sp,1
|
||||
70: 0220ff33 remu t5,ra,sp
|
||||
74: 00000e93 li t4,0
|
||||
78: 00600193 li gp,6
|
||||
7c: 07df1463 bne t5,t4,e4 <fail>
|
||||
|
||||
00000080 <test_7>:
|
||||
80: 00000093 li ra,0
|
||||
84: fff00113 li sp,-1
|
||||
88: 0220ff33 remu t5,ra,sp
|
||||
8c: 00000e93 li t4,0
|
||||
90: 00700193 li gp,7
|
||||
94: 05df1863 bne t5,t4,e4 <fail>
|
||||
|
||||
00000098 <test_8>:
|
||||
98: 00000093 li ra,0
|
||||
9c: 00000113 li sp,0
|
||||
a0: 0220ff33 remu t5,ra,sp
|
||||
a4: 00000e93 li t4,0
|
||||
a8: 00800193 li gp,8
|
||||
ac: 03df1c63 bne t5,t4,e4 <fail>
|
||||
|
||||
000000b0 <test_9>:
|
||||
b0: 00100093 li ra,1
|
||||
b4: 00000113 li sp,0
|
||||
b8: 0220ff33 remu t5,ra,sp
|
||||
bc: 00100e93 li t4,1
|
||||
c0: 00900193 li gp,9
|
||||
c4: 03df1063 bne t5,t4,e4 <fail>
|
||||
|
||||
000000c8 <test_10>:
|
||||
c8: 00000093 li ra,0
|
||||
cc: 00000113 li sp,0
|
||||
d0: 0220ff33 remu t5,ra,sp
|
||||
d4: 00000e93 li t4,0
|
||||
d8: 00a00193 li gp,10
|
||||
dc: 01df1463 bne t5,t4,e4 <fail>
|
||||
e0: 00301863 bne zero,gp,f0 <pass>
|
||||
|
||||
000000e4 <fail>:
|
||||
e4: 00100d13 li s10,1
|
||||
e8: 00000d93 li s11,0
|
||||
|
||||
000000ec <loop_fail>:
|
||||
ec: 0000006f j ec <loop_fail>
|
||||
|
||||
000000f0 <pass>:
|
||||
f0: 00100d13 li s10,1
|
||||
f4: 00100d93 li s11,1
|
||||
|
||||
000000f8 <loop_pass>:
|
||||
f8: 0000006f j f8 <loop_pass>
|
||||
...
|
||||
|
||||
Disassembly of section .tohost:
|
||||
|
||||
00000140 <tohost>:
|
||||
...
|
||||
|
||||
00000180 <fromhost>:
|
||||
...
|
|
@ -0,0 +1,24 @@
|
|||
@00000000
|
||||
13 0D 00 00 93 0D 00 00 93 00 40 01 13 01 60 00
|
||||
33 FF 20 02 93 0E 20 00 93 01 20 00 63 14 DF 0D
|
||||
93 00 C0 FE 13 01 60 00 33 FF 20 02 93 0E 20 00
|
||||
93 01 30 00 63 18 DF 0B 93 00 40 01 13 01 A0 FF
|
||||
33 FF 20 02 93 0E 40 01 93 01 40 00 63 1C DF 09
|
||||
93 00 C0 FE 13 01 A0 FF 33 FF 20 02 93 0E C0 FE
|
||||
93 01 50 00 63 10 DF 09 93 00 00 00 13 01 10 00
|
||||
33 FF 20 02 93 0E 00 00 93 01 60 00 63 14 DF 07
|
||||
93 00 00 00 13 01 F0 FF 33 FF 20 02 93 0E 00 00
|
||||
93 01 70 00 63 18 DF 05 93 00 00 00 13 01 00 00
|
||||
33 FF 20 02 93 0E 00 00 93 01 80 00 63 1C DF 03
|
||||
93 00 10 00 13 01 00 00 33 FF 20 02 93 0E 10 00
|
||||
93 01 90 00 63 10 DF 03 93 00 00 00 13 01 00 00
|
||||
33 FF 20 02 93 0E 00 00 93 01 A0 00 63 14 DF 01
|
||||
63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00
|
||||
13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00
|
||||
00 00 00 00
|
||||
@00000140
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
00 00 00 00 00 00 00 00
|
|
@ -4,6 +4,7 @@
|
|||
|
||||
rv32um_sc_tests = \
|
||||
mul mulh mulhsu mulhu \
|
||||
div divu rem remu
|
||||
|
||||
|
||||
rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests))
|
||||
|
|
|
@ -0,0 +1,41 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# div.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test div instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, div, 3, 20, 6 );
|
||||
TEST_RR_OP( 3, div, -3, -20, 6 );
|
||||
TEST_RR_OP( 4, div, -3, 20, -6 );
|
||||
TEST_RR_OP( 5, div, 3, -20, -6 );
|
||||
|
||||
TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 );
|
||||
TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 );
|
||||
|
||||
TEST_RR_OP( 8, div, -1, -1<<63, 0 );
|
||||
TEST_RR_OP( 9, div, -1, 1, 0 );
|
||||
TEST_RR_OP(10, div, -1, 0, 0 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
|
@ -0,0 +1,41 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# divu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test divu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, divu, 3, 20, 6 );
|
||||
TEST_RR_OP( 3, divu, 715827879, -20, 6 );
|
||||
TEST_RR_OP( 4, divu, 0, 20, -6 );
|
||||
TEST_RR_OP( 5, divu, 0, -20, -6 );
|
||||
|
||||
TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 );
|
||||
TEST_RR_OP( 7, divu, 0, -1<<31, -1 );
|
||||
|
||||
TEST_RR_OP( 8, divu, -1, -1<<31, 0 );
|
||||
TEST_RR_OP( 9, divu, -1, 1, 0 );
|
||||
TEST_RR_OP(10, divu, -1, 0, 0 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
|
@ -0,0 +1,41 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# rem.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test rem instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, rem, 2, 20, 6 );
|
||||
TEST_RR_OP( 3, rem, -2, -20, 6 );
|
||||
TEST_RR_OP( 4, rem, 2, 20, -6 );
|
||||
TEST_RR_OP( 5, rem, -2, -20, -6 );
|
||||
|
||||
TEST_RR_OP( 6, rem, 0, -1<<63, 1 );
|
||||
TEST_RR_OP( 7, rem, 0, -1<<63, -1 );
|
||||
|
||||
TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 );
|
||||
TEST_RR_OP( 9, rem, 1, 1, 0 );
|
||||
TEST_RR_OP(10, rem, 0, 0, 0 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
|
@ -0,0 +1,41 @@
|
|||
# See LICENSE for license details.
|
||||
|
||||
#*****************************************************************************
|
||||
# remu.S
|
||||
#-----------------------------------------------------------------------------
|
||||
#
|
||||
# Test remu instruction.
|
||||
#
|
||||
|
||||
#include "riscv_test.h"
|
||||
#include "test_macros.h"
|
||||
|
||||
RVTEST_RV32U
|
||||
RVTEST_CODE_BEGIN
|
||||
|
||||
#-------------------------------------------------------------
|
||||
# Arithmetic tests
|
||||
#-------------------------------------------------------------
|
||||
|
||||
TEST_RR_OP( 2, remu, 2, 20, 6 );
|
||||
TEST_RR_OP( 3, remu, 2, -20, 6 );
|
||||
TEST_RR_OP( 4, remu, 20, 20, -6 );
|
||||
TEST_RR_OP( 5, remu, -20, -20, -6 );
|
||||
|
||||
TEST_RR_OP( 6, remu, 0, -1<<63, 1 );
|
||||
TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 );
|
||||
|
||||
TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 );
|
||||
TEST_RR_OP( 9, remu, 1, 1, 0 );
|
||||
TEST_RR_OP(10, remu, 0, 0, 0 );
|
||||
|
||||
TEST_PASSFAIL
|
||||
|
||||
RVTEST_CODE_END
|
||||
|
||||
.data
|
||||
RVTEST_DATA_BEGIN
|
||||
|
||||
TEST_DATA
|
||||
|
||||
RVTEST_DATA_END
|
Loading…
Reference in New Issue