sdk:bsp: add i2c0 slave api
Signed-off-by: liangkangnan <liangkangnan@163.com>pull/4/head
liangkangnan
parent
08492931fc
commit
9905a7c3a2
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@ -1,90 +1,96 @@
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// Generated register defines for i2c
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// Copyright information found in source file:
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// Copyright lowRISC contributors.
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// Licensing information found in source file:
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef _I2C_REG_DEFS_
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#define _I2C_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define I2C_PARAM_REG_WIDTH 32
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#define I2C0_BASE_ADDR (0x60000000)
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#define I2C0_REG(offset) (*((volatile uint32_t *)(I2C0_BASE_ADDR + offset)))
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typedef enum {
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I2C_MODE_MASTER = 0,
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I2C_MODE_SLAVE
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} i2c_mode_e;
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void i2c0_set_clk(uint16_t clk_div);
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void i2c0_set_mode(i2c_mode_e mode);
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void i2c0_master_set_write(uint8_t yes);
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void i2c0_set_interrupt_enable(uint8_t en);
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void i2c0_clear_irq_pending();
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uint8_t i2c0_get_irq_pending();
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void i2c0_master_set_info(uint8_t addr, uint8_t reg, uint8_t data);
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uint8_t i2c0_master_get_data();
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void i2c0_start();
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void i2c0_stop();
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// I2C control register
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#define I2C_CTRL_REG_OFFSET 0x0
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#define I2C_CTRL_REG_RESVAL 0x0
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#define I2C_CTRL_START_BIT 0
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#define I2C_CTRL_INT_EN_BIT 1
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#define I2C_CTRL_INT_PENDING_BIT 2
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#define I2C_CTRL_MODE_BIT 3
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#define I2C_CTRL_WRITE_BIT 4
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#define I2C_CTRL_ERROR_BIT 5
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#define I2C_CTRL_SLAVE_WR_BIT 6
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#define I2C_CTRL_SLAVE_RDY_BIT 7
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#define I2C_CTRL_SLAVE_ADDR_MASK 0xff
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#define I2C_CTRL_SLAVE_ADDR_OFFSET 8
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#define I2C_CTRL_SLAVE_ADDR_FIELD \
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((bitfield_field32_t) { .mask = I2C_CTRL_SLAVE_ADDR_MASK, .index = I2C_CTRL_SLAVE_ADDR_OFFSET })
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#define I2C_CTRL_CLK_DIV_MASK 0xffff
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#define I2C_CTRL_CLK_DIV_OFFSET 16
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#define I2C_CTRL_CLK_DIV_FIELD \
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((bitfield_field32_t) { .mask = I2C_CTRL_CLK_DIV_MASK, .index = I2C_CTRL_CLK_DIV_OFFSET })
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// I2C master transfer data register
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#define I2C_MASTER_DATA_REG_OFFSET 0x4
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#define I2C_MASTER_DATA_REG_RESVAL 0x0
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#define I2C_MASTER_DATA_ADDRESS_MASK 0xff
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#define I2C_MASTER_DATA_ADDRESS_OFFSET 0
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#define I2C_MASTER_DATA_ADDRESS_FIELD \
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((bitfield_field32_t) { .mask = I2C_MASTER_DATA_ADDRESS_MASK, .index = I2C_MASTER_DATA_ADDRESS_OFFSET })
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#define I2C_MASTER_DATA_REGREG_MASK 0xff
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#define I2C_MASTER_DATA_REGREG_OFFSET 8
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#define I2C_MASTER_DATA_REGREG_FIELD \
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((bitfield_field32_t) { .mask = I2C_MASTER_DATA_REGREG_MASK, .index = I2C_MASTER_DATA_REGREG_OFFSET })
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#define I2C_MASTER_DATA_DATA_MASK 0xff
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#define I2C_MASTER_DATA_DATA_OFFSET 16
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#define I2C_MASTER_DATA_DATA_FIELD \
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((bitfield_field32_t) { .mask = I2C_MASTER_DATA_DATA_MASK, .index = I2C_MASTER_DATA_DATA_OFFSET })
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// I2C slave read or write address register
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#define I2C_SLAVE_ADDR_REG_OFFSET 0x8
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#define I2C_SLAVE_ADDR_REG_RESVAL 0x0
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// I2C slave write data register
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#define I2C_SLAVE_WDATA_REG_OFFSET 0xc
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#define I2C_SLAVE_WDATA_REG_RESVAL 0x0
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// I2C slave read data register
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#define I2C_SLAVE_RDATA_REG_OFFSET 0x10
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#define I2C_SLAVE_RDATA_REG_RESVAL 0x0
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _I2C_REG_DEFS_
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// Generated register defines for i2c
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// Copyright information found in source file:
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// Copyright lowRISC contributors.
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// Licensing information found in source file:
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// Licensed under the Apache License, Version 2.0, see LICENSE for details.
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// SPDX-License-Identifier: Apache-2.0
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#ifndef _I2C_REG_DEFS_
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#define _I2C_REG_DEFS_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// Register width
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#define I2C_PARAM_REG_WIDTH 32
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#define I2C0_BASE_ADDR (0x60000000)
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#define I2C0_REG(offset) (*((volatile uint32_t *)(I2C0_BASE_ADDR + offset)))
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typedef enum {
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I2C_MODE_MASTER = 0,
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I2C_MODE_SLAVE
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} i2c_mode_e;
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void i2c0_set_clk(uint16_t clk_div);
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void i2c0_set_mode(i2c_mode_e mode);
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void i2c0_master_set_write(uint8_t yes);
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void i2c0_set_interrupt_enable(uint8_t en);
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void i2c0_clear_irq_pending();
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uint8_t i2c0_get_irq_pending();
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void i2c0_master_set_info(uint8_t addr, uint8_t reg, uint8_t data);
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uint8_t i2c0_master_get_data();
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void i2c0_slave_set_address(uint8_t addr);
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void i2c0_slave_set_ready(uint8_t yes);
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uint8_t i2c0_slave_op_read();
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uint32_t i2c0_slave_get_op_address();
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uint32_t i2c0_slave_get_op_data();
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void i2c0_slave_set_rsp_data(uint32_t data);
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void i2c0_start();
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void i2c0_stop();
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// I2C control register
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#define I2C_CTRL_REG_OFFSET 0x0
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#define I2C_CTRL_REG_RESVAL 0x0
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#define I2C_CTRL_START_BIT 0
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#define I2C_CTRL_INT_EN_BIT 1
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#define I2C_CTRL_INT_PENDING_BIT 2
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#define I2C_CTRL_MODE_BIT 3
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#define I2C_CTRL_WRITE_BIT 4
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#define I2C_CTRL_ERROR_BIT 5
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#define I2C_CTRL_SLAVE_WR_BIT 6
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#define I2C_CTRL_SLAVE_RDY_BIT 7
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#define I2C_CTRL_SLAVE_ADDR_MASK 0xff
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#define I2C_CTRL_SLAVE_ADDR_OFFSET 8
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#define I2C_CTRL_SLAVE_ADDR_FIELD \
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((bitfield_field32_t) { .mask = I2C_CTRL_SLAVE_ADDR_MASK, .index = I2C_CTRL_SLAVE_ADDR_OFFSET })
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#define I2C_CTRL_CLK_DIV_MASK 0xffff
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#define I2C_CTRL_CLK_DIV_OFFSET 16
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#define I2C_CTRL_CLK_DIV_FIELD \
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((bitfield_field32_t) { .mask = I2C_CTRL_CLK_DIV_MASK, .index = I2C_CTRL_CLK_DIV_OFFSET })
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// I2C master transfer data register
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#define I2C_MASTER_DATA_REG_OFFSET 0x4
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#define I2C_MASTER_DATA_REG_RESVAL 0x0
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#define I2C_MASTER_DATA_ADDRESS_MASK 0xff
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#define I2C_MASTER_DATA_ADDRESS_OFFSET 0
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#define I2C_MASTER_DATA_ADDRESS_FIELD \
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((bitfield_field32_t) { .mask = I2C_MASTER_DATA_ADDRESS_MASK, .index = I2C_MASTER_DATA_ADDRESS_OFFSET })
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#define I2C_MASTER_DATA_REGREG_MASK 0xff
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#define I2C_MASTER_DATA_REGREG_OFFSET 8
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#define I2C_MASTER_DATA_REGREG_FIELD \
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((bitfield_field32_t) { .mask = I2C_MASTER_DATA_REGREG_MASK, .index = I2C_MASTER_DATA_REGREG_OFFSET })
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#define I2C_MASTER_DATA_DATA_MASK 0xff
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#define I2C_MASTER_DATA_DATA_OFFSET 16
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#define I2C_MASTER_DATA_DATA_FIELD \
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((bitfield_field32_t) { .mask = I2C_MASTER_DATA_DATA_MASK, .index = I2C_MASTER_DATA_DATA_OFFSET })
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// I2C slave read or write address register
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#define I2C_SLAVE_ADDR_REG_OFFSET 0x8
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#define I2C_SLAVE_ADDR_REG_RESVAL 0x0
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// I2C slave write data register
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#define I2C_SLAVE_WDATA_REG_OFFSET 0xc
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#define I2C_SLAVE_WDATA_REG_RESVAL 0x0
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// I2C slave read data register
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#define I2C_SLAVE_RDATA_REG_OFFSET 0x10
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#define I2C_SLAVE_RDATA_REG_RESVAL 0x0
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#ifdef __cplusplus
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} // extern "C"
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#endif
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#endif // _I2C_REG_DEFS_
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// End generated register defines for i2c
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@ -62,6 +62,43 @@ uint8_t i2c0_master_get_data()
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return data;
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}
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void i2c0_slave_set_address(uint8_t addr)
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{
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I2C0_REG(I2C_CTRL_REG_OFFSET) &= ~(I2C_CTRL_SLAVE_ADDR_MASK << I2C_CTRL_SLAVE_ADDR_OFFSET);
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I2C0_REG(I2C_CTRL_REG_OFFSET) |= addr << I2C_CTRL_SLAVE_ADDR_OFFSET;
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}
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void i2c0_slave_set_ready(uint8_t yes)
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{
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if (yes)
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I2C0_REG(I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_SLAVE_RDY_BIT;
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else
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I2C0_REG(I2C_CTRL_REG_OFFSET) &= ~(1 << I2C_CTRL_SLAVE_RDY_BIT);
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}
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uint8_t i2c0_slave_op_read()
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{
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if (I2C0_REG(I2C_CTRL_REG_OFFSET) & (1 << I2C_CTRL_SLAVE_WR_BIT))
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return 1;
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else
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return 0;
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}
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uint32_t i2c0_slave_get_op_address()
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{
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return (I2C0_REG(I2C_SLAVE_ADDR_REG_OFFSET));
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}
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uint32_t i2c0_slave_get_op_data()
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{
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return (I2C0_REG(I2C_SLAVE_WDATA_REG_OFFSET));
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}
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void i2c0_slave_set_rsp_data(uint32_t data)
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{
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I2C0_REG(I2C_SLAVE_RDATA_REG_OFFSET) = data;
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}
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void i2c0_start()
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{
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I2C0_REG(I2C_CTRL_REG_OFFSET) |= 1 << I2C_CTRL_START_BIT;
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