first release

Signed-off-by: Blue Liang <liangkangnan@163.com>

.gitignore

@@ -1,52 +1,7 @@
-# Prerequisites
-*.d
-
 # Object files
 *.o
 *.ko
 *.obj
 *.elf
 
-# Linker output
-*.ilk
-*.map
-*.exp
-
-# Precompiled Headers
-*.gch
-*.pch
-
-# Libraries
-*.lib
-*.a
-*.la
-*.lo
-
-# Shared objects (inc. Windows DLLs)
-*.dll
-*.so
-*.so.*
-*.dylib
-
-# Executables
-*.exe
-*.out
-*.app
-*.i*86
-*.x86_64
-*.hex
-
-# Debug files
-*.dSYM/
-*.su
-*.idb
-*.pdb
-
-# Kernel Module Compile Results
-*.mod*
-*.cmd
-.tmp_versions/
-modules.order
-Module.symvers
-Mkfile.old
-dkms.conf
+tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64

LICENSE

@@ -1,3 +1,4 @@
+
                                  Apache License
                            Version 2.0, January 2004
                         http://www.apache.org/licenses/
@@ -186,7 +187,7 @@
       same "printed page" as the copyright notice for easier
       identification within third-party archives.
 
-   Copyright [yyyy] [name of copyright owner]
+   Copyright Blue Liang, liangkangnan@163.com
 
    Licensed under the Apache License, Version 2.0 (the "License");
    you may not use this file except in compliance with the License.

README.en.md

@@ -1,36 +1,4 @@
-# tinyriscv
+# tinyriscv
 
 #### Description
-从零开始写的极简、非常易懂的RISC-V处理器核。
-
-#### Software Architecture
-Software architecture description
-
-#### Installation
-
-1.  xxxx
-2.  xxxx
-3.  xxxx
-
-#### Instructions
-
-1.  xxxx
-2.  xxxx
-3.  xxxx
-
-#### Contribution
-
-1.  Fork the repository
-2.  Create Feat_xxx branch
-3.  Commit your code
-4.  Create Pull Request
-
-
-#### Gitee Feature
-
-1.  You can use Readme\_XXX.md to support different languages, such as Readme\_en.md, Readme\_zh.md
-2.  Gitee blog [blog.gitee.com](https://blog.gitee.com)
-3.  Explore open source project [https://gitee.com/explore](https://gitee.com/explore)
-4.  The most valuable open source project [GVP](https://gitee.com/gvp)
-5.  The manual of Gitee [https://gitee.com/help](https://gitee.com/help)
-6.  The most popular members  [https://gitee.com/gitee-stars/](https://gitee.com/gitee-stars/)
+opensource RISC-V core

rtl/defines.v

@@ -0,0 +1,98 @@
+ /*                                                                      
+ Copyright 2019 Blue Liang, liangkangnan@163.com
+                                                                         
+ Licensed under the Apache License, Version 2.0 (the "License");         
+ you may not use this file except in compliance with the License.        
+ You may obtain a copy of the License at                                 
+                                                                         
+     http://www.apache.org/licenses/LICENSE-2.0                          
+                                                                         
+ Unless required by applicable law or agreed to in writing, software    
+ distributed under the License is distributed on an "AS IS" BASIS,       
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and     
+ limitations under the License.                                          
+ */
+
+`define RstEnable 1'b0
+`define RstDisable 1'b1
+`define ZeroWord 32'h00000000
+`define WriteEnable 1'b1
+`define WriteDisable 1'b0
+`define ReadEnable 1'b1
+`define ReadDisable 1'b0
+`define InstValid 1'b1
+`define InstInvalid 1'b0
+`define True 1'b1
+`define False 1'b0
+`define ChipEnable 1'b1
+`define ChipDisable 1'b0
+`define JumpEnable 1'b1
+`define JumpDisable 1'b0
+
+// I type inst
+`define INST_TYPE_I 7'b0010011
+`define INST_ADDI   3'b000
+`define INST_SLTI   3'b010
+`define INST_SLTIU  3'b011
+`define INST_XORI   3'b100
+`define INST_ORI    3'b110
+`define INST_ANDI   3'b111
+`define INST_SLLI   3'b001
+`define INST_SRI    3'b101
+
+// L type inst
+`define INST_TYPE_L 7'b0000011
+`define INST_LB     3'b000
+`define INST_LH     3'b001
+`define INST_LW     3'b010
+`define INST_LBU    3'b100
+`define INST_LHU    3'b101
+
+// S type inst
+`define INST_TYPE_S 7'b0100011
+`define INST_SB     3'b000
+`define INST_SH     3'b001
+`define INST_SW     3'b010
+
+// R type inst
+`define INST_TYPE_R 7'b0110011
+`define INST_ADD_SUB 3'b000
+`define INST_SLL    3'b001
+`define INST_SLT    3'b010
+`define INST_SLTU   3'b011
+`define INST_XOR    3'b100
+`define INST_SR     3'b101
+`define INST_OR     3'b110
+`define INST_AND    3'b111
+
+// J type inst
+`define INST_JAL    7'b1101111
+`define INST_JALR   7'b1100111
+
+`define INST_LUI    7'b0110111
+`define INST_AUIPC  7'b0010111
+`define INST_NOP    32'h00000001
+
+`define INST_FENCE  7'b0001111
+
+// J type inst
+`define INST_TYPE_B 7'b1100011
+`define INST_BEQ    3'b000
+`define INST_BNE    3'b001
+`define INST_BLT    3'b100
+`define INST_BGE    3'b101
+`define INST_BLTU   3'b110
+`define INST_BGEU   3'b111
+
+// SIM RAM
+`define SramMemNum 2048   // memory depth(how many words)
+`define SramBus 31:0
+`define SramAddrBus 31:0
+
+// common regs
+`define RegAddrBus 4:0
+`define RegBus 31:0
+`define RegWidth 32
+`define RegNum 32        // reg count
+`define RegNumLog2 5

rtl/ex.v

@@ -0,0 +1,478 @@
+ /*                                                                      
+ Copyright 2019 Blue Liang, liangkangnan@163.com
+                                                                         
+ Licensed under the Apache License, Version 2.0 (the "License");         
+ you may not use this file except in compliance with the License.        
+ You may obtain a copy of the License at                                 
+                                                                         
+     http://www.apache.org/licenses/LICENSE-2.0                          
+                                                                         
+ Unless required by applicable law or agreed to in writing, software    
+ distributed under the License is distributed on an "AS IS" BASIS,       
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and     
+ limitations under the License.                                          
+ */
+
+`include "defines.v"
+
+// excute and writeback module
+module ex (
+
+    input wire clk,
+    input wire rst,
+
+    // from id
+    input wire[`SramBus] inst_i,            // inst content
+    input wire inst_valid_i,
+    input wire[`SramAddrBus] inst_addr_i,   // inst addr
+
+    // from regs
+    input wire[`RegBus] reg1_rdata_i,       // reg1 read data
+    input wire[`RegBus] reg2_rdata_i,       // reg2 read data
+
+    // from sram
+    input wire[`SramBus] sram_rdata_i,      // ram read data
+
+    // to sram
+    output reg[`SramBus] sram_wdata_o,      // ram write data
+    output reg[`SramAddrBus] sram_raddr_o,  // ram read addr
+    output reg[`SramAddrBus] sram_waddr_o,  // ram write addr
+
+    // to regs
+    output reg[`RegBus] reg_wdata_o,        // reg write data
+
+    // to pc_reg
+    output reg jump_flag_o,                // if jump or not flag
+    output reg[`RegBus] jump_addr_o        // jump dest addr
+
+);
+
+    wire[31:0] sign_extend_tmp;
+    wire[4:0] shift_bits;
+    reg[1:0] sram_raddr_index;
+    reg[1:0] sram_waddr_index;
+
+    wire[6:0] opcode = inst_i[6:0];
+    wire[2:0] funct3 = inst_i[14:12];
+
+    assign sign_extend_tmp = {{20{inst_i[31]}}, inst_i[31:20]};
+    assign shift_bits = inst_i[24:20];
+
+    always @ (posedge clk) begin
+        if (rst == `RstEnable) begin
+            sram_raddr_o <= `ZeroWord;
+            jump_flag_o <= `JumpDisable;
+            sram_raddr_index <= 2'b0;
+            sram_waddr_index <= 2'b0;
+        end
+    end
+
+    always @ (*) begin
+        if (inst_valid_i == `InstValid) begin
+            case (opcode)
+                `INST_TYPE_I: begin
+                    case (funct3)
+                        `INST_ADDI: begin
+                            jump_flag_o <= `JumpDisable;
+                            reg_wdata_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
+                        end
+                        `INST_SLTI: begin
+                            jump_flag_o <= `JumpDisable;
+                            if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin
+                                if (reg1_rdata_i < sign_extend_tmp) begin
+                                    reg_wdata_o <= 32'h00000001;
+                                end else begin
+                                    reg_wdata_o <= 32'h00000000;
+                                end
+                            end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin
+                                reg_wdata_o <= 32'h00000001;
+                            end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin
+                                reg_wdata_o <= 32'h00000000;
+                            end else begin
+                                if (reg1_rdata_i < sign_extend_tmp) begin
+                                    reg_wdata_o <= 32'h00000001;
+                                end else begin
+                                    reg_wdata_o <= 32'h00000000;
+                                end
+                            end
+                        end
+                        `INST_SLTIU: begin
+                            jump_flag_o <= `JumpDisable;
+                            if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin
+                                if (reg1_rdata_i < sign_extend_tmp) begin
+                                    reg_wdata_o <= 32'h00000001;
+                                end else begin
+                                    reg_wdata_o <= 32'h00000000;
+                                end
+                            end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin
+                                reg_wdata_o <= 32'h00000000;
+                            end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin
+                                reg_wdata_o <= 32'h00000001;
+                            end else begin
+                                if (reg1_rdata_i < sign_extend_tmp) begin
+                                    reg_wdata_o <= 32'h00000001;
+                                end else begin
+                                    reg_wdata_o <= 32'h00000000;
+                                end
+                            end
+                        end
+                        `INST_XORI: begin
+                            jump_flag_o <= `JumpDisable;
+                            reg_wdata_o <= reg1_rdata_i ^ {{20{inst_i[31]}}, inst_i[31:20]};
+                        end
+                        `INST_ORI: begin
+                            jump_flag_o <= `JumpDisable;
+                            reg_wdata_o <= reg1_rdata_i | {{20{inst_i[31]}}, inst_i[31:20]};
+                        end
+                        `INST_ANDI: begin
+                            jump_flag_o <= `JumpDisable;
+                            reg_wdata_o <= reg1_rdata_i & {{20{inst_i[31]}}, inst_i[31:20]};
+                        end
+                        `INST_SLLI: begin
+                            jump_flag_o <= `JumpDisable;
+                            reg_wdata_o <= reg1_rdata_i << shift_bits;
+                        end
+                        `INST_SRI: begin
+                            jump_flag_o <= `JumpDisable;
+                            if (inst_i[30] == 1'b1) begin
+                                reg_wdata_o <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, shift_bits})) | (reg1_rdata_i >> shift_bits);
+                            end else begin
+                                reg_wdata_o <= reg1_rdata_i >> shift_bits;
+                            end
+                        end
+                    endcase
+                end
+                `INST_TYPE_R: begin
+                    case (funct3)
+                        `INST_ADD_SUB: begin
+                            jump_flag_o <= `JumpDisable;
+                            if (inst_i[30] == 1'b0) begin
+                                reg_wdata_o <= reg1_rdata_i + reg2_rdata_i;
+                            end else begin
+                                reg_wdata_o <= reg1_rdata_i - reg2_rdata_i;
+                            end
+                        end
+                        `INST_SLL: begin
+                            jump_flag_o <= `JumpDisable;
+                            reg_wdata_o <= reg1_rdata_i << reg2_rdata_i[4:0];
+                        end
+                        `INST_SLT: begin
+                            jump_flag_o <= `JumpDisable;
+                            if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
+                                if (reg1_rdata_i < reg2_rdata_i) begin
+                                    reg_wdata_o <= 32'h00000001;
+                                end else begin
+                                    reg_wdata_o <= 32'h00000000;
+                                end
+                            end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
+                                reg_wdata_o <= 32'h00000001;
+                            end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
+                                reg_wdata_o <= 32'h00000000;
+                            end else begin
+                                if (reg1_rdata_i < reg2_rdata_i) begin
+                                    reg_wdata_o <= 32'h00000001;
+                                end else begin
+                                    reg_wdata_o <= 32'h00000000;
+                                end
+                            end
+                        end
+                        `INST_SLTU: begin
+                            jump_flag_o <= `JumpDisable;
+                            if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
+                                if (reg1_rdata_i < reg2_rdata_i) begin
+                                    reg_wdata_o <= 32'h00000001;
+                                end else begin
+                                    reg_wdata_o <= 32'h00000000;
+                                end
+                            end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
+                                reg_wdata_o <= 32'h00000000;
+                            end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
+                                reg_wdata_o <= 32'h00000001;
+                            end else begin
+                                if (reg1_rdata_i < reg2_rdata_i) begin
+                                    reg_wdata_o <= 32'h00000001;
+                                end else begin
+                                    reg_wdata_o <= 32'h00000000;
+                                end
+                            end
+                        end
+                        `INST_XOR: begin
+                            jump_flag_o <= `JumpDisable;
+                            reg_wdata_o <= reg1_rdata_i ^ reg2_rdata_i;
+                        end
+                        `INST_SR: begin
+                            jump_flag_o <= `JumpDisable;
+                            if (inst_i[30] == 1'b1) begin
+                                reg_wdata_o <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]);
+                            end else begin
+                                reg_wdata_o <= reg1_rdata_i >> reg2_rdata_i[4:0];
+                            end
+                        end
+                        `INST_OR: begin
+                            jump_flag_o <= `JumpDisable;
+                            reg_wdata_o <= reg1_rdata_i | reg2_rdata_i;
+                        end
+                        `INST_AND: begin
+                            jump_flag_o <= `JumpDisable;
+                            reg_wdata_o <= reg1_rdata_i & reg2_rdata_i;
+                        end
+                    endcase
+                end
+                `INST_TYPE_L: begin
+                    case (funct3)
+                        `INST_LB: begin
+                            jump_flag_o <= `JumpDisable;
+                            sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
+                            sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11;
+                        end
+                        `INST_LH: begin
+                            jump_flag_o <= `JumpDisable;
+                            sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
+                            sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11;
+                        end
+                        `INST_LW: begin
+                            jump_flag_o <= `JumpDisable;
+                            sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
+                            sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11;
+                        end
+                        `INST_LBU: begin
+                            jump_flag_o <= `JumpDisable;
+                            sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
+                            sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11;
+                        end
+                        `INST_LHU: begin
+                            jump_flag_o <= `JumpDisable;
+                            sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]};
+                            sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11;
+                        end
+                    endcase
+                end
+                `INST_TYPE_S: begin
+                    case (funct3)
+                        `INST_SB: begin
+                            jump_flag_o <= `JumpDisable;
+                            sram_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
+                            sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
+                            sram_waddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11;
+                        end
+                        `INST_SH: begin
+                            jump_flag_o <= `JumpDisable;
+                            sram_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
+                            sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
+                            sram_waddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11;
+                        end
+                        `INST_SW: begin
+                            jump_flag_o <= `JumpDisable;
+                            sram_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]};
+                            sram_wdata_o <= reg2_rdata_i;
+                        end
+                    endcase
+                end
+                `INST_TYPE_B: begin
+                    case (funct3)
+                        `INST_BEQ: begin
+                            if (reg1_rdata_i == reg2_rdata_i) begin
+                                jump_flag_o <= `JumpEnable;
+                                jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                            end else begin
+                                jump_flag_o <= `JumpDisable;
+                            end
+                        end
+                        `INST_BNE: begin
+                            if (reg1_rdata_i != reg2_rdata_i) begin
+                                jump_flag_o <= `JumpEnable;
+                                jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                            end else begin
+                                jump_flag_o <= `JumpDisable;
+                            end
+                        end
+                        `INST_BLT: begin
+                            if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
+                                jump_flag_o <= `JumpEnable;
+                                jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                            end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
+                                if (reg1_rdata_i >= reg2_rdata_i) begin
+                                    jump_flag_o <= `JumpDisable;
+                                end else begin
+                                    jump_flag_o <= `JumpEnable;
+                                    jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                                end
+                            end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
+                                if (reg1_rdata_i >= reg2_rdata_i) begin
+                                    jump_flag_o <= `JumpDisable;
+                                end else begin
+                                    jump_flag_o <= `JumpEnable;
+                                    jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                                end
+                            end else begin
+                                jump_flag_o <= `JumpDisable;
+                            end
+                        end
+                        `INST_BGE: begin
+                            if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
+                                jump_flag_o <= `JumpEnable;
+                                jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                            end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
+                                if (reg1_rdata_i < reg2_rdata_i) begin
+                                    jump_flag_o <= `JumpDisable;
+                                end else begin
+                                    jump_flag_o <= `JumpEnable;
+                                    jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                                end
+                            end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
+                                if (reg1_rdata_i < reg2_rdata_i) begin
+                                    jump_flag_o <= `JumpDisable;
+                                end else begin
+                                    jump_flag_o <= `JumpEnable;
+                                    jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                                end
+                            end else begin
+                                jump_flag_o <= `JumpDisable;
+                            end
+                        end
+                        `INST_BLTU: begin
+                            if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin
+                                jump_flag_o <= `JumpDisable;
+                            end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
+                                if (reg1_rdata_i >= reg2_rdata_i) begin
+                                    jump_flag_o <= `JumpDisable;
+                                end else begin
+                                    jump_flag_o <= `JumpEnable;
+                                    jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                                end
+                            end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
+                                if (reg1_rdata_i >= reg2_rdata_i) begin
+                                    jump_flag_o <= `JumpDisable;
+                                end else begin
+                                    jump_flag_o <= `JumpEnable;
+                                    jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                                end
+                            end else begin
+                                jump_flag_o <= `JumpEnable;
+                                jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                            end
+                        end
+                        `INST_BGEU: begin
+                            if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin
+                                jump_flag_o <= `JumpDisable;
+                            end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin
+                                if (reg1_rdata_i < reg2_rdata_i) begin
+                                    jump_flag_o <= `JumpDisable;
+                                end else begin
+                                    jump_flag_o <= `JumpEnable;
+                                    jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                                end
+                            end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin
+                                if (reg1_rdata_i < reg2_rdata_i) begin
+                                    jump_flag_o <= `JumpDisable;
+                                end else begin
+                                    jump_flag_o <= `JumpEnable;
+                                    jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                                end
+                            end else begin
+                                jump_flag_o <= `JumpEnable;
+                                jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0};
+                            end
+                        end
+                    endcase
+                end
+                `INST_JAL: begin
+					jump_flag_o <= `JumpEnable;
+                    jump_addr_o <= inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0};
+                    reg_wdata_o <= inst_addr_i + 4'h4;
+                end
+                `INST_JALR: begin
+					jump_flag_o <= `JumpEnable;
+                    jump_addr_o <= (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe);
+					reg_wdata_o <= inst_addr_i + 4'h4;
+				end
+                `INST_LUI: begin
+                    jump_flag_o <= `JumpDisable;
+                    reg_wdata_o <= {inst_i[31:12], 12'b0};
+                end
+                `INST_AUIPC: begin
+                    jump_flag_o <= `JumpDisable;
+                    reg_wdata_o <= {inst_i[31:12], 12'b0} + inst_addr_i;
+                end
+                `INST_NOP: begin
+                    jump_flag_o <= `JumpDisable;
+                end
+                `INST_FENCE: begin
+                    jump_flag_o <= `JumpEnable;
+                    jump_addr_o <= inst_addr_i + 4'h4;
+                end
+                default: begin
+
+                end
+            endcase
+        end
+    end
+
+    always @ (*) begin
+        if (inst_valid_i == `InstValid) begin
+            case (opcode)
+                `INST_TYPE_L: begin
+                    case (funct3)
+                        `INST_LB: begin
+                            if (sram_raddr_index == 2'b0)
+                                reg_wdata_o <= {{24{sram_rdata_i[7]}}, sram_rdata_i[7:0]};
+                            else if (sram_raddr_index == 2'b01)
+                                reg_wdata_o <= {{24{sram_rdata_i[15]}}, sram_rdata_i[15:8]};
+                            else if (sram_raddr_index == 2'b10)
+                                reg_wdata_o <= {{24{sram_rdata_i[23]}}, sram_rdata_i[23:16]};
+                            else
+                                reg_wdata_o <= {{24{sram_rdata_i[31]}}, sram_rdata_i[31:24]};
+                        end
+                        `INST_LH: begin
+                            if (sram_raddr_index == 2'b0)
+                                reg_wdata_o <= {{16{sram_rdata_i[15]}}, sram_rdata_i[15:0]};
+                            else
+                                reg_wdata_o <= {{16{sram_rdata_i[31]}}, sram_rdata_i[31:16]};
+                        end
+                        `INST_LW: begin
+                            reg_wdata_o <= sram_rdata_i;
+                        end
+                        `INST_LBU: begin
+                            if (sram_raddr_index == 2'b0)
+                                reg_wdata_o <= {24'h0, sram_rdata_i[7:0]};
+                            else if (sram_raddr_index == 2'b01)
+                                reg_wdata_o <= {24'h0, sram_rdata_i[15:8]};
+                            else if (sram_raddr_index == 2'b10)
+                                reg_wdata_o <= {24'h0, sram_rdata_i[23:16]};
+                            else
+                                reg_wdata_o <= {24'h0, sram_rdata_i[31:24]};
+                        end
+                        `INST_LHU: begin
+                            if (sram_raddr_index == 2'b0)
+                                reg_wdata_o <= {16'h0, sram_rdata_i[15:0]};
+                            else
+                                reg_wdata_o <= {16'h0, sram_rdata_i[31:16]};
+                        end
+                    endcase
+                end
+                `INST_TYPE_S: begin
+                    case (funct3)
+                        `INST_SB: begin
+                            if (sram_waddr_index == 2'b00)
+                                sram_wdata_o <= {sram_rdata_i[31:8], reg2_rdata_i[7:0]};
+                            else if (sram_waddr_index == 2'b01)
+                                sram_wdata_o <= {sram_rdata_i[31:16], reg2_rdata_i[7:0], sram_rdata_i[7:0]};
+                            else if (sram_waddr_index == 2'b10)
+                                sram_wdata_o <= {sram_rdata_i[31:24], reg2_rdata_i[7:0], sram_rdata_i[15:0]};
+                            else
+                                sram_wdata_o <= {reg2_rdata_i[7:0], sram_rdata_i[23:0]};
+                        end
+                        `INST_SH: begin
+                            if (sram_waddr_index == 2'b00)
+                                sram_wdata_o <= {sram_rdata_i[31:16], reg2_rdata_i[15:0]};
+                            else
+                                sram_wdata_o <= {reg2_rdata_i[15:0], sram_rdata_i[15:0]};
+                        end
+                    endcase
+                end
+            endcase
+        end
+    end
+
+endmodule

rtl/id.v

@@ -0,0 +1,425 @@
+ /*                                                                      
+ Copyright 2019 Blue Liang, liangkangnan@163.com
+                                                                         
+ Licensed under the Apache License, Version 2.0 (the "License");         
+ you may not use this file except in compliance with the License.        
+ You may obtain a copy of the License at                                 
+                                                                         
+     http://www.apache.org/licenses/LICENSE-2.0                          
+                                                                         
+ Unless required by applicable law or agreed to in writing, software    
+ distributed under the License is distributed on an "AS IS" BASIS,       
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and     
+ limitations under the License.                                          
+ */
+
+`include "defines.v"
+
+// identify module
+module id (
+
+	input wire clk,
+	input wire rst,
+	input wire[`SramBus] inst_i,             // inst content
+    input wire[`SramAddrBus] inst_addr_i,    // inst addr
+    input wire jump_flag_ex_i,
+
+    // to regs
+    output reg reg1_re_o,                    // reg1 read enable
+    output reg[`RegAddrBus] reg1_raddr_o,    // reg1 read addr
+    output reg reg2_re_o,                    // reg2 read enable
+    output reg[`RegAddrBus] reg2_raddr_o,    // reg2 read addr
+    output reg reg_we_o,                     // reg write enable
+    output reg[`RegAddrBus] reg_waddr_o,     // reg write addr
+
+    // to ex
+    output reg[`SramBus] inst_o,
+    output reg inst_valid_o,                 // inst is valid flag
+    output reg[`SramAddrBus] inst_addr_o,
+
+    // to sram
+    output reg sram_re_o,                    // ram read enable
+    output reg sram_we_o                     // ram write enable
+
+);
+
+    wire[6:0] opcode = inst_i[6:0];
+    wire[2:0] funct3 = inst_i[14:12];
+    wire[4:0] rd = inst_i[11:7];
+    wire[4:0] rs1 = inst_i[19:15];
+    wire[4:0] rs2 = inst_i[24:20];
+
+
+    always @ (posedge clk) begin
+        if (rst == `RstEnable) begin
+            inst_o <= `ZeroWord;
+            reg_we_o <= `WriteDisable;
+            sram_we_o <= `WriteDisable;
+            reg1_re_o <= `ReadDisable;
+            reg2_re_o <= `ReadDisable;
+            sram_re_o <= `ReadDisable;
+            inst_valid_o <= `InstInvalid;
+        end else if (jump_flag_ex_i == `JumpEnable && inst_i != `INST_NOP) begin
+            inst_valid_o <= `InstValid;
+            sram_we_o <= `WriteDisable;
+            reg_we_o <= `WriteDisable;
+            inst_o <= `INST_NOP;
+        end else begin
+            inst_o <= inst_i;
+            inst_addr_o <= inst_addr_i;
+
+            case (opcode)
+                `INST_TYPE_I: begin
+                    case (funct3)
+                        `INST_ADDI: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_SLTI: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_SLTIU: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_XORI: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_ORI: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_ANDI: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_SLLI: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_SRI: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        default: begin
+                            inst_valid_o <= `InstInvalid;
+                        end
+                    endcase
+                end
+                `INST_TYPE_R: begin
+                    case (funct3)
+                        `INST_ADD_SUB: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_SLL: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_SLT: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_SLTU: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_XOR: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_SR: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_OR: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_AND: begin
+                            inst_valid_o <= `InstValid;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        default: begin
+                            inst_valid_o <= `InstInvalid;
+                        end
+                    endcase
+                end
+                `INST_TYPE_L: begin
+                    case (funct3)
+                        `INST_LB: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            sram_re_o <= `ReadEnable;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_LH: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            sram_re_o <= `ReadEnable;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_LW: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            sram_re_o <= `ReadEnable;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_LBU: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            sram_re_o <= `ReadEnable;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        `INST_LHU: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg_we_o <= `WriteEnable;
+                            reg_waddr_o <= rd;
+                            sram_re_o <= `ReadEnable;
+                            sram_we_o <= `WriteDisable;
+                        end
+                        default: begin
+                            inst_valid_o <= `InstInvalid;
+                        end
+                    endcase
+                end
+                `INST_TYPE_S: begin
+                    case (funct3)
+                        `INST_SB: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteEnable;
+                            sram_re_o <= `ReadEnable;
+                            reg_we_o <= `WriteDisable;
+                        end
+                        `INST_SH: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteEnable;
+                            sram_re_o <= `ReadEnable;
+                            reg_we_o <= `WriteDisable;
+                        end
+                        `INST_SW: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_re_o <= `ReadEnable;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteEnable;
+                            reg_we_o <= `WriteDisable;
+                        end
+                        default: begin
+                            inst_valid_o <= `InstInvalid;
+                        end
+                    endcase
+                end
+                `INST_TYPE_B: begin
+                    case (funct3)
+                        `INST_BEQ: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg2_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                            reg_we_o <= `WriteDisable;
+                        end
+                        `INST_BNE: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg2_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                            reg_we_o <= `WriteDisable;
+                        end
+                        `INST_BLT: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg2_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                            reg_we_o <= `WriteDisable;
+                        end
+                        `INST_BGE: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg2_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                            reg_we_o <= `WriteDisable;
+                        end
+                        `INST_BLTU: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg2_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                            reg_we_o <= `WriteDisable;
+                        end
+                        `INST_BGEU: begin
+                            inst_valid_o <= `InstValid;
+                            reg1_re_o <= `ReadEnable;
+                            reg2_re_o <= `ReadEnable;
+                            reg1_raddr_o <= rs1;
+                            reg2_raddr_o <= rs2;
+                            sram_we_o <= `WriteDisable;
+                            reg_we_o <= `WriteDisable;
+                        end
+                        default: begin
+                            inst_valid_o <= `InstInvalid;
+                        end
+                    endcase
+                end
+                `INST_JAL: begin
+                    inst_valid_o <= `InstValid;
+                    sram_we_o <= `WriteDisable;
+                    reg_we_o <= `WriteEnable;
+                    reg_waddr_o <= rd;
+                end
+                `INST_JALR: begin
+                    inst_valid_o <= `InstValid;
+                    sram_we_o <= `WriteDisable;
+                    reg_we_o <= `WriteEnable;
+					reg1_re_o <= `ReadEnable;
+					reg1_raddr_o <= rs1;
+                    reg_waddr_o <= rd;
+                end
+                `INST_LUI: begin
+                    inst_valid_o <= `InstValid;
+                    sram_we_o <= `WriteDisable;
+                    reg_we_o <= `WriteEnable;
+                    reg_waddr_o <= rd;
+                end
+                `INST_AUIPC: begin
+                    inst_valid_o <= `InstValid;
+                    sram_we_o <= `WriteDisable;
+                    reg_we_o <= `WriteEnable;
+                    reg_waddr_o <= rd;
+                end
+                `INST_NOP: begin
+                    inst_valid_o <= `InstValid;
+                    sram_we_o <= `WriteDisable;
+                    reg_we_o <= `WriteDisable;
+                end
+                `INST_FENCE: begin
+                    inst_valid_o <= `InstValid;
+                    sram_we_o <= `WriteDisable;
+                    reg_we_o <= `WriteDisable;
+                end
+                default: begin
+                    inst_valid_o <= `InstInvalid;
+                    sram_we_o <= `WriteDisable;
+                    reg_we_o <= `WriteDisable;
+                end
+            endcase
+        end
+    end
+
+endmodule

rtl/if_id.v

@@ -0,0 +1,48 @@
+ /*                                                                      
+ Copyright 2019 Blue Liang, liangkangnan@163.com
+                                                                         
+ Licensed under the Apache License, Version 2.0 (the "License");         
+ you may not use this file except in compliance with the License.        
+ You may obtain a copy of the License at                                 
+                                                                         
+     http://www.apache.org/licenses/LICENSE-2.0                          
+                                                                         
+ Unless required by applicable law or agreed to in writing, software    
+ distributed under the License is distributed on an "AS IS" BASIS,       
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and     
+ limitations under the License.                                          
+ */
+
+`include "defines.v"
+
+// inst fetch module
+module if_id (
+
+    input wire clk,
+    input wire rst,
+
+    input wire[`SramBus] inst_i,            // inst content
+    input wire[`SramAddrBus] inst_addr_i,   // inst addr
+
+    input wire jump_flag_ex_i,
+
+    output reg[`SramBus] inst_o,
+    output reg[`SramAddrBus] inst_addr_o
+
+);
+
+    always @ (posedge clk) begin
+        if (rst == `RstEnable) begin
+            inst_o <= `ZeroWord;
+            inst_addr_o <= `ZeroWord;
+        end else if (jump_flag_ex_i == `JumpEnable) begin
+            inst_o <= `INST_NOP;
+            inst_addr_o <= `ZeroWord;
+        end else begin
+            inst_o <= inst_i;
+            inst_addr_o <= inst_addr_i;
+        end
+    end
+
+endmodule

rtl/openriscv_core.v

@@ -0,0 +1,148 @@
+ /*                                                                      
+ Copyright 2019 Blue Liang, liangkangnan@163.com
+                                                                         
+ Licensed under the Apache License, Version 2.0 (the "License");         
+ you may not use this file except in compliance with the License.        
+ You may obtain a copy of the License at                                 
+                                                                         
+     http://www.apache.org/licenses/LICENSE-2.0                          
+                                                                         
+ Unless required by applicable law or agreed to in writing, software    
+ distributed under the License is distributed on an "AS IS" BASIS,       
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and     
+ limitations under the License.                                          
+ */
+
+`include "defines.v"
+
+// CPU core module
+module openriscv_core (
+
+    input wire clk,
+    input wire rst
+
+);
+
+    // pc_reg
+	wire[`SramAddrBus] pc_pc_o;
+	wire pc_re_o;
+
+    // if_id
+	wire[`SramBus] if_inst_o;
+    wire[`SramAddrBus] if_inst_addr_o;
+
+    // id
+    wire id_reg1_re_o;
+    wire[`RegAddrBus] id_reg1_raddr_o;
+    wire id_reg2_re_o;
+    wire[`RegAddrBus] id_reg2_raddr_o;
+    wire[`SramBus] id_inst_o;
+    wire id_inst_valid_o;
+    wire id_reg_we_o;
+    wire[`RegAddrBus] id_reg_waddr_o;
+    wire id_sram_re_o;
+    wire id_sram_we_o;
+    wire[`SramAddrBus] id_pc_o;
+    wire[`SramAddrBus] id_inst_addr_o;
+
+    // ex
+    wire[`RegBus] ex_reg_wdata_o;
+    wire[`SramBus] ex_sram_wdata_o;
+    wire[`SramAddrBus] ex_sram_raddr_o;
+    wire[`SramAddrBus] ex_sram_waddr_o;
+    wire ex_jump_flag_o;
+    wire[`RegBus] ex_jump_addr_o;
+
+    // regs
+    wire[`RegBus] regs_rdata1_o;
+    wire[`RegBus] regs_rdata2_o;
+
+    // sim_ram
+    wire[`SramBus] ram_pc_rdata_o;
+    wire[`SramBus] ram_ex_rdata_o;
+
+    sim_ram u_sim_ram(
+        .clk(clk),
+        .rst(rst),
+        .we_i(id_sram_we_o),
+        .waddr_i(ex_sram_waddr_o),
+        .wdata_i(ex_sram_wdata_o),
+        .pc_re_i(pc_re_o),
+        .pc_raddr_i(pc_pc_o),
+        .pc_rdata_o(ram_pc_rdata_o),
+        .ex_re_i(id_sram_re_o),
+        .ex_raddr_i(ex_sram_raddr_o),
+        .ex_rdata_o(ram_ex_rdata_o)
+    );
+
+    pc_reg u_pc_reg(
+        .clk(clk),
+        .rst(rst),
+        .pc_o(pc_pc_o),
+        .re_o(pc_re_o),
+        .jump_flag_ex_i(ex_jump_flag_o),
+        .jump_addr_ex_i(ex_jump_addr_o)
+    );
+
+    regs u_regs(
+        .clk(clk),
+        .rst(rst),
+        .we(id_reg_we_o),
+        .waddr(id_reg_waddr_o),
+        .wdata(ex_reg_wdata_o),
+        .re1(id_reg1_re_o),
+        .raddr1(id_reg1_raddr_o),
+        .rdata1(regs_rdata1_o),
+        .re2(id_reg2_re_o),
+        .raddr2(id_reg2_raddr_o),
+        .rdata2(regs_rdata2_o)
+    );
+
+    if_id u_if_id(
+        .clk(clk),
+        .rst(rst),
+        .inst_i(ram_pc_rdata_o),
+        .inst_addr_i(pc_pc_o),
+        .inst_o(if_inst_o),
+        .inst_addr_o(if_inst_addr_o),
+        .jump_flag_ex_i(ex_jump_flag_o)
+    );
+
+    id u_id(
+        .clk(clk),
+        .rst(rst),
+        .inst_i(if_inst_o),
+        .inst_addr_o(id_inst_addr_o),
+        .inst_addr_i(if_inst_addr_o),
+        .jump_flag_ex_i(ex_jump_flag_o),
+        .reg1_re_o(id_reg1_re_o),
+        .reg1_raddr_o(id_reg1_raddr_o),
+        .reg2_re_o(id_reg2_re_o),
+        .reg2_raddr_o(id_reg2_raddr_o),
+        .inst_o(id_inst_o),
+        .inst_valid_o(id_inst_valid_o),
+        .reg_we_o(id_reg_we_o),
+        .reg_waddr_o(id_reg_waddr_o),
+        .sram_re_o(id_sram_re_o),
+        .sram_we_o(id_sram_we_o)
+    );
+
+    ex u_ex(
+        .clk(clk),
+        .rst(rst),
+        .inst_i(id_inst_o),
+        .inst_addr_i(id_inst_addr_o),
+        .inst_valid_i(id_inst_valid_o),
+        .reg1_rdata_i(regs_rdata1_o),
+        .reg2_rdata_i(regs_rdata2_o),
+        .reg_wdata_o(ex_reg_wdata_o),
+        .sram_rdata_i(ram_ex_rdata_o),
+        .sram_wdata_o(ex_sram_wdata_o),
+        .sram_raddr_o(ex_sram_raddr_o),
+        .sram_waddr_o(ex_sram_waddr_o),
+        .jump_flag_o(ex_jump_flag_o),
+        .jump_addr_o(ex_jump_addr_o)
+    );
+
+endmodule

rtl/pc_reg.v

@@ -0,0 +1,56 @@
+ /*                                                                      
+ Copyright 2019 Blue Liang, liangkangnan@163.com
+                                                                         
+ Licensed under the Apache License, Version 2.0 (the "License");         
+ you may not use this file except in compliance with the License.        
+ You may obtain a copy of the License at                                 
+                                                                         
+     http://www.apache.org/licenses/LICENSE-2.0                          
+                                                                         
+ Unless required by applicable law or agreed to in writing, software    
+ distributed under the License is distributed on an "AS IS" BASIS,       
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and     
+ limitations under the License.                                          
+ */
+
+`include "defines.v"
+
+// pc reg module
+module pc_reg (
+
+    input wire clk,
+    input wire rst,
+
+    input wire jump_flag_ex_i,
+    input wire[`RegBus] jump_addr_ex_i,
+
+	output reg[`SramAddrBus] pc_o,
+	output reg re_o
+
+);
+
+    reg[`SramAddrBus] offset;
+
+    always @ (posedge clk) begin
+        if (rst == `RstEnable) begin
+            pc_o <= `ZeroWord;
+            offset <= `ZeroWord;
+        end else if (jump_flag_ex_i == `JumpEnable) begin
+            pc_o <= jump_addr_ex_i;
+            offset <= jump_addr_ex_i + 4'h4;
+        end else begin
+            pc_o <= offset;
+            offset <= offset + 4'h4;
+        end
+    end
+
+    always @ (posedge clk) begin
+        if (rst == `RstEnable) begin
+            re_o <= `ReadDisable;
+        end else begin
+            re_o <= `ReadEnable;
+        end
+    end
+
+endmodule

rtl/regs.v

@@ -0,0 +1,73 @@
+ /*                                                                      
+ Copyright 2019 Blue Liang, liangkangnan@163.com
+                                                                         
+ Licensed under the Apache License, Version 2.0 (the "License");         
+ you may not use this file except in compliance with the License.        
+ You may obtain a copy of the License at                                 
+                                                                         
+     http://www.apache.org/licenses/LICENSE-2.0                          
+                                                                         
+ Unless required by applicable law or agreed to in writing, software    
+ distributed under the License is distributed on an "AS IS" BASIS,       
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and     
+ limitations under the License.                                          
+ */
+
+`include "defines.v"
+
+// common reg module
+module regs (
+
+    input wire clk,
+    input wire rst,
+
+    input wire we,                  // reg write enable
+    input wire[`RegAddrBus] waddr,  // reg write addr
+    input wire[`RegBus] wdata,      // reg write data
+
+    input wire re1,                 // reg1 read enable
+    input wire[`RegAddrBus] raddr1, // reg1 read addr
+    output reg[`RegBus] rdata1,     // reg1 read data
+
+    input wire re2,                 // reg2 read enable
+    input wire[`RegAddrBus] raddr2, // reg2 read addr
+    output reg[`RegBus] rdata2      // reg2 read data
+
+);
+
+    reg[`RegBus] regs[0:`RegNum - 1];
+
+    always @ (posedge clk) begin
+        if (rst == `RstDisable) begin
+            if((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin
+                regs[waddr] <= wdata;
+            end
+        end
+    end
+
+    always @ (*) begin
+        if(rst == `RstEnable) begin
+            rdata1 <= `ZeroWord;
+        end else if(raddr1 == `RegNumLog2'h0) begin
+            rdata1 <= `ZeroWord;
+        end else if(re1 == `ReadEnable) begin
+            rdata1 <= regs[raddr1];
+        end else begin
+            rdata1 <= `ZeroWord;
+        end
+    end
+
+    always @ (*) begin
+        if(rst == `RstEnable) begin
+            rdata2 <= `ZeroWord;
+        end else if(raddr2 == `RegNumLog2'h0) begin
+            rdata2 <= `ZeroWord;
+        end else if(re2 == `ReadEnable) begin
+            rdata2 <= regs[raddr2];
+        end else begin
+            rdata2 <= `ZeroWord;
+        end
+    end
+
+endmodule

rtl/sim_ram.v

@@ -0,0 +1,71 @@
+ /*                                                                      
+ Copyright 2019 Blue Liang, liangkangnan@163.com
+                                                                         
+ Licensed under the Apache License, Version 2.0 (the "License");         
+ you may not use this file except in compliance with the License.        
+ You may obtain a copy of the License at                                 
+                                                                         
+     http://www.apache.org/licenses/LICENSE-2.0                          
+                                                                         
+ Unless required by applicable law or agreed to in writing, software    
+ distributed under the License is distributed on an "AS IS" BASIS,       
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and     
+ limitations under the License.                                          
+ */
+
+`include "defines.v"
+
+// simulation ram module
+module sim_ram (
+
+    input wire clk,
+    input wire rst,
+
+    input wire we_i,                     // write enable
+    input wire[`SramAddrBus] waddr_i,    // write addr
+    input wire[`SramBus] wdata_i,        // write data
+
+    input wire pc_re_i,                  // pc read enable
+    input wire[`SramAddrBus] pc_raddr_i, // pc read addr
+    output reg[`SramBus] pc_rdata_o,     // pc read data
+
+    input wire ex_re_i,                  // ex read enable
+    input wire[`SramAddrBus] ex_raddr_i, // ex read addr
+    output reg[`SramBus] ex_rdata_o      // ex read data
+
+);
+
+    reg[`SramBus] ram[0:`SramMemNum - 1];
+
+    always @ (posedge clk) begin
+        if (rst == `RstDisable) begin
+            if(we_i == `WriteEnable) begin
+                ram[waddr_i[13:2]] <= wdata_i;
+            end
+        end
+    end
+
+    always @ (*) begin
+        if(rst == `RstEnable) begin
+            pc_rdata_o <= `ZeroWord;
+        end else if((pc_raddr_i == waddr_i) && (pc_re_i == `ReadEnable)) begin
+            pc_rdata_o <= wdata_i;
+        end else if(pc_re_i == `ReadEnable) begin
+            pc_rdata_o <= ram[pc_raddr_i >> 2];
+        end else begin
+            pc_rdata_o <= `ZeroWord;
+        end
+    end
+
+    always @ (*) begin
+        if(rst == `RstEnable) begin
+            ex_rdata_o <= `ZeroWord;
+        end else if(ex_re_i == `ReadEnable) begin
+            ex_rdata_o <= ram[ex_raddr_i[13:2]];
+        end else begin
+            ex_rdata_o <= `ZeroWord;
+        end
+    end
+
+endmodule

sim/inst.data

@@ -0,0 +1,354 @@
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sim/openriscv_core_tb.v

@@ -0,0 +1,77 @@
+`timescale 1 ns / 1 ps
+
+`include "defines.v"
+
+// top module
+module openriscv_core_tb;
+
+    reg clk;
+    reg rst;
+
+    always #10 clk = ~clk;     // 50MHz
+
+    wire[`RegBus] x3 = u_openriscv_core.u_regs.regs[3];
+    wire[`RegBus] x26 = u_openriscv_core.u_regs.regs[26];
+    wire[`RegBus] x27 = u_openriscv_core.u_regs.regs[27];
+
+    integer r;
+    initial begin
+        clk = 0;
+        rst = `RstEnable;
+        $display("test running...");
+        #40
+        rst = `RstDisable;
+        #100
+        wait(x26 == 32'b1)   // wait sim end, when x26 == 1
+        #100
+        if (x27 == 32'b1) begin
+            $display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~");
+            $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
+            $display("~~~~~~~~~ #####     ##     ####    #### ~~~~~~~~~");
+            $display("~~~~~~~~~ #    #   #  #   #       #     ~~~~~~~~~");
+            $display("~~~~~~~~~ #    #  #    #   ####    #### ~~~~~~~~~");
+            $display("~~~~~~~~~ #####   ######       #       #~~~~~~~~~");
+            $display("~~~~~~~~~ #       #    #  #    #  #    #~~~~~~~~~");
+            $display("~~~~~~~~~ #       #    #   ####    #### ~~~~~~~~~");
+            $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
+        end else begin
+            $display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~");
+            $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
+            $display("~~~~~~~~~~######    ##       #    #     ~~~~~~~~~~");
+            $display("~~~~~~~~~~#        #  #      #    #     ~~~~~~~~~~");
+            $display("~~~~~~~~~~#####   #    #     #    #     ~~~~~~~~~~");
+            $display("~~~~~~~~~~#       ######     #    #     ~~~~~~~~~~");
+            $display("~~~~~~~~~~#       #    #     #    #     ~~~~~~~~~~");
+            $display("~~~~~~~~~~#       #    #     #    ######~~~~~~~~~~");
+            $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~");
+            $display("fail testnum = %2d", x3);
+            for (r = 0; r < 32; r++)
+                $display("x%2d = 0x%x", r, u_openriscv_core.u_regs.regs[r]);
+        end
+        $finish;
+    end
+
+    // sim timeout
+    initial begin
+        #100000
+        $display("Time Out.");
+        $finish;
+    end
+
+    // read mem data
+    initial begin
+        $readmemh ("inst.data", u_openriscv_core.u_sim_ram.ram);
+    end
+
+    // generate wave file, use by gtkwave
+    initial begin
+        $dumpfile("openriscv_core_tb.vcd");
+        $dumpvars(0, openriscv_core_tb);
+    end
+
+    openriscv_core u_openriscv_core(
+        .clk(clk),
+        .rst(rst)
+    );
+
+endmodule

sim/sim_default_nowave.bat

@@ -0,0 +1,2 @@
+iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v
+vvp out.vvp

sim/sim_new_nowave.bat

@@ -0,0 +1,3 @@
+..\tools\BinToMem_CLI.exe %1 %2
+iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v
+vvp out.vvp

tests/example/Makefile

@@ -0,0 +1,25 @@
+
+RISCV_ARCH := rv32i
+RISCV_ABI := ilp32
+
+RISCV_PATH := ../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/
+
+CFLAGS += -march=$(RISCV_ARCH)
+CFLAGS += -mabi=$(RISCV_ABI)
+CFLAGS += -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+
+RISCV_GCC     := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc)
+RISCV_AS      := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-as)
+RISCV_GXX     := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++)
+RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump)
+RISCV_GDB     := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb)
+RISCV_AR      := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar)
+RISCV_OBJCOPY := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objcopy)
+RISCV_READELF := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-readelf)
+
+
+.PHONY: all
+all:
+	$(RISCV_GCC) $(CFLAGS) reset.S main.c -Tlink.ld -o example
+	$(RISCV_OBJCOPY) -O binary example example.bin
+	$(RISCV_OBJDUMP) --disassemble-all example > example.dump

tests/example/README.md

@@ -0,0 +1 @@
+a simple c program which can run on tinyriscv.

tests/example/example.dump

@@ -0,0 +1,96 @@
+
+example:     file format elf32-littleriscv
+
+
+Disassembly of section .text:
+
+00000000 <_reset>:
+   0:	10000113          	li	sp,256
+   4:	00000d13          	li	s10,0
+   8:	00000d93          	li	s11,0
+   c:	04c000ef          	jal	ra,58 <main>
+  10:	00100d13          	li	s10,1
+
+00000014 <loop>:
+  14:	0000006f          	j	14 <loop>
+
+00000018 <set_test_pass>:
+  18:	ff010113          	addi	sp,sp,-16
+  1c:	00812623          	sw	s0,12(sp)
+  20:	01010413          	addi	s0,sp,16
+  24:	00100d93          	li	s11,1
+  28:	00000013          	nop
+  2c:	00c12403          	lw	s0,12(sp)
+  30:	01010113          	addi	sp,sp,16
+  34:	00008067          	ret
+
+00000038 <set_test_fail>:
+  38:	ff010113          	addi	sp,sp,-16
+  3c:	00812623          	sw	s0,12(sp)
+  40:	01010413          	addi	s0,sp,16
+  44:	00000d93          	li	s11,0
+  48:	00000013          	nop
+  4c:	00c12403          	lw	s0,12(sp)
+  50:	01010113          	addi	sp,sp,16
+  54:	00008067          	ret
+
+00000058 <main>:
+  58:	fe010113          	addi	sp,sp,-32
+  5c:	00112e23          	sw	ra,28(sp)
+  60:	00812c23          	sw	s0,24(sp)
+  64:	02010413          	addi	s0,sp,32
+  68:	fe042423          	sw	zero,-24(s0)
+  6c:	fe042623          	sw	zero,-20(s0)
+  70:	0200006f          	j	90 <main+0x38>
+  74:	fe842703          	lw	a4,-24(s0)
+  78:	fec42783          	lw	a5,-20(s0)
+  7c:	00f707b3          	add	a5,a4,a5
+  80:	fef42423          	sw	a5,-24(s0)
+  84:	fec42783          	lw	a5,-20(s0)
+  88:	00178793          	addi	a5,a5,1
+  8c:	fef42623          	sw	a5,-20(s0)
+  90:	fec42703          	lw	a4,-20(s0)
+  94:	06400793          	li	a5,100
+  98:	fce7dee3          	bge	a5,a4,74 <main+0x1c>
+  9c:	fe842703          	lw	a4,-24(s0)
+  a0:	000017b7          	lui	a5,0x1
+  a4:	3ba78793          	addi	a5,a5,954 # 13ba <_end+0x12ba>
+  a8:	00f71663          	bne	a4,a5,b4 <main+0x5c>
+  ac:	f6dff0ef          	jal	ra,18 <set_test_pass>
+  b0:	0080006f          	j	b8 <main+0x60>
+  b4:	f85ff0ef          	jal	ra,38 <set_test_fail>
+  b8:	00000793          	li	a5,0
+  bc:	00078513          	mv	a0,a5
+  c0:	01c12083          	lw	ra,28(sp)
+  c4:	01812403          	lw	s0,24(sp)
+  c8:	02010113          	addi	sp,sp,32
+  cc:	00008067          	ret
+
+Disassembly of section .comment:
+
+00000000 <.comment>:
+   0:	3a434347          	fmsub.d	ft6,ft6,ft4,ft7,rmm
+   4:	2820                	fld	fs0,80(s0)
+   6:	20554e47          	fmsub.s	ft8,fa0,ft5,ft4,rmm
+   a:	434d                	li	t1,19
+   c:	2055                	jal	b0 <main+0x58>
+   e:	6345                	lui	t1,0x11
+  10:	696c                	flw	fa1,84(a0)
+  12:	7370                	flw	fa2,100(a4)
+  14:	2065                	jal	bc <main+0x64>
+  16:	4952                	lw	s2,20(sp)
+  18:	562d4353          	0x562d4353
+  1c:	4520                	lw	s0,72(a0)
+  1e:	626d                	lui	tp,0x1b
+  20:	6465                	lui	s0,0x19
+  22:	6564                	flw	fs1,76(a0)
+  24:	2064                	fld	fs1,192(s0)
+  26:	2c434347          	0x2c434347
+  2a:	3620                	fld	fs0,104(a2)
+  2c:	2d34                	fld	fa3,88(a0)
+  2e:	6962                	flw	fs2,24(sp)
+  30:	2974                	fld	fa3,208(a0)
+  32:	3820                	fld	fs0,112(s0)
+  34:	322e                	fld	ft4,232(sp)
+  36:	302e                	fld	ft0,232(sp)
+	...

tests/example/link.ld

@@ -0,0 +1,25 @@
+OUTPUT_ARCH( "riscv" )
+ENTRY(_reset)
+
+SECTIONS
+{
+    __stack_size = 0x100;
+
+    . = 0x00000000;
+    .text : { *(.text) }
+
+    PROVIDE( _data_start = . );
+    .data ALIGN(0x1000) : { *(.data) }
+    . = ALIGN(4);
+    PROVIDE( _data_end = . );
+
+    PROVIDE( _bss_start = . );
+    .bss : { *(.bss) }
+    PROVIDE( _bss_end = . );
+
+    PROVIDE(_stack_begin = .);
+    . = __stack_size;
+    PROVIDE( _sp = . );
+    PROVIDE(_stack_end = .);
+    _end = .;
+}

tests/example/main.c

@@ -0,0 +1,29 @@
+
+static void set_test_pass()
+{
+    asm("li x27, 0x01");
+}
+
+static void set_test_fail()
+{
+    asm("li x27, 0x00");
+}
+
+// add 1 to 100
+int main()
+{
+    int i;
+    int sum;
+
+    sum = 0;
+
+    for (i = 0; i <= 100; i++)
+        sum += i;
+
+    if (sum == 5050)
+        set_test_pass();
+    else
+        set_test_fail();
+
+    return 0;
+}

tests/example/reset.S

@@ -0,0 +1,15 @@
+    .section .text;
+    .align  2;
+    .globl _reset;
+
+_reset:
+    la sp, _sp
+    li x26, 0x00
+    li x27, 0x00
+
+    call main
+
+    li x26, 0x01
+
+loop:
+    j loop

tests/isa/Makefile

@@ -0,0 +1,65 @@
+#=======================================================================
+# Makefile for riscv-tests/isa
+#-----------------------------------------------------------------------
+
+XLEN := 32
+
+src_dir := .
+
+include $(src_dir)/rv32ui/Makefrag
+
+default: all
+
+#--------------------------------------------------------------------
+# Build rules
+#--------------------------------------------------------------------
+
+RISCV_PREFIX ?= ../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/bin/riscv-none-embed-
+RISCV_GCC ?= $(RISCV_PREFIX)gcc
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all
+RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy
+
+
+vpath %.S $(src_dir)
+
+#------------------------------------------------------------
+# Build assembly tests
+
+%.dump: % 
+	$(RISCV_OBJDUMP) generated/$< > generated/$@
+	$(RISCV_OBJCOPY) -O verilog generated/$<   generated/$<.verilog
+	$(RISCV_OBJCOPY) -O binary generated/$<   generated/$<.bin
+
+
+define compile_template
+
+$$($(1)_p_tests): $(1)-p-%: $(1)/%.S
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir) -T$(src_dir)/link.ld $$< -o generated/$$@
+$(1)_tests += $$($(1)_p_tests)
+
+$(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
+
+$(1): $$($(1)_tests_dump)
+
+.PHONY: $(1)
+
+tests += $$($(1)_tests)
+
+endef
+
+$(eval $(call compile_template,rv32ui,-march=rv32i -mabi=ilp32))
+
+
+tests_verilog = $(addsuffix .verilog, $(tests))
+tests_dump = $(addsuffix .dump, $(tests))
+
+
+#------------------------------------------------------------
+# Default
+
+all: $(tests_dump)
+
+clean:
+	rm -rf generated/*
+

tests/isa/README.md

@@ -0,0 +1,4 @@
+RV32I instruction source code which copy from riscv(github).
+I have modified it so can run on tinyriscv.
+compile: type make under the cmd windows
+recompile: type make after make clean under the cmd windows

tests/isa/generated/rv32ui-p-add.dump

@@ -0,0 +1,419 @@
+
+generated/rv32ui-p-add:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00000093          	li	ra,0
+   c:	00000113          	li	sp,0
+  10:	00208f33          	add	t5,ra,sp
+  14:	00000e93          	li	t4,0
+  18:	00200193          	li	gp,2
+  1c:	4ddf1663          	bne	t5,t4,4e8 <fail>
+
+00000020 <test_3>:
+  20:	00100093          	li	ra,1
+  24:	00100113          	li	sp,1
+  28:	00208f33          	add	t5,ra,sp
+  2c:	00200e93          	li	t4,2
+  30:	00300193          	li	gp,3
+  34:	4bdf1a63          	bne	t5,t4,4e8 <fail>
+
+00000038 <test_4>:
+  38:	00300093          	li	ra,3
+  3c:	00700113          	li	sp,7
+  40:	00208f33          	add	t5,ra,sp
+  44:	00a00e93          	li	t4,10
+  48:	00400193          	li	gp,4
+  4c:	49df1e63          	bne	t5,t4,4e8 <fail>
+
+00000050 <test_5>:
+  50:	00000093          	li	ra,0
+  54:	ffff8137          	lui	sp,0xffff8
+  58:	00208f33          	add	t5,ra,sp
+  5c:	ffff8eb7          	lui	t4,0xffff8
+  60:	00500193          	li	gp,5
+  64:	49df1263          	bne	t5,t4,4e8 <fail>
+
+00000068 <test_6>:
+  68:	800000b7          	lui	ra,0x80000
+  6c:	00000113          	li	sp,0
+  70:	00208f33          	add	t5,ra,sp
+  74:	80000eb7          	lui	t4,0x80000
+  78:	00600193          	li	gp,6
+  7c:	47df1663          	bne	t5,t4,4e8 <fail>
+
+00000080 <test_7>:
+  80:	800000b7          	lui	ra,0x80000
+  84:	ffff8137          	lui	sp,0xffff8
+  88:	00208f33          	add	t5,ra,sp
+  8c:	7fff8eb7          	lui	t4,0x7fff8
+  90:	00700193          	li	gp,7
+  94:	45df1a63          	bne	t5,t4,4e8 <fail>
+
+00000098 <test_8>:
+  98:	00000093          	li	ra,0
+  9c:	00008137          	lui	sp,0x8
+  a0:	fff10113          	addi	sp,sp,-1 # 7fff <begin_signature+0x6fff>
+  a4:	00208f33          	add	t5,ra,sp
+  a8:	00008eb7          	lui	t4,0x8
+  ac:	fffe8e93          	addi	t4,t4,-1 # 7fff <begin_signature+0x6fff>
+  b0:	00800193          	li	gp,8
+  b4:	43df1a63          	bne	t5,t4,4e8 <fail>
+
+000000b8 <test_9>:
+  b8:	800000b7          	lui	ra,0x80000
+  bc:	fff08093          	addi	ra,ra,-1 # 7fffffff <begin_signature+0x7fffefff>
+  c0:	00000113          	li	sp,0
+  c4:	00208f33          	add	t5,ra,sp
+  c8:	80000eb7          	lui	t4,0x80000
+  cc:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <begin_signature+0x7fffefff>
+  d0:	00900193          	li	gp,9
+  d4:	41df1a63          	bne	t5,t4,4e8 <fail>
+
+000000d8 <test_10>:
+  d8:	800000b7          	lui	ra,0x80000
+  dc:	fff08093          	addi	ra,ra,-1 # 7fffffff <begin_signature+0x7fffefff>
+  e0:	00008137          	lui	sp,0x8
+  e4:	fff10113          	addi	sp,sp,-1 # 7fff <begin_signature+0x6fff>
+  e8:	00208f33          	add	t5,ra,sp
+  ec:	80008eb7          	lui	t4,0x80008
+  f0:	ffee8e93          	addi	t4,t4,-2 # 80007ffe <begin_signature+0x80006ffe>
+  f4:	00a00193          	li	gp,10
+  f8:	3fdf1863          	bne	t5,t4,4e8 <fail>
+
+000000fc <test_11>:
+  fc:	800000b7          	lui	ra,0x80000
+ 100:	00008137          	lui	sp,0x8
+ 104:	fff10113          	addi	sp,sp,-1 # 7fff <begin_signature+0x6fff>
+ 108:	00208f33          	add	t5,ra,sp
+ 10c:	80008eb7          	lui	t4,0x80008
+ 110:	fffe8e93          	addi	t4,t4,-1 # 80007fff <begin_signature+0x80006fff>
+ 114:	00b00193          	li	gp,11
+ 118:	3ddf1863          	bne	t5,t4,4e8 <fail>
+
+0000011c <test_12>:
+ 11c:	800000b7          	lui	ra,0x80000
+ 120:	fff08093          	addi	ra,ra,-1 # 7fffffff <begin_signature+0x7fffefff>
+ 124:	ffff8137          	lui	sp,0xffff8
+ 128:	00208f33          	add	t5,ra,sp
+ 12c:	7fff8eb7          	lui	t4,0x7fff8
+ 130:	fffe8e93          	addi	t4,t4,-1 # 7fff7fff <begin_signature+0x7fff6fff>
+ 134:	00c00193          	li	gp,12
+ 138:	3bdf1863          	bne	t5,t4,4e8 <fail>
+
+0000013c <test_13>:
+ 13c:	00000093          	li	ra,0
+ 140:	fff00113          	li	sp,-1
+ 144:	00208f33          	add	t5,ra,sp
+ 148:	fff00e93          	li	t4,-1
+ 14c:	00d00193          	li	gp,13
+ 150:	39df1c63          	bne	t5,t4,4e8 <fail>
+
+00000154 <test_14>:
+ 154:	fff00093          	li	ra,-1
+ 158:	00100113          	li	sp,1
+ 15c:	00208f33          	add	t5,ra,sp
+ 160:	00000e93          	li	t4,0
+ 164:	00e00193          	li	gp,14
+ 168:	39df1063          	bne	t5,t4,4e8 <fail>
+
+0000016c <test_15>:
+ 16c:	fff00093          	li	ra,-1
+ 170:	fff00113          	li	sp,-1
+ 174:	00208f33          	add	t5,ra,sp
+ 178:	ffe00e93          	li	t4,-2
+ 17c:	00f00193          	li	gp,15
+ 180:	37df1463          	bne	t5,t4,4e8 <fail>
+
+00000184 <test_16>:
+ 184:	00100093          	li	ra,1
+ 188:	80000137          	lui	sp,0x80000
+ 18c:	fff10113          	addi	sp,sp,-1 # 7fffffff <begin_signature+0x7fffefff>
+ 190:	00208f33          	add	t5,ra,sp
+ 194:	80000eb7          	lui	t4,0x80000
+ 198:	01000193          	li	gp,16
+ 19c:	35df1663          	bne	t5,t4,4e8 <fail>
+
+000001a0 <test_17>:
+ 1a0:	00d00093          	li	ra,13
+ 1a4:	00b00113          	li	sp,11
+ 1a8:	002080b3          	add	ra,ra,sp
+ 1ac:	01800e93          	li	t4,24
+ 1b0:	01100193          	li	gp,17
+ 1b4:	33d09a63          	bne	ra,t4,4e8 <fail>
+
+000001b8 <test_18>:
+ 1b8:	00e00093          	li	ra,14
+ 1bc:	00b00113          	li	sp,11
+ 1c0:	00208133          	add	sp,ra,sp
+ 1c4:	01900e93          	li	t4,25
+ 1c8:	01200193          	li	gp,18
+ 1cc:	31d11e63          	bne	sp,t4,4e8 <fail>
+
+000001d0 <test_19>:
+ 1d0:	00d00093          	li	ra,13
+ 1d4:	001080b3          	add	ra,ra,ra
+ 1d8:	01a00e93          	li	t4,26
+ 1dc:	01300193          	li	gp,19
+ 1e0:	31d09463          	bne	ra,t4,4e8 <fail>
+
+000001e4 <test_20>:
+ 1e4:	00000213          	li	tp,0
+ 1e8:	00d00093          	li	ra,13
+ 1ec:	00b00113          	li	sp,11
+ 1f0:	00208f33          	add	t5,ra,sp
+ 1f4:	000f0313          	mv	t1,t5
+ 1f8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1fc:	00200293          	li	t0,2
+ 200:	fe5214e3          	bne	tp,t0,1e8 <test_20+0x4>
+ 204:	01800e93          	li	t4,24
+ 208:	01400193          	li	gp,20
+ 20c:	2dd31e63          	bne	t1,t4,4e8 <fail>
+
+00000210 <test_21>:
+ 210:	00000213          	li	tp,0
+ 214:	00e00093          	li	ra,14
+ 218:	00b00113          	li	sp,11
+ 21c:	00208f33          	add	t5,ra,sp
+ 220:	00000013          	nop
+ 224:	000f0313          	mv	t1,t5
+ 228:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 22c:	00200293          	li	t0,2
+ 230:	fe5212e3          	bne	tp,t0,214 <test_21+0x4>
+ 234:	01900e93          	li	t4,25
+ 238:	01500193          	li	gp,21
+ 23c:	2bd31663          	bne	t1,t4,4e8 <fail>
+
+00000240 <test_22>:
+ 240:	00000213          	li	tp,0
+ 244:	00f00093          	li	ra,15
+ 248:	00b00113          	li	sp,11
+ 24c:	00208f33          	add	t5,ra,sp
+ 250:	00000013          	nop
+ 254:	00000013          	nop
+ 258:	000f0313          	mv	t1,t5
+ 25c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 260:	00200293          	li	t0,2
+ 264:	fe5210e3          	bne	tp,t0,244 <test_22+0x4>
+ 268:	01a00e93          	li	t4,26
+ 26c:	01600193          	li	gp,22
+ 270:	27d31c63          	bne	t1,t4,4e8 <fail>
+
+00000274 <test_23>:
+ 274:	00000213          	li	tp,0
+ 278:	00d00093          	li	ra,13
+ 27c:	00b00113          	li	sp,11
+ 280:	00208f33          	add	t5,ra,sp
+ 284:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 288:	00200293          	li	t0,2
+ 28c:	fe5216e3          	bne	tp,t0,278 <test_23+0x4>
+ 290:	01800e93          	li	t4,24
+ 294:	01700193          	li	gp,23
+ 298:	25df1863          	bne	t5,t4,4e8 <fail>
+
+0000029c <test_24>:
+ 29c:	00000213          	li	tp,0
+ 2a0:	00e00093          	li	ra,14
+ 2a4:	00b00113          	li	sp,11
+ 2a8:	00000013          	nop
+ 2ac:	00208f33          	add	t5,ra,sp
+ 2b0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2b4:	00200293          	li	t0,2
+ 2b8:	fe5214e3          	bne	tp,t0,2a0 <test_24+0x4>
+ 2bc:	01900e93          	li	t4,25
+ 2c0:	01800193          	li	gp,24
+ 2c4:	23df1263          	bne	t5,t4,4e8 <fail>
+
+000002c8 <test_25>:
+ 2c8:	00000213          	li	tp,0
+ 2cc:	00f00093          	li	ra,15
+ 2d0:	00b00113          	li	sp,11
+ 2d4:	00000013          	nop
+ 2d8:	00000013          	nop
+ 2dc:	00208f33          	add	t5,ra,sp
+ 2e0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2e4:	00200293          	li	t0,2
+ 2e8:	fe5212e3          	bne	tp,t0,2cc <test_25+0x4>
+ 2ec:	01a00e93          	li	t4,26
+ 2f0:	01900193          	li	gp,25
+ 2f4:	1fdf1a63          	bne	t5,t4,4e8 <fail>
+
+000002f8 <test_26>:
+ 2f8:	00000213          	li	tp,0
+ 2fc:	00d00093          	li	ra,13
+ 300:	00000013          	nop
+ 304:	00b00113          	li	sp,11
+ 308:	00208f33          	add	t5,ra,sp
+ 30c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 310:	00200293          	li	t0,2
+ 314:	fe5214e3          	bne	tp,t0,2fc <test_26+0x4>
+ 318:	01800e93          	li	t4,24
+ 31c:	01a00193          	li	gp,26
+ 320:	1ddf1463          	bne	t5,t4,4e8 <fail>
+
+00000324 <test_27>:
+ 324:	00000213          	li	tp,0
+ 328:	00e00093          	li	ra,14
+ 32c:	00000013          	nop
+ 330:	00b00113          	li	sp,11
+ 334:	00000013          	nop
+ 338:	00208f33          	add	t5,ra,sp
+ 33c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 340:	00200293          	li	t0,2
+ 344:	fe5212e3          	bne	tp,t0,328 <test_27+0x4>
+ 348:	01900e93          	li	t4,25
+ 34c:	01b00193          	li	gp,27
+ 350:	19df1c63          	bne	t5,t4,4e8 <fail>
+
+00000354 <test_28>:
+ 354:	00000213          	li	tp,0
+ 358:	00f00093          	li	ra,15
+ 35c:	00000013          	nop
+ 360:	00000013          	nop
+ 364:	00b00113          	li	sp,11
+ 368:	00208f33          	add	t5,ra,sp
+ 36c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 370:	00200293          	li	t0,2
+ 374:	fe5212e3          	bne	tp,t0,358 <test_28+0x4>
+ 378:	01a00e93          	li	t4,26
+ 37c:	01c00193          	li	gp,28
+ 380:	17df1463          	bne	t5,t4,4e8 <fail>
+
+00000384 <test_29>:
+ 384:	00000213          	li	tp,0
+ 388:	00b00113          	li	sp,11
+ 38c:	00d00093          	li	ra,13
+ 390:	00208f33          	add	t5,ra,sp
+ 394:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 398:	00200293          	li	t0,2
+ 39c:	fe5216e3          	bne	tp,t0,388 <test_29+0x4>
+ 3a0:	01800e93          	li	t4,24
+ 3a4:	01d00193          	li	gp,29
+ 3a8:	15df1063          	bne	t5,t4,4e8 <fail>
+
+000003ac <test_30>:
+ 3ac:	00000213          	li	tp,0
+ 3b0:	00b00113          	li	sp,11
+ 3b4:	00e00093          	li	ra,14
+ 3b8:	00000013          	nop
+ 3bc:	00208f33          	add	t5,ra,sp
+ 3c0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 3c4:	00200293          	li	t0,2
+ 3c8:	fe5214e3          	bne	tp,t0,3b0 <test_30+0x4>
+ 3cc:	01900e93          	li	t4,25
+ 3d0:	01e00193          	li	gp,30
+ 3d4:	11df1a63          	bne	t5,t4,4e8 <fail>
+
+000003d8 <test_31>:
+ 3d8:	00000213          	li	tp,0
+ 3dc:	00b00113          	li	sp,11
+ 3e0:	00f00093          	li	ra,15
+ 3e4:	00000013          	nop
+ 3e8:	00000013          	nop
+ 3ec:	00208f33          	add	t5,ra,sp
+ 3f0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 3f4:	00200293          	li	t0,2
+ 3f8:	fe5212e3          	bne	tp,t0,3dc <test_31+0x4>
+ 3fc:	01a00e93          	li	t4,26
+ 400:	01f00193          	li	gp,31
+ 404:	0fdf1263          	bne	t5,t4,4e8 <fail>
+
+00000408 <test_32>:
+ 408:	00000213          	li	tp,0
+ 40c:	00b00113          	li	sp,11
+ 410:	00000013          	nop
+ 414:	00d00093          	li	ra,13
+ 418:	00208f33          	add	t5,ra,sp
+ 41c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 420:	00200293          	li	t0,2
+ 424:	fe5214e3          	bne	tp,t0,40c <test_32+0x4>
+ 428:	01800e93          	li	t4,24
+ 42c:	02000193          	li	gp,32
+ 430:	0bdf1c63          	bne	t5,t4,4e8 <fail>
+
+00000434 <test_33>:
+ 434:	00000213          	li	tp,0
+ 438:	00b00113          	li	sp,11
+ 43c:	00000013          	nop
+ 440:	00e00093          	li	ra,14
+ 444:	00000013          	nop
+ 448:	00208f33          	add	t5,ra,sp
+ 44c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 450:	00200293          	li	t0,2
+ 454:	fe5212e3          	bne	tp,t0,438 <test_33+0x4>
+ 458:	01900e93          	li	t4,25
+ 45c:	02100193          	li	gp,33
+ 460:	09df1463          	bne	t5,t4,4e8 <fail>
+
+00000464 <test_34>:
+ 464:	00000213          	li	tp,0
+ 468:	00b00113          	li	sp,11
+ 46c:	00000013          	nop
+ 470:	00000013          	nop
+ 474:	00f00093          	li	ra,15
+ 478:	00208f33          	add	t5,ra,sp
+ 47c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 480:	00200293          	li	t0,2
+ 484:	fe5212e3          	bne	tp,t0,468 <test_34+0x4>
+ 488:	01a00e93          	li	t4,26
+ 48c:	02200193          	li	gp,34
+ 490:	05df1c63          	bne	t5,t4,4e8 <fail>
+
+00000494 <test_35>:
+ 494:	00f00093          	li	ra,15
+ 498:	00100133          	add	sp,zero,ra
+ 49c:	00f00e93          	li	t4,15
+ 4a0:	02300193          	li	gp,35
+ 4a4:	05d11263          	bne	sp,t4,4e8 <fail>
+
+000004a8 <test_36>:
+ 4a8:	02000093          	li	ra,32
+ 4ac:	00008133          	add	sp,ra,zero
+ 4b0:	02000e93          	li	t4,32
+ 4b4:	02400193          	li	gp,36
+ 4b8:	03d11863          	bne	sp,t4,4e8 <fail>
+
+000004bc <test_37>:
+ 4bc:	000000b3          	add	ra,zero,zero
+ 4c0:	00000e93          	li	t4,0
+ 4c4:	02500193          	li	gp,37
+ 4c8:	03d09063          	bne	ra,t4,4e8 <fail>
+
+000004cc <test_38>:
+ 4cc:	01000093          	li	ra,16
+ 4d0:	01e00113          	li	sp,30
+ 4d4:	00208033          	add	zero,ra,sp
+ 4d8:	00000e93          	li	t4,0
+ 4dc:	02600193          	li	gp,38
+ 4e0:	01d01463          	bne	zero,t4,4e8 <fail>
+ 4e4:	00301863          	bne	zero,gp,4f4 <pass>
+
+000004e8 <fail>:
+ 4e8:	00100d13          	li	s10,1
+ 4ec:	00000d93          	li	s11,0
+
+000004f0 <loop_fail>:
+ 4f0:	0000006f          	j	4f0 <loop_fail>
+
+000004f4 <pass>:
+ 4f4:	00100d13          	li	s10,1
+ 4f8:	00100d93          	li	s11,1
+
+000004fc <loop_pass>:
+ 4fc:	0000006f          	j	4fc <loop_pass>
+ 500:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00000540 <tohost>:
+	...
+
+00000580 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-add.verilog

@@ -0,0 +1,88 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 00 00 00 13 01 00 00 
+33 8F 20 00 93 0E 00 00 93 01 20 00 63 16 DF 4D 
+93 00 10 00 13 01 10 00 33 8F 20 00 93 0E 20 00 
+93 01 30 00 63 1A DF 4B 93 00 30 00 13 01 70 00 
+33 8F 20 00 93 0E A0 00 93 01 40 00 63 1E DF 49 
+93 00 00 00 37 81 FF FF 33 8F 20 00 B7 8E FF FF 
+93 01 50 00 63 12 DF 49 B7 00 00 80 13 01 00 00 
+33 8F 20 00 B7 0E 00 80 93 01 60 00 63 16 DF 47 
+B7 00 00 80 37 81 FF FF 33 8F 20 00 B7 8E FF 7F 
+93 01 70 00 63 1A DF 45 93 00 00 00 37 81 00 00 
+13 01 F1 FF 33 8F 20 00 B7 8E 00 00 93 8E FE FF 
+93 01 80 00 63 1A DF 43 B7 00 00 80 93 80 F0 FF 
+13 01 00 00 33 8F 20 00 B7 0E 00 80 93 8E FE FF 
+93 01 90 00 63 1A DF 41 B7 00 00 80 93 80 F0 FF 
+37 81 00 00 13 01 F1 FF 33 8F 20 00 B7 8E 00 80 
+93 8E EE FF 93 01 A0 00 63 18 DF 3F B7 00 00 80 
+37 81 00 00 13 01 F1 FF 33 8F 20 00 B7 8E 00 80 
+93 8E FE FF 93 01 B0 00 63 18 DF 3D B7 00 00 80 
+93 80 F0 FF 37 81 FF FF 33 8F 20 00 B7 8E FF 7F 
+93 8E FE FF 93 01 C0 00 63 18 DF 3B 93 00 00 00 
+13 01 F0 FF 33 8F 20 00 93 0E F0 FF 93 01 D0 00 
+63 1C DF 39 93 00 F0 FF 13 01 10 00 33 8F 20 00 
+93 0E 00 00 93 01 E0 00 63 10 DF 39 93 00 F0 FF 
+13 01 F0 FF 33 8F 20 00 93 0E E0 FF 93 01 F0 00 
+63 14 DF 37 93 00 10 00 37 01 00 80 13 01 F1 FF 
+33 8F 20 00 B7 0E 00 80 93 01 00 01 63 16 DF 35 
+93 00 D0 00 13 01 B0 00 B3 80 20 00 93 0E 80 01 
+93 01 10 01 63 9A D0 33 93 00 E0 00 13 01 B0 00 
+33 81 20 00 93 0E 90 01 93 01 20 01 63 1E D1 31 
+93 00 D0 00 B3 80 10 00 93 0E A0 01 93 01 30 01 
+63 94 D0 31 13 02 00 00 93 00 D0 00 13 01 B0 00 
+33 8F 20 00 13 03 0F 00 13 02 12 00 93 02 20 00 
+E3 14 52 FE 93 0E 80 01 93 01 40 01 63 1E D3 2D 
+13 02 00 00 93 00 E0 00 13 01 B0 00 33 8F 20 00 
+13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 0E 90 01 93 01 50 01 63 16 D3 2B 
+13 02 00 00 93 00 F0 00 13 01 B0 00 33 8F 20 00 
+13 00 00 00 13 00 00 00 13 03 0F 00 13 02 12 00 
+93 02 20 00 E3 10 52 FE 93 0E A0 01 93 01 60 01 
+63 1C D3 27 13 02 00 00 93 00 D0 00 13 01 B0 00 
+33 8F 20 00 13 02 12 00 93 02 20 00 E3 16 52 FE 
+93 0E 80 01 93 01 70 01 63 18 DF 25 13 02 00 00 
+93 00 E0 00 13 01 B0 00 13 00 00 00 33 8F 20 00 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 90 01 
+93 01 80 01 63 12 DF 23 13 02 00 00 93 00 F0 00 
+13 01 B0 00 13 00 00 00 13 00 00 00 33 8F 20 00 
+13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E A0 01 
+93 01 90 01 63 1A DF 1F 13 02 00 00 93 00 D0 00 
+13 00 00 00 13 01 B0 00 33 8F 20 00 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 0E 80 01 93 01 A0 01 
+63 14 DF 1D 13 02 00 00 93 00 E0 00 13 00 00 00 
+13 01 B0 00 13 00 00 00 33 8F 20 00 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 0E 90 01 93 01 B0 01 
+63 1C DF 19 13 02 00 00 93 00 F0 00 13 00 00 00 
+13 00 00 00 13 01 B0 00 33 8F 20 00 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 0E A0 01 93 01 C0 01 
+63 14 DF 17 13 02 00 00 13 01 B0 00 93 00 D0 00 
+33 8F 20 00 13 02 12 00 93 02 20 00 E3 16 52 FE 
+93 0E 80 01 93 01 D0 01 63 10 DF 15 13 02 00 00 
+13 01 B0 00 93 00 E0 00 13 00 00 00 33 8F 20 00 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 90 01 
+93 01 E0 01 63 1A DF 11 13 02 00 00 13 01 B0 00 
+93 00 F0 00 13 00 00 00 13 00 00 00 33 8F 20 00 
+13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E A0 01 
+93 01 F0 01 63 12 DF 0F 13 02 00 00 13 01 B0 00 
+13 00 00 00 93 00 D0 00 33 8F 20 00 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 0E 80 01 93 01 00 02 
+63 1C DF 0B 13 02 00 00 13 01 B0 00 13 00 00 00 
+93 00 E0 00 13 00 00 00 33 8F 20 00 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 0E 90 01 93 01 10 02 
+63 14 DF 09 13 02 00 00 13 01 B0 00 13 00 00 00 
+13 00 00 00 93 00 F0 00 33 8F 20 00 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 0E A0 01 93 01 20 02 
+63 1C DF 05 93 00 F0 00 33 01 10 00 93 0E F0 00 
+93 01 30 02 63 12 D1 05 93 00 00 02 33 81 00 00 
+93 0E 00 02 93 01 40 02 63 18 D1 03 B3 00 00 00 
+93 0E 00 00 93 01 50 02 63 90 D0 03 93 00 00 01 
+13 01 E0 01 33 80 20 00 93 0E 00 00 93 01 60 02 
+63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 
+6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 
+00 00 00 00 
+@00000540
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-addi.dump

@@ -0,0 +1,242 @@
+
+generated/rv32ui-p-addi:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00000093          	li	ra,0
+   c:	00008f13          	mv	t5,ra
+  10:	00000e93          	li	t4,0
+  14:	00200193          	li	gp,2
+  18:	27df1c63          	bne	t5,t4,290 <fail>
+
+0000001c <test_3>:
+  1c:	00100093          	li	ra,1
+  20:	00108f13          	addi	t5,ra,1
+  24:	00200e93          	li	t4,2
+  28:	00300193          	li	gp,3
+  2c:	27df1263          	bne	t5,t4,290 <fail>
+
+00000030 <test_4>:
+  30:	00300093          	li	ra,3
+  34:	00708f13          	addi	t5,ra,7
+  38:	00a00e93          	li	t4,10
+  3c:	00400193          	li	gp,4
+  40:	25df1863          	bne	t5,t4,290 <fail>
+
+00000044 <test_5>:
+  44:	00000093          	li	ra,0
+  48:	80008f13          	addi	t5,ra,-2048
+  4c:	80000e93          	li	t4,-2048
+  50:	00500193          	li	gp,5
+  54:	23df1e63          	bne	t5,t4,290 <fail>
+
+00000058 <test_6>:
+  58:	800000b7          	lui	ra,0x80000
+  5c:	00008f13          	mv	t5,ra
+  60:	80000eb7          	lui	t4,0x80000
+  64:	00600193          	li	gp,6
+  68:	23df1463          	bne	t5,t4,290 <fail>
+
+0000006c <test_7>:
+  6c:	800000b7          	lui	ra,0x80000
+  70:	80008f13          	addi	t5,ra,-2048 # 7ffff800 <begin_signature+0x7fffe800>
+  74:	80000eb7          	lui	t4,0x80000
+  78:	800e8e93          	addi	t4,t4,-2048 # 7ffff800 <begin_signature+0x7fffe800>
+  7c:	00700193          	li	gp,7
+  80:	21df1863          	bne	t5,t4,290 <fail>
+
+00000084 <test_8>:
+  84:	00000093          	li	ra,0
+  88:	7ff08f13          	addi	t5,ra,2047
+  8c:	7ff00e93          	li	t4,2047
+  90:	00800193          	li	gp,8
+  94:	1fdf1e63          	bne	t5,t4,290 <fail>
+
+00000098 <test_9>:
+  98:	800000b7          	lui	ra,0x80000
+  9c:	fff08093          	addi	ra,ra,-1 # 7fffffff <begin_signature+0x7fffefff>
+  a0:	00008f13          	mv	t5,ra
+  a4:	80000eb7          	lui	t4,0x80000
+  a8:	fffe8e93          	addi	t4,t4,-1 # 7fffffff <begin_signature+0x7fffefff>
+  ac:	00900193          	li	gp,9
+  b0:	1fdf1063          	bne	t5,t4,290 <fail>
+
+000000b4 <test_10>:
+  b4:	800000b7          	lui	ra,0x80000
+  b8:	fff08093          	addi	ra,ra,-1 # 7fffffff <begin_signature+0x7fffefff>
+  bc:	7ff08f13          	addi	t5,ra,2047
+  c0:	80000eb7          	lui	t4,0x80000
+  c4:	7fee8e93          	addi	t4,t4,2046 # 800007fe <begin_signature+0x7ffff7fe>
+  c8:	00a00193          	li	gp,10
+  cc:	1ddf1263          	bne	t5,t4,290 <fail>
+
+000000d0 <test_11>:
+  d0:	800000b7          	lui	ra,0x80000
+  d4:	7ff08f13          	addi	t5,ra,2047 # 800007ff <begin_signature+0x7ffff7ff>
+  d8:	80000eb7          	lui	t4,0x80000
+  dc:	7ffe8e93          	addi	t4,t4,2047 # 800007ff <begin_signature+0x7ffff7ff>
+  e0:	00b00193          	li	gp,11
+  e4:	1bdf1663          	bne	t5,t4,290 <fail>
+
+000000e8 <test_12>:
+  e8:	800000b7          	lui	ra,0x80000
+  ec:	fff08093          	addi	ra,ra,-1 # 7fffffff <begin_signature+0x7fffefff>
+  f0:	80008f13          	addi	t5,ra,-2048
+  f4:	7ffffeb7          	lui	t4,0x7ffff
+  f8:	7ffe8e93          	addi	t4,t4,2047 # 7ffff7ff <begin_signature+0x7fffe7ff>
+  fc:	00c00193          	li	gp,12
+ 100:	19df1863          	bne	t5,t4,290 <fail>
+
+00000104 <test_13>:
+ 104:	00000093          	li	ra,0
+ 108:	fff08f13          	addi	t5,ra,-1
+ 10c:	fff00e93          	li	t4,-1
+ 110:	00d00193          	li	gp,13
+ 114:	17df1e63          	bne	t5,t4,290 <fail>
+
+00000118 <test_14>:
+ 118:	fff00093          	li	ra,-1
+ 11c:	00108f13          	addi	t5,ra,1
+ 120:	00000e93          	li	t4,0
+ 124:	00e00193          	li	gp,14
+ 128:	17df1463          	bne	t5,t4,290 <fail>
+
+0000012c <test_15>:
+ 12c:	fff00093          	li	ra,-1
+ 130:	fff08f13          	addi	t5,ra,-1
+ 134:	ffe00e93          	li	t4,-2
+ 138:	00f00193          	li	gp,15
+ 13c:	15df1a63          	bne	t5,t4,290 <fail>
+
+00000140 <test_16>:
+ 140:	800000b7          	lui	ra,0x80000
+ 144:	fff08093          	addi	ra,ra,-1 # 7fffffff <begin_signature+0x7fffefff>
+ 148:	00108f13          	addi	t5,ra,1
+ 14c:	80000eb7          	lui	t4,0x80000
+ 150:	01000193          	li	gp,16
+ 154:	13df1e63          	bne	t5,t4,290 <fail>
+
+00000158 <test_17>:
+ 158:	00d00093          	li	ra,13
+ 15c:	00b08093          	addi	ra,ra,11
+ 160:	01800e93          	li	t4,24
+ 164:	01100193          	li	gp,17
+ 168:	13d09463          	bne	ra,t4,290 <fail>
+
+0000016c <test_18>:
+ 16c:	00000213          	li	tp,0
+ 170:	00d00093          	li	ra,13
+ 174:	00b08f13          	addi	t5,ra,11
+ 178:	000f0313          	mv	t1,t5
+ 17c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 180:	00200293          	li	t0,2
+ 184:	fe5216e3          	bne	tp,t0,170 <test_18+0x4>
+ 188:	01800e93          	li	t4,24
+ 18c:	01200193          	li	gp,18
+ 190:	11d31063          	bne	t1,t4,290 <fail>
+
+00000194 <test_19>:
+ 194:	00000213          	li	tp,0
+ 198:	00d00093          	li	ra,13
+ 19c:	00a08f13          	addi	t5,ra,10
+ 1a0:	00000013          	nop
+ 1a4:	000f0313          	mv	t1,t5
+ 1a8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1ac:	00200293          	li	t0,2
+ 1b0:	fe5214e3          	bne	tp,t0,198 <test_19+0x4>
+ 1b4:	01700e93          	li	t4,23
+ 1b8:	01300193          	li	gp,19
+ 1bc:	0dd31a63          	bne	t1,t4,290 <fail>
+
+000001c0 <test_20>:
+ 1c0:	00000213          	li	tp,0
+ 1c4:	00d00093          	li	ra,13
+ 1c8:	00908f13          	addi	t5,ra,9
+ 1cc:	00000013          	nop
+ 1d0:	00000013          	nop
+ 1d4:	000f0313          	mv	t1,t5
+ 1d8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1dc:	00200293          	li	t0,2
+ 1e0:	fe5212e3          	bne	tp,t0,1c4 <test_20+0x4>
+ 1e4:	01600e93          	li	t4,22
+ 1e8:	01400193          	li	gp,20
+ 1ec:	0bd31263          	bne	t1,t4,290 <fail>
+
+000001f0 <test_21>:
+ 1f0:	00000213          	li	tp,0
+ 1f4:	00d00093          	li	ra,13
+ 1f8:	00b08f13          	addi	t5,ra,11
+ 1fc:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 200:	00200293          	li	t0,2
+ 204:	fe5218e3          	bne	tp,t0,1f4 <test_21+0x4>
+ 208:	01800e93          	li	t4,24
+ 20c:	01500193          	li	gp,21
+ 210:	09df1063          	bne	t5,t4,290 <fail>
+
+00000214 <test_22>:
+ 214:	00000213          	li	tp,0
+ 218:	00d00093          	li	ra,13
+ 21c:	00000013          	nop
+ 220:	00a08f13          	addi	t5,ra,10
+ 224:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 228:	00200293          	li	t0,2
+ 22c:	fe5216e3          	bne	tp,t0,218 <test_22+0x4>
+ 230:	01700e93          	li	t4,23
+ 234:	01600193          	li	gp,22
+ 238:	05df1c63          	bne	t5,t4,290 <fail>
+
+0000023c <test_23>:
+ 23c:	00000213          	li	tp,0
+ 240:	00d00093          	li	ra,13
+ 244:	00000013          	nop
+ 248:	00000013          	nop
+ 24c:	00908f13          	addi	t5,ra,9
+ 250:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 254:	00200293          	li	t0,2
+ 258:	fe5214e3          	bne	tp,t0,240 <test_23+0x4>
+ 25c:	01600e93          	li	t4,22
+ 260:	01700193          	li	gp,23
+ 264:	03df1663          	bne	t5,t4,290 <fail>
+
+00000268 <test_24>:
+ 268:	02000093          	li	ra,32
+ 26c:	02000e93          	li	t4,32
+ 270:	01800193          	li	gp,24
+ 274:	01d09e63          	bne	ra,t4,290 <fail>
+
+00000278 <test_25>:
+ 278:	02100093          	li	ra,33
+ 27c:	03208013          	addi	zero,ra,50
+ 280:	00000e93          	li	t4,0
+ 284:	01900193          	li	gp,25
+ 288:	01d01463          	bne	zero,t4,290 <fail>
+ 28c:	00301863          	bne	zero,gp,29c <pass>
+
+00000290 <fail>:
+ 290:	00100d13          	li	s10,1
+ 294:	00000d93          	li	s11,0
+
+00000298 <loop_fail>:
+ 298:	0000006f          	j	298 <loop_fail>
+
+0000029c <pass>:
+ 29c:	00100d13          	li	s10,1
+ 2a0:	00100d93          	li	s11,1
+
+000002a4 <loop_pass>:
+ 2a4:	0000006f          	j	2a4 <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+00000300 <tohost>:
+	...
+
+00000340 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-addi.verilog

@@ -0,0 +1,52 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 00 00 00 13 8F 00 00 
+93 0E 00 00 93 01 20 00 63 1C DF 27 93 00 10 00 
+13 8F 10 00 93 0E 20 00 93 01 30 00 63 12 DF 27 
+93 00 30 00 13 8F 70 00 93 0E A0 00 93 01 40 00 
+63 18 DF 25 93 00 00 00 13 8F 00 80 93 0E 00 80 
+93 01 50 00 63 1E DF 23 B7 00 00 80 13 8F 00 00 
+B7 0E 00 80 93 01 60 00 63 14 DF 23 B7 00 00 80 
+13 8F 00 80 B7 0E 00 80 93 8E 0E 80 93 01 70 00 
+63 18 DF 21 93 00 00 00 13 8F F0 7F 93 0E F0 7F 
+93 01 80 00 63 1E DF 1F B7 00 00 80 93 80 F0 FF 
+13 8F 00 00 B7 0E 00 80 93 8E FE FF 93 01 90 00 
+63 10 DF 1F B7 00 00 80 93 80 F0 FF 13 8F F0 7F 
+B7 0E 00 80 93 8E EE 7F 93 01 A0 00 63 12 DF 1D 
+B7 00 00 80 13 8F F0 7F B7 0E 00 80 93 8E FE 7F 
+93 01 B0 00 63 16 DF 1B B7 00 00 80 93 80 F0 FF 
+13 8F 00 80 B7 FE FF 7F 93 8E FE 7F 93 01 C0 00 
+63 18 DF 19 93 00 00 00 13 8F F0 FF 93 0E F0 FF 
+93 01 D0 00 63 1E DF 17 93 00 F0 FF 13 8F 10 00 
+93 0E 00 00 93 01 E0 00 63 14 DF 17 93 00 F0 FF 
+13 8F F0 FF 93 0E E0 FF 93 01 F0 00 63 1A DF 15 
+B7 00 00 80 93 80 F0 FF 13 8F 10 00 B7 0E 00 80 
+93 01 00 01 63 1E DF 13 93 00 D0 00 93 80 B0 00 
+93 0E 80 01 93 01 10 01 63 94 D0 13 13 02 00 00 
+93 00 D0 00 13 8F B0 00 13 03 0F 00 13 02 12 00 
+93 02 20 00 E3 16 52 FE 93 0E 80 01 93 01 20 01 
+63 10 D3 11 13 02 00 00 93 00 D0 00 13 8F A0 00 
+13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 
+E3 14 52 FE 93 0E 70 01 93 01 30 01 63 1A D3 0D 
+13 02 00 00 93 00 D0 00 13 8F 90 00 13 00 00 00 
+13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 0E 60 01 93 01 40 01 63 12 D3 0B 
+13 02 00 00 93 00 D0 00 13 8F B0 00 13 02 12 00 
+93 02 20 00 E3 18 52 FE 93 0E 80 01 93 01 50 01 
+63 10 DF 09 13 02 00 00 93 00 D0 00 13 00 00 00 
+13 8F A0 00 13 02 12 00 93 02 20 00 E3 16 52 FE 
+93 0E 70 01 93 01 60 01 63 1C DF 05 13 02 00 00 
+93 00 D0 00 13 00 00 00 13 00 00 00 13 8F 90 00 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 60 01 
+93 01 70 01 63 16 DF 03 93 00 00 02 93 0E 00 02 
+93 01 80 01 63 9E D0 01 93 00 10 02 13 80 20 03 
+93 0E 00 00 93 01 90 01 63 14 D0 01 63 18 30 00 
+13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00 
+93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00000300
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-and.dump

@@ -0,0 +1,386 @@
+
+generated/rv32ui-p-and:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	ff0100b7          	lui	ra,0xff010
+   c:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+  10:	0f0f1137          	lui	sp,0xf0f1
+  14:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+  18:	0020ff33          	and	t5,ra,sp
+  1c:	0f001eb7          	lui	t4,0xf001
+  20:	f00e8e93          	addi	t4,t4,-256 # f000f00 <begin_signature+0xeffff00>
+  24:	00200193          	li	gp,2
+  28:	49df1c63          	bne	t5,t4,4c0 <fail>
+
+0000002c <test_3>:
+  2c:	0ff010b7          	lui	ra,0xff01
+  30:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+  34:	f0f0f137          	lui	sp,0xf0f0f
+  38:	0f010113          	addi	sp,sp,240 # f0f0f0f0 <begin_signature+0xf0f0e0f0>
+  3c:	0020ff33          	and	t5,ra,sp
+  40:	00f00eb7          	lui	t4,0xf00
+  44:	0f0e8e93          	addi	t4,t4,240 # f000f0 <begin_signature+0xeff0f0>
+  48:	00300193          	li	gp,3
+  4c:	47df1a63          	bne	t5,t4,4c0 <fail>
+
+00000050 <test_4>:
+  50:	00ff00b7          	lui	ra,0xff0
+  54:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+  58:	0f0f1137          	lui	sp,0xf0f1
+  5c:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+  60:	0020ff33          	and	t5,ra,sp
+  64:	000f0eb7          	lui	t4,0xf0
+  68:	00fe8e93          	addi	t4,t4,15 # f000f <begin_signature+0xef00f>
+  6c:	00400193          	li	gp,4
+  70:	45df1863          	bne	t5,t4,4c0 <fail>
+
+00000074 <test_5>:
+  74:	f00ff0b7          	lui	ra,0xf00ff
+  78:	00f08093          	addi	ra,ra,15 # f00ff00f <begin_signature+0xf00fe00f>
+  7c:	f0f0f137          	lui	sp,0xf0f0f
+  80:	0f010113          	addi	sp,sp,240 # f0f0f0f0 <begin_signature+0xf0f0e0f0>
+  84:	0020ff33          	and	t5,ra,sp
+  88:	f000feb7          	lui	t4,0xf000f
+  8c:	00500193          	li	gp,5
+  90:	43df1863          	bne	t5,t4,4c0 <fail>
+
+00000094 <test_6>:
+  94:	ff0100b7          	lui	ra,0xff010
+  98:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+  9c:	0f0f1137          	lui	sp,0xf0f1
+  a0:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+  a4:	0020f0b3          	and	ra,ra,sp
+  a8:	0f001eb7          	lui	t4,0xf001
+  ac:	f00e8e93          	addi	t4,t4,-256 # f000f00 <begin_signature+0xeffff00>
+  b0:	00600193          	li	gp,6
+  b4:	41d09663          	bne	ra,t4,4c0 <fail>
+
+000000b8 <test_7>:
+  b8:	0ff010b7          	lui	ra,0xff01
+  bc:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+  c0:	f0f0f137          	lui	sp,0xf0f0f
+  c4:	0f010113          	addi	sp,sp,240 # f0f0f0f0 <begin_signature+0xf0f0e0f0>
+  c8:	0020f133          	and	sp,ra,sp
+  cc:	00f00eb7          	lui	t4,0xf00
+  d0:	0f0e8e93          	addi	t4,t4,240 # f000f0 <begin_signature+0xeff0f0>
+  d4:	00700193          	li	gp,7
+  d8:	3fd11463          	bne	sp,t4,4c0 <fail>
+
+000000dc <test_8>:
+  dc:	ff0100b7          	lui	ra,0xff010
+  e0:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+  e4:	0010f0b3          	and	ra,ra,ra
+  e8:	ff010eb7          	lui	t4,0xff010
+  ec:	f00e8e93          	addi	t4,t4,-256 # ff00ff00 <begin_signature+0xff00ef00>
+  f0:	00800193          	li	gp,8
+  f4:	3dd09663          	bne	ra,t4,4c0 <fail>
+
+000000f8 <test_9>:
+  f8:	00000213          	li	tp,0
+  fc:	ff0100b7          	lui	ra,0xff010
+ 100:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+ 104:	0f0f1137          	lui	sp,0xf0f1
+ 108:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 10c:	0020ff33          	and	t5,ra,sp
+ 110:	000f0313          	mv	t1,t5
+ 114:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 118:	00200293          	li	t0,2
+ 11c:	fe5210e3          	bne	tp,t0,fc <test_9+0x4>
+ 120:	0f001eb7          	lui	t4,0xf001
+ 124:	f00e8e93          	addi	t4,t4,-256 # f000f00 <begin_signature+0xeffff00>
+ 128:	00900193          	li	gp,9
+ 12c:	39d31a63          	bne	t1,t4,4c0 <fail>
+
+00000130 <test_10>:
+ 130:	00000213          	li	tp,0
+ 134:	0ff010b7          	lui	ra,0xff01
+ 138:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+ 13c:	f0f0f137          	lui	sp,0xf0f0f
+ 140:	0f010113          	addi	sp,sp,240 # f0f0f0f0 <begin_signature+0xf0f0e0f0>
+ 144:	0020ff33          	and	t5,ra,sp
+ 148:	00000013          	nop
+ 14c:	000f0313          	mv	t1,t5
+ 150:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 154:	00200293          	li	t0,2
+ 158:	fc521ee3          	bne	tp,t0,134 <test_10+0x4>
+ 15c:	00f00eb7          	lui	t4,0xf00
+ 160:	0f0e8e93          	addi	t4,t4,240 # f000f0 <begin_signature+0xeff0f0>
+ 164:	00a00193          	li	gp,10
+ 168:	35d31c63          	bne	t1,t4,4c0 <fail>
+
+0000016c <test_11>:
+ 16c:	00000213          	li	tp,0
+ 170:	00ff00b7          	lui	ra,0xff0
+ 174:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+ 178:	0f0f1137          	lui	sp,0xf0f1
+ 17c:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 180:	0020ff33          	and	t5,ra,sp
+ 184:	00000013          	nop
+ 188:	00000013          	nop
+ 18c:	000f0313          	mv	t1,t5
+ 190:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 194:	00200293          	li	t0,2
+ 198:	fc521ce3          	bne	tp,t0,170 <test_11+0x4>
+ 19c:	000f0eb7          	lui	t4,0xf0
+ 1a0:	00fe8e93          	addi	t4,t4,15 # f000f <begin_signature+0xef00f>
+ 1a4:	00b00193          	li	gp,11
+ 1a8:	31d31c63          	bne	t1,t4,4c0 <fail>
+
+000001ac <test_12>:
+ 1ac:	00000213          	li	tp,0
+ 1b0:	ff0100b7          	lui	ra,0xff010
+ 1b4:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+ 1b8:	0f0f1137          	lui	sp,0xf0f1
+ 1bc:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 1c0:	0020ff33          	and	t5,ra,sp
+ 1c4:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1c8:	00200293          	li	t0,2
+ 1cc:	fe5212e3          	bne	tp,t0,1b0 <test_12+0x4>
+ 1d0:	0f001eb7          	lui	t4,0xf001
+ 1d4:	f00e8e93          	addi	t4,t4,-256 # f000f00 <begin_signature+0xeffff00>
+ 1d8:	00c00193          	li	gp,12
+ 1dc:	2fdf1263          	bne	t5,t4,4c0 <fail>
+
+000001e0 <test_13>:
+ 1e0:	00000213          	li	tp,0
+ 1e4:	0ff010b7          	lui	ra,0xff01
+ 1e8:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+ 1ec:	f0f0f137          	lui	sp,0xf0f0f
+ 1f0:	0f010113          	addi	sp,sp,240 # f0f0f0f0 <begin_signature+0xf0f0e0f0>
+ 1f4:	00000013          	nop
+ 1f8:	0020ff33          	and	t5,ra,sp
+ 1fc:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 200:	00200293          	li	t0,2
+ 204:	fe5210e3          	bne	tp,t0,1e4 <test_13+0x4>
+ 208:	00f00eb7          	lui	t4,0xf00
+ 20c:	0f0e8e93          	addi	t4,t4,240 # f000f0 <begin_signature+0xeff0f0>
+ 210:	00d00193          	li	gp,13
+ 214:	2bdf1663          	bne	t5,t4,4c0 <fail>
+
+00000218 <test_14>:
+ 218:	00000213          	li	tp,0
+ 21c:	00ff00b7          	lui	ra,0xff0
+ 220:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+ 224:	0f0f1137          	lui	sp,0xf0f1
+ 228:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 22c:	00000013          	nop
+ 230:	00000013          	nop
+ 234:	0020ff33          	and	t5,ra,sp
+ 238:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 23c:	00200293          	li	t0,2
+ 240:	fc521ee3          	bne	tp,t0,21c <test_14+0x4>
+ 244:	000f0eb7          	lui	t4,0xf0
+ 248:	00fe8e93          	addi	t4,t4,15 # f000f <begin_signature+0xef00f>
+ 24c:	00e00193          	li	gp,14
+ 250:	27df1863          	bne	t5,t4,4c0 <fail>
+
+00000254 <test_15>:
+ 254:	00000213          	li	tp,0
+ 258:	ff0100b7          	lui	ra,0xff010
+ 25c:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+ 260:	00000013          	nop
+ 264:	0f0f1137          	lui	sp,0xf0f1
+ 268:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 26c:	0020ff33          	and	t5,ra,sp
+ 270:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 274:	00200293          	li	t0,2
+ 278:	fe5210e3          	bne	tp,t0,258 <test_15+0x4>
+ 27c:	0f001eb7          	lui	t4,0xf001
+ 280:	f00e8e93          	addi	t4,t4,-256 # f000f00 <begin_signature+0xeffff00>
+ 284:	00f00193          	li	gp,15
+ 288:	23df1c63          	bne	t5,t4,4c0 <fail>
+
+0000028c <test_16>:
+ 28c:	00000213          	li	tp,0
+ 290:	0ff010b7          	lui	ra,0xff01
+ 294:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+ 298:	00000013          	nop
+ 29c:	f0f0f137          	lui	sp,0xf0f0f
+ 2a0:	0f010113          	addi	sp,sp,240 # f0f0f0f0 <begin_signature+0xf0f0e0f0>
+ 2a4:	00000013          	nop
+ 2a8:	0020ff33          	and	t5,ra,sp
+ 2ac:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2b0:	00200293          	li	t0,2
+ 2b4:	fc521ee3          	bne	tp,t0,290 <test_16+0x4>
+ 2b8:	00f00eb7          	lui	t4,0xf00
+ 2bc:	0f0e8e93          	addi	t4,t4,240 # f000f0 <begin_signature+0xeff0f0>
+ 2c0:	01000193          	li	gp,16
+ 2c4:	1fdf1e63          	bne	t5,t4,4c0 <fail>
+
+000002c8 <test_17>:
+ 2c8:	00000213          	li	tp,0
+ 2cc:	00ff00b7          	lui	ra,0xff0
+ 2d0:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+ 2d4:	00000013          	nop
+ 2d8:	00000013          	nop
+ 2dc:	0f0f1137          	lui	sp,0xf0f1
+ 2e0:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 2e4:	0020ff33          	and	t5,ra,sp
+ 2e8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2ec:	00200293          	li	t0,2
+ 2f0:	fc521ee3          	bne	tp,t0,2cc <test_17+0x4>
+ 2f4:	000f0eb7          	lui	t4,0xf0
+ 2f8:	00fe8e93          	addi	t4,t4,15 # f000f <begin_signature+0xef00f>
+ 2fc:	01100193          	li	gp,17
+ 300:	1ddf1063          	bne	t5,t4,4c0 <fail>
+
+00000304 <test_18>:
+ 304:	00000213          	li	tp,0
+ 308:	0f0f1137          	lui	sp,0xf0f1
+ 30c:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 310:	ff0100b7          	lui	ra,0xff010
+ 314:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+ 318:	0020ff33          	and	t5,ra,sp
+ 31c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 320:	00200293          	li	t0,2
+ 324:	fe5212e3          	bne	tp,t0,308 <test_18+0x4>
+ 328:	0f001eb7          	lui	t4,0xf001
+ 32c:	f00e8e93          	addi	t4,t4,-256 # f000f00 <begin_signature+0xeffff00>
+ 330:	01200193          	li	gp,18
+ 334:	19df1663          	bne	t5,t4,4c0 <fail>
+
+00000338 <test_19>:
+ 338:	00000213          	li	tp,0
+ 33c:	f0f0f137          	lui	sp,0xf0f0f
+ 340:	0f010113          	addi	sp,sp,240 # f0f0f0f0 <begin_signature+0xf0f0e0f0>
+ 344:	0ff010b7          	lui	ra,0xff01
+ 348:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+ 34c:	00000013          	nop
+ 350:	0020ff33          	and	t5,ra,sp
+ 354:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 358:	00200293          	li	t0,2
+ 35c:	fe5210e3          	bne	tp,t0,33c <test_19+0x4>
+ 360:	00f00eb7          	lui	t4,0xf00
+ 364:	0f0e8e93          	addi	t4,t4,240 # f000f0 <begin_signature+0xeff0f0>
+ 368:	01300193          	li	gp,19
+ 36c:	15df1a63          	bne	t5,t4,4c0 <fail>
+
+00000370 <test_20>:
+ 370:	00000213          	li	tp,0
+ 374:	0f0f1137          	lui	sp,0xf0f1
+ 378:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 37c:	00ff00b7          	lui	ra,0xff0
+ 380:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+ 384:	00000013          	nop
+ 388:	00000013          	nop
+ 38c:	0020ff33          	and	t5,ra,sp
+ 390:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 394:	00200293          	li	t0,2
+ 398:	fc521ee3          	bne	tp,t0,374 <test_20+0x4>
+ 39c:	000f0eb7          	lui	t4,0xf0
+ 3a0:	00fe8e93          	addi	t4,t4,15 # f000f <begin_signature+0xef00f>
+ 3a4:	01400193          	li	gp,20
+ 3a8:	11df1c63          	bne	t5,t4,4c0 <fail>
+
+000003ac <test_21>:
+ 3ac:	00000213          	li	tp,0
+ 3b0:	0f0f1137          	lui	sp,0xf0f1
+ 3b4:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 3b8:	00000013          	nop
+ 3bc:	ff0100b7          	lui	ra,0xff010
+ 3c0:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+ 3c4:	0020ff33          	and	t5,ra,sp
+ 3c8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 3cc:	00200293          	li	t0,2
+ 3d0:	fe5210e3          	bne	tp,t0,3b0 <test_21+0x4>
+ 3d4:	0f001eb7          	lui	t4,0xf001
+ 3d8:	f00e8e93          	addi	t4,t4,-256 # f000f00 <begin_signature+0xeffff00>
+ 3dc:	01500193          	li	gp,21
+ 3e0:	0fdf1063          	bne	t5,t4,4c0 <fail>
+
+000003e4 <test_22>:
+ 3e4:	00000213          	li	tp,0
+ 3e8:	f0f0f137          	lui	sp,0xf0f0f
+ 3ec:	0f010113          	addi	sp,sp,240 # f0f0f0f0 <begin_signature+0xf0f0e0f0>
+ 3f0:	00000013          	nop
+ 3f4:	0ff010b7          	lui	ra,0xff01
+ 3f8:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+ 3fc:	00000013          	nop
+ 400:	0020ff33          	and	t5,ra,sp
+ 404:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 408:	00200293          	li	t0,2
+ 40c:	fc521ee3          	bne	tp,t0,3e8 <test_22+0x4>
+ 410:	00f00eb7          	lui	t4,0xf00
+ 414:	0f0e8e93          	addi	t4,t4,240 # f000f0 <begin_signature+0xeff0f0>
+ 418:	01600193          	li	gp,22
+ 41c:	0bdf1263          	bne	t5,t4,4c0 <fail>
+
+00000420 <test_23>:
+ 420:	00000213          	li	tp,0
+ 424:	0f0f1137          	lui	sp,0xf0f1
+ 428:	f0f10113          	addi	sp,sp,-241 # f0f0f0f <begin_signature+0xf0eff0f>
+ 42c:	00000013          	nop
+ 430:	00000013          	nop
+ 434:	00ff00b7          	lui	ra,0xff0
+ 438:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+ 43c:	0020ff33          	and	t5,ra,sp
+ 440:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 444:	00200293          	li	t0,2
+ 448:	fc521ee3          	bne	tp,t0,424 <test_23+0x4>
+ 44c:	000f0eb7          	lui	t4,0xf0
+ 450:	00fe8e93          	addi	t4,t4,15 # f000f <begin_signature+0xef00f>
+ 454:	01700193          	li	gp,23
+ 458:	07df1463          	bne	t5,t4,4c0 <fail>
+
+0000045c <test_24>:
+ 45c:	ff0100b7          	lui	ra,0xff010
+ 460:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+ 464:	00107133          	and	sp,zero,ra
+ 468:	00000e93          	li	t4,0
+ 46c:	01800193          	li	gp,24
+ 470:	05d11863          	bne	sp,t4,4c0 <fail>
+
+00000474 <test_25>:
+ 474:	00ff00b7          	lui	ra,0xff0
+ 478:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+ 47c:	0000f133          	and	sp,ra,zero
+ 480:	00000e93          	li	t4,0
+ 484:	01900193          	li	gp,25
+ 488:	03d11c63          	bne	sp,t4,4c0 <fail>
+
+0000048c <test_26>:
+ 48c:	000070b3          	and	ra,zero,zero
+ 490:	00000e93          	li	t4,0
+ 494:	01a00193          	li	gp,26
+ 498:	03d09463          	bne	ra,t4,4c0 <fail>
+
+0000049c <test_27>:
+ 49c:	111110b7          	lui	ra,0x11111
+ 4a0:	11108093          	addi	ra,ra,273 # 11111111 <begin_signature+0x11110111>
+ 4a4:	22222137          	lui	sp,0x22222
+ 4a8:	22210113          	addi	sp,sp,546 # 22222222 <begin_signature+0x22221222>
+ 4ac:	0020f033          	and	zero,ra,sp
+ 4b0:	00000e93          	li	t4,0
+ 4b4:	01b00193          	li	gp,27
+ 4b8:	01d01463          	bne	zero,t4,4c0 <fail>
+ 4bc:	00301863          	bne	zero,gp,4cc <pass>
+
+000004c0 <fail>:
+ 4c0:	00100d13          	li	s10,1
+ 4c4:	00000d93          	li	s11,0
+
+000004c8 <loop_fail>:
+ 4c8:	0000006f          	j	4c8 <loop_fail>
+
+000004cc <pass>:
+ 4cc:	00100d13          	li	s10,1
+ 4d0:	00100d93          	li	s11,1
+
+000004d4 <loop_pass>:
+ 4d4:	0000006f          	j	4d4 <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+00000540 <tohost>:
+	...
+
+00000580 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-and.verilog

@@ -0,0 +1,88 @@
+@00000000
+13 0D 00 00 93 0D 00 00 B7 00 01 FF 93 80 00 F0 
+37 11 0F 0F 13 01 F1 F0 33 FF 20 00 B7 1E 00 0F 
+93 8E 0E F0 93 01 20 00 63 1C DF 49 B7 10 F0 0F 
+93 80 00 FF 37 F1 F0 F0 13 01 01 0F 33 FF 20 00 
+B7 0E F0 00 93 8E 0E 0F 93 01 30 00 63 1A DF 47 
+B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 
+33 FF 20 00 B7 0E 0F 00 93 8E FE 00 93 01 40 00 
+63 18 DF 45 B7 F0 0F F0 93 80 F0 00 37 F1 F0 F0 
+13 01 01 0F 33 FF 20 00 B7 FE 00 F0 93 01 50 00 
+63 18 DF 43 B7 00 01 FF 93 80 00 F0 37 11 0F 0F 
+13 01 F1 F0 B3 F0 20 00 B7 1E 00 0F 93 8E 0E F0 
+93 01 60 00 63 96 D0 41 B7 10 F0 0F 93 80 00 FF 
+37 F1 F0 F0 13 01 01 0F 33 F1 20 00 B7 0E F0 00 
+93 8E 0E 0F 93 01 70 00 63 14 D1 3F B7 00 01 FF 
+93 80 00 F0 B3 F0 10 00 B7 0E 01 FF 93 8E 0E F0 
+93 01 80 00 63 96 D0 3D 13 02 00 00 B7 00 01 FF 
+93 80 00 F0 37 11 0F 0F 13 01 F1 F0 33 FF 20 00 
+13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE 
+B7 1E 00 0F 93 8E 0E F0 93 01 90 00 63 1A D3 39 
+13 02 00 00 B7 10 F0 0F 93 80 00 FF 37 F1 F0 F0 
+13 01 01 0F 33 FF 20 00 13 00 00 00 13 03 0F 00 
+13 02 12 00 93 02 20 00 E3 1E 52 FC B7 0E F0 00 
+93 8E 0E 0F 93 01 A0 00 63 1C D3 35 13 02 00 00 
+B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 
+33 FF 20 00 13 00 00 00 13 00 00 00 13 03 0F 00 
+13 02 12 00 93 02 20 00 E3 1C 52 FC B7 0E 0F 00 
+93 8E FE 00 93 01 B0 00 63 1C D3 31 13 02 00 00 
+B7 00 01 FF 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 
+33 FF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE 
+B7 1E 00 0F 93 8E 0E F0 93 01 C0 00 63 12 DF 2F 
+13 02 00 00 B7 10 F0 0F 93 80 00 FF 37 F1 F0 F0 
+13 01 01 0F 13 00 00 00 33 FF 20 00 13 02 12 00 
+93 02 20 00 E3 10 52 FE B7 0E F0 00 93 8E 0E 0F 
+93 01 D0 00 63 16 DF 2B 13 02 00 00 B7 00 FF 00 
+93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 13 00 00 00 
+13 00 00 00 33 FF 20 00 13 02 12 00 93 02 20 00 
+E3 1E 52 FC B7 0E 0F 00 93 8E FE 00 93 01 E0 00 
+63 18 DF 27 13 02 00 00 B7 00 01 FF 93 80 00 F0 
+13 00 00 00 37 11 0F 0F 13 01 F1 F0 33 FF 20 00 
+13 02 12 00 93 02 20 00 E3 10 52 FE B7 1E 00 0F 
+93 8E 0E F0 93 01 F0 00 63 1C DF 23 13 02 00 00 
+B7 10 F0 0F 93 80 00 FF 13 00 00 00 37 F1 F0 F0 
+13 01 01 0F 13 00 00 00 33 FF 20 00 13 02 12 00 
+93 02 20 00 E3 1E 52 FC B7 0E F0 00 93 8E 0E 0F 
+93 01 00 01 63 1E DF 1F 13 02 00 00 B7 00 FF 00 
+93 80 F0 0F 13 00 00 00 13 00 00 00 37 11 0F 0F 
+13 01 F1 F0 33 FF 20 00 13 02 12 00 93 02 20 00 
+E3 1E 52 FC B7 0E 0F 00 93 8E FE 00 93 01 10 01 
+63 10 DF 1D 13 02 00 00 37 11 0F 0F 13 01 F1 F0 
+B7 00 01 FF 93 80 00 F0 33 FF 20 00 13 02 12 00 
+93 02 20 00 E3 12 52 FE B7 1E 00 0F 93 8E 0E F0 
+93 01 20 01 63 16 DF 19 13 02 00 00 37 F1 F0 F0 
+13 01 01 0F B7 10 F0 0F 93 80 00 FF 13 00 00 00 
+33 FF 20 00 13 02 12 00 93 02 20 00 E3 10 52 FE 
+B7 0E F0 00 93 8E 0E 0F 93 01 30 01 63 1A DF 15 
+13 02 00 00 37 11 0F 0F 13 01 F1 F0 B7 00 FF 00 
+93 80 F0 0F 13 00 00 00 13 00 00 00 33 FF 20 00 
+13 02 12 00 93 02 20 00 E3 1E 52 FC B7 0E 0F 00 
+93 8E FE 00 93 01 40 01 63 1C DF 11 13 02 00 00 
+37 11 0F 0F 13 01 F1 F0 13 00 00 00 B7 00 01 FF 
+93 80 00 F0 33 FF 20 00 13 02 12 00 93 02 20 00 
+E3 10 52 FE B7 1E 00 0F 93 8E 0E F0 93 01 50 01 
+63 10 DF 0F 13 02 00 00 37 F1 F0 F0 13 01 01 0F 
+13 00 00 00 B7 10 F0 0F 93 80 00 FF 13 00 00 00 
+33 FF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC 
+B7 0E F0 00 93 8E 0E 0F 93 01 60 01 63 12 DF 0B 
+13 02 00 00 37 11 0F 0F 13 01 F1 F0 13 00 00 00 
+13 00 00 00 B7 00 FF 00 93 80 F0 0F 33 FF 20 00 
+13 02 12 00 93 02 20 00 E3 1E 52 FC B7 0E 0F 00 
+93 8E FE 00 93 01 70 01 63 14 DF 07 B7 00 01 FF 
+93 80 00 F0 33 71 10 00 93 0E 00 00 93 01 80 01 
+63 18 D1 05 B7 00 FF 00 93 80 F0 0F 33 F1 00 00 
+93 0E 00 00 93 01 90 01 63 1C D1 03 B3 70 00 00 
+93 0E 00 00 93 01 A0 01 63 94 D0 03 B7 10 11 11 
+93 80 10 11 37 21 22 22 13 01 21 22 33 F0 20 00 
+93 0E 00 00 93 01 B0 01 63 14 D0 01 63 18 30 00 
+13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00 
+93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00000540
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-andi.dump

@@ -0,0 +1,170 @@
+
+generated/rv32ui-p-andi:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	ff0100b7          	lui	ra,0xff010
+   c:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+  10:	f0f0ff13          	andi	t5,ra,-241
+  14:	ff010eb7          	lui	t4,0xff010
+  18:	f00e8e93          	addi	t4,t4,-256 # ff00ff00 <begin_signature+0xff00ef00>
+  1c:	00200193          	li	gp,2
+  20:	1bdf1463          	bne	t5,t4,1c8 <fail>
+
+00000024 <test_3>:
+  24:	0ff010b7          	lui	ra,0xff01
+  28:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+  2c:	0f00ff13          	andi	t5,ra,240
+  30:	0f000e93          	li	t4,240
+  34:	00300193          	li	gp,3
+  38:	19df1863          	bne	t5,t4,1c8 <fail>
+
+0000003c <test_4>:
+  3c:	00ff00b7          	lui	ra,0xff0
+  40:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+  44:	70f0ff13          	andi	t5,ra,1807
+  48:	00f00e93          	li	t4,15
+  4c:	00400193          	li	gp,4
+  50:	17df1c63          	bne	t5,t4,1c8 <fail>
+
+00000054 <test_5>:
+  54:	f00ff0b7          	lui	ra,0xf00ff
+  58:	00f08093          	addi	ra,ra,15 # f00ff00f <begin_signature+0xf00fe00f>
+  5c:	0f00ff13          	andi	t5,ra,240
+  60:	00000e93          	li	t4,0
+  64:	00500193          	li	gp,5
+  68:	17df1063          	bne	t5,t4,1c8 <fail>
+
+0000006c <test_6>:
+  6c:	ff0100b7          	lui	ra,0xff010
+  70:	f0008093          	addi	ra,ra,-256 # ff00ff00 <begin_signature+0xff00ef00>
+  74:	0f00f093          	andi	ra,ra,240
+  78:	00000e93          	li	t4,0
+  7c:	00600193          	li	gp,6
+  80:	15d09463          	bne	ra,t4,1c8 <fail>
+
+00000084 <test_7>:
+  84:	00000213          	li	tp,0
+  88:	0ff010b7          	lui	ra,0xff01
+  8c:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+  90:	70f0ff13          	andi	t5,ra,1807
+  94:	000f0313          	mv	t1,t5
+  98:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+  9c:	00200293          	li	t0,2
+  a0:	fe5214e3          	bne	tp,t0,88 <test_7+0x4>
+  a4:	70000e93          	li	t4,1792
+  a8:	00700193          	li	gp,7
+  ac:	11d31e63          	bne	t1,t4,1c8 <fail>
+
+000000b0 <test_8>:
+  b0:	00000213          	li	tp,0
+  b4:	00ff00b7          	lui	ra,0xff0
+  b8:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+  bc:	0f00ff13          	andi	t5,ra,240
+  c0:	00000013          	nop
+  c4:	000f0313          	mv	t1,t5
+  c8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+  cc:	00200293          	li	t0,2
+  d0:	fe5212e3          	bne	tp,t0,b4 <test_8+0x4>
+  d4:	0f000e93          	li	t4,240
+  d8:	00800193          	li	gp,8
+  dc:	0fd31663          	bne	t1,t4,1c8 <fail>
+
+000000e0 <test_9>:
+  e0:	00000213          	li	tp,0
+  e4:	f00ff0b7          	lui	ra,0xf00ff
+  e8:	00f08093          	addi	ra,ra,15 # f00ff00f <begin_signature+0xf00fe00f>
+  ec:	f0f0ff13          	andi	t5,ra,-241
+  f0:	00000013          	nop
+  f4:	00000013          	nop
+  f8:	000f0313          	mv	t1,t5
+  fc:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 100:	00200293          	li	t0,2
+ 104:	fe5210e3          	bne	tp,t0,e4 <test_9+0x4>
+ 108:	f00ffeb7          	lui	t4,0xf00ff
+ 10c:	00fe8e93          	addi	t4,t4,15 # f00ff00f <begin_signature+0xf00fe00f>
+ 110:	00900193          	li	gp,9
+ 114:	0bd31a63          	bne	t1,t4,1c8 <fail>
+
+00000118 <test_10>:
+ 118:	00000213          	li	tp,0
+ 11c:	0ff010b7          	lui	ra,0xff01
+ 120:	ff008093          	addi	ra,ra,-16 # ff00ff0 <begin_signature+0xfeffff0>
+ 124:	70f0ff13          	andi	t5,ra,1807
+ 128:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 12c:	00200293          	li	t0,2
+ 130:	fe5216e3          	bne	tp,t0,11c <test_10+0x4>
+ 134:	70000e93          	li	t4,1792
+ 138:	00a00193          	li	gp,10
+ 13c:	09df1663          	bne	t5,t4,1c8 <fail>
+
+00000140 <test_11>:
+ 140:	00000213          	li	tp,0
+ 144:	00ff00b7          	lui	ra,0xff0
+ 148:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+ 14c:	00000013          	nop
+ 150:	0f00ff13          	andi	t5,ra,240
+ 154:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 158:	00200293          	li	t0,2
+ 15c:	fe5214e3          	bne	tp,t0,144 <test_11+0x4>
+ 160:	0f000e93          	li	t4,240
+ 164:	00b00193          	li	gp,11
+ 168:	07df1063          	bne	t5,t4,1c8 <fail>
+
+0000016c <test_12>:
+ 16c:	00000213          	li	tp,0
+ 170:	f00ff0b7          	lui	ra,0xf00ff
+ 174:	00f08093          	addi	ra,ra,15 # f00ff00f <begin_signature+0xf00fe00f>
+ 178:	00000013          	nop
+ 17c:	00000013          	nop
+ 180:	70f0ff13          	andi	t5,ra,1807
+ 184:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 188:	00200293          	li	t0,2
+ 18c:	fe5212e3          	bne	tp,t0,170 <test_12+0x4>
+ 190:	00f00e93          	li	t4,15
+ 194:	00c00193          	li	gp,12
+ 198:	03df1863          	bne	t5,t4,1c8 <fail>
+
+0000019c <test_13>:
+ 19c:	0f007093          	andi	ra,zero,240
+ 1a0:	00000e93          	li	t4,0
+ 1a4:	00d00193          	li	gp,13
+ 1a8:	03d09063          	bne	ra,t4,1c8 <fail>
+
+000001ac <test_14>:
+ 1ac:	00ff00b7          	lui	ra,0xff0
+ 1b0:	0ff08093          	addi	ra,ra,255 # ff00ff <begin_signature+0xfef0ff>
+ 1b4:	70f0f013          	andi	zero,ra,1807
+ 1b8:	00000e93          	li	t4,0
+ 1bc:	00e00193          	li	gp,14
+ 1c0:	01d01463          	bne	zero,t4,1c8 <fail>
+ 1c4:	00301863          	bne	zero,gp,1d4 <pass>
+
+000001c8 <fail>:
+ 1c8:	00100d13          	li	s10,1
+ 1cc:	00000d93          	li	s11,0
+
+000001d0 <loop_fail>:
+ 1d0:	0000006f          	j	1d0 <loop_fail>
+
+000001d4 <pass>:
+ 1d4:	00100d13          	li	s10,1
+ 1d8:	00100d93          	li	s11,1
+
+000001dc <loop_pass>:
+ 1dc:	0000006f          	j	1dc <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+00000240 <tohost>:
+	...
+
+00000280 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-andi.verilog

@@ -0,0 +1,40 @@
+@00000000
+13 0D 00 00 93 0D 00 00 B7 00 01 FF 93 80 00 F0 
+13 FF F0 F0 B7 0E 01 FF 93 8E 0E F0 93 01 20 00 
+63 14 DF 1B B7 10 F0 0F 93 80 00 FF 13 FF 00 0F 
+93 0E 00 0F 93 01 30 00 63 18 DF 19 B7 00 FF 00 
+93 80 F0 0F 13 FF F0 70 93 0E F0 00 93 01 40 00 
+63 1C DF 17 B7 F0 0F F0 93 80 F0 00 13 FF 00 0F 
+93 0E 00 00 93 01 50 00 63 10 DF 17 B7 00 01 FF 
+93 80 00 F0 93 F0 00 0F 93 0E 00 00 93 01 60 00 
+63 94 D0 15 13 02 00 00 B7 10 F0 0F 93 80 00 FF 
+13 FF F0 70 13 03 0F 00 13 02 12 00 93 02 20 00 
+E3 14 52 FE 93 0E 00 70 93 01 70 00 63 1E D3 11 
+13 02 00 00 B7 00 FF 00 93 80 F0 0F 13 FF 00 0F 
+13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 0E 00 0F 93 01 80 00 63 16 D3 0F 
+13 02 00 00 B7 F0 0F F0 93 80 F0 00 13 FF F0 F0 
+13 00 00 00 13 00 00 00 13 03 0F 00 13 02 12 00 
+93 02 20 00 E3 10 52 FE B7 FE 0F F0 93 8E FE 00 
+93 01 90 00 63 1A D3 0B 13 02 00 00 B7 10 F0 0F 
+93 80 00 FF 13 FF F0 70 13 02 12 00 93 02 20 00 
+E3 16 52 FE 93 0E 00 70 93 01 A0 00 63 16 DF 09 
+13 02 00 00 B7 00 FF 00 93 80 F0 0F 13 00 00 00 
+13 FF 00 0F 13 02 12 00 93 02 20 00 E3 14 52 FE 
+93 0E 00 0F 93 01 B0 00 63 10 DF 07 13 02 00 00 
+B7 F0 0F F0 93 80 F0 00 13 00 00 00 13 00 00 00 
+13 FF F0 70 13 02 12 00 93 02 20 00 E3 12 52 FE 
+93 0E F0 00 93 01 C0 00 63 18 DF 03 93 70 00 0F 
+93 0E 00 00 93 01 D0 00 63 90 D0 03 B7 00 FF 00 
+93 80 F0 0F 13 F0 F0 70 93 0E 00 00 93 01 E0 00 
+63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 
+6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00000240
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-auipc.dump

@@ -0,0 +1,53 @@
+
+generated/rv32ui-p-auipc:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00002517          	auipc	a0,0x2
+   c:	71c50513          	addi	a0,a0,1820 # 2724 <begin_signature+0x1724>
+  10:	004005ef          	jal	a1,14 <test_2+0xc>
+  14:	40b50533          	sub	a0,a0,a1
+  18:	00002eb7          	lui	t4,0x2
+  1c:	710e8e93          	addi	t4,t4,1808 # 2710 <begin_signature+0x1710>
+  20:	00200193          	li	gp,2
+  24:	03d51463          	bne	a0,t4,4c <fail>
+
+00000028 <test_3>:
+  28:	ffffe517          	auipc	a0,0xffffe
+  2c:	8fc50513          	addi	a0,a0,-1796 # ffffd924 <begin_signature+0xffffc924>
+  30:	004005ef          	jal	a1,34 <test_3+0xc>
+  34:	40b50533          	sub	a0,a0,a1
+  38:	ffffeeb7          	lui	t4,0xffffe
+  3c:	8f0e8e93          	addi	t4,t4,-1808 # ffffd8f0 <begin_signature+0xffffc8f0>
+  40:	00300193          	li	gp,3
+  44:	01d51463          	bne	a0,t4,4c <fail>
+  48:	00301863          	bne	zero,gp,58 <pass>
+
+0000004c <fail>:
+  4c:	00100d13          	li	s10,1
+  50:	00000d93          	li	s11,0
+
+00000054 <loop_fail>:
+  54:	0000006f          	j	54 <loop_fail>
+
+00000058 <pass>:
+  58:	00100d13          	li	s10,1
+  5c:	00100d93          	li	s11,1
+
+00000060 <loop_pass>:
+  60:	0000006f          	j	60 <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+00000080 <tohost>:
+	...
+
+000000c0 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-auipc.verilog

@@ -0,0 +1,15 @@
+@00000000
+13 0D 00 00 93 0D 00 00 17 25 00 00 13 05 C5 71 
+EF 05 40 00 33 05 B5 40 B7 2E 00 00 93 8E 0E 71 
+93 01 20 00 63 14 D5 03 17 E5 FF FF 13 05 C5 8F 
+EF 05 40 00 33 05 B5 40 B7 EE FF FF 93 8E 0E 8F 
+93 01 30 00 63 14 D5 01 63 18 30 00 13 0D 10 00 
+93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 
+6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 
+@00000080
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-beq.dump

@@ -0,0 +1,248 @@
+
+generated/rv32ui-p-beq:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00200193          	li	gp,2
+   c:	00000093          	li	ra,0
+  10:	00000113          	li	sp,0
+  14:	00208663          	beq	ra,sp,20 <test_2+0x18>
+  18:	2a301863          	bne	zero,gp,2c8 <fail>
+  1c:	00301663          	bne	zero,gp,28 <test_3>
+  20:	fe208ee3          	beq	ra,sp,1c <test_2+0x14>
+  24:	2a301263          	bne	zero,gp,2c8 <fail>
+
+00000028 <test_3>:
+  28:	00300193          	li	gp,3
+  2c:	00100093          	li	ra,1
+  30:	00100113          	li	sp,1
+  34:	00208663          	beq	ra,sp,40 <test_3+0x18>
+  38:	28301863          	bne	zero,gp,2c8 <fail>
+  3c:	00301663          	bne	zero,gp,48 <test_4>
+  40:	fe208ee3          	beq	ra,sp,3c <test_3+0x14>
+  44:	28301263          	bne	zero,gp,2c8 <fail>
+
+00000048 <test_4>:
+  48:	00400193          	li	gp,4
+  4c:	fff00093          	li	ra,-1
+  50:	fff00113          	li	sp,-1
+  54:	00208663          	beq	ra,sp,60 <test_4+0x18>
+  58:	26301863          	bne	zero,gp,2c8 <fail>
+  5c:	00301663          	bne	zero,gp,68 <test_5>
+  60:	fe208ee3          	beq	ra,sp,5c <test_4+0x14>
+  64:	26301263          	bne	zero,gp,2c8 <fail>
+
+00000068 <test_5>:
+  68:	00500193          	li	gp,5
+  6c:	00000093          	li	ra,0
+  70:	00100113          	li	sp,1
+  74:	00208463          	beq	ra,sp,7c <test_5+0x14>
+  78:	00301463          	bne	zero,gp,80 <test_5+0x18>
+  7c:	24301663          	bne	zero,gp,2c8 <fail>
+  80:	fe208ee3          	beq	ra,sp,7c <test_5+0x14>
+
+00000084 <test_6>:
+  84:	00600193          	li	gp,6
+  88:	00100093          	li	ra,1
+  8c:	00000113          	li	sp,0
+  90:	00208463          	beq	ra,sp,98 <test_6+0x14>
+  94:	00301463          	bne	zero,gp,9c <test_6+0x18>
+  98:	22301863          	bne	zero,gp,2c8 <fail>
+  9c:	fe208ee3          	beq	ra,sp,98 <test_6+0x14>
+
+000000a0 <test_7>:
+  a0:	00700193          	li	gp,7
+  a4:	fff00093          	li	ra,-1
+  a8:	00100113          	li	sp,1
+  ac:	00208463          	beq	ra,sp,b4 <test_7+0x14>
+  b0:	00301463          	bne	zero,gp,b8 <test_7+0x18>
+  b4:	20301a63          	bne	zero,gp,2c8 <fail>
+  b8:	fe208ee3          	beq	ra,sp,b4 <test_7+0x14>
+
+000000bc <test_8>:
+  bc:	00800193          	li	gp,8
+  c0:	00100093          	li	ra,1
+  c4:	fff00113          	li	sp,-1
+  c8:	00208463          	beq	ra,sp,d0 <test_8+0x14>
+  cc:	00301463          	bne	zero,gp,d4 <test_8+0x18>
+  d0:	1e301c63          	bne	zero,gp,2c8 <fail>
+  d4:	fe208ee3          	beq	ra,sp,d0 <test_8+0x14>
+
+000000d8 <test_9>:
+  d8:	00900193          	li	gp,9
+  dc:	00000213          	li	tp,0
+  e0:	00000093          	li	ra,0
+  e4:	fff00113          	li	sp,-1
+  e8:	1e208063          	beq	ra,sp,2c8 <fail>
+  ec:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+  f0:	00200293          	li	t0,2
+  f4:	fe5216e3          	bne	tp,t0,e0 <test_9+0x8>
+
+000000f8 <test_10>:
+  f8:	00a00193          	li	gp,10
+  fc:	00000213          	li	tp,0
+ 100:	00000093          	li	ra,0
+ 104:	fff00113          	li	sp,-1
+ 108:	00000013          	nop
+ 10c:	1a208e63          	beq	ra,sp,2c8 <fail>
+ 110:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 114:	00200293          	li	t0,2
+ 118:	fe5214e3          	bne	tp,t0,100 <test_10+0x8>
+
+0000011c <test_11>:
+ 11c:	00b00193          	li	gp,11
+ 120:	00000213          	li	tp,0
+ 124:	00000093          	li	ra,0
+ 128:	fff00113          	li	sp,-1
+ 12c:	00000013          	nop
+ 130:	00000013          	nop
+ 134:	18208a63          	beq	ra,sp,2c8 <fail>
+ 138:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 13c:	00200293          	li	t0,2
+ 140:	fe5212e3          	bne	tp,t0,124 <test_11+0x8>
+
+00000144 <test_12>:
+ 144:	00c00193          	li	gp,12
+ 148:	00000213          	li	tp,0
+ 14c:	00000093          	li	ra,0
+ 150:	00000013          	nop
+ 154:	fff00113          	li	sp,-1
+ 158:	16208863          	beq	ra,sp,2c8 <fail>
+ 15c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 160:	00200293          	li	t0,2
+ 164:	fe5214e3          	bne	tp,t0,14c <test_12+0x8>
+
+00000168 <test_13>:
+ 168:	00d00193          	li	gp,13
+ 16c:	00000213          	li	tp,0
+ 170:	00000093          	li	ra,0
+ 174:	00000013          	nop
+ 178:	fff00113          	li	sp,-1
+ 17c:	00000013          	nop
+ 180:	14208463          	beq	ra,sp,2c8 <fail>
+ 184:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 188:	00200293          	li	t0,2
+ 18c:	fe5212e3          	bne	tp,t0,170 <test_13+0x8>
+
+00000190 <test_14>:
+ 190:	00e00193          	li	gp,14
+ 194:	00000213          	li	tp,0
+ 198:	00000093          	li	ra,0
+ 19c:	00000013          	nop
+ 1a0:	00000013          	nop
+ 1a4:	fff00113          	li	sp,-1
+ 1a8:	12208063          	beq	ra,sp,2c8 <fail>
+ 1ac:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1b0:	00200293          	li	t0,2
+ 1b4:	fe5212e3          	bne	tp,t0,198 <test_14+0x8>
+
+000001b8 <test_15>:
+ 1b8:	00f00193          	li	gp,15
+ 1bc:	00000213          	li	tp,0
+ 1c0:	00000093          	li	ra,0
+ 1c4:	fff00113          	li	sp,-1
+ 1c8:	10208063          	beq	ra,sp,2c8 <fail>
+ 1cc:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1d0:	00200293          	li	t0,2
+ 1d4:	fe5216e3          	bne	tp,t0,1c0 <test_15+0x8>
+
+000001d8 <test_16>:
+ 1d8:	01000193          	li	gp,16
+ 1dc:	00000213          	li	tp,0
+ 1e0:	00000093          	li	ra,0
+ 1e4:	fff00113          	li	sp,-1
+ 1e8:	00000013          	nop
+ 1ec:	0c208e63          	beq	ra,sp,2c8 <fail>
+ 1f0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1f4:	00200293          	li	t0,2
+ 1f8:	fe5214e3          	bne	tp,t0,1e0 <test_16+0x8>
+
+000001fc <test_17>:
+ 1fc:	01100193          	li	gp,17
+ 200:	00000213          	li	tp,0
+ 204:	00000093          	li	ra,0
+ 208:	fff00113          	li	sp,-1
+ 20c:	00000013          	nop
+ 210:	00000013          	nop
+ 214:	0a208a63          	beq	ra,sp,2c8 <fail>
+ 218:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 21c:	00200293          	li	t0,2
+ 220:	fe5212e3          	bne	tp,t0,204 <test_17+0x8>
+
+00000224 <test_18>:
+ 224:	01200193          	li	gp,18
+ 228:	00000213          	li	tp,0
+ 22c:	00000093          	li	ra,0
+ 230:	00000013          	nop
+ 234:	fff00113          	li	sp,-1
+ 238:	08208863          	beq	ra,sp,2c8 <fail>
+ 23c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 240:	00200293          	li	t0,2
+ 244:	fe5214e3          	bne	tp,t0,22c <test_18+0x8>
+
+00000248 <test_19>:
+ 248:	01300193          	li	gp,19
+ 24c:	00000213          	li	tp,0
+ 250:	00000093          	li	ra,0
+ 254:	00000013          	nop
+ 258:	fff00113          	li	sp,-1
+ 25c:	00000013          	nop
+ 260:	06208463          	beq	ra,sp,2c8 <fail>
+ 264:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 268:	00200293          	li	t0,2
+ 26c:	fe5212e3          	bne	tp,t0,250 <test_19+0x8>
+
+00000270 <test_20>:
+ 270:	01400193          	li	gp,20
+ 274:	00000213          	li	tp,0
+ 278:	00000093          	li	ra,0
+ 27c:	00000013          	nop
+ 280:	00000013          	nop
+ 284:	fff00113          	li	sp,-1
+ 288:	04208063          	beq	ra,sp,2c8 <fail>
+ 28c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 290:	00200293          	li	t0,2
+ 294:	fe5212e3          	bne	tp,t0,278 <test_20+0x8>
+
+00000298 <test_21>:
+ 298:	00100093          	li	ra,1
+ 29c:	00000a63          	beqz	zero,2b0 <test_21+0x18>
+ 2a0:	00108093          	addi	ra,ra,1
+ 2a4:	00108093          	addi	ra,ra,1
+ 2a8:	00108093          	addi	ra,ra,1
+ 2ac:	00108093          	addi	ra,ra,1
+ 2b0:	00108093          	addi	ra,ra,1
+ 2b4:	00108093          	addi	ra,ra,1
+ 2b8:	00300e93          	li	t4,3
+ 2bc:	01500193          	li	gp,21
+ 2c0:	01d09463          	bne	ra,t4,2c8 <fail>
+ 2c4:	00301863          	bne	zero,gp,2d4 <pass>
+
+000002c8 <fail>:
+ 2c8:	00100d13          	li	s10,1
+ 2cc:	00000d93          	li	s11,0
+
+000002d0 <loop_fail>:
+ 2d0:	0000006f          	j	2d0 <loop_fail>
+
+000002d4 <pass>:
+ 2d4:	00100d13          	li	s10,1
+ 2d8:	00100d93          	li	s11,1
+
+000002dc <loop_pass>:
+ 2dc:	0000006f          	j	2dc <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+00000340 <tohost>:
+	...
+
+00000380 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-beq.verilog

@@ -0,0 +1,56 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 
+13 01 00 00 63 86 20 00 63 18 30 2A 63 16 30 00 
+E3 8E 20 FE 63 12 30 2A 93 01 30 00 93 00 10 00 
+13 01 10 00 63 86 20 00 63 18 30 28 63 16 30 00 
+E3 8E 20 FE 63 12 30 28 93 01 40 00 93 00 F0 FF 
+13 01 F0 FF 63 86 20 00 63 18 30 26 63 16 30 00 
+E3 8E 20 FE 63 12 30 26 93 01 50 00 93 00 00 00 
+13 01 10 00 63 84 20 00 63 14 30 00 63 16 30 24 
+E3 8E 20 FE 93 01 60 00 93 00 10 00 13 01 00 00 
+63 84 20 00 63 14 30 00 63 18 30 22 E3 8E 20 FE 
+93 01 70 00 93 00 F0 FF 13 01 10 00 63 84 20 00 
+63 14 30 00 63 1A 30 20 E3 8E 20 FE 93 01 80 00 
+93 00 10 00 13 01 F0 FF 63 84 20 00 63 14 30 00 
+63 1C 30 1E E3 8E 20 FE 93 01 90 00 13 02 00 00 
+93 00 00 00 13 01 F0 FF 63 80 20 1E 13 02 12 00 
+93 02 20 00 E3 16 52 FE 93 01 A0 00 13 02 00 00 
+93 00 00 00 13 01 F0 FF 13 00 00 00 63 8E 20 1A 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 B0 00 
+13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 
+13 00 00 00 63 8A 20 18 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 C0 00 13 02 00 00 93 00 00 00 
+13 00 00 00 13 01 F0 FF 63 88 20 16 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 01 D0 00 13 02 00 00 
+93 00 00 00 13 00 00 00 13 01 F0 FF 13 00 00 00 
+63 84 20 14 13 02 12 00 93 02 20 00 E3 12 52 FE 
+93 01 E0 00 13 02 00 00 93 00 00 00 13 00 00 00 
+13 00 00 00 13 01 F0 FF 63 80 20 12 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 F0 00 13 02 00 00 
+93 00 00 00 13 01 F0 FF 63 80 20 10 13 02 12 00 
+93 02 20 00 E3 16 52 FE 93 01 00 01 13 02 00 00 
+93 00 00 00 13 01 F0 FF 13 00 00 00 63 8E 20 0C 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 10 01 
+13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 
+13 00 00 00 63 8A 20 0A 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 20 01 13 02 00 00 93 00 00 00 
+13 00 00 00 13 01 F0 FF 63 88 20 08 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 01 30 01 13 02 00 00 
+93 00 00 00 13 00 00 00 13 01 F0 FF 13 00 00 00 
+63 84 20 06 13 02 12 00 93 02 20 00 E3 12 52 FE 
+93 01 40 01 13 02 00 00 93 00 00 00 13 00 00 00 
+13 00 00 00 13 01 F0 FF 63 80 20 04 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 00 10 00 63 0A 00 00 
+93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 
+93 80 10 00 93 80 10 00 93 0E 30 00 93 01 50 01 
+63 94 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 
+6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00000340
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-bge.dump

@@ -0,0 +1,279 @@
+
+generated/rv32ui-p-bge:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00200193          	li	gp,2
+   c:	00000093          	li	ra,0
+  10:	00000113          	li	sp,0
+  14:	0020d663          	bge	ra,sp,20 <test_2+0x18>
+  18:	30301863          	bne	zero,gp,328 <fail>
+  1c:	00301663          	bne	zero,gp,28 <test_3>
+  20:	fe20dee3          	bge	ra,sp,1c <test_2+0x14>
+  24:	30301263          	bne	zero,gp,328 <fail>
+
+00000028 <test_3>:
+  28:	00300193          	li	gp,3
+  2c:	00100093          	li	ra,1
+  30:	00100113          	li	sp,1
+  34:	0020d663          	bge	ra,sp,40 <test_3+0x18>
+  38:	2e301863          	bne	zero,gp,328 <fail>
+  3c:	00301663          	bne	zero,gp,48 <test_4>
+  40:	fe20dee3          	bge	ra,sp,3c <test_3+0x14>
+  44:	2e301263          	bne	zero,gp,328 <fail>
+
+00000048 <test_4>:
+  48:	00400193          	li	gp,4
+  4c:	fff00093          	li	ra,-1
+  50:	fff00113          	li	sp,-1
+  54:	0020d663          	bge	ra,sp,60 <test_4+0x18>
+  58:	2c301863          	bne	zero,gp,328 <fail>
+  5c:	00301663          	bne	zero,gp,68 <test_5>
+  60:	fe20dee3          	bge	ra,sp,5c <test_4+0x14>
+  64:	2c301263          	bne	zero,gp,328 <fail>
+
+00000068 <test_5>:
+  68:	00500193          	li	gp,5
+  6c:	00100093          	li	ra,1
+  70:	00000113          	li	sp,0
+  74:	0020d663          	bge	ra,sp,80 <test_5+0x18>
+  78:	2a301863          	bne	zero,gp,328 <fail>
+  7c:	00301663          	bne	zero,gp,88 <test_6>
+  80:	fe20dee3          	bge	ra,sp,7c <test_5+0x14>
+  84:	2a301263          	bne	zero,gp,328 <fail>
+
+00000088 <test_6>:
+  88:	00600193          	li	gp,6
+  8c:	00100093          	li	ra,1
+  90:	fff00113          	li	sp,-1
+  94:	0020d663          	bge	ra,sp,a0 <test_6+0x18>
+  98:	28301863          	bne	zero,gp,328 <fail>
+  9c:	00301663          	bne	zero,gp,a8 <test_7>
+  a0:	fe20dee3          	bge	ra,sp,9c <test_6+0x14>
+  a4:	28301263          	bne	zero,gp,328 <fail>
+
+000000a8 <test_7>:
+  a8:	00700193          	li	gp,7
+  ac:	fff00093          	li	ra,-1
+  b0:	ffe00113          	li	sp,-2
+  b4:	0020d663          	bge	ra,sp,c0 <test_7+0x18>
+  b8:	26301863          	bne	zero,gp,328 <fail>
+  bc:	00301663          	bne	zero,gp,c8 <test_8>
+  c0:	fe20dee3          	bge	ra,sp,bc <test_7+0x14>
+  c4:	26301263          	bne	zero,gp,328 <fail>
+
+000000c8 <test_8>:
+  c8:	00800193          	li	gp,8
+  cc:	00000093          	li	ra,0
+  d0:	00100113          	li	sp,1
+  d4:	0020d463          	bge	ra,sp,dc <test_8+0x14>
+  d8:	00301463          	bne	zero,gp,e0 <test_8+0x18>
+  dc:	24301663          	bne	zero,gp,328 <fail>
+  e0:	fe20dee3          	bge	ra,sp,dc <test_8+0x14>
+
+000000e4 <test_9>:
+  e4:	00900193          	li	gp,9
+  e8:	fff00093          	li	ra,-1
+  ec:	00100113          	li	sp,1
+  f0:	0020d463          	bge	ra,sp,f8 <test_9+0x14>
+  f4:	00301463          	bne	zero,gp,fc <test_9+0x18>
+  f8:	22301863          	bne	zero,gp,328 <fail>
+  fc:	fe20dee3          	bge	ra,sp,f8 <test_9+0x14>
+
+00000100 <test_10>:
+ 100:	00a00193          	li	gp,10
+ 104:	ffe00093          	li	ra,-2
+ 108:	fff00113          	li	sp,-1
+ 10c:	0020d463          	bge	ra,sp,114 <test_10+0x14>
+ 110:	00301463          	bne	zero,gp,118 <test_10+0x18>
+ 114:	20301a63          	bne	zero,gp,328 <fail>
+ 118:	fe20dee3          	bge	ra,sp,114 <test_10+0x14>
+
+0000011c <test_11>:
+ 11c:	00b00193          	li	gp,11
+ 120:	ffe00093          	li	ra,-2
+ 124:	00100113          	li	sp,1
+ 128:	0020d463          	bge	ra,sp,130 <test_11+0x14>
+ 12c:	00301463          	bne	zero,gp,134 <test_11+0x18>
+ 130:	1e301c63          	bne	zero,gp,328 <fail>
+ 134:	fe20dee3          	bge	ra,sp,130 <test_11+0x14>
+
+00000138 <test_12>:
+ 138:	00c00193          	li	gp,12
+ 13c:	00000213          	li	tp,0
+ 140:	fff00093          	li	ra,-1
+ 144:	00000113          	li	sp,0
+ 148:	1e20d063          	bge	ra,sp,328 <fail>
+ 14c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 150:	00200293          	li	t0,2
+ 154:	fe5216e3          	bne	tp,t0,140 <test_12+0x8>
+
+00000158 <test_13>:
+ 158:	00d00193          	li	gp,13
+ 15c:	00000213          	li	tp,0
+ 160:	fff00093          	li	ra,-1
+ 164:	00000113          	li	sp,0
+ 168:	00000013          	nop
+ 16c:	1a20de63          	bge	ra,sp,328 <fail>
+ 170:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 174:	00200293          	li	t0,2
+ 178:	fe5214e3          	bne	tp,t0,160 <test_13+0x8>
+
+0000017c <test_14>:
+ 17c:	00e00193          	li	gp,14
+ 180:	00000213          	li	tp,0
+ 184:	fff00093          	li	ra,-1
+ 188:	00000113          	li	sp,0
+ 18c:	00000013          	nop
+ 190:	00000013          	nop
+ 194:	1820da63          	bge	ra,sp,328 <fail>
+ 198:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 19c:	00200293          	li	t0,2
+ 1a0:	fe5212e3          	bne	tp,t0,184 <test_14+0x8>
+
+000001a4 <test_15>:
+ 1a4:	00f00193          	li	gp,15
+ 1a8:	00000213          	li	tp,0
+ 1ac:	fff00093          	li	ra,-1
+ 1b0:	00000013          	nop
+ 1b4:	00000113          	li	sp,0
+ 1b8:	1620d863          	bge	ra,sp,328 <fail>
+ 1bc:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1c0:	00200293          	li	t0,2
+ 1c4:	fe5214e3          	bne	tp,t0,1ac <test_15+0x8>
+
+000001c8 <test_16>:
+ 1c8:	01000193          	li	gp,16
+ 1cc:	00000213          	li	tp,0
+ 1d0:	fff00093          	li	ra,-1
+ 1d4:	00000013          	nop
+ 1d8:	00000113          	li	sp,0
+ 1dc:	00000013          	nop
+ 1e0:	1420d463          	bge	ra,sp,328 <fail>
+ 1e4:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1e8:	00200293          	li	t0,2
+ 1ec:	fe5212e3          	bne	tp,t0,1d0 <test_16+0x8>
+
+000001f0 <test_17>:
+ 1f0:	01100193          	li	gp,17
+ 1f4:	00000213          	li	tp,0
+ 1f8:	fff00093          	li	ra,-1
+ 1fc:	00000013          	nop
+ 200:	00000013          	nop
+ 204:	00000113          	li	sp,0
+ 208:	1220d063          	bge	ra,sp,328 <fail>
+ 20c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 210:	00200293          	li	t0,2
+ 214:	fe5212e3          	bne	tp,t0,1f8 <test_17+0x8>
+
+00000218 <test_18>:
+ 218:	01200193          	li	gp,18
+ 21c:	00000213          	li	tp,0
+ 220:	fff00093          	li	ra,-1
+ 224:	00000113          	li	sp,0
+ 228:	1020d063          	bge	ra,sp,328 <fail>
+ 22c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 230:	00200293          	li	t0,2
+ 234:	fe5216e3          	bne	tp,t0,220 <test_18+0x8>
+
+00000238 <test_19>:
+ 238:	01300193          	li	gp,19
+ 23c:	00000213          	li	tp,0
+ 240:	fff00093          	li	ra,-1
+ 244:	00000113          	li	sp,0
+ 248:	00000013          	nop
+ 24c:	0c20de63          	bge	ra,sp,328 <fail>
+ 250:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 254:	00200293          	li	t0,2
+ 258:	fe5214e3          	bne	tp,t0,240 <test_19+0x8>
+
+0000025c <test_20>:
+ 25c:	01400193          	li	gp,20
+ 260:	00000213          	li	tp,0
+ 264:	fff00093          	li	ra,-1
+ 268:	00000113          	li	sp,0
+ 26c:	00000013          	nop
+ 270:	00000013          	nop
+ 274:	0a20da63          	bge	ra,sp,328 <fail>
+ 278:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 27c:	00200293          	li	t0,2
+ 280:	fe5212e3          	bne	tp,t0,264 <test_20+0x8>
+
+00000284 <test_21>:
+ 284:	01500193          	li	gp,21
+ 288:	00000213          	li	tp,0
+ 28c:	fff00093          	li	ra,-1
+ 290:	00000013          	nop
+ 294:	00000113          	li	sp,0
+ 298:	0820d863          	bge	ra,sp,328 <fail>
+ 29c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2a0:	00200293          	li	t0,2
+ 2a4:	fe5214e3          	bne	tp,t0,28c <test_21+0x8>
+
+000002a8 <test_22>:
+ 2a8:	01600193          	li	gp,22
+ 2ac:	00000213          	li	tp,0
+ 2b0:	fff00093          	li	ra,-1
+ 2b4:	00000013          	nop
+ 2b8:	00000113          	li	sp,0
+ 2bc:	00000013          	nop
+ 2c0:	0620d463          	bge	ra,sp,328 <fail>
+ 2c4:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2c8:	00200293          	li	t0,2
+ 2cc:	fe5212e3          	bne	tp,t0,2b0 <test_22+0x8>
+
+000002d0 <test_23>:
+ 2d0:	01700193          	li	gp,23
+ 2d4:	00000213          	li	tp,0
+ 2d8:	fff00093          	li	ra,-1
+ 2dc:	00000013          	nop
+ 2e0:	00000013          	nop
+ 2e4:	00000113          	li	sp,0
+ 2e8:	0420d063          	bge	ra,sp,328 <fail>
+ 2ec:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2f0:	00200293          	li	t0,2
+ 2f4:	fe5212e3          	bne	tp,t0,2d8 <test_23+0x8>
+
+000002f8 <test_24>:
+ 2f8:	00100093          	li	ra,1
+ 2fc:	0000da63          	bgez	ra,310 <test_24+0x18>
+ 300:	00108093          	addi	ra,ra,1
+ 304:	00108093          	addi	ra,ra,1
+ 308:	00108093          	addi	ra,ra,1
+ 30c:	00108093          	addi	ra,ra,1
+ 310:	00108093          	addi	ra,ra,1
+ 314:	00108093          	addi	ra,ra,1
+ 318:	00300e93          	li	t4,3
+ 31c:	01800193          	li	gp,24
+ 320:	01d09463          	bne	ra,t4,328 <fail>
+ 324:	00301863          	bne	zero,gp,334 <pass>
+
+00000328 <fail>:
+ 328:	00100d13          	li	s10,1
+ 32c:	00000d93          	li	s11,0
+
+00000330 <loop_fail>:
+ 330:	0000006f          	j	330 <loop_fail>
+
+00000334 <pass>:
+ 334:	00100d13          	li	s10,1
+ 338:	00100d93          	li	s11,1
+
+0000033c <loop_pass>:
+ 33c:	0000006f          	j	33c <loop_pass>
+ 340:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00000380 <tohost>:
+	...
+
+000003c0 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-bge.verilog

@@ -0,0 +1,60 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 
+13 01 00 00 63 D6 20 00 63 18 30 30 63 16 30 00 
+E3 DE 20 FE 63 12 30 30 93 01 30 00 93 00 10 00 
+13 01 10 00 63 D6 20 00 63 18 30 2E 63 16 30 00 
+E3 DE 20 FE 63 12 30 2E 93 01 40 00 93 00 F0 FF 
+13 01 F0 FF 63 D6 20 00 63 18 30 2C 63 16 30 00 
+E3 DE 20 FE 63 12 30 2C 93 01 50 00 93 00 10 00 
+13 01 00 00 63 D6 20 00 63 18 30 2A 63 16 30 00 
+E3 DE 20 FE 63 12 30 2A 93 01 60 00 93 00 10 00 
+13 01 F0 FF 63 D6 20 00 63 18 30 28 63 16 30 00 
+E3 DE 20 FE 63 12 30 28 93 01 70 00 93 00 F0 FF 
+13 01 E0 FF 63 D6 20 00 63 18 30 26 63 16 30 00 
+E3 DE 20 FE 63 12 30 26 93 01 80 00 93 00 00 00 
+13 01 10 00 63 D4 20 00 63 14 30 00 63 16 30 24 
+E3 DE 20 FE 93 01 90 00 93 00 F0 FF 13 01 10 00 
+63 D4 20 00 63 14 30 00 63 18 30 22 E3 DE 20 FE 
+93 01 A0 00 93 00 E0 FF 13 01 F0 FF 63 D4 20 00 
+63 14 30 00 63 1A 30 20 E3 DE 20 FE 93 01 B0 00 
+93 00 E0 FF 13 01 10 00 63 D4 20 00 63 14 30 00 
+63 1C 30 1E E3 DE 20 FE 93 01 C0 00 13 02 00 00 
+93 00 F0 FF 13 01 00 00 63 D0 20 1E 13 02 12 00 
+93 02 20 00 E3 16 52 FE 93 01 D0 00 13 02 00 00 
+93 00 F0 FF 13 01 00 00 13 00 00 00 63 DE 20 1A 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 E0 00 
+13 02 00 00 93 00 F0 FF 13 01 00 00 13 00 00 00 
+13 00 00 00 63 DA 20 18 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 F0 00 13 02 00 00 93 00 F0 FF 
+13 00 00 00 13 01 00 00 63 D8 20 16 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 01 00 01 13 02 00 00 
+93 00 F0 FF 13 00 00 00 13 01 00 00 13 00 00 00 
+63 D4 20 14 13 02 12 00 93 02 20 00 E3 12 52 FE 
+93 01 10 01 13 02 00 00 93 00 F0 FF 13 00 00 00 
+13 00 00 00 13 01 00 00 63 D0 20 12 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 20 01 13 02 00 00 
+93 00 F0 FF 13 01 00 00 63 D0 20 10 13 02 12 00 
+93 02 20 00 E3 16 52 FE 93 01 30 01 13 02 00 00 
+93 00 F0 FF 13 01 00 00 13 00 00 00 63 DE 20 0C 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 40 01 
+13 02 00 00 93 00 F0 FF 13 01 00 00 13 00 00 00 
+13 00 00 00 63 DA 20 0A 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 50 01 13 02 00 00 93 00 F0 FF 
+13 00 00 00 13 01 00 00 63 D8 20 08 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 01 60 01 13 02 00 00 
+93 00 F0 FF 13 00 00 00 13 01 00 00 13 00 00 00 
+63 D4 20 06 13 02 12 00 93 02 20 00 E3 12 52 FE 
+93 01 70 01 13 02 00 00 93 00 F0 FF 13 00 00 00 
+13 00 00 00 13 01 00 00 63 D0 20 04 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 00 10 00 63 DA 00 00 
+93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 
+93 80 10 00 93 80 10 00 93 0E 30 00 93 01 80 01 
+63 94 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 
+6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 
+00 00 00 00 
+@00000380
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-bgeu.dump

@@ -0,0 +1,291 @@
+
+generated/rv32ui-p-bgeu:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00200193          	li	gp,2
+   c:	00000093          	li	ra,0
+  10:	00000113          	li	sp,0
+  14:	0020f663          	bgeu	ra,sp,20 <test_2+0x18>
+  18:	34301263          	bne	zero,gp,35c <fail>
+  1c:	00301663          	bne	zero,gp,28 <test_3>
+  20:	fe20fee3          	bgeu	ra,sp,1c <test_2+0x14>
+  24:	32301c63          	bne	zero,gp,35c <fail>
+
+00000028 <test_3>:
+  28:	00300193          	li	gp,3
+  2c:	00100093          	li	ra,1
+  30:	00100113          	li	sp,1
+  34:	0020f663          	bgeu	ra,sp,40 <test_3+0x18>
+  38:	32301263          	bne	zero,gp,35c <fail>
+  3c:	00301663          	bne	zero,gp,48 <test_4>
+  40:	fe20fee3          	bgeu	ra,sp,3c <test_3+0x14>
+  44:	30301c63          	bne	zero,gp,35c <fail>
+
+00000048 <test_4>:
+  48:	00400193          	li	gp,4
+  4c:	fff00093          	li	ra,-1
+  50:	fff00113          	li	sp,-1
+  54:	0020f663          	bgeu	ra,sp,60 <test_4+0x18>
+  58:	30301263          	bne	zero,gp,35c <fail>
+  5c:	00301663          	bne	zero,gp,68 <test_5>
+  60:	fe20fee3          	bgeu	ra,sp,5c <test_4+0x14>
+  64:	2e301c63          	bne	zero,gp,35c <fail>
+
+00000068 <test_5>:
+  68:	00500193          	li	gp,5
+  6c:	00100093          	li	ra,1
+  70:	00000113          	li	sp,0
+  74:	0020f663          	bgeu	ra,sp,80 <test_5+0x18>
+  78:	2e301263          	bne	zero,gp,35c <fail>
+  7c:	00301663          	bne	zero,gp,88 <test_6>
+  80:	fe20fee3          	bgeu	ra,sp,7c <test_5+0x14>
+  84:	2c301c63          	bne	zero,gp,35c <fail>
+
+00000088 <test_6>:
+  88:	00600193          	li	gp,6
+  8c:	fff00093          	li	ra,-1
+  90:	ffe00113          	li	sp,-2
+  94:	0020f663          	bgeu	ra,sp,a0 <test_6+0x18>
+  98:	2c301263          	bne	zero,gp,35c <fail>
+  9c:	00301663          	bne	zero,gp,a8 <test_7>
+  a0:	fe20fee3          	bgeu	ra,sp,9c <test_6+0x14>
+  a4:	2a301c63          	bne	zero,gp,35c <fail>
+
+000000a8 <test_7>:
+  a8:	00700193          	li	gp,7
+  ac:	fff00093          	li	ra,-1
+  b0:	00000113          	li	sp,0
+  b4:	0020f663          	bgeu	ra,sp,c0 <test_7+0x18>
+  b8:	2a301263          	bne	zero,gp,35c <fail>
+  bc:	00301663          	bne	zero,gp,c8 <test_8>
+  c0:	fe20fee3          	bgeu	ra,sp,bc <test_7+0x14>
+  c4:	28301c63          	bne	zero,gp,35c <fail>
+
+000000c8 <test_8>:
+  c8:	00800193          	li	gp,8
+  cc:	00000093          	li	ra,0
+  d0:	00100113          	li	sp,1
+  d4:	0020f463          	bgeu	ra,sp,dc <test_8+0x14>
+  d8:	00301463          	bne	zero,gp,e0 <test_8+0x18>
+  dc:	28301063          	bne	zero,gp,35c <fail>
+  e0:	fe20fee3          	bgeu	ra,sp,dc <test_8+0x14>
+
+000000e4 <test_9>:
+  e4:	00900193          	li	gp,9
+  e8:	ffe00093          	li	ra,-2
+  ec:	fff00113          	li	sp,-1
+  f0:	0020f463          	bgeu	ra,sp,f8 <test_9+0x14>
+  f4:	00301463          	bne	zero,gp,fc <test_9+0x18>
+  f8:	26301263          	bne	zero,gp,35c <fail>
+  fc:	fe20fee3          	bgeu	ra,sp,f8 <test_9+0x14>
+
+00000100 <test_10>:
+ 100:	00a00193          	li	gp,10
+ 104:	00000093          	li	ra,0
+ 108:	fff00113          	li	sp,-1
+ 10c:	0020f463          	bgeu	ra,sp,114 <test_10+0x14>
+ 110:	00301463          	bne	zero,gp,118 <test_10+0x18>
+ 114:	24301463          	bne	zero,gp,35c <fail>
+ 118:	fe20fee3          	bgeu	ra,sp,114 <test_10+0x14>
+
+0000011c <test_11>:
+ 11c:	00b00193          	li	gp,11
+ 120:	800000b7          	lui	ra,0x80000
+ 124:	fff08093          	addi	ra,ra,-1 # 7fffffff <begin_signature+0x7fffefff>
+ 128:	80000137          	lui	sp,0x80000
+ 12c:	0020f463          	bgeu	ra,sp,134 <test_11+0x18>
+ 130:	00301463          	bne	zero,gp,138 <test_11+0x1c>
+ 134:	22301463          	bne	zero,gp,35c <fail>
+ 138:	fe20fee3          	bgeu	ra,sp,134 <test_11+0x18>
+
+0000013c <test_12>:
+ 13c:	00c00193          	li	gp,12
+ 140:	00000213          	li	tp,0
+ 144:	f00000b7          	lui	ra,0xf0000
+ 148:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 14c:	f0000137          	lui	sp,0xf0000
+ 150:	2020f663          	bgeu	ra,sp,35c <fail>
+ 154:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 158:	00200293          	li	t0,2
+ 15c:	fe5214e3          	bne	tp,t0,144 <test_12+0x8>
+
+00000160 <test_13>:
+ 160:	00d00193          	li	gp,13
+ 164:	00000213          	li	tp,0
+ 168:	f00000b7          	lui	ra,0xf0000
+ 16c:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 170:	f0000137          	lui	sp,0xf0000
+ 174:	00000013          	nop
+ 178:	1e20f263          	bgeu	ra,sp,35c <fail>
+ 17c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 180:	00200293          	li	t0,2
+ 184:	fe5212e3          	bne	tp,t0,168 <test_13+0x8>
+
+00000188 <test_14>:
+ 188:	00e00193          	li	gp,14
+ 18c:	00000213          	li	tp,0
+ 190:	f00000b7          	lui	ra,0xf0000
+ 194:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 198:	f0000137          	lui	sp,0xf0000
+ 19c:	00000013          	nop
+ 1a0:	00000013          	nop
+ 1a4:	1a20fc63          	bgeu	ra,sp,35c <fail>
+ 1a8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1ac:	00200293          	li	t0,2
+ 1b0:	fe5210e3          	bne	tp,t0,190 <test_14+0x8>
+
+000001b4 <test_15>:
+ 1b4:	00f00193          	li	gp,15
+ 1b8:	00000213          	li	tp,0
+ 1bc:	f00000b7          	lui	ra,0xf0000
+ 1c0:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 1c4:	00000013          	nop
+ 1c8:	f0000137          	lui	sp,0xf0000
+ 1cc:	1820f863          	bgeu	ra,sp,35c <fail>
+ 1d0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1d4:	00200293          	li	t0,2
+ 1d8:	fe5212e3          	bne	tp,t0,1bc <test_15+0x8>
+
+000001dc <test_16>:
+ 1dc:	01000193          	li	gp,16
+ 1e0:	00000213          	li	tp,0
+ 1e4:	f00000b7          	lui	ra,0xf0000
+ 1e8:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 1ec:	00000013          	nop
+ 1f0:	f0000137          	lui	sp,0xf0000
+ 1f4:	00000013          	nop
+ 1f8:	1620f263          	bgeu	ra,sp,35c <fail>
+ 1fc:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 200:	00200293          	li	t0,2
+ 204:	fe5210e3          	bne	tp,t0,1e4 <test_16+0x8>
+
+00000208 <test_17>:
+ 208:	01100193          	li	gp,17
+ 20c:	00000213          	li	tp,0
+ 210:	f00000b7          	lui	ra,0xf0000
+ 214:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 218:	00000013          	nop
+ 21c:	00000013          	nop
+ 220:	f0000137          	lui	sp,0xf0000
+ 224:	1220fc63          	bgeu	ra,sp,35c <fail>
+ 228:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 22c:	00200293          	li	t0,2
+ 230:	fe5210e3          	bne	tp,t0,210 <test_17+0x8>
+
+00000234 <test_18>:
+ 234:	01200193          	li	gp,18
+ 238:	00000213          	li	tp,0
+ 23c:	f00000b7          	lui	ra,0xf0000
+ 240:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 244:	f0000137          	lui	sp,0xf0000
+ 248:	1020fa63          	bgeu	ra,sp,35c <fail>
+ 24c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 250:	00200293          	li	t0,2
+ 254:	fe5214e3          	bne	tp,t0,23c <test_18+0x8>
+
+00000258 <test_19>:
+ 258:	01300193          	li	gp,19
+ 25c:	00000213          	li	tp,0
+ 260:	f00000b7          	lui	ra,0xf0000
+ 264:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 268:	f0000137          	lui	sp,0xf0000
+ 26c:	00000013          	nop
+ 270:	0e20f663          	bgeu	ra,sp,35c <fail>
+ 274:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 278:	00200293          	li	t0,2
+ 27c:	fe5212e3          	bne	tp,t0,260 <test_19+0x8>
+
+00000280 <test_20>:
+ 280:	01400193          	li	gp,20
+ 284:	00000213          	li	tp,0
+ 288:	f00000b7          	lui	ra,0xf0000
+ 28c:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 290:	f0000137          	lui	sp,0xf0000
+ 294:	00000013          	nop
+ 298:	00000013          	nop
+ 29c:	0c20f063          	bgeu	ra,sp,35c <fail>
+ 2a0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2a4:	00200293          	li	t0,2
+ 2a8:	fe5210e3          	bne	tp,t0,288 <test_20+0x8>
+
+000002ac <test_21>:
+ 2ac:	01500193          	li	gp,21
+ 2b0:	00000213          	li	tp,0
+ 2b4:	f00000b7          	lui	ra,0xf0000
+ 2b8:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 2bc:	00000013          	nop
+ 2c0:	f0000137          	lui	sp,0xf0000
+ 2c4:	0820fc63          	bgeu	ra,sp,35c <fail>
+ 2c8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2cc:	00200293          	li	t0,2
+ 2d0:	fe5212e3          	bne	tp,t0,2b4 <test_21+0x8>
+
+000002d4 <test_22>:
+ 2d4:	01600193          	li	gp,22
+ 2d8:	00000213          	li	tp,0
+ 2dc:	f00000b7          	lui	ra,0xf0000
+ 2e0:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 2e4:	00000013          	nop
+ 2e8:	f0000137          	lui	sp,0xf0000
+ 2ec:	00000013          	nop
+ 2f0:	0620f663          	bgeu	ra,sp,35c <fail>
+ 2f4:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2f8:	00200293          	li	t0,2
+ 2fc:	fe5210e3          	bne	tp,t0,2dc <test_22+0x8>
+
+00000300 <test_23>:
+ 300:	01700193          	li	gp,23
+ 304:	00000213          	li	tp,0
+ 308:	f00000b7          	lui	ra,0xf0000
+ 30c:	fff08093          	addi	ra,ra,-1 # efffffff <begin_signature+0xefffefff>
+ 310:	00000013          	nop
+ 314:	00000013          	nop
+ 318:	f0000137          	lui	sp,0xf0000
+ 31c:	0420f063          	bgeu	ra,sp,35c <fail>
+ 320:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 324:	00200293          	li	t0,2
+ 328:	fe5210e3          	bne	tp,t0,308 <test_23+0x8>
+
+0000032c <test_24>:
+ 32c:	00100093          	li	ra,1
+ 330:	0000fa63          	bgeu	ra,zero,344 <test_24+0x18>
+ 334:	00108093          	addi	ra,ra,1
+ 338:	00108093          	addi	ra,ra,1
+ 33c:	00108093          	addi	ra,ra,1
+ 340:	00108093          	addi	ra,ra,1
+ 344:	00108093          	addi	ra,ra,1
+ 348:	00108093          	addi	ra,ra,1
+ 34c:	00300e93          	li	t4,3
+ 350:	01800193          	li	gp,24
+ 354:	01d09463          	bne	ra,t4,35c <fail>
+ 358:	00301863          	bne	zero,gp,368 <pass>
+
+0000035c <fail>:
+ 35c:	00100d13          	li	s10,1
+ 360:	00000d93          	li	s11,0
+
+00000364 <loop_fail>:
+ 364:	0000006f          	j	364 <loop_fail>
+
+00000368 <pass>:
+ 368:	00100d13          	li	s10,1
+ 36c:	00100d93          	li	s11,1
+
+00000370 <loop_pass>:
+ 370:	0000006f          	j	370 <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+000003c0 <tohost>:
+	...
+
+00000400 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-bgeu.verilog

@@ -0,0 +1,64 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 
+13 01 00 00 63 F6 20 00 63 12 30 34 63 16 30 00 
+E3 FE 20 FE 63 1C 30 32 93 01 30 00 93 00 10 00 
+13 01 10 00 63 F6 20 00 63 12 30 32 63 16 30 00 
+E3 FE 20 FE 63 1C 30 30 93 01 40 00 93 00 F0 FF 
+13 01 F0 FF 63 F6 20 00 63 12 30 30 63 16 30 00 
+E3 FE 20 FE 63 1C 30 2E 93 01 50 00 93 00 10 00 
+13 01 00 00 63 F6 20 00 63 12 30 2E 63 16 30 00 
+E3 FE 20 FE 63 1C 30 2C 93 01 60 00 93 00 F0 FF 
+13 01 E0 FF 63 F6 20 00 63 12 30 2C 63 16 30 00 
+E3 FE 20 FE 63 1C 30 2A 93 01 70 00 93 00 F0 FF 
+13 01 00 00 63 F6 20 00 63 12 30 2A 63 16 30 00 
+E3 FE 20 FE 63 1C 30 28 93 01 80 00 93 00 00 00 
+13 01 10 00 63 F4 20 00 63 14 30 00 63 10 30 28 
+E3 FE 20 FE 93 01 90 00 93 00 E0 FF 13 01 F0 FF 
+63 F4 20 00 63 14 30 00 63 12 30 26 E3 FE 20 FE 
+93 01 A0 00 93 00 00 00 13 01 F0 FF 63 F4 20 00 
+63 14 30 00 63 14 30 24 E3 FE 20 FE 93 01 B0 00 
+B7 00 00 80 93 80 F0 FF 37 01 00 80 63 F4 20 00 
+63 14 30 00 63 14 30 22 E3 FE 20 FE 93 01 C0 00 
+13 02 00 00 B7 00 00 F0 93 80 F0 FF 37 01 00 F0 
+63 F6 20 20 13 02 12 00 93 02 20 00 E3 14 52 FE 
+93 01 D0 00 13 02 00 00 B7 00 00 F0 93 80 F0 FF 
+37 01 00 F0 13 00 00 00 63 F2 20 1E 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 E0 00 13 02 00 00 
+B7 00 00 F0 93 80 F0 FF 37 01 00 F0 13 00 00 00 
+13 00 00 00 63 FC 20 1A 13 02 12 00 93 02 20 00 
+E3 10 52 FE 93 01 F0 00 13 02 00 00 B7 00 00 F0 
+93 80 F0 FF 13 00 00 00 37 01 00 F0 63 F8 20 18 
+13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 00 01 
+13 02 00 00 B7 00 00 F0 93 80 F0 FF 13 00 00 00 
+37 01 00 F0 13 00 00 00 63 F2 20 16 13 02 12 00 
+93 02 20 00 E3 10 52 FE 93 01 10 01 13 02 00 00 
+B7 00 00 F0 93 80 F0 FF 13 00 00 00 13 00 00 00 
+37 01 00 F0 63 FC 20 12 13 02 12 00 93 02 20 00 
+E3 10 52 FE 93 01 20 01 13 02 00 00 B7 00 00 F0 
+93 80 F0 FF 37 01 00 F0 63 FA 20 10 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 01 30 01 13 02 00 00 
+B7 00 00 F0 93 80 F0 FF 37 01 00 F0 13 00 00 00 
+63 F6 20 0E 13 02 12 00 93 02 20 00 E3 12 52 FE 
+93 01 40 01 13 02 00 00 B7 00 00 F0 93 80 F0 FF 
+37 01 00 F0 13 00 00 00 13 00 00 00 63 F0 20 0C 
+13 02 12 00 93 02 20 00 E3 10 52 FE 93 01 50 01 
+13 02 00 00 B7 00 00 F0 93 80 F0 FF 13 00 00 00 
+37 01 00 F0 63 FC 20 08 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 60 01 13 02 00 00 B7 00 00 F0 
+93 80 F0 FF 13 00 00 00 37 01 00 F0 13 00 00 00 
+63 F6 20 06 13 02 12 00 93 02 20 00 E3 10 52 FE 
+93 01 70 01 13 02 00 00 B7 00 00 F0 93 80 F0 FF 
+13 00 00 00 13 00 00 00 37 01 00 F0 63 F0 20 04 
+13 02 12 00 93 02 20 00 E3 10 52 FE 93 00 10 00 
+63 FA 00 00 93 80 10 00 93 80 10 00 93 80 10 00 
+93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 
+93 01 80 01 63 94 D0 01 63 18 30 00 13 0D 10 00 
+93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 
+6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@000003C0
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-blt.dump

@@ -0,0 +1,248 @@
+
+generated/rv32ui-p-blt:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00200193          	li	gp,2
+   c:	00000093          	li	ra,0
+  10:	00100113          	li	sp,1
+  14:	0020c663          	blt	ra,sp,20 <test_2+0x18>
+  18:	2a301863          	bne	zero,gp,2c8 <fail>
+  1c:	00301663          	bne	zero,gp,28 <test_3>
+  20:	fe20cee3          	blt	ra,sp,1c <test_2+0x14>
+  24:	2a301263          	bne	zero,gp,2c8 <fail>
+
+00000028 <test_3>:
+  28:	00300193          	li	gp,3
+  2c:	fff00093          	li	ra,-1
+  30:	00100113          	li	sp,1
+  34:	0020c663          	blt	ra,sp,40 <test_3+0x18>
+  38:	28301863          	bne	zero,gp,2c8 <fail>
+  3c:	00301663          	bne	zero,gp,48 <test_4>
+  40:	fe20cee3          	blt	ra,sp,3c <test_3+0x14>
+  44:	28301263          	bne	zero,gp,2c8 <fail>
+
+00000048 <test_4>:
+  48:	00400193          	li	gp,4
+  4c:	ffe00093          	li	ra,-2
+  50:	fff00113          	li	sp,-1
+  54:	0020c663          	blt	ra,sp,60 <test_4+0x18>
+  58:	26301863          	bne	zero,gp,2c8 <fail>
+  5c:	00301663          	bne	zero,gp,68 <test_5>
+  60:	fe20cee3          	blt	ra,sp,5c <test_4+0x14>
+  64:	26301263          	bne	zero,gp,2c8 <fail>
+
+00000068 <test_5>:
+  68:	00500193          	li	gp,5
+  6c:	00100093          	li	ra,1
+  70:	00000113          	li	sp,0
+  74:	0020c463          	blt	ra,sp,7c <test_5+0x14>
+  78:	00301463          	bne	zero,gp,80 <test_5+0x18>
+  7c:	24301663          	bne	zero,gp,2c8 <fail>
+  80:	fe20cee3          	blt	ra,sp,7c <test_5+0x14>
+
+00000084 <test_6>:
+  84:	00600193          	li	gp,6
+  88:	00100093          	li	ra,1
+  8c:	fff00113          	li	sp,-1
+  90:	0020c463          	blt	ra,sp,98 <test_6+0x14>
+  94:	00301463          	bne	zero,gp,9c <test_6+0x18>
+  98:	22301863          	bne	zero,gp,2c8 <fail>
+  9c:	fe20cee3          	blt	ra,sp,98 <test_6+0x14>
+
+000000a0 <test_7>:
+  a0:	00700193          	li	gp,7
+  a4:	fff00093          	li	ra,-1
+  a8:	ffe00113          	li	sp,-2
+  ac:	0020c463          	blt	ra,sp,b4 <test_7+0x14>
+  b0:	00301463          	bne	zero,gp,b8 <test_7+0x18>
+  b4:	20301a63          	bne	zero,gp,2c8 <fail>
+  b8:	fe20cee3          	blt	ra,sp,b4 <test_7+0x14>
+
+000000bc <test_8>:
+  bc:	00800193          	li	gp,8
+  c0:	00100093          	li	ra,1
+  c4:	ffe00113          	li	sp,-2
+  c8:	0020c463          	blt	ra,sp,d0 <test_8+0x14>
+  cc:	00301463          	bne	zero,gp,d4 <test_8+0x18>
+  d0:	1e301c63          	bne	zero,gp,2c8 <fail>
+  d4:	fe20cee3          	blt	ra,sp,d0 <test_8+0x14>
+
+000000d8 <test_9>:
+  d8:	00900193          	li	gp,9
+  dc:	00000213          	li	tp,0
+  e0:	00000093          	li	ra,0
+  e4:	fff00113          	li	sp,-1
+  e8:	1e20c063          	blt	ra,sp,2c8 <fail>
+  ec:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+  f0:	00200293          	li	t0,2
+  f4:	fe5216e3          	bne	tp,t0,e0 <test_9+0x8>
+
+000000f8 <test_10>:
+  f8:	00a00193          	li	gp,10
+  fc:	00000213          	li	tp,0
+ 100:	00000093          	li	ra,0
+ 104:	fff00113          	li	sp,-1
+ 108:	00000013          	nop
+ 10c:	1a20ce63          	blt	ra,sp,2c8 <fail>
+ 110:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 114:	00200293          	li	t0,2
+ 118:	fe5214e3          	bne	tp,t0,100 <test_10+0x8>
+
+0000011c <test_11>:
+ 11c:	00b00193          	li	gp,11
+ 120:	00000213          	li	tp,0
+ 124:	00000093          	li	ra,0
+ 128:	fff00113          	li	sp,-1
+ 12c:	00000013          	nop
+ 130:	00000013          	nop
+ 134:	1820ca63          	blt	ra,sp,2c8 <fail>
+ 138:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 13c:	00200293          	li	t0,2
+ 140:	fe5212e3          	bne	tp,t0,124 <test_11+0x8>
+
+00000144 <test_12>:
+ 144:	00c00193          	li	gp,12
+ 148:	00000213          	li	tp,0
+ 14c:	00000093          	li	ra,0
+ 150:	00000013          	nop
+ 154:	fff00113          	li	sp,-1
+ 158:	1620c863          	blt	ra,sp,2c8 <fail>
+ 15c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 160:	00200293          	li	t0,2
+ 164:	fe5214e3          	bne	tp,t0,14c <test_12+0x8>
+
+00000168 <test_13>:
+ 168:	00d00193          	li	gp,13
+ 16c:	00000213          	li	tp,0
+ 170:	00000093          	li	ra,0
+ 174:	00000013          	nop
+ 178:	fff00113          	li	sp,-1
+ 17c:	00000013          	nop
+ 180:	1420c463          	blt	ra,sp,2c8 <fail>
+ 184:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 188:	00200293          	li	t0,2
+ 18c:	fe5212e3          	bne	tp,t0,170 <test_13+0x8>
+
+00000190 <test_14>:
+ 190:	00e00193          	li	gp,14
+ 194:	00000213          	li	tp,0
+ 198:	00000093          	li	ra,0
+ 19c:	00000013          	nop
+ 1a0:	00000013          	nop
+ 1a4:	fff00113          	li	sp,-1
+ 1a8:	1220c063          	blt	ra,sp,2c8 <fail>
+ 1ac:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1b0:	00200293          	li	t0,2
+ 1b4:	fe5212e3          	bne	tp,t0,198 <test_14+0x8>
+
+000001b8 <test_15>:
+ 1b8:	00f00193          	li	gp,15
+ 1bc:	00000213          	li	tp,0
+ 1c0:	00000093          	li	ra,0
+ 1c4:	fff00113          	li	sp,-1
+ 1c8:	1020c063          	blt	ra,sp,2c8 <fail>
+ 1cc:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1d0:	00200293          	li	t0,2
+ 1d4:	fe5216e3          	bne	tp,t0,1c0 <test_15+0x8>
+
+000001d8 <test_16>:
+ 1d8:	01000193          	li	gp,16
+ 1dc:	00000213          	li	tp,0
+ 1e0:	00000093          	li	ra,0
+ 1e4:	fff00113          	li	sp,-1
+ 1e8:	00000013          	nop
+ 1ec:	0c20ce63          	blt	ra,sp,2c8 <fail>
+ 1f0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1f4:	00200293          	li	t0,2
+ 1f8:	fe5214e3          	bne	tp,t0,1e0 <test_16+0x8>
+
+000001fc <test_17>:
+ 1fc:	01100193          	li	gp,17
+ 200:	00000213          	li	tp,0
+ 204:	00000093          	li	ra,0
+ 208:	fff00113          	li	sp,-1
+ 20c:	00000013          	nop
+ 210:	00000013          	nop
+ 214:	0a20ca63          	blt	ra,sp,2c8 <fail>
+ 218:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 21c:	00200293          	li	t0,2
+ 220:	fe5212e3          	bne	tp,t0,204 <test_17+0x8>
+
+00000224 <test_18>:
+ 224:	01200193          	li	gp,18
+ 228:	00000213          	li	tp,0
+ 22c:	00000093          	li	ra,0
+ 230:	00000013          	nop
+ 234:	fff00113          	li	sp,-1
+ 238:	0820c863          	blt	ra,sp,2c8 <fail>
+ 23c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 240:	00200293          	li	t0,2
+ 244:	fe5214e3          	bne	tp,t0,22c <test_18+0x8>
+
+00000248 <test_19>:
+ 248:	01300193          	li	gp,19
+ 24c:	00000213          	li	tp,0
+ 250:	00000093          	li	ra,0
+ 254:	00000013          	nop
+ 258:	fff00113          	li	sp,-1
+ 25c:	00000013          	nop
+ 260:	0620c463          	blt	ra,sp,2c8 <fail>
+ 264:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 268:	00200293          	li	t0,2
+ 26c:	fe5212e3          	bne	tp,t0,250 <test_19+0x8>
+
+00000270 <test_20>:
+ 270:	01400193          	li	gp,20
+ 274:	00000213          	li	tp,0
+ 278:	00000093          	li	ra,0
+ 27c:	00000013          	nop
+ 280:	00000013          	nop
+ 284:	fff00113          	li	sp,-1
+ 288:	0420c063          	blt	ra,sp,2c8 <fail>
+ 28c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 290:	00200293          	li	t0,2
+ 294:	fe5212e3          	bne	tp,t0,278 <test_20+0x8>
+
+00000298 <test_21>:
+ 298:	00100093          	li	ra,1
+ 29c:	00104a63          	bgtz	ra,2b0 <test_21+0x18>
+ 2a0:	00108093          	addi	ra,ra,1
+ 2a4:	00108093          	addi	ra,ra,1
+ 2a8:	00108093          	addi	ra,ra,1
+ 2ac:	00108093          	addi	ra,ra,1
+ 2b0:	00108093          	addi	ra,ra,1
+ 2b4:	00108093          	addi	ra,ra,1
+ 2b8:	00300e93          	li	t4,3
+ 2bc:	01500193          	li	gp,21
+ 2c0:	01d09463          	bne	ra,t4,2c8 <fail>
+ 2c4:	00301863          	bne	zero,gp,2d4 <pass>
+
+000002c8 <fail>:
+ 2c8:	00100d13          	li	s10,1
+ 2cc:	00000d93          	li	s11,0
+
+000002d0 <loop_fail>:
+ 2d0:	0000006f          	j	2d0 <loop_fail>
+
+000002d4 <pass>:
+ 2d4:	00100d13          	li	s10,1
+ 2d8:	00100d93          	li	s11,1
+
+000002dc <loop_pass>:
+ 2dc:	0000006f          	j	2dc <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+00000340 <tohost>:
+	...
+
+00000380 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-blt.verilog

@@ -0,0 +1,56 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 
+13 01 10 00 63 C6 20 00 63 18 30 2A 63 16 30 00 
+E3 CE 20 FE 63 12 30 2A 93 01 30 00 93 00 F0 FF 
+13 01 10 00 63 C6 20 00 63 18 30 28 63 16 30 00 
+E3 CE 20 FE 63 12 30 28 93 01 40 00 93 00 E0 FF 
+13 01 F0 FF 63 C6 20 00 63 18 30 26 63 16 30 00 
+E3 CE 20 FE 63 12 30 26 93 01 50 00 93 00 10 00 
+13 01 00 00 63 C4 20 00 63 14 30 00 63 16 30 24 
+E3 CE 20 FE 93 01 60 00 93 00 10 00 13 01 F0 FF 
+63 C4 20 00 63 14 30 00 63 18 30 22 E3 CE 20 FE 
+93 01 70 00 93 00 F0 FF 13 01 E0 FF 63 C4 20 00 
+63 14 30 00 63 1A 30 20 E3 CE 20 FE 93 01 80 00 
+93 00 10 00 13 01 E0 FF 63 C4 20 00 63 14 30 00 
+63 1C 30 1E E3 CE 20 FE 93 01 90 00 13 02 00 00 
+93 00 00 00 13 01 F0 FF 63 C0 20 1E 13 02 12 00 
+93 02 20 00 E3 16 52 FE 93 01 A0 00 13 02 00 00 
+93 00 00 00 13 01 F0 FF 13 00 00 00 63 CE 20 1A 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 B0 00 
+13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 
+13 00 00 00 63 CA 20 18 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 C0 00 13 02 00 00 93 00 00 00 
+13 00 00 00 13 01 F0 FF 63 C8 20 16 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 01 D0 00 13 02 00 00 
+93 00 00 00 13 00 00 00 13 01 F0 FF 13 00 00 00 
+63 C4 20 14 13 02 12 00 93 02 20 00 E3 12 52 FE 
+93 01 E0 00 13 02 00 00 93 00 00 00 13 00 00 00 
+13 00 00 00 13 01 F0 FF 63 C0 20 12 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 F0 00 13 02 00 00 
+93 00 00 00 13 01 F0 FF 63 C0 20 10 13 02 12 00 
+93 02 20 00 E3 16 52 FE 93 01 00 01 13 02 00 00 
+93 00 00 00 13 01 F0 FF 13 00 00 00 63 CE 20 0C 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 10 01 
+13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 
+13 00 00 00 63 CA 20 0A 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 20 01 13 02 00 00 93 00 00 00 
+13 00 00 00 13 01 F0 FF 63 C8 20 08 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 01 30 01 13 02 00 00 
+93 00 00 00 13 00 00 00 13 01 F0 FF 13 00 00 00 
+63 C4 20 06 13 02 12 00 93 02 20 00 E3 12 52 FE 
+93 01 40 01 13 02 00 00 93 00 00 00 13 00 00 00 
+13 00 00 00 13 01 F0 FF 63 C0 20 04 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 00 10 00 63 4A 10 00 
+93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 
+93 80 10 00 93 80 10 00 93 0E 30 00 93 01 50 01 
+63 94 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 
+6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00000340
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-bltu.dump

@@ -0,0 +1,261 @@
+
+generated/rv32ui-p-bltu:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00200193          	li	gp,2
+   c:	00000093          	li	ra,0
+  10:	00100113          	li	sp,1
+  14:	0020e663          	bltu	ra,sp,20 <test_2+0x18>
+  18:	2e301263          	bne	zero,gp,2fc <fail>
+  1c:	00301663          	bne	zero,gp,28 <test_3>
+  20:	fe20eee3          	bltu	ra,sp,1c <test_2+0x14>
+  24:	2c301c63          	bne	zero,gp,2fc <fail>
+
+00000028 <test_3>:
+  28:	00300193          	li	gp,3
+  2c:	ffe00093          	li	ra,-2
+  30:	fff00113          	li	sp,-1
+  34:	0020e663          	bltu	ra,sp,40 <test_3+0x18>
+  38:	2c301263          	bne	zero,gp,2fc <fail>
+  3c:	00301663          	bne	zero,gp,48 <test_4>
+  40:	fe20eee3          	bltu	ra,sp,3c <test_3+0x14>
+  44:	2a301c63          	bne	zero,gp,2fc <fail>
+
+00000048 <test_4>:
+  48:	00400193          	li	gp,4
+  4c:	00000093          	li	ra,0
+  50:	fff00113          	li	sp,-1
+  54:	0020e663          	bltu	ra,sp,60 <test_4+0x18>
+  58:	2a301263          	bne	zero,gp,2fc <fail>
+  5c:	00301663          	bne	zero,gp,68 <test_5>
+  60:	fe20eee3          	bltu	ra,sp,5c <test_4+0x14>
+  64:	28301c63          	bne	zero,gp,2fc <fail>
+
+00000068 <test_5>:
+  68:	00500193          	li	gp,5
+  6c:	00100093          	li	ra,1
+  70:	00000113          	li	sp,0
+  74:	0020e463          	bltu	ra,sp,7c <test_5+0x14>
+  78:	00301463          	bne	zero,gp,80 <test_5+0x18>
+  7c:	28301063          	bne	zero,gp,2fc <fail>
+  80:	fe20eee3          	bltu	ra,sp,7c <test_5+0x14>
+
+00000084 <test_6>:
+  84:	00600193          	li	gp,6
+  88:	fff00093          	li	ra,-1
+  8c:	ffe00113          	li	sp,-2
+  90:	0020e463          	bltu	ra,sp,98 <test_6+0x14>
+  94:	00301463          	bne	zero,gp,9c <test_6+0x18>
+  98:	26301263          	bne	zero,gp,2fc <fail>
+  9c:	fe20eee3          	bltu	ra,sp,98 <test_6+0x14>
+
+000000a0 <test_7>:
+  a0:	00700193          	li	gp,7
+  a4:	fff00093          	li	ra,-1
+  a8:	00000113          	li	sp,0
+  ac:	0020e463          	bltu	ra,sp,b4 <test_7+0x14>
+  b0:	00301463          	bne	zero,gp,b8 <test_7+0x18>
+  b4:	24301463          	bne	zero,gp,2fc <fail>
+  b8:	fe20eee3          	bltu	ra,sp,b4 <test_7+0x14>
+
+000000bc <test_8>:
+  bc:	00800193          	li	gp,8
+  c0:	800000b7          	lui	ra,0x80000
+  c4:	80000137          	lui	sp,0x80000
+  c8:	fff10113          	addi	sp,sp,-1 # 7fffffff <begin_signature+0x7fffefff>
+  cc:	0020e463          	bltu	ra,sp,d4 <test_8+0x18>
+  d0:	00301463          	bne	zero,gp,d8 <test_8+0x1c>
+  d4:	22301463          	bne	zero,gp,2fc <fail>
+  d8:	fe20eee3          	bltu	ra,sp,d4 <test_8+0x18>
+
+000000dc <test_9>:
+  dc:	00900193          	li	gp,9
+  e0:	00000213          	li	tp,0
+  e4:	f00000b7          	lui	ra,0xf0000
+  e8:	f0000137          	lui	sp,0xf0000
+  ec:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+  f0:	2020e663          	bltu	ra,sp,2fc <fail>
+  f4:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+  f8:	00200293          	li	t0,2
+  fc:	fe5214e3          	bne	tp,t0,e4 <test_9+0x8>
+
+00000100 <test_10>:
+ 100:	00a00193          	li	gp,10
+ 104:	00000213          	li	tp,0
+ 108:	f00000b7          	lui	ra,0xf0000
+ 10c:	f0000137          	lui	sp,0xf0000
+ 110:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 114:	00000013          	nop
+ 118:	1e20e263          	bltu	ra,sp,2fc <fail>
+ 11c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 120:	00200293          	li	t0,2
+ 124:	fe5212e3          	bne	tp,t0,108 <test_10+0x8>
+
+00000128 <test_11>:
+ 128:	00b00193          	li	gp,11
+ 12c:	00000213          	li	tp,0
+ 130:	f00000b7          	lui	ra,0xf0000
+ 134:	f0000137          	lui	sp,0xf0000
+ 138:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 13c:	00000013          	nop
+ 140:	00000013          	nop
+ 144:	1a20ec63          	bltu	ra,sp,2fc <fail>
+ 148:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 14c:	00200293          	li	t0,2
+ 150:	fe5210e3          	bne	tp,t0,130 <test_11+0x8>
+
+00000154 <test_12>:
+ 154:	00c00193          	li	gp,12
+ 158:	00000213          	li	tp,0
+ 15c:	f00000b7          	lui	ra,0xf0000
+ 160:	00000013          	nop
+ 164:	f0000137          	lui	sp,0xf0000
+ 168:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 16c:	1820e863          	bltu	ra,sp,2fc <fail>
+ 170:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 174:	00200293          	li	t0,2
+ 178:	fe5212e3          	bne	tp,t0,15c <test_12+0x8>
+
+0000017c <test_13>:
+ 17c:	00d00193          	li	gp,13
+ 180:	00000213          	li	tp,0
+ 184:	f00000b7          	lui	ra,0xf0000
+ 188:	00000013          	nop
+ 18c:	f0000137          	lui	sp,0xf0000
+ 190:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 194:	00000013          	nop
+ 198:	1620e263          	bltu	ra,sp,2fc <fail>
+ 19c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1a0:	00200293          	li	t0,2
+ 1a4:	fe5210e3          	bne	tp,t0,184 <test_13+0x8>
+
+000001a8 <test_14>:
+ 1a8:	00e00193          	li	gp,14
+ 1ac:	00000213          	li	tp,0
+ 1b0:	f00000b7          	lui	ra,0xf0000
+ 1b4:	00000013          	nop
+ 1b8:	00000013          	nop
+ 1bc:	f0000137          	lui	sp,0xf0000
+ 1c0:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 1c4:	1220ec63          	bltu	ra,sp,2fc <fail>
+ 1c8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1cc:	00200293          	li	t0,2
+ 1d0:	fe5210e3          	bne	tp,t0,1b0 <test_14+0x8>
+
+000001d4 <test_15>:
+ 1d4:	00f00193          	li	gp,15
+ 1d8:	00000213          	li	tp,0
+ 1dc:	f00000b7          	lui	ra,0xf0000
+ 1e0:	f0000137          	lui	sp,0xf0000
+ 1e4:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 1e8:	1020ea63          	bltu	ra,sp,2fc <fail>
+ 1ec:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1f0:	00200293          	li	t0,2
+ 1f4:	fe5214e3          	bne	tp,t0,1dc <test_15+0x8>
+
+000001f8 <test_16>:
+ 1f8:	01000193          	li	gp,16
+ 1fc:	00000213          	li	tp,0
+ 200:	f00000b7          	lui	ra,0xf0000
+ 204:	f0000137          	lui	sp,0xf0000
+ 208:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 20c:	00000013          	nop
+ 210:	0e20e663          	bltu	ra,sp,2fc <fail>
+ 214:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 218:	00200293          	li	t0,2
+ 21c:	fe5212e3          	bne	tp,t0,200 <test_16+0x8>
+
+00000220 <test_17>:
+ 220:	01100193          	li	gp,17
+ 224:	00000213          	li	tp,0
+ 228:	f00000b7          	lui	ra,0xf0000
+ 22c:	f0000137          	lui	sp,0xf0000
+ 230:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 234:	00000013          	nop
+ 238:	00000013          	nop
+ 23c:	0c20e063          	bltu	ra,sp,2fc <fail>
+ 240:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 244:	00200293          	li	t0,2
+ 248:	fe5210e3          	bne	tp,t0,228 <test_17+0x8>
+
+0000024c <test_18>:
+ 24c:	01200193          	li	gp,18
+ 250:	00000213          	li	tp,0
+ 254:	f00000b7          	lui	ra,0xf0000
+ 258:	00000013          	nop
+ 25c:	f0000137          	lui	sp,0xf0000
+ 260:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 264:	0820ec63          	bltu	ra,sp,2fc <fail>
+ 268:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 26c:	00200293          	li	t0,2
+ 270:	fe5212e3          	bne	tp,t0,254 <test_18+0x8>
+
+00000274 <test_19>:
+ 274:	01300193          	li	gp,19
+ 278:	00000213          	li	tp,0
+ 27c:	f00000b7          	lui	ra,0xf0000
+ 280:	00000013          	nop
+ 284:	f0000137          	lui	sp,0xf0000
+ 288:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 28c:	00000013          	nop
+ 290:	0620e663          	bltu	ra,sp,2fc <fail>
+ 294:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 298:	00200293          	li	t0,2
+ 29c:	fe5210e3          	bne	tp,t0,27c <test_19+0x8>
+
+000002a0 <test_20>:
+ 2a0:	01400193          	li	gp,20
+ 2a4:	00000213          	li	tp,0
+ 2a8:	f00000b7          	lui	ra,0xf0000
+ 2ac:	00000013          	nop
+ 2b0:	00000013          	nop
+ 2b4:	f0000137          	lui	sp,0xf0000
+ 2b8:	fff10113          	addi	sp,sp,-1 # efffffff <begin_signature+0xefffefff>
+ 2bc:	0420e063          	bltu	ra,sp,2fc <fail>
+ 2c0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 2c4:	00200293          	li	t0,2
+ 2c8:	fe5210e3          	bne	tp,t0,2a8 <test_20+0x8>
+
+000002cc <test_21>:
+ 2cc:	00100093          	li	ra,1
+ 2d0:	00106a63          	bltu	zero,ra,2e4 <test_21+0x18>
+ 2d4:	00108093          	addi	ra,ra,1 # f0000001 <begin_signature+0xeffff001>
+ 2d8:	00108093          	addi	ra,ra,1
+ 2dc:	00108093          	addi	ra,ra,1
+ 2e0:	00108093          	addi	ra,ra,1
+ 2e4:	00108093          	addi	ra,ra,1
+ 2e8:	00108093          	addi	ra,ra,1
+ 2ec:	00300e93          	li	t4,3
+ 2f0:	01500193          	li	gp,21
+ 2f4:	01d09463          	bne	ra,t4,2fc <fail>
+ 2f8:	00301863          	bne	zero,gp,308 <pass>
+
+000002fc <fail>:
+ 2fc:	00100d13          	li	s10,1
+ 300:	00000d93          	li	s11,0
+
+00000304 <loop_fail>:
+ 304:	0000006f          	j	304 <loop_fail>
+
+00000308 <pass>:
+ 308:	00100d13          	li	s10,1
+ 30c:	00100d93          	li	s11,1
+
+00000310 <loop_pass>:
+ 310:	0000006f          	j	310 <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+00000380 <tohost>:
+	...
+
+000003c0 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-bltu.verilog

@@ -0,0 +1,60 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 
+13 01 10 00 63 E6 20 00 63 12 30 2E 63 16 30 00 
+E3 EE 20 FE 63 1C 30 2C 93 01 30 00 93 00 E0 FF 
+13 01 F0 FF 63 E6 20 00 63 12 30 2C 63 16 30 00 
+E3 EE 20 FE 63 1C 30 2A 93 01 40 00 93 00 00 00 
+13 01 F0 FF 63 E6 20 00 63 12 30 2A 63 16 30 00 
+E3 EE 20 FE 63 1C 30 28 93 01 50 00 93 00 10 00 
+13 01 00 00 63 E4 20 00 63 14 30 00 63 10 30 28 
+E3 EE 20 FE 93 01 60 00 93 00 F0 FF 13 01 E0 FF 
+63 E4 20 00 63 14 30 00 63 12 30 26 E3 EE 20 FE 
+93 01 70 00 93 00 F0 FF 13 01 00 00 63 E4 20 00 
+63 14 30 00 63 14 30 24 E3 EE 20 FE 93 01 80 00 
+B7 00 00 80 37 01 00 80 13 01 F1 FF 63 E4 20 00 
+63 14 30 00 63 14 30 22 E3 EE 20 FE 93 01 90 00 
+13 02 00 00 B7 00 00 F0 37 01 00 F0 13 01 F1 FF 
+63 E6 20 20 13 02 12 00 93 02 20 00 E3 14 52 FE 
+93 01 A0 00 13 02 00 00 B7 00 00 F0 37 01 00 F0 
+13 01 F1 FF 13 00 00 00 63 E2 20 1E 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 B0 00 13 02 00 00 
+B7 00 00 F0 37 01 00 F0 13 01 F1 FF 13 00 00 00 
+13 00 00 00 63 EC 20 1A 13 02 12 00 93 02 20 00 
+E3 10 52 FE 93 01 C0 00 13 02 00 00 B7 00 00 F0 
+13 00 00 00 37 01 00 F0 13 01 F1 FF 63 E8 20 18 
+13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 D0 00 
+13 02 00 00 B7 00 00 F0 13 00 00 00 37 01 00 F0 
+13 01 F1 FF 13 00 00 00 63 E2 20 16 13 02 12 00 
+93 02 20 00 E3 10 52 FE 93 01 E0 00 13 02 00 00 
+B7 00 00 F0 13 00 00 00 13 00 00 00 37 01 00 F0 
+13 01 F1 FF 63 EC 20 12 13 02 12 00 93 02 20 00 
+E3 10 52 FE 93 01 F0 00 13 02 00 00 B7 00 00 F0 
+37 01 00 F0 13 01 F1 FF 63 EA 20 10 13 02 12 00 
+93 02 20 00 E3 14 52 FE 93 01 00 01 13 02 00 00 
+B7 00 00 F0 37 01 00 F0 13 01 F1 FF 13 00 00 00 
+63 E6 20 0E 13 02 12 00 93 02 20 00 E3 12 52 FE 
+93 01 10 01 13 02 00 00 B7 00 00 F0 37 01 00 F0 
+13 01 F1 FF 13 00 00 00 13 00 00 00 63 E0 20 0C 
+13 02 12 00 93 02 20 00 E3 10 52 FE 93 01 20 01 
+13 02 00 00 B7 00 00 F0 13 00 00 00 37 01 00 F0 
+13 01 F1 FF 63 EC 20 08 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 30 01 13 02 00 00 B7 00 00 F0 
+13 00 00 00 37 01 00 F0 13 01 F1 FF 13 00 00 00 
+63 E6 20 06 13 02 12 00 93 02 20 00 E3 10 52 FE 
+93 01 40 01 13 02 00 00 B7 00 00 F0 13 00 00 00 
+13 00 00 00 37 01 00 F0 13 01 F1 FF 63 E0 20 04 
+13 02 12 00 93 02 20 00 E3 10 52 FE 93 00 10 00 
+63 6A 10 00 93 80 10 00 93 80 10 00 93 80 10 00 
+93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 
+93 01 50 01 63 94 D0 01 63 18 30 00 13 0D 10 00 
+93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 
+6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00000380
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-bne.dump

@@ -0,0 +1,249 @@
+
+generated/rv32ui-p-bne:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00200193          	li	gp,2
+   c:	00000093          	li	ra,0
+  10:	00100113          	li	sp,1
+  14:	00209663          	bne	ra,sp,20 <test_2+0x18>
+  18:	2a301a63          	bne	zero,gp,2cc <fail>
+  1c:	00301663          	bne	zero,gp,28 <test_3>
+  20:	fe209ee3          	bne	ra,sp,1c <test_2+0x14>
+  24:	2a301463          	bne	zero,gp,2cc <fail>
+
+00000028 <test_3>:
+  28:	00300193          	li	gp,3
+  2c:	00100093          	li	ra,1
+  30:	00000113          	li	sp,0
+  34:	00209663          	bne	ra,sp,40 <test_3+0x18>
+  38:	28301a63          	bne	zero,gp,2cc <fail>
+  3c:	00301663          	bne	zero,gp,48 <test_4>
+  40:	fe209ee3          	bne	ra,sp,3c <test_3+0x14>
+  44:	28301463          	bne	zero,gp,2cc <fail>
+
+00000048 <test_4>:
+  48:	00400193          	li	gp,4
+  4c:	fff00093          	li	ra,-1
+  50:	00100113          	li	sp,1
+  54:	00209663          	bne	ra,sp,60 <test_4+0x18>
+  58:	26301a63          	bne	zero,gp,2cc <fail>
+  5c:	00301663          	bne	zero,gp,68 <test_5>
+  60:	fe209ee3          	bne	ra,sp,5c <test_4+0x14>
+  64:	26301463          	bne	zero,gp,2cc <fail>
+
+00000068 <test_5>:
+  68:	00500193          	li	gp,5
+  6c:	00100093          	li	ra,1
+  70:	fff00113          	li	sp,-1
+  74:	00209663          	bne	ra,sp,80 <test_5+0x18>
+  78:	24301a63          	bne	zero,gp,2cc <fail>
+  7c:	00301663          	bne	zero,gp,88 <test_6>
+  80:	fe209ee3          	bne	ra,sp,7c <test_5+0x14>
+  84:	24301463          	bne	zero,gp,2cc <fail>
+
+00000088 <test_6>:
+  88:	00600193          	li	gp,6
+  8c:	00000093          	li	ra,0
+  90:	00000113          	li	sp,0
+  94:	00209463          	bne	ra,sp,9c <test_6+0x14>
+  98:	00301463          	bne	zero,gp,a0 <test_6+0x18>
+  9c:	22301863          	bne	zero,gp,2cc <fail>
+  a0:	fe209ee3          	bne	ra,sp,9c <test_6+0x14>
+
+000000a4 <test_7>:
+  a4:	00700193          	li	gp,7
+  a8:	00100093          	li	ra,1
+  ac:	00100113          	li	sp,1
+  b0:	00209463          	bne	ra,sp,b8 <test_7+0x14>
+  b4:	00301463          	bne	zero,gp,bc <test_7+0x18>
+  b8:	20301a63          	bne	zero,gp,2cc <fail>
+  bc:	fe209ee3          	bne	ra,sp,b8 <test_7+0x14>
+
+000000c0 <test_8>:
+  c0:	00800193          	li	gp,8
+  c4:	fff00093          	li	ra,-1
+  c8:	fff00113          	li	sp,-1
+  cc:	00209463          	bne	ra,sp,d4 <test_8+0x14>
+  d0:	00301463          	bne	zero,gp,d8 <test_8+0x18>
+  d4:	1e301c63          	bne	zero,gp,2cc <fail>
+  d8:	fe209ee3          	bne	ra,sp,d4 <test_8+0x14>
+
+000000dc <test_9>:
+  dc:	00900193          	li	gp,9
+  e0:	00000213          	li	tp,0
+  e4:	00000093          	li	ra,0
+  e8:	00000113          	li	sp,0
+  ec:	1e209063          	bne	ra,sp,2cc <fail>
+  f0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+  f4:	00200293          	li	t0,2
+  f8:	fe5216e3          	bne	tp,t0,e4 <test_9+0x8>
+
+000000fc <test_10>:
+  fc:	00a00193          	li	gp,10
+ 100:	00000213          	li	tp,0
+ 104:	00000093          	li	ra,0
+ 108:	00000113          	li	sp,0
+ 10c:	00000013          	nop
+ 110:	1a209e63          	bne	ra,sp,2cc <fail>
+ 114:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 118:	00200293          	li	t0,2
+ 11c:	fe5214e3          	bne	tp,t0,104 <test_10+0x8>
+
+00000120 <test_11>:
+ 120:	00b00193          	li	gp,11
+ 124:	00000213          	li	tp,0
+ 128:	00000093          	li	ra,0
+ 12c:	00000113          	li	sp,0
+ 130:	00000013          	nop
+ 134:	00000013          	nop
+ 138:	18209a63          	bne	ra,sp,2cc <fail>
+ 13c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 140:	00200293          	li	t0,2
+ 144:	fe5212e3          	bne	tp,t0,128 <test_11+0x8>
+
+00000148 <test_12>:
+ 148:	00c00193          	li	gp,12
+ 14c:	00000213          	li	tp,0
+ 150:	00000093          	li	ra,0
+ 154:	00000013          	nop
+ 158:	00000113          	li	sp,0
+ 15c:	16209863          	bne	ra,sp,2cc <fail>
+ 160:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 164:	00200293          	li	t0,2
+ 168:	fe5214e3          	bne	tp,t0,150 <test_12+0x8>
+
+0000016c <test_13>:
+ 16c:	00d00193          	li	gp,13
+ 170:	00000213          	li	tp,0
+ 174:	00000093          	li	ra,0
+ 178:	00000013          	nop
+ 17c:	00000113          	li	sp,0
+ 180:	00000013          	nop
+ 184:	14209463          	bne	ra,sp,2cc <fail>
+ 188:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 18c:	00200293          	li	t0,2
+ 190:	fe5212e3          	bne	tp,t0,174 <test_13+0x8>
+
+00000194 <test_14>:
+ 194:	00e00193          	li	gp,14
+ 198:	00000213          	li	tp,0
+ 19c:	00000093          	li	ra,0
+ 1a0:	00000013          	nop
+ 1a4:	00000013          	nop
+ 1a8:	00000113          	li	sp,0
+ 1ac:	12209063          	bne	ra,sp,2cc <fail>
+ 1b0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1b4:	00200293          	li	t0,2
+ 1b8:	fe5212e3          	bne	tp,t0,19c <test_14+0x8>
+
+000001bc <test_15>:
+ 1bc:	00f00193          	li	gp,15
+ 1c0:	00000213          	li	tp,0
+ 1c4:	00000093          	li	ra,0
+ 1c8:	00000113          	li	sp,0
+ 1cc:	10209063          	bne	ra,sp,2cc <fail>
+ 1d0:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1d4:	00200293          	li	t0,2
+ 1d8:	fe5216e3          	bne	tp,t0,1c4 <test_15+0x8>
+
+000001dc <test_16>:
+ 1dc:	01000193          	li	gp,16
+ 1e0:	00000213          	li	tp,0
+ 1e4:	00000093          	li	ra,0
+ 1e8:	00000113          	li	sp,0
+ 1ec:	00000013          	nop
+ 1f0:	0c209e63          	bne	ra,sp,2cc <fail>
+ 1f4:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1f8:	00200293          	li	t0,2
+ 1fc:	fe5214e3          	bne	tp,t0,1e4 <test_16+0x8>
+
+00000200 <test_17>:
+ 200:	01100193          	li	gp,17
+ 204:	00000213          	li	tp,0
+ 208:	00000093          	li	ra,0
+ 20c:	00000113          	li	sp,0
+ 210:	00000013          	nop
+ 214:	00000013          	nop
+ 218:	0a209a63          	bne	ra,sp,2cc <fail>
+ 21c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 220:	00200293          	li	t0,2
+ 224:	fe5212e3          	bne	tp,t0,208 <test_17+0x8>
+
+00000228 <test_18>:
+ 228:	01200193          	li	gp,18
+ 22c:	00000213          	li	tp,0
+ 230:	00000093          	li	ra,0
+ 234:	00000013          	nop
+ 238:	00000113          	li	sp,0
+ 23c:	08209863          	bne	ra,sp,2cc <fail>
+ 240:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 244:	00200293          	li	t0,2
+ 248:	fe5214e3          	bne	tp,t0,230 <test_18+0x8>
+
+0000024c <test_19>:
+ 24c:	01300193          	li	gp,19
+ 250:	00000213          	li	tp,0
+ 254:	00000093          	li	ra,0
+ 258:	00000013          	nop
+ 25c:	00000113          	li	sp,0
+ 260:	00000013          	nop
+ 264:	06209463          	bne	ra,sp,2cc <fail>
+ 268:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 26c:	00200293          	li	t0,2
+ 270:	fe5212e3          	bne	tp,t0,254 <test_19+0x8>
+
+00000274 <test_20>:
+ 274:	01400193          	li	gp,20
+ 278:	00000213          	li	tp,0
+ 27c:	00000093          	li	ra,0
+ 280:	00000013          	nop
+ 284:	00000013          	nop
+ 288:	00000113          	li	sp,0
+ 28c:	04209063          	bne	ra,sp,2cc <fail>
+ 290:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 294:	00200293          	li	t0,2
+ 298:	fe5212e3          	bne	tp,t0,27c <test_20+0x8>
+
+0000029c <test_21>:
+ 29c:	00100093          	li	ra,1
+ 2a0:	00009a63          	bnez	ra,2b4 <test_21+0x18>
+ 2a4:	00108093          	addi	ra,ra,1
+ 2a8:	00108093          	addi	ra,ra,1
+ 2ac:	00108093          	addi	ra,ra,1
+ 2b0:	00108093          	addi	ra,ra,1
+ 2b4:	00108093          	addi	ra,ra,1
+ 2b8:	00108093          	addi	ra,ra,1
+ 2bc:	00300e93          	li	t4,3
+ 2c0:	01500193          	li	gp,21
+ 2c4:	01d09463          	bne	ra,t4,2cc <fail>
+ 2c8:	00301863          	bne	zero,gp,2d8 <pass>
+
+000002cc <fail>:
+ 2cc:	00100d13          	li	s10,1
+ 2d0:	00000d93          	li	s11,0
+
+000002d4 <loop_fail>:
+ 2d4:	0000006f          	j	2d4 <loop_fail>
+
+000002d8 <pass>:
+ 2d8:	00100d13          	li	s10,1
+ 2dc:	00100d93          	li	s11,1
+
+000002e0 <loop_pass>:
+ 2e0:	0000006f          	j	2e0 <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+00000340 <tohost>:
+	...
+
+00000380 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-bne.verilog

@@ -0,0 +1,56 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 
+13 01 10 00 63 96 20 00 63 1A 30 2A 63 16 30 00 
+E3 9E 20 FE 63 14 30 2A 93 01 30 00 93 00 10 00 
+13 01 00 00 63 96 20 00 63 1A 30 28 63 16 30 00 
+E3 9E 20 FE 63 14 30 28 93 01 40 00 93 00 F0 FF 
+13 01 10 00 63 96 20 00 63 1A 30 26 63 16 30 00 
+E3 9E 20 FE 63 14 30 26 93 01 50 00 93 00 10 00 
+13 01 F0 FF 63 96 20 00 63 1A 30 24 63 16 30 00 
+E3 9E 20 FE 63 14 30 24 93 01 60 00 93 00 00 00 
+13 01 00 00 63 94 20 00 63 14 30 00 63 18 30 22 
+E3 9E 20 FE 93 01 70 00 93 00 10 00 13 01 10 00 
+63 94 20 00 63 14 30 00 63 1A 30 20 E3 9E 20 FE 
+93 01 80 00 93 00 F0 FF 13 01 F0 FF 63 94 20 00 
+63 14 30 00 63 1C 30 1E E3 9E 20 FE 93 01 90 00 
+13 02 00 00 93 00 00 00 13 01 00 00 63 90 20 1E 
+13 02 12 00 93 02 20 00 E3 16 52 FE 93 01 A0 00 
+13 02 00 00 93 00 00 00 13 01 00 00 13 00 00 00 
+63 9E 20 1A 13 02 12 00 93 02 20 00 E3 14 52 FE 
+93 01 B0 00 13 02 00 00 93 00 00 00 13 01 00 00 
+13 00 00 00 13 00 00 00 63 9A 20 18 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 C0 00 13 02 00 00 
+93 00 00 00 13 00 00 00 13 01 00 00 63 98 20 16 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 D0 00 
+13 02 00 00 93 00 00 00 13 00 00 00 13 01 00 00 
+13 00 00 00 63 94 20 14 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 E0 00 13 02 00 00 93 00 00 00 
+13 00 00 00 13 00 00 00 13 01 00 00 63 90 20 12 
+13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 F0 00 
+13 02 00 00 93 00 00 00 13 01 00 00 63 90 20 10 
+13 02 12 00 93 02 20 00 E3 16 52 FE 93 01 00 01 
+13 02 00 00 93 00 00 00 13 01 00 00 13 00 00 00 
+63 9E 20 0C 13 02 12 00 93 02 20 00 E3 14 52 FE 
+93 01 10 01 13 02 00 00 93 00 00 00 13 01 00 00 
+13 00 00 00 13 00 00 00 63 9A 20 0A 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 20 01 13 02 00 00 
+93 00 00 00 13 00 00 00 13 01 00 00 63 98 20 08 
+13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 30 01 
+13 02 00 00 93 00 00 00 13 00 00 00 13 01 00 00 
+13 00 00 00 63 94 20 06 13 02 12 00 93 02 20 00 
+E3 12 52 FE 93 01 40 01 13 02 00 00 93 00 00 00 
+13 00 00 00 13 00 00 00 13 01 00 00 63 90 20 04 
+13 02 12 00 93 02 20 00 E3 12 52 FE 93 00 10 00 
+63 9A 00 00 93 80 10 00 93 80 10 00 93 80 10 00 
+93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 
+93 01 50 01 63 94 D0 01 63 18 30 00 13 0D 10 00 
+93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 
+6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00000340
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-fence_i.dump

@@ -0,0 +1,94 @@
+
+generated/rv32ui-p-fence_i:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+   8:	06f00693          	li	a3,111
+   c:	00001517          	auipc	a0,0x1
+  10:	ff451503          	lh	a0,-12(a0) # 1000 <begin_signature>
+  14:	00001597          	auipc	a1,0x1
+  18:	fee59583          	lh	a1,-18(a1) # 1002 <begin_signature+0x2>
+  1c:	00000013          	nop
+  20:	00000013          	nop
+  24:	00000013          	nop
+  28:	00000013          	nop
+  2c:	00000013          	nop
+  30:	00000013          	nop
+  34:	00000013          	nop
+  38:	00000013          	nop
+  3c:	00000013          	nop
+  40:	00000297          	auipc	t0,0x0
+  44:	00a29a23          	sh	a0,20(t0) # 54 <_start+0x54>
+  48:	00000297          	auipc	t0,0x0
+  4c:	00b29723          	sh	a1,14(t0) # 56 <_start+0x56>
+  50:	0000100f          	fence.i
+  54:	0de68693          	addi	a3,a3,222
+
+00000058 <test_2>:
+  58:	00000013          	nop
+  5c:	1bc00e93          	li	t4,444
+  60:	00200193          	li	gp,2
+  64:	07d69a63          	bne	a3,t4,d8 <fail>
+  68:	06400713          	li	a4,100
+  6c:	fff70713          	addi	a4,a4,-1
+  70:	fe071ee3          	bnez	a4,6c <test_2+0x14>
+  74:	00000297          	auipc	t0,0x0
+  78:	04a29623          	sh	a0,76(t0) # c0 <test_2+0x68>
+  7c:	00000297          	auipc	t0,0x0
+  80:	04b29323          	sh	a1,70(t0) # c2 <test_2+0x6a>
+  84:	0000100f          	fence.i
+  88:	00000013          	nop
+  8c:	00000013          	nop
+  90:	00000013          	nop
+  94:	00000013          	nop
+  98:	00000013          	nop
+  9c:	00000013          	nop
+  a0:	00000013          	nop
+  a4:	00000013          	nop
+  a8:	00000013          	nop
+  ac:	00000013          	nop
+  b0:	00000013          	nop
+  b4:	00000013          	nop
+  b8:	00000013          	nop
+  bc:	00000013          	nop
+  c0:	22b68693          	addi	a3,a3,555
+
+000000c4 <test_3>:
+  c4:	00000013          	nop
+  c8:	30900e93          	li	t4,777
+  cc:	00300193          	li	gp,3
+  d0:	01d69463          	bne	a3,t4,d8 <fail>
+  d4:	00301863          	bne	zero,gp,e4 <pass>
+
+000000d8 <fail>:
+  d8:	00100d13          	li	s10,1
+  dc:	00000d93          	li	s11,0
+
+000000e0 <loop_fail>:
+  e0:	0000006f          	j	e0 <loop_fail>
+
+000000e4 <pass>:
+  e4:	00100d13          	li	s10,1
+  e8:	00100d93          	li	s11,1
+
+000000ec <loop_pass>:
+  ec:	0000006f          	j	ec <loop_pass>
+	...
+
+Disassembly of section .data:
+
+00001000 <begin_signature>:
+    1000:	14d68693          	addi	a3,a3,333
+	...
+
+Disassembly of section .tohost:
+
+00001040 <tohost>:
+	...
+
+00001080 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-fence_i.verilog

@@ -0,0 +1,28 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 06 F0 06 17 15 00 00 
+03 15 45 FF 97 15 00 00 83 95 E5 FE 13 00 00 00 
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 
+97 02 00 00 23 9A A2 00 97 02 00 00 23 97 B2 00 
+0F 10 00 00 93 86 E6 0D 13 00 00 00 93 0E C0 1B 
+93 01 20 00 63 9A D6 07 13 07 40 06 13 07 F7 FF 
+E3 1E 07 FE 97 02 00 00 23 96 A2 04 97 02 00 00 
+23 93 B2 04 0F 10 00 00 13 00 00 00 13 00 00 00 
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 
+13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 
+93 86 B6 22 13 00 00 00 93 0E 90 30 93 01 30 00 
+63 94 D6 01 63 18 30 00 13 0D 10 00 93 0D 00 00 
+6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 
+@00001000
+93 86 D6 14 00 00 00 00 00 00 00 00 00 00 00 00 
+@00001040
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-jal.dump

@@ -0,0 +1,61 @@
+
+generated/rv32ui-p-jal:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00200193          	li	gp,2
+   c:	00000093          	li	ra,0
+  10:	0100026f          	jal	tp,20 <target_2>
+
+00000014 <linkaddr_2>:
+  14:	00000013          	nop
+  18:	00000013          	nop
+  1c:	0400006f          	j	5c <fail>
+
+00000020 <target_2>:
+  20:	00000117          	auipc	sp,0x0
+  24:	ff410113          	addi	sp,sp,-12 # 14 <linkaddr_2>
+  28:	02411a63          	bne	sp,tp,5c <fail>
+
+0000002c <test_3>:
+  2c:	00100093          	li	ra,1
+  30:	0140006f          	j	44 <test_3+0x18>
+  34:	00108093          	addi	ra,ra,1
+  38:	00108093          	addi	ra,ra,1
+  3c:	00108093          	addi	ra,ra,1
+  40:	00108093          	addi	ra,ra,1
+  44:	00108093          	addi	ra,ra,1
+  48:	00108093          	addi	ra,ra,1
+  4c:	00300e93          	li	t4,3
+  50:	00300193          	li	gp,3
+  54:	01d09463          	bne	ra,t4,5c <fail>
+  58:	00301863          	bne	zero,gp,68 <pass>
+
+0000005c <fail>:
+  5c:	00100d13          	li	s10,1
+  60:	00000d93          	li	s11,0
+
+00000064 <loop_fail>:
+  64:	0000006f          	j	64 <loop_fail>
+
+00000068 <pass>:
+  68:	00100d13          	li	s10,1
+  6c:	00100d93          	li	s11,1
+
+00000070 <loop_pass>:
+  70:	0000006f          	j	70 <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+000000c0 <tohost>:
+	...
+
+00000100 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-jal.verilog

@@ -0,0 +1,16 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 
+6F 02 00 01 13 00 00 00 13 00 00 00 6F 00 00 04 
+17 01 00 00 13 01 41 FF 63 1A 41 02 93 00 10 00 
+6F 00 40 01 93 80 10 00 93 80 10 00 93 80 10 00 
+93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 
+93 01 30 00 63 94 D0 01 63 18 30 00 13 0D 10 00 
+93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 
+6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@000000C0
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-jalr.dump

@@ -0,0 +1,99 @@
+
+generated/rv32ui-p-jalr:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00200193          	li	gp,2
+   c:	00000293          	li	t0,0
+  10:	00000317          	auipc	t1,0x0
+  14:	01030313          	addi	t1,t1,16 # 20 <target_2>
+  18:	000302e7          	jalr	t0,t1
+
+0000001c <linkaddr_2>:
+  1c:	0c00006f          	j	dc <fail>
+
+00000020 <target_2>:
+  20:	00000317          	auipc	t1,0x0
+  24:	ffc30313          	addi	t1,t1,-4 # 1c <linkaddr_2>
+  28:	0a629a63          	bne	t0,t1,dc <fail>
+
+0000002c <test_4>:
+  2c:	00400193          	li	gp,4
+  30:	00000213          	li	tp,0
+  34:	00000317          	auipc	t1,0x0
+  38:	01030313          	addi	t1,t1,16 # 44 <test_4+0x18>
+  3c:	000309e7          	jalr	s3,t1
+  40:	08301e63          	bne	zero,gp,dc <fail>
+  44:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+  48:	00200293          	li	t0,2
+  4c:	fe5214e3          	bne	tp,t0,34 <test_4+0x8>
+
+00000050 <test_5>:
+  50:	00500193          	li	gp,5
+  54:	00000213          	li	tp,0
+  58:	00000317          	auipc	t1,0x0
+  5c:	01430313          	addi	t1,t1,20 # 6c <test_5+0x1c>
+  60:	00000013          	nop
+  64:	000309e7          	jalr	s3,t1
+  68:	06301a63          	bne	zero,gp,dc <fail>
+  6c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+  70:	00200293          	li	t0,2
+  74:	fe5212e3          	bne	tp,t0,58 <test_5+0x8>
+
+00000078 <test_6>:
+  78:	00600193          	li	gp,6
+  7c:	00000213          	li	tp,0
+  80:	00000317          	auipc	t1,0x0
+  84:	01830313          	addi	t1,t1,24 # 98 <test_6+0x20>
+  88:	00000013          	nop
+  8c:	00000013          	nop
+  90:	000309e7          	jalr	s3,t1
+  94:	04301463          	bne	zero,gp,dc <fail>
+  98:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+  9c:	00200293          	li	t0,2
+  a0:	fe5210e3          	bne	tp,t0,80 <test_6+0x8>
+
+000000a4 <test_7>:
+  a4:	00100293          	li	t0,1
+  a8:	00000317          	auipc	t1,0x0
+  ac:	01c30313          	addi	t1,t1,28 # c4 <test_7+0x20>
+  b0:	ffc30067          	jr	-4(t1)
+  b4:	00128293          	addi	t0,t0,1
+  b8:	00128293          	addi	t0,t0,1
+  bc:	00128293          	addi	t0,t0,1
+  c0:	00128293          	addi	t0,t0,1
+  c4:	00128293          	addi	t0,t0,1
+  c8:	00128293          	addi	t0,t0,1
+  cc:	00400e93          	li	t4,4
+  d0:	00700193          	li	gp,7
+  d4:	01d29463          	bne	t0,t4,dc <fail>
+  d8:	00301863          	bne	zero,gp,e8 <pass>
+
+000000dc <fail>:
+  dc:	00100d13          	li	s10,1
+  e0:	00000d93          	li	s11,0
+
+000000e4 <loop_fail>:
+  e4:	0000006f          	j	e4 <loop_fail>
+
+000000e8 <pass>:
+  e8:	00100d13          	li	s10,1
+  ec:	00100d93          	li	s11,1
+
+000000f0 <loop_pass>:
+  f0:	0000006f          	j	f0 <loop_pass>
+	...
+
+Disassembly of section .tohost:
+
+00000140 <tohost>:
+	...
+
+00000180 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-jalr.verilog

@@ -0,0 +1,24 @@
+@00000000
+13 0D 00 00 93 0D 00 00 93 01 20 00 93 02 00 00 
+17 03 00 00 13 03 03 01 E7 02 03 00 6F 00 00 0C 
+17 03 00 00 13 03 C3 FF 63 9A 62 0A 93 01 40 00 
+13 02 00 00 17 03 00 00 13 03 03 01 E7 09 03 00 
+63 1E 30 08 13 02 12 00 93 02 20 00 E3 14 52 FE 
+93 01 50 00 13 02 00 00 17 03 00 00 13 03 43 01 
+13 00 00 00 E7 09 03 00 63 1A 30 06 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 60 00 13 02 00 00 
+17 03 00 00 13 03 83 01 13 00 00 00 13 00 00 00 
+E7 09 03 00 63 14 30 04 13 02 12 00 93 02 20 00 
+E3 10 52 FE 93 02 10 00 17 03 00 00 13 03 C3 01 
+67 00 C3 FF 93 82 12 00 93 82 12 00 93 82 12 00 
+93 82 12 00 93 82 12 00 93 82 12 00 93 0E 40 00 
+93 01 70 00 63 94 D2 01 63 18 30 00 13 0D 10 00 
+93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 
+6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00000140
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-lb.dump

@@ -0,0 +1,230 @@
+
+generated/rv32ui-p-lb:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00001097          	auipc	ra,0x1
+   c:	ff808093          	addi	ra,ra,-8 # 1000 <begin_signature>
+  10:	00008f03          	lb	t5,0(ra)
+  14:	fff00e93          	li	t4,-1
+  18:	00200193          	li	gp,2
+  1c:	23df1c63          	bne	t5,t4,254 <fail>
+
+00000020 <test_3>:
+  20:	00001097          	auipc	ra,0x1
+  24:	fe008093          	addi	ra,ra,-32 # 1000 <begin_signature>
+  28:	00108f03          	lb	t5,1(ra)
+  2c:	00000e93          	li	t4,0
+  30:	00300193          	li	gp,3
+  34:	23df1063          	bne	t5,t4,254 <fail>
+
+00000038 <test_4>:
+  38:	00001097          	auipc	ra,0x1
+  3c:	fc808093          	addi	ra,ra,-56 # 1000 <begin_signature>
+  40:	00208f03          	lb	t5,2(ra)
+  44:	ff000e93          	li	t4,-16
+  48:	00400193          	li	gp,4
+  4c:	21df1463          	bne	t5,t4,254 <fail>
+
+00000050 <test_5>:
+  50:	00001097          	auipc	ra,0x1
+  54:	fb008093          	addi	ra,ra,-80 # 1000 <begin_signature>
+  58:	00308f03          	lb	t5,3(ra)
+  5c:	00f00e93          	li	t4,15
+  60:	00500193          	li	gp,5
+  64:	1fdf1863          	bne	t5,t4,254 <fail>
+
+00000068 <test_6>:
+  68:	00001097          	auipc	ra,0x1
+  6c:	f9b08093          	addi	ra,ra,-101 # 1003 <tdat4>
+  70:	ffd08f03          	lb	t5,-3(ra)
+  74:	fff00e93          	li	t4,-1
+  78:	00600193          	li	gp,6
+  7c:	1ddf1c63          	bne	t5,t4,254 <fail>
+
+00000080 <test_7>:
+  80:	00001097          	auipc	ra,0x1
+  84:	f8308093          	addi	ra,ra,-125 # 1003 <tdat4>
+  88:	ffe08f03          	lb	t5,-2(ra)
+  8c:	00000e93          	li	t4,0
+  90:	00700193          	li	gp,7
+  94:	1ddf1063          	bne	t5,t4,254 <fail>
+
+00000098 <test_8>:
+  98:	00001097          	auipc	ra,0x1
+  9c:	f6b08093          	addi	ra,ra,-149 # 1003 <tdat4>
+  a0:	fff08f03          	lb	t5,-1(ra)
+  a4:	ff000e93          	li	t4,-16
+  a8:	00800193          	li	gp,8
+  ac:	1bdf1463          	bne	t5,t4,254 <fail>
+
+000000b0 <test_9>:
+  b0:	00001097          	auipc	ra,0x1
+  b4:	f5308093          	addi	ra,ra,-173 # 1003 <tdat4>
+  b8:	00008f03          	lb	t5,0(ra)
+  bc:	00f00e93          	li	t4,15
+  c0:	00900193          	li	gp,9
+  c4:	19df1863          	bne	t5,t4,254 <fail>
+
+000000c8 <test_10>:
+  c8:	00001097          	auipc	ra,0x1
+  cc:	f3808093          	addi	ra,ra,-200 # 1000 <begin_signature>
+  d0:	fe008093          	addi	ra,ra,-32
+  d4:	02008283          	lb	t0,32(ra)
+  d8:	fff00e93          	li	t4,-1
+  dc:	00a00193          	li	gp,10
+  e0:	17d29a63          	bne	t0,t4,254 <fail>
+
+000000e4 <test_11>:
+  e4:	00001097          	auipc	ra,0x1
+  e8:	f1c08093          	addi	ra,ra,-228 # 1000 <begin_signature>
+  ec:	ffa08093          	addi	ra,ra,-6
+  f0:	00708283          	lb	t0,7(ra)
+  f4:	00000e93          	li	t4,0
+  f8:	00b00193          	li	gp,11
+  fc:	15d29c63          	bne	t0,t4,254 <fail>
+
+00000100 <test_12>:
+ 100:	00c00193          	li	gp,12
+ 104:	00000213          	li	tp,0
+ 108:	00001097          	auipc	ra,0x1
+ 10c:	ef908093          	addi	ra,ra,-263 # 1001 <tdat2>
+ 110:	00108f03          	lb	t5,1(ra)
+ 114:	000f0313          	mv	t1,t5
+ 118:	ff000e93          	li	t4,-16
+ 11c:	13d31c63          	bne	t1,t4,254 <fail>
+ 120:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 124:	00200293          	li	t0,2
+ 128:	fe5210e3          	bne	tp,t0,108 <test_12+0x8>
+
+0000012c <test_13>:
+ 12c:	00d00193          	li	gp,13
+ 130:	00000213          	li	tp,0
+ 134:	00001097          	auipc	ra,0x1
+ 138:	ece08093          	addi	ra,ra,-306 # 1002 <tdat3>
+ 13c:	00108f03          	lb	t5,1(ra)
+ 140:	00000013          	nop
+ 144:	000f0313          	mv	t1,t5
+ 148:	00f00e93          	li	t4,15
+ 14c:	11d31463          	bne	t1,t4,254 <fail>
+ 150:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 154:	00200293          	li	t0,2
+ 158:	fc521ee3          	bne	tp,t0,134 <test_13+0x8>
+
+0000015c <test_14>:
+ 15c:	00e00193          	li	gp,14
+ 160:	00000213          	li	tp,0
+ 164:	00001097          	auipc	ra,0x1
+ 168:	e9c08093          	addi	ra,ra,-356 # 1000 <begin_signature>
+ 16c:	00108f03          	lb	t5,1(ra)
+ 170:	00000013          	nop
+ 174:	00000013          	nop
+ 178:	000f0313          	mv	t1,t5
+ 17c:	00000e93          	li	t4,0
+ 180:	0dd31a63          	bne	t1,t4,254 <fail>
+ 184:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 188:	00200293          	li	t0,2
+ 18c:	fc521ce3          	bne	tp,t0,164 <test_14+0x8>
+
+00000190 <test_15>:
+ 190:	00f00193          	li	gp,15
+ 194:	00000213          	li	tp,0
+ 198:	00001097          	auipc	ra,0x1
+ 19c:	e6908093          	addi	ra,ra,-407 # 1001 <tdat2>
+ 1a0:	00108f03          	lb	t5,1(ra)
+ 1a4:	ff000e93          	li	t4,-16
+ 1a8:	0bdf1663          	bne	t5,t4,254 <fail>
+ 1ac:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1b0:	00200293          	li	t0,2
+ 1b4:	fe5212e3          	bne	tp,t0,198 <test_15+0x8>
+
+000001b8 <test_16>:
+ 1b8:	01000193          	li	gp,16
+ 1bc:	00000213          	li	tp,0
+ 1c0:	00001097          	auipc	ra,0x1
+ 1c4:	e4208093          	addi	ra,ra,-446 # 1002 <tdat3>
+ 1c8:	00000013          	nop
+ 1cc:	00108f03          	lb	t5,1(ra)
+ 1d0:	00f00e93          	li	t4,15
+ 1d4:	09df1063          	bne	t5,t4,254 <fail>
+ 1d8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1dc:	00200293          	li	t0,2
+ 1e0:	fe5210e3          	bne	tp,t0,1c0 <test_16+0x8>
+
+000001e4 <test_17>:
+ 1e4:	01100193          	li	gp,17
+ 1e8:	00000213          	li	tp,0
+ 1ec:	00001097          	auipc	ra,0x1
+ 1f0:	e1408093          	addi	ra,ra,-492 # 1000 <begin_signature>
+ 1f4:	00000013          	nop
+ 1f8:	00000013          	nop
+ 1fc:	00108f03          	lb	t5,1(ra)
+ 200:	00000e93          	li	t4,0
+ 204:	05df1863          	bne	t5,t4,254 <fail>
+ 208:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 20c:	00200293          	li	t0,2
+ 210:	fc521ee3          	bne	tp,t0,1ec <test_17+0x8>
+
+00000214 <test_18>:
+ 214:	00001297          	auipc	t0,0x1
+ 218:	dec28293          	addi	t0,t0,-532 # 1000 <begin_signature>
+ 21c:	00028103          	lb	sp,0(t0)
+ 220:	00200113          	li	sp,2
+ 224:	00200e93          	li	t4,2
+ 228:	01200193          	li	gp,18
+ 22c:	03d11463          	bne	sp,t4,254 <fail>
+
+00000230 <test_19>:
+ 230:	00001297          	auipc	t0,0x1
+ 234:	dd028293          	addi	t0,t0,-560 # 1000 <begin_signature>
+ 238:	00028103          	lb	sp,0(t0)
+ 23c:	00000013          	nop
+ 240:	00200113          	li	sp,2
+ 244:	00200e93          	li	t4,2
+ 248:	01300193          	li	gp,19
+ 24c:	01d11463          	bne	sp,t4,254 <fail>
+ 250:	00301863          	bne	zero,gp,260 <pass>
+
+00000254 <fail>:
+ 254:	00100d13          	li	s10,1
+ 258:	00000d93          	li	s11,0
+
+0000025c <loop_fail>:
+ 25c:	0000006f          	j	25c <loop_fail>
+
+00000260 <pass>:
+ 260:	00100d13          	li	s10,1
+ 264:	00100d93          	li	s11,1
+
+00000268 <loop_pass>:
+ 268:	0000006f          	j	268 <loop_pass>
+	...
+
+Disassembly of section .data:
+
+00001000 <begin_signature>:
+    1000:	                	0xff
+
+00001001 <tdat2>:
+	...
+
+00001002 <tdat3>:
+    1002:	                	addi	a2,sp,988
+
+00001003 <tdat4>:
+    1003:	0000000f          	fence	unknown,unknown
+	...
+
+Disassembly of section .tohost:
+
+00001040 <tohost>:
+	...
+
+00001080 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-lb.verilog

@@ -0,0 +1,50 @@
+@00000000
+13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF 
+03 8F 00 00 93 0E F0 FF 93 01 20 00 63 1C DF 23 
+97 10 00 00 93 80 00 FE 03 8F 10 00 93 0E 00 00 
+93 01 30 00 63 10 DF 23 97 10 00 00 93 80 80 FC 
+03 8F 20 00 93 0E 00 FF 93 01 40 00 63 14 DF 21 
+97 10 00 00 93 80 00 FB 03 8F 30 00 93 0E F0 00 
+93 01 50 00 63 18 DF 1F 97 10 00 00 93 80 B0 F9 
+03 8F D0 FF 93 0E F0 FF 93 01 60 00 63 1C DF 1D 
+97 10 00 00 93 80 30 F8 03 8F E0 FF 93 0E 00 00 
+93 01 70 00 63 10 DF 1D 97 10 00 00 93 80 B0 F6 
+03 8F F0 FF 93 0E 00 FF 93 01 80 00 63 14 DF 1B 
+97 10 00 00 93 80 30 F5 03 8F 00 00 93 0E F0 00 
+93 01 90 00 63 18 DF 19 97 10 00 00 93 80 80 F3 
+93 80 00 FE 83 82 00 02 93 0E F0 FF 93 01 A0 00 
+63 9A D2 17 97 10 00 00 93 80 C0 F1 93 80 A0 FF 
+83 82 70 00 93 0E 00 00 93 01 B0 00 63 9C D2 15 
+93 01 C0 00 13 02 00 00 97 10 00 00 93 80 90 EF 
+03 8F 10 00 13 03 0F 00 93 0E 00 FF 63 1C D3 13 
+13 02 12 00 93 02 20 00 E3 10 52 FE 93 01 D0 00 
+13 02 00 00 97 10 00 00 93 80 E0 EC 03 8F 10 00 
+13 00 00 00 13 03 0F 00 93 0E F0 00 63 14 D3 11 
+13 02 12 00 93 02 20 00 E3 1E 52 FC 93 01 E0 00 
+13 02 00 00 97 10 00 00 93 80 C0 E9 03 8F 10 00 
+13 00 00 00 13 00 00 00 13 03 0F 00 93 0E 00 00 
+63 1A D3 0D 13 02 12 00 93 02 20 00 E3 1C 52 FC 
+93 01 F0 00 13 02 00 00 97 10 00 00 93 80 90 E6 
+03 8F 10 00 93 0E 00 FF 63 16 DF 0B 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 00 01 13 02 00 00 
+97 10 00 00 93 80 20 E4 13 00 00 00 03 8F 10 00 
+93 0E F0 00 63 10 DF 09 13 02 12 00 93 02 20 00 
+E3 10 52 FE 93 01 10 01 13 02 00 00 97 10 00 00 
+93 80 40 E1 13 00 00 00 13 00 00 00 03 8F 10 00 
+93 0E 00 00 63 18 DF 05 13 02 12 00 93 02 20 00 
+E3 1E 52 FC 97 12 00 00 93 82 C2 DE 03 81 02 00 
+13 01 20 00 93 0E 20 00 93 01 20 01 63 14 D1 03 
+97 12 00 00 93 82 02 DD 03 81 02 00 13 00 00 00 
+13 01 20 00 93 0E 20 00 93 01 30 01 63 14 D1 01 
+63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 
+13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00001000
+FF 00 F0 0F 00 00 00 00 00 00 00 00 00 00 00 00 
+@00001040
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-lbu.dump

@@ -0,0 +1,230 @@
+
+generated/rv32ui-p-lbu:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00001097          	auipc	ra,0x1
+   c:	ff808093          	addi	ra,ra,-8 # 1000 <begin_signature>
+  10:	0000cf03          	lbu	t5,0(ra)
+  14:	0ff00e93          	li	t4,255
+  18:	00200193          	li	gp,2
+  1c:	23df1c63          	bne	t5,t4,254 <fail>
+
+00000020 <test_3>:
+  20:	00001097          	auipc	ra,0x1
+  24:	fe008093          	addi	ra,ra,-32 # 1000 <begin_signature>
+  28:	0010cf03          	lbu	t5,1(ra)
+  2c:	00000e93          	li	t4,0
+  30:	00300193          	li	gp,3
+  34:	23df1063          	bne	t5,t4,254 <fail>
+
+00000038 <test_4>:
+  38:	00001097          	auipc	ra,0x1
+  3c:	fc808093          	addi	ra,ra,-56 # 1000 <begin_signature>
+  40:	0020cf03          	lbu	t5,2(ra)
+  44:	0f000e93          	li	t4,240
+  48:	00400193          	li	gp,4
+  4c:	21df1463          	bne	t5,t4,254 <fail>
+
+00000050 <test_5>:
+  50:	00001097          	auipc	ra,0x1
+  54:	fb008093          	addi	ra,ra,-80 # 1000 <begin_signature>
+  58:	0030cf03          	lbu	t5,3(ra)
+  5c:	00f00e93          	li	t4,15
+  60:	00500193          	li	gp,5
+  64:	1fdf1863          	bne	t5,t4,254 <fail>
+
+00000068 <test_6>:
+  68:	00001097          	auipc	ra,0x1
+  6c:	f9b08093          	addi	ra,ra,-101 # 1003 <tdat4>
+  70:	ffd0cf03          	lbu	t5,-3(ra)
+  74:	0ff00e93          	li	t4,255
+  78:	00600193          	li	gp,6
+  7c:	1ddf1c63          	bne	t5,t4,254 <fail>
+
+00000080 <test_7>:
+  80:	00001097          	auipc	ra,0x1
+  84:	f8308093          	addi	ra,ra,-125 # 1003 <tdat4>
+  88:	ffe0cf03          	lbu	t5,-2(ra)
+  8c:	00000e93          	li	t4,0
+  90:	00700193          	li	gp,7
+  94:	1ddf1063          	bne	t5,t4,254 <fail>
+
+00000098 <test_8>:
+  98:	00001097          	auipc	ra,0x1
+  9c:	f6b08093          	addi	ra,ra,-149 # 1003 <tdat4>
+  a0:	fff0cf03          	lbu	t5,-1(ra)
+  a4:	0f000e93          	li	t4,240
+  a8:	00800193          	li	gp,8
+  ac:	1bdf1463          	bne	t5,t4,254 <fail>
+
+000000b0 <test_9>:
+  b0:	00001097          	auipc	ra,0x1
+  b4:	f5308093          	addi	ra,ra,-173 # 1003 <tdat4>
+  b8:	0000cf03          	lbu	t5,0(ra)
+  bc:	00f00e93          	li	t4,15
+  c0:	00900193          	li	gp,9
+  c4:	19df1863          	bne	t5,t4,254 <fail>
+
+000000c8 <test_10>:
+  c8:	00001097          	auipc	ra,0x1
+  cc:	f3808093          	addi	ra,ra,-200 # 1000 <begin_signature>
+  d0:	fe008093          	addi	ra,ra,-32
+  d4:	0200c283          	lbu	t0,32(ra)
+  d8:	0ff00e93          	li	t4,255
+  dc:	00a00193          	li	gp,10
+  e0:	17d29a63          	bne	t0,t4,254 <fail>
+
+000000e4 <test_11>:
+  e4:	00001097          	auipc	ra,0x1
+  e8:	f1c08093          	addi	ra,ra,-228 # 1000 <begin_signature>
+  ec:	ffa08093          	addi	ra,ra,-6
+  f0:	0070c283          	lbu	t0,7(ra)
+  f4:	00000e93          	li	t4,0
+  f8:	00b00193          	li	gp,11
+  fc:	15d29c63          	bne	t0,t4,254 <fail>
+
+00000100 <test_12>:
+ 100:	00c00193          	li	gp,12
+ 104:	00000213          	li	tp,0
+ 108:	00001097          	auipc	ra,0x1
+ 10c:	ef908093          	addi	ra,ra,-263 # 1001 <tdat2>
+ 110:	0010cf03          	lbu	t5,1(ra)
+ 114:	000f0313          	mv	t1,t5
+ 118:	0f000e93          	li	t4,240
+ 11c:	13d31c63          	bne	t1,t4,254 <fail>
+ 120:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 124:	00200293          	li	t0,2
+ 128:	fe5210e3          	bne	tp,t0,108 <test_12+0x8>
+
+0000012c <test_13>:
+ 12c:	00d00193          	li	gp,13
+ 130:	00000213          	li	tp,0
+ 134:	00001097          	auipc	ra,0x1
+ 138:	ece08093          	addi	ra,ra,-306 # 1002 <tdat3>
+ 13c:	0010cf03          	lbu	t5,1(ra)
+ 140:	00000013          	nop
+ 144:	000f0313          	mv	t1,t5
+ 148:	00f00e93          	li	t4,15
+ 14c:	11d31463          	bne	t1,t4,254 <fail>
+ 150:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 154:	00200293          	li	t0,2
+ 158:	fc521ee3          	bne	tp,t0,134 <test_13+0x8>
+
+0000015c <test_14>:
+ 15c:	00e00193          	li	gp,14
+ 160:	00000213          	li	tp,0
+ 164:	00001097          	auipc	ra,0x1
+ 168:	e9c08093          	addi	ra,ra,-356 # 1000 <begin_signature>
+ 16c:	0010cf03          	lbu	t5,1(ra)
+ 170:	00000013          	nop
+ 174:	00000013          	nop
+ 178:	000f0313          	mv	t1,t5
+ 17c:	00000e93          	li	t4,0
+ 180:	0dd31a63          	bne	t1,t4,254 <fail>
+ 184:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 188:	00200293          	li	t0,2
+ 18c:	fc521ce3          	bne	tp,t0,164 <test_14+0x8>
+
+00000190 <test_15>:
+ 190:	00f00193          	li	gp,15
+ 194:	00000213          	li	tp,0
+ 198:	00001097          	auipc	ra,0x1
+ 19c:	e6908093          	addi	ra,ra,-407 # 1001 <tdat2>
+ 1a0:	0010cf03          	lbu	t5,1(ra)
+ 1a4:	0f000e93          	li	t4,240
+ 1a8:	0bdf1663          	bne	t5,t4,254 <fail>
+ 1ac:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1b0:	00200293          	li	t0,2
+ 1b4:	fe5212e3          	bne	tp,t0,198 <test_15+0x8>
+
+000001b8 <test_16>:
+ 1b8:	01000193          	li	gp,16
+ 1bc:	00000213          	li	tp,0
+ 1c0:	00001097          	auipc	ra,0x1
+ 1c4:	e4208093          	addi	ra,ra,-446 # 1002 <tdat3>
+ 1c8:	00000013          	nop
+ 1cc:	0010cf03          	lbu	t5,1(ra)
+ 1d0:	00f00e93          	li	t4,15
+ 1d4:	09df1063          	bne	t5,t4,254 <fail>
+ 1d8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1dc:	00200293          	li	t0,2
+ 1e0:	fe5210e3          	bne	tp,t0,1c0 <test_16+0x8>
+
+000001e4 <test_17>:
+ 1e4:	01100193          	li	gp,17
+ 1e8:	00000213          	li	tp,0
+ 1ec:	00001097          	auipc	ra,0x1
+ 1f0:	e1408093          	addi	ra,ra,-492 # 1000 <begin_signature>
+ 1f4:	00000013          	nop
+ 1f8:	00000013          	nop
+ 1fc:	0010cf03          	lbu	t5,1(ra)
+ 200:	00000e93          	li	t4,0
+ 204:	05df1863          	bne	t5,t4,254 <fail>
+ 208:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 20c:	00200293          	li	t0,2
+ 210:	fc521ee3          	bne	tp,t0,1ec <test_17+0x8>
+
+00000214 <test_18>:
+ 214:	00001297          	auipc	t0,0x1
+ 218:	dec28293          	addi	t0,t0,-532 # 1000 <begin_signature>
+ 21c:	0002c103          	lbu	sp,0(t0)
+ 220:	00200113          	li	sp,2
+ 224:	00200e93          	li	t4,2
+ 228:	01200193          	li	gp,18
+ 22c:	03d11463          	bne	sp,t4,254 <fail>
+
+00000230 <test_19>:
+ 230:	00001297          	auipc	t0,0x1
+ 234:	dd028293          	addi	t0,t0,-560 # 1000 <begin_signature>
+ 238:	0002c103          	lbu	sp,0(t0)
+ 23c:	00000013          	nop
+ 240:	00200113          	li	sp,2
+ 244:	00200e93          	li	t4,2
+ 248:	01300193          	li	gp,19
+ 24c:	01d11463          	bne	sp,t4,254 <fail>
+ 250:	00301863          	bne	zero,gp,260 <pass>
+
+00000254 <fail>:
+ 254:	00100d13          	li	s10,1
+ 258:	00000d93          	li	s11,0
+
+0000025c <loop_fail>:
+ 25c:	0000006f          	j	25c <loop_fail>
+
+00000260 <pass>:
+ 260:	00100d13          	li	s10,1
+ 264:	00100d93          	li	s11,1
+
+00000268 <loop_pass>:
+ 268:	0000006f          	j	268 <loop_pass>
+	...
+
+Disassembly of section .data:
+
+00001000 <begin_signature>:
+    1000:	                	0xff
+
+00001001 <tdat2>:
+	...
+
+00001002 <tdat3>:
+    1002:	                	addi	a2,sp,988
+
+00001003 <tdat4>:
+    1003:	0000000f          	fence	unknown,unknown
+	...
+
+Disassembly of section .tohost:
+
+00001040 <tohost>:
+	...
+
+00001080 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-lbu.verilog

@@ -0,0 +1,50 @@
+@00000000
+13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF 
+03 CF 00 00 93 0E F0 0F 93 01 20 00 63 1C DF 23 
+97 10 00 00 93 80 00 FE 03 CF 10 00 93 0E 00 00 
+93 01 30 00 63 10 DF 23 97 10 00 00 93 80 80 FC 
+03 CF 20 00 93 0E 00 0F 93 01 40 00 63 14 DF 21 
+97 10 00 00 93 80 00 FB 03 CF 30 00 93 0E F0 00 
+93 01 50 00 63 18 DF 1F 97 10 00 00 93 80 B0 F9 
+03 CF D0 FF 93 0E F0 0F 93 01 60 00 63 1C DF 1D 
+97 10 00 00 93 80 30 F8 03 CF E0 FF 93 0E 00 00 
+93 01 70 00 63 10 DF 1D 97 10 00 00 93 80 B0 F6 
+03 CF F0 FF 93 0E 00 0F 93 01 80 00 63 14 DF 1B 
+97 10 00 00 93 80 30 F5 03 CF 00 00 93 0E F0 00 
+93 01 90 00 63 18 DF 19 97 10 00 00 93 80 80 F3 
+93 80 00 FE 83 C2 00 02 93 0E F0 0F 93 01 A0 00 
+63 9A D2 17 97 10 00 00 93 80 C0 F1 93 80 A0 FF 
+83 C2 70 00 93 0E 00 00 93 01 B0 00 63 9C D2 15 
+93 01 C0 00 13 02 00 00 97 10 00 00 93 80 90 EF 
+03 CF 10 00 13 03 0F 00 93 0E 00 0F 63 1C D3 13 
+13 02 12 00 93 02 20 00 E3 10 52 FE 93 01 D0 00 
+13 02 00 00 97 10 00 00 93 80 E0 EC 03 CF 10 00 
+13 00 00 00 13 03 0F 00 93 0E F0 00 63 14 D3 11 
+13 02 12 00 93 02 20 00 E3 1E 52 FC 93 01 E0 00 
+13 02 00 00 97 10 00 00 93 80 C0 E9 03 CF 10 00 
+13 00 00 00 13 00 00 00 13 03 0F 00 93 0E 00 00 
+63 1A D3 0D 13 02 12 00 93 02 20 00 E3 1C 52 FC 
+93 01 F0 00 13 02 00 00 97 10 00 00 93 80 90 E6 
+03 CF 10 00 93 0E 00 0F 63 16 DF 0B 13 02 12 00 
+93 02 20 00 E3 12 52 FE 93 01 00 01 13 02 00 00 
+97 10 00 00 93 80 20 E4 13 00 00 00 03 CF 10 00 
+93 0E F0 00 63 10 DF 09 13 02 12 00 93 02 20 00 
+E3 10 52 FE 93 01 10 01 13 02 00 00 97 10 00 00 
+93 80 40 E1 13 00 00 00 13 00 00 00 03 CF 10 00 
+93 0E 00 00 63 18 DF 05 13 02 12 00 93 02 20 00 
+E3 1E 52 FC 97 12 00 00 93 82 C2 DE 03 C1 02 00 
+13 01 20 00 93 0E 20 00 93 01 20 01 63 14 D1 03 
+97 12 00 00 93 82 02 DD 03 C1 02 00 13 00 00 00 
+13 01 20 00 93 0E 20 00 93 01 30 01 63 14 D1 01 
+63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 
+13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00001000
+FF 00 F0 0F 00 00 00 00 00 00 00 00 00 00 00 00 
+@00001040
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-lh.dump

@@ -0,0 +1,240 @@
+
+generated/rv32ui-p-lh:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00001097          	auipc	ra,0x1
+   c:	ff808093          	addi	ra,ra,-8 # 1000 <begin_signature>
+  10:	00009f03          	lh	t5,0(ra)
+  14:	0ff00e93          	li	t4,255
+  18:	00200193          	li	gp,2
+  1c:	25df1c63          	bne	t5,t4,274 <fail>
+
+00000020 <test_3>:
+  20:	00001097          	auipc	ra,0x1
+  24:	fe008093          	addi	ra,ra,-32 # 1000 <begin_signature>
+  28:	00209f03          	lh	t5,2(ra)
+  2c:	f0000e93          	li	t4,-256
+  30:	00300193          	li	gp,3
+  34:	25df1063          	bne	t5,t4,274 <fail>
+
+00000038 <test_4>:
+  38:	00001097          	auipc	ra,0x1
+  3c:	fc808093          	addi	ra,ra,-56 # 1000 <begin_signature>
+  40:	00409f03          	lh	t5,4(ra)
+  44:	00001eb7          	lui	t4,0x1
+  48:	ff0e8e93          	addi	t4,t4,-16 # ff0 <loop_pass+0xd68>
+  4c:	00400193          	li	gp,4
+  50:	23df1263          	bne	t5,t4,274 <fail>
+
+00000054 <test_5>:
+  54:	00001097          	auipc	ra,0x1
+  58:	fac08093          	addi	ra,ra,-84 # 1000 <begin_signature>
+  5c:	00609f03          	lh	t5,6(ra)
+  60:	fffffeb7          	lui	t4,0xfffff
+  64:	00fe8e93          	addi	t4,t4,15 # fffff00f <_end+0xffffdf87>
+  68:	00500193          	li	gp,5
+  6c:	21df1463          	bne	t5,t4,274 <fail>
+
+00000070 <test_6>:
+  70:	00001097          	auipc	ra,0x1
+  74:	f9608093          	addi	ra,ra,-106 # 1006 <tdat4>
+  78:	ffa09f03          	lh	t5,-6(ra)
+  7c:	0ff00e93          	li	t4,255
+  80:	00600193          	li	gp,6
+  84:	1fdf1863          	bne	t5,t4,274 <fail>
+
+00000088 <test_7>:
+  88:	00001097          	auipc	ra,0x1
+  8c:	f7e08093          	addi	ra,ra,-130 # 1006 <tdat4>
+  90:	ffc09f03          	lh	t5,-4(ra)
+  94:	f0000e93          	li	t4,-256
+  98:	00700193          	li	gp,7
+  9c:	1ddf1c63          	bne	t5,t4,274 <fail>
+
+000000a0 <test_8>:
+  a0:	00001097          	auipc	ra,0x1
+  a4:	f6608093          	addi	ra,ra,-154 # 1006 <tdat4>
+  a8:	ffe09f03          	lh	t5,-2(ra)
+  ac:	00001eb7          	lui	t4,0x1
+  b0:	ff0e8e93          	addi	t4,t4,-16 # ff0 <loop_pass+0xd68>
+  b4:	00800193          	li	gp,8
+  b8:	1bdf1e63          	bne	t5,t4,274 <fail>
+
+000000bc <test_9>:
+  bc:	00001097          	auipc	ra,0x1
+  c0:	f4a08093          	addi	ra,ra,-182 # 1006 <tdat4>
+  c4:	00009f03          	lh	t5,0(ra)
+  c8:	fffffeb7          	lui	t4,0xfffff
+  cc:	00fe8e93          	addi	t4,t4,15 # fffff00f <_end+0xffffdf87>
+  d0:	00900193          	li	gp,9
+  d4:	1bdf1063          	bne	t5,t4,274 <fail>
+
+000000d8 <test_10>:
+  d8:	00001097          	auipc	ra,0x1
+  dc:	f2808093          	addi	ra,ra,-216 # 1000 <begin_signature>
+  e0:	fe008093          	addi	ra,ra,-32
+  e4:	02009283          	lh	t0,32(ra)
+  e8:	0ff00e93          	li	t4,255
+  ec:	00a00193          	li	gp,10
+  f0:	19d29263          	bne	t0,t4,274 <fail>
+
+000000f4 <test_11>:
+  f4:	00001097          	auipc	ra,0x1
+  f8:	f0c08093          	addi	ra,ra,-244 # 1000 <begin_signature>
+  fc:	ffb08093          	addi	ra,ra,-5
+ 100:	00709283          	lh	t0,7(ra)
+ 104:	f0000e93          	li	t4,-256
+ 108:	00b00193          	li	gp,11
+ 10c:	17d29463          	bne	t0,t4,274 <fail>
+
+00000110 <test_12>:
+ 110:	00c00193          	li	gp,12
+ 114:	00000213          	li	tp,0
+ 118:	00001097          	auipc	ra,0x1
+ 11c:	eea08093          	addi	ra,ra,-278 # 1002 <tdat2>
+ 120:	00209f03          	lh	t5,2(ra)
+ 124:	000f0313          	mv	t1,t5
+ 128:	00001eb7          	lui	t4,0x1
+ 12c:	ff0e8e93          	addi	t4,t4,-16 # ff0 <loop_pass+0xd68>
+ 130:	15d31263          	bne	t1,t4,274 <fail>
+ 134:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 138:	00200293          	li	t0,2
+ 13c:	fc521ee3          	bne	tp,t0,118 <test_12+0x8>
+
+00000140 <test_13>:
+ 140:	00d00193          	li	gp,13
+ 144:	00000213          	li	tp,0
+ 148:	00001097          	auipc	ra,0x1
+ 14c:	ebc08093          	addi	ra,ra,-324 # 1004 <tdat3>
+ 150:	00209f03          	lh	t5,2(ra)
+ 154:	00000013          	nop
+ 158:	000f0313          	mv	t1,t5
+ 15c:	fffffeb7          	lui	t4,0xfffff
+ 160:	00fe8e93          	addi	t4,t4,15 # fffff00f <_end+0xffffdf87>
+ 164:	11d31863          	bne	t1,t4,274 <fail>
+ 168:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 16c:	00200293          	li	t0,2
+ 170:	fc521ce3          	bne	tp,t0,148 <test_13+0x8>
+
+00000174 <test_14>:
+ 174:	00e00193          	li	gp,14
+ 178:	00000213          	li	tp,0
+ 17c:	00001097          	auipc	ra,0x1
+ 180:	e8408093          	addi	ra,ra,-380 # 1000 <begin_signature>
+ 184:	00209f03          	lh	t5,2(ra)
+ 188:	00000013          	nop
+ 18c:	00000013          	nop
+ 190:	000f0313          	mv	t1,t5
+ 194:	f0000e93          	li	t4,-256
+ 198:	0dd31e63          	bne	t1,t4,274 <fail>
+ 19c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1a0:	00200293          	li	t0,2
+ 1a4:	fc521ce3          	bne	tp,t0,17c <test_14+0x8>
+
+000001a8 <test_15>:
+ 1a8:	00f00193          	li	gp,15
+ 1ac:	00000213          	li	tp,0
+ 1b0:	00001097          	auipc	ra,0x1
+ 1b4:	e5208093          	addi	ra,ra,-430 # 1002 <tdat2>
+ 1b8:	00209f03          	lh	t5,2(ra)
+ 1bc:	00001eb7          	lui	t4,0x1
+ 1c0:	ff0e8e93          	addi	t4,t4,-16 # ff0 <loop_pass+0xd68>
+ 1c4:	0bdf1863          	bne	t5,t4,274 <fail>
+ 1c8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1cc:	00200293          	li	t0,2
+ 1d0:	fe5210e3          	bne	tp,t0,1b0 <test_15+0x8>
+
+000001d4 <test_16>:
+ 1d4:	01000193          	li	gp,16
+ 1d8:	00000213          	li	tp,0
+ 1dc:	00001097          	auipc	ra,0x1
+ 1e0:	e2808093          	addi	ra,ra,-472 # 1004 <tdat3>
+ 1e4:	00000013          	nop
+ 1e8:	00209f03          	lh	t5,2(ra)
+ 1ec:	fffffeb7          	lui	t4,0xfffff
+ 1f0:	00fe8e93          	addi	t4,t4,15 # fffff00f <_end+0xffffdf87>
+ 1f4:	09df1063          	bne	t5,t4,274 <fail>
+ 1f8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1fc:	00200293          	li	t0,2
+ 200:	fc521ee3          	bne	tp,t0,1dc <test_16+0x8>
+
+00000204 <test_17>:
+ 204:	01100193          	li	gp,17
+ 208:	00000213          	li	tp,0
+ 20c:	00001097          	auipc	ra,0x1
+ 210:	df408093          	addi	ra,ra,-524 # 1000 <begin_signature>
+ 214:	00000013          	nop
+ 218:	00000013          	nop
+ 21c:	00209f03          	lh	t5,2(ra)
+ 220:	f0000e93          	li	t4,-256
+ 224:	05df1863          	bne	t5,t4,274 <fail>
+ 228:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 22c:	00200293          	li	t0,2
+ 230:	fc521ee3          	bne	tp,t0,20c <test_17+0x8>
+
+00000234 <test_18>:
+ 234:	00001297          	auipc	t0,0x1
+ 238:	dcc28293          	addi	t0,t0,-564 # 1000 <begin_signature>
+ 23c:	00029103          	lh	sp,0(t0)
+ 240:	00200113          	li	sp,2
+ 244:	00200e93          	li	t4,2
+ 248:	01200193          	li	gp,18
+ 24c:	03d11463          	bne	sp,t4,274 <fail>
+
+00000250 <test_19>:
+ 250:	00001297          	auipc	t0,0x1
+ 254:	db028293          	addi	t0,t0,-592 # 1000 <begin_signature>
+ 258:	00029103          	lh	sp,0(t0)
+ 25c:	00000013          	nop
+ 260:	00200113          	li	sp,2
+ 264:	00200e93          	li	t4,2
+ 268:	01300193          	li	gp,19
+ 26c:	01d11463          	bne	sp,t4,274 <fail>
+ 270:	00301863          	bne	zero,gp,280 <pass>
+
+00000274 <fail>:
+ 274:	00100d13          	li	s10,1
+ 278:	00000d93          	li	s11,0
+
+0000027c <loop_fail>:
+ 27c:	0000006f          	j	27c <loop_fail>
+
+00000280 <pass>:
+ 280:	00100d13          	li	s10,1
+ 284:	00100d93          	li	s11,1
+
+00000288 <loop_pass>:
+ 288:	0000006f          	j	288 <loop_pass>
+	...
+
+Disassembly of section .data:
+
+00001000 <begin_signature>:
+    1000:	00ff                	0xff
+
+00001002 <tdat2>:
+    1002:	ff00                	fsw	fs0,56(a4)
+
+00001004 <tdat3>:
+    1004:	0ff0                	addi	a2,sp,988
+
+00001006 <tdat4>:
+    1006:	0000f00f          	0xf00f
+    100a:	0000                	unimp
+    100c:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001040 <tohost>:
+	...
+
+00001080 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-lh.verilog

@@ -0,0 +1,54 @@
+@00000000
+13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF 
+03 9F 00 00 93 0E F0 0F 93 01 20 00 63 1C DF 25 
+97 10 00 00 93 80 00 FE 03 9F 20 00 93 0E 00 F0 
+93 01 30 00 63 10 DF 25 97 10 00 00 93 80 80 FC 
+03 9F 40 00 B7 1E 00 00 93 8E 0E FF 93 01 40 00 
+63 12 DF 23 97 10 00 00 93 80 C0 FA 03 9F 60 00 
+B7 FE FF FF 93 8E FE 00 93 01 50 00 63 14 DF 21 
+97 10 00 00 93 80 60 F9 03 9F A0 FF 93 0E F0 0F 
+93 01 60 00 63 18 DF 1F 97 10 00 00 93 80 E0 F7 
+03 9F C0 FF 93 0E 00 F0 93 01 70 00 63 1C DF 1D 
+97 10 00 00 93 80 60 F6 03 9F E0 FF B7 1E 00 00 
+93 8E 0E FF 93 01 80 00 63 1E DF 1B 97 10 00 00 
+93 80 A0 F4 03 9F 00 00 B7 FE FF FF 93 8E FE 00 
+93 01 90 00 63 10 DF 1B 97 10 00 00 93 80 80 F2 
+93 80 00 FE 83 92 00 02 93 0E F0 0F 93 01 A0 00 
+63 92 D2 19 97 10 00 00 93 80 C0 F0 93 80 B0 FF 
+83 92 70 00 93 0E 00 F0 93 01 B0 00 63 94 D2 17 
+93 01 C0 00 13 02 00 00 97 10 00 00 93 80 A0 EE 
+03 9F 20 00 13 03 0F 00 B7 1E 00 00 93 8E 0E FF 
+63 12 D3 15 13 02 12 00 93 02 20 00 E3 1E 52 FC 
+93 01 D0 00 13 02 00 00 97 10 00 00 93 80 C0 EB 
+03 9F 20 00 13 00 00 00 13 03 0F 00 B7 FE FF FF 
+93 8E FE 00 63 18 D3 11 13 02 12 00 93 02 20 00 
+E3 1C 52 FC 93 01 E0 00 13 02 00 00 97 10 00 00 
+93 80 40 E8 03 9F 20 00 13 00 00 00 13 00 00 00 
+13 03 0F 00 93 0E 00 F0 63 1E D3 0D 13 02 12 00 
+93 02 20 00 E3 1C 52 FC 93 01 F0 00 13 02 00 00 
+97 10 00 00 93 80 20 E5 03 9F 20 00 B7 1E 00 00 
+93 8E 0E FF 63 18 DF 0B 13 02 12 00 93 02 20 00 
+E3 10 52 FE 93 01 00 01 13 02 00 00 97 10 00 00 
+93 80 80 E2 13 00 00 00 03 9F 20 00 B7 FE FF FF 
+93 8E FE 00 63 10 DF 09 13 02 12 00 93 02 20 00 
+E3 1E 52 FC 93 01 10 01 13 02 00 00 97 10 00 00 
+93 80 40 DF 13 00 00 00 13 00 00 00 03 9F 20 00 
+93 0E 00 F0 63 18 DF 05 13 02 12 00 93 02 20 00 
+E3 1E 52 FC 97 12 00 00 93 82 C2 DC 03 91 02 00 
+13 01 20 00 93 0E 20 00 93 01 20 01 63 14 D1 03 
+97 12 00 00 93 82 02 DB 03 91 02 00 13 00 00 00 
+13 01 20 00 93 0E 20 00 93 01 30 01 63 14 D1 01 
+63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 
+13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00001000
+FF 00 00 FF F0 0F 0F F0 00 00 00 00 00 00 00 00 
+@00001040
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 

tests/isa/generated/rv32ui-p-lhu.dump

@@ -0,0 +1,245 @@
+
+generated/rv32ui-p-lhu:     file format elf32-littleriscv
+
+
+Disassembly of section .text.init:
+
+00000000 <_start>:
+   0:	00000d13          	li	s10,0
+   4:	00000d93          	li	s11,0
+
+00000008 <test_2>:
+   8:	00001097          	auipc	ra,0x1
+   c:	ff808093          	addi	ra,ra,-8 # 1000 <begin_signature>
+  10:	0000df03          	lhu	t5,0(ra)
+  14:	0ff00e93          	li	t4,255
+  18:	00200193          	li	gp,2
+  1c:	27df1663          	bne	t5,t4,288 <fail>
+
+00000020 <test_3>:
+  20:	00001097          	auipc	ra,0x1
+  24:	fe008093          	addi	ra,ra,-32 # 1000 <begin_signature>
+  28:	0020df03          	lhu	t5,2(ra)
+  2c:	00010eb7          	lui	t4,0x10
+  30:	f00e8e93          	addi	t4,t4,-256 # ff00 <_end+0xee78>
+  34:	00300193          	li	gp,3
+  38:	25df1863          	bne	t5,t4,288 <fail>
+
+0000003c <test_4>:
+  3c:	00001097          	auipc	ra,0x1
+  40:	fc408093          	addi	ra,ra,-60 # 1000 <begin_signature>
+  44:	0040df03          	lhu	t5,4(ra)
+  48:	00001eb7          	lui	t4,0x1
+  4c:	ff0e8e93          	addi	t4,t4,-16 # ff0 <loop_pass+0xd54>
+  50:	00400193          	li	gp,4
+  54:	23df1a63          	bne	t5,t4,288 <fail>
+
+00000058 <test_5>:
+  58:	00001097          	auipc	ra,0x1
+  5c:	fa808093          	addi	ra,ra,-88 # 1000 <begin_signature>
+  60:	0060df03          	lhu	t5,6(ra)
+  64:	0000feb7          	lui	t4,0xf
+  68:	00fe8e93          	addi	t4,t4,15 # f00f <_end+0xdf87>
+  6c:	00500193          	li	gp,5
+  70:	21df1c63          	bne	t5,t4,288 <fail>
+
+00000074 <test_6>:
+  74:	00001097          	auipc	ra,0x1
+  78:	f9208093          	addi	ra,ra,-110 # 1006 <tdat4>
+  7c:	ffa0df03          	lhu	t5,-6(ra)
+  80:	0ff00e93          	li	t4,255
+  84:	00600193          	li	gp,6
+  88:	21df1063          	bne	t5,t4,288 <fail>
+
+0000008c <test_7>:
+  8c:	00001097          	auipc	ra,0x1
+  90:	f7a08093          	addi	ra,ra,-134 # 1006 <tdat4>
+  94:	ffc0df03          	lhu	t5,-4(ra)
+  98:	00010eb7          	lui	t4,0x10
+  9c:	f00e8e93          	addi	t4,t4,-256 # ff00 <_end+0xee78>
+  a0:	00700193          	li	gp,7
+  a4:	1fdf1263          	bne	t5,t4,288 <fail>
+
+000000a8 <test_8>:
+  a8:	00001097          	auipc	ra,0x1
+  ac:	f5e08093          	addi	ra,ra,-162 # 1006 <tdat4>
+  b0:	ffe0df03          	lhu	t5,-2(ra)
+  b4:	00001eb7          	lui	t4,0x1
+  b8:	ff0e8e93          	addi	t4,t4,-16 # ff0 <loop_pass+0xd54>
+  bc:	00800193          	li	gp,8
+  c0:	1ddf1463          	bne	t5,t4,288 <fail>
+
+000000c4 <test_9>:
+  c4:	00001097          	auipc	ra,0x1
+  c8:	f4208093          	addi	ra,ra,-190 # 1006 <tdat4>
+  cc:	0000df03          	lhu	t5,0(ra)
+  d0:	0000feb7          	lui	t4,0xf
+  d4:	00fe8e93          	addi	t4,t4,15 # f00f <_end+0xdf87>
+  d8:	00900193          	li	gp,9
+  dc:	1bdf1663          	bne	t5,t4,288 <fail>
+
+000000e0 <test_10>:
+  e0:	00001097          	auipc	ra,0x1
+  e4:	f2008093          	addi	ra,ra,-224 # 1000 <begin_signature>
+  e8:	fe008093          	addi	ra,ra,-32
+  ec:	0200d283          	lhu	t0,32(ra)
+  f0:	0ff00e93          	li	t4,255
+  f4:	00a00193          	li	gp,10
+  f8:	19d29863          	bne	t0,t4,288 <fail>
+
+000000fc <test_11>:
+  fc:	00001097          	auipc	ra,0x1
+ 100:	f0408093          	addi	ra,ra,-252 # 1000 <begin_signature>
+ 104:	ffb08093          	addi	ra,ra,-5
+ 108:	0070d283          	lhu	t0,7(ra)
+ 10c:	00010eb7          	lui	t4,0x10
+ 110:	f00e8e93          	addi	t4,t4,-256 # ff00 <_end+0xee78>
+ 114:	00b00193          	li	gp,11
+ 118:	17d29863          	bne	t0,t4,288 <fail>
+
+0000011c <test_12>:
+ 11c:	00c00193          	li	gp,12
+ 120:	00000213          	li	tp,0
+ 124:	00001097          	auipc	ra,0x1
+ 128:	ede08093          	addi	ra,ra,-290 # 1002 <tdat2>
+ 12c:	0020df03          	lhu	t5,2(ra)
+ 130:	000f0313          	mv	t1,t5
+ 134:	00001eb7          	lui	t4,0x1
+ 138:	ff0e8e93          	addi	t4,t4,-16 # ff0 <loop_pass+0xd54>
+ 13c:	15d31663          	bne	t1,t4,288 <fail>
+ 140:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 144:	00200293          	li	t0,2
+ 148:	fc521ee3          	bne	tp,t0,124 <test_12+0x8>
+
+0000014c <test_13>:
+ 14c:	00d00193          	li	gp,13
+ 150:	00000213          	li	tp,0
+ 154:	00001097          	auipc	ra,0x1
+ 158:	eb008093          	addi	ra,ra,-336 # 1004 <tdat3>
+ 15c:	0020df03          	lhu	t5,2(ra)
+ 160:	00000013          	nop
+ 164:	000f0313          	mv	t1,t5
+ 168:	0000feb7          	lui	t4,0xf
+ 16c:	00fe8e93          	addi	t4,t4,15 # f00f <_end+0xdf87>
+ 170:	11d31c63          	bne	t1,t4,288 <fail>
+ 174:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 178:	00200293          	li	t0,2
+ 17c:	fc521ce3          	bne	tp,t0,154 <test_13+0x8>
+
+00000180 <test_14>:
+ 180:	00e00193          	li	gp,14
+ 184:	00000213          	li	tp,0
+ 188:	00001097          	auipc	ra,0x1
+ 18c:	e7808093          	addi	ra,ra,-392 # 1000 <begin_signature>
+ 190:	0020df03          	lhu	t5,2(ra)
+ 194:	00000013          	nop
+ 198:	00000013          	nop
+ 19c:	000f0313          	mv	t1,t5
+ 1a0:	00010eb7          	lui	t4,0x10
+ 1a4:	f00e8e93          	addi	t4,t4,-256 # ff00 <_end+0xee78>
+ 1a8:	0fd31063          	bne	t1,t4,288 <fail>
+ 1ac:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1b0:	00200293          	li	t0,2
+ 1b4:	fc521ae3          	bne	tp,t0,188 <test_14+0x8>
+
+000001b8 <test_15>:
+ 1b8:	00f00193          	li	gp,15
+ 1bc:	00000213          	li	tp,0
+ 1c0:	00001097          	auipc	ra,0x1
+ 1c4:	e4208093          	addi	ra,ra,-446 # 1002 <tdat2>
+ 1c8:	0020df03          	lhu	t5,2(ra)
+ 1cc:	00001eb7          	lui	t4,0x1
+ 1d0:	ff0e8e93          	addi	t4,t4,-16 # ff0 <loop_pass+0xd54>
+ 1d4:	0bdf1a63          	bne	t5,t4,288 <fail>
+ 1d8:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 1dc:	00200293          	li	t0,2
+ 1e0:	fe5210e3          	bne	tp,t0,1c0 <test_15+0x8>
+
+000001e4 <test_16>:
+ 1e4:	01000193          	li	gp,16
+ 1e8:	00000213          	li	tp,0
+ 1ec:	00001097          	auipc	ra,0x1
+ 1f0:	e1808093          	addi	ra,ra,-488 # 1004 <tdat3>
+ 1f4:	00000013          	nop
+ 1f8:	0020df03          	lhu	t5,2(ra)
+ 1fc:	0000feb7          	lui	t4,0xf
+ 200:	00fe8e93          	addi	t4,t4,15 # f00f <_end+0xdf87>
+ 204:	09df1263          	bne	t5,t4,288 <fail>
+ 208:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 20c:	00200293          	li	t0,2
+ 210:	fc521ee3          	bne	tp,t0,1ec <test_16+0x8>
+
+00000214 <test_17>:
+ 214:	01100193          	li	gp,17
+ 218:	00000213          	li	tp,0
+ 21c:	00001097          	auipc	ra,0x1
+ 220:	de408093          	addi	ra,ra,-540 # 1000 <begin_signature>
+ 224:	00000013          	nop
+ 228:	00000013          	nop
+ 22c:	0020df03          	lhu	t5,2(ra)
+ 230:	00010eb7          	lui	t4,0x10
+ 234:	f00e8e93          	addi	t4,t4,-256 # ff00 <_end+0xee78>
+ 238:	05df1863          	bne	t5,t4,288 <fail>
+ 23c:	00120213          	addi	tp,tp,1 # 1 <_start+0x1>
+ 240:	00200293          	li	t0,2
+ 244:	fc521ce3          	bne	tp,t0,21c <test_17+0x8>
+
+00000248 <test_18>:
+ 248:	00001297          	auipc	t0,0x1
+ 24c:	db828293          	addi	t0,t0,-584 # 1000 <begin_signature>
+ 250:	0002d103          	lhu	sp,0(t0)
+ 254:	00200113          	li	sp,2
+ 258:	00200e93          	li	t4,2
+ 25c:	01200193          	li	gp,18
+ 260:	03d11463          	bne	sp,t4,288 <fail>
+
+00000264 <test_19>:
+ 264:	00001297          	auipc	t0,0x1
+ 268:	d9c28293          	addi	t0,t0,-612 # 1000 <begin_signature>
+ 26c:	0002d103          	lhu	sp,0(t0)
+ 270:	00000013          	nop
+ 274:	00200113          	li	sp,2
+ 278:	00200e93          	li	t4,2
+ 27c:	01300193          	li	gp,19
+ 280:	01d11463          	bne	sp,t4,288 <fail>
+ 284:	00301863          	bne	zero,gp,294 <pass>
+
+00000288 <fail>:
+ 288:	00100d13          	li	s10,1
+ 28c:	00000d93          	li	s11,0
+
+00000290 <loop_fail>:
+ 290:	0000006f          	j	290 <loop_fail>
+
+00000294 <pass>:
+ 294:	00100d13          	li	s10,1
+ 298:	00100d93          	li	s11,1
+
+0000029c <loop_pass>:
+ 29c:	0000006f          	j	29c <loop_pass>
+	...
+
+Disassembly of section .data:
+
+00001000 <begin_signature>:
+    1000:	00ff                	0xff
+
+00001002 <tdat2>:
+    1002:	ff00                	fsw	fs0,56(a4)
+
+00001004 <tdat3>:
+    1004:	0ff0                	addi	a2,sp,988
+
+00001006 <tdat4>:
+    1006:	0000f00f          	0xf00f
+    100a:	0000                	unimp
+    100c:	0000                	unimp
+	...
+
+Disassembly of section .tohost:
+
+00001040 <tohost>:
+	...
+
+00001080 <fromhost>:
+	...

tests/isa/generated/rv32ui-p-lhu.verilog

@@ -0,0 +1,54 @@
+@00000000
+13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF 
+03 DF 00 00 93 0E F0 0F 93 01 20 00 63 16 DF 27 
+97 10 00 00 93 80 00 FE 03 DF 20 00 B7 0E 01 00 
+93 8E 0E F0 93 01 30 00 63 18 DF 25 97 10 00 00 
+93 80 40 FC 03 DF 40 00 B7 1E 00 00 93 8E 0E FF 
+93 01 40 00 63 1A DF 23 97 10 00 00 93 80 80 FA 
+03 DF 60 00 B7 FE 00 00 93 8E FE 00 93 01 50 00 
+63 1C DF 21 97 10 00 00 93 80 20 F9 03 DF A0 FF 
+93 0E F0 0F 93 01 60 00 63 10 DF 21 97 10 00 00 
+93 80 A0 F7 03 DF C0 FF B7 0E 01 00 93 8E 0E F0 
+93 01 70 00 63 12 DF 1F 97 10 00 00 93 80 E0 F5 
+03 DF E0 FF B7 1E 00 00 93 8E 0E FF 93 01 80 00 
+63 14 DF 1D 97 10 00 00 93 80 20 F4 03 DF 00 00 
+B7 FE 00 00 93 8E FE 00 93 01 90 00 63 16 DF 1B 
+97 10 00 00 93 80 00 F2 93 80 00 FE 83 D2 00 02 
+93 0E F0 0F 93 01 A0 00 63 98 D2 19 97 10 00 00 
+93 80 40 F0 93 80 B0 FF 83 D2 70 00 B7 0E 01 00 
+93 8E 0E F0 93 01 B0 00 63 98 D2 17 93 01 C0 00 
+13 02 00 00 97 10 00 00 93 80 E0 ED 03 DF 20 00 
+13 03 0F 00 B7 1E 00 00 93 8E 0E FF 63 16 D3 15 
+13 02 12 00 93 02 20 00 E3 1E 52 FC 93 01 D0 00 
+13 02 00 00 97 10 00 00 93 80 00 EB 03 DF 20 00 
+13 00 00 00 13 03 0F 00 B7 FE 00 00 93 8E FE 00 
+63 1C D3 11 13 02 12 00 93 02 20 00 E3 1C 52 FC 
+93 01 E0 00 13 02 00 00 97 10 00 00 93 80 80 E7 
+03 DF 20 00 13 00 00 00 13 00 00 00 13 03 0F 00 
+B7 0E 01 00 93 8E 0E F0 63 10 D3 0F 13 02 12 00 
+93 02 20 00 E3 1A 52 FC 93 01 F0 00 13 02 00 00 
+97 10 00 00 93 80 20 E4 03 DF 20 00 B7 1E 00 00 
+93 8E 0E FF 63 1A DF 0B 13 02 12 00 93 02 20 00 
+E3 10 52 FE 93 01 00 01 13 02 00 00 97 10 00 00 
+93 80 80 E1 13 00 00 00 03 DF 20 00 B7 FE 00 00 
+93 8E FE 00 63 12 DF 09 13 02 12 00 93 02 20 00 
+E3 1E 52 FC 93 01 10 01 13 02 00 00 97 10 00 00 
+93 80 40 DE 13 00 00 00 13 00 00 00 03 DF 20 00 
+B7 0E 01 00 93 8E 0E F0 63 18 DF 05 13 02 12 00 
+93 02 20 00 E3 1C 52 FC 97 12 00 00 93 82 82 DB 
+03 D1 02 00 13 01 20 00 93 0E 20 00 93 01 20 01 
+63 14 D1 03 97 12 00 00 93 82 C2 D9 03 D1 02 00 
+13 00 00 00 13 01 20 00 93 0E 20 00 93 01 30 01 
+63 14 D1 01 63 18 30 00 13 0D 10 00 93 0D 00 00 
+6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 
+@00001000
+FF 00 00 FF F0 0F 0F F0 00 00 00 00 00 00 00 00 
+@00001040
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00