diff --git a/.gitignore b/.gitignore index c6127b3..8750c35 100644 --- a/.gitignore +++ b/.gitignore @@ -1,52 +1,7 @@ -# Prerequisites -*.d - # Object files *.o *.ko *.obj *.elf -# Linker output -*.ilk -*.map -*.exp - -# Precompiled Headers -*.gch -*.pch - -# Libraries -*.lib -*.a -*.la -*.lo - -# Shared objects (inc. Windows DLLs) -*.dll -*.so -*.so.* -*.dylib - -# Executables -*.exe -*.out -*.app -*.i*86 -*.x86_64 -*.hex - -# Debug files -*.dSYM/ -*.su -*.idb -*.pdb - -# Kernel Module Compile Results -*.mod* -*.cmd -.tmp_versions/ -modules.order -Module.symvers -Mkfile.old -dkms.conf +tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64 \ No newline at end of file diff --git a/LICENSE b/LICENSE index 261eeb9..203e340 100644 --- a/LICENSE +++ b/LICENSE @@ -1,3 +1,4 @@ + Apache License Version 2.0, January 2004 http://www.apache.org/licenses/ @@ -186,7 +187,7 @@ same "printed page" as the copyright notice for easier identification within third-party archives. - Copyright [yyyy] [name of copyright owner] + Copyright Blue Liang, liangkangnan@163.com Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/README.en.md b/README.en.md index 4dfd61d..918fc31 100644 --- a/README.en.md +++ b/README.en.md @@ -1,36 +1,4 @@ -# tinyriscv +# tinyriscv #### Description -从零开始写的极简、非常易懂的RISC-V处理器核。 - -#### Software Architecture -Software architecture description - -#### Installation - -1. xxxx -2. xxxx -3. xxxx - -#### Instructions - -1. xxxx -2. xxxx -3. xxxx - -#### Contribution - -1. Fork the repository -2. Create Feat_xxx branch -3. Commit your code -4. Create Pull Request - - -#### Gitee Feature - -1. You can use Readme\_XXX.md to support different languages, such as Readme\_en.md, Readme\_zh.md -2. Gitee blog [blog.gitee.com](https://blog.gitee.com) -3. Explore open source project [https://gitee.com/explore](https://gitee.com/explore) -4. The most valuable open source project [GVP](https://gitee.com/gvp) -5. The manual of Gitee [https://gitee.com/help](https://gitee.com/help) -6. The most popular members [https://gitee.com/gitee-stars/](https://gitee.com/gitee-stars/) +opensource RISC-V core diff --git a/README.md b/README.md index feac335..1da7580 100644 --- a/README.md +++ b/README.md @@ -1,37 +1,65 @@ -# tinyriscv +###1.初衷 -#### 介绍 -从零开始写的极简、非常易懂的RISC-V处理器核。 +本开源项目的初衷是本人想入门riscv，熟悉riscv的指令内容和汇编语法。 -#### 软件架构 -软件架构说明 +本人对riscv很感兴趣，很看好riscv的发展前景，觉得riscv就是cpu界中的linux。由于riscv是这两年才开始迅速发展的，因此关于riscv的学习参考资料目前还很少，特别是适合入门的资料，因此学习起来进度很缓慢，于是萌生了自己从零开始写riscv处理器核的想法。 +本人是一名fpga小白，为了快速入门、深入掌握riscv，我开始了学习fpga和verilog的"艰难"历程。我工作的内容是和嵌入式软件相关的，平时根本不会接触到fpga，也不会用到riscv，因此只能用业余时间来学习riscv，在经过断断续续学习fpga和verilog一个多月后，总算有点成果了，也即本项目。 -#### 安装教程 +网上有不少关于riscv的开源项目，但是大多都写得很"高深"，对于我这种小白来说学习起来是非常吃力的，不太适合入门。本项目目前的代码量非常少，是很简单易懂的，对于想入门riscv的同学来说是一个很好的参考，希望能吸引更多的同学能够参与到riscv的学习中来，促进riscv的发展，如果能起到抛砖引玉的作用的话那就更好了，也许说是砖的话或者有点夸大了，但哪怕是起到一颗沙子的作用，也就足矣了。 -1. xxxx -2. xxxx -3. xxxx +###2.介绍 -#### 使用说明 +本项目实现的是一个微riscv处理器核(tinyriscv)，用verilog语言编写，只求以最简单、最通俗易懂的方式实现riscv指令的功能，因此没有特意去对代码做任何的优化，因此你会看到里面写的代码有很多冗余的地方。tinyriscv处理器核有以下特点： -1. xxxx -2. xxxx -3. xxxx +1)实现了RV32I指令集，通过riscv的RV32I指令兼容性测试，支持以下指令：add addi and andi auipc beq bge bgeu blt bltu bne fence\_i jal jalr lb lbu lh lhu lw lui or ori sb sh sw sll slli slt slti sltiu sltu sra srai srl srli sub xor xori； -#### 参与贡献 +2)采用三级流水线，即取指，译码、访存、执行，回写； -1. Fork 本仓库 -2. 新建 Feat_xxx 分支 -3. 提交代码 -4. 新建 Pull Request +3)可以运行简单的c语言程序； +项目中的各目录说明： -#### 码云特技 +rtl：该目录包含tinyriscv核的所有verilog源码； -1. 使用 Readme\_XXX.md 来支持不同的语言，例如 Readme\_en.md, Readme\_zh.md -2. 码云官方博客 [blog.gitee.com](https://blog.gitee.com) -3. 你可以 [https://gitee.com/explore](https://gitee.com/explore) 这个地址来了解码云上的优秀开源项目 -4. [GVP](https://gitee.com/gvp) 全称是码云最有价值开源项目，是码云综合评定出的优秀开源项目 -5. 码云官方提供的使用手册 [https://gitee.com/help](https://gitee.com/help) -6. 码云封面人物是一档用来展示码云会员风采的栏目 [https://gitee.com/gitee-stars/](https://gitee.com/gitee-stars/) +sim：该目录包含仿真的顶层testbench代码和批处理bat文件； + +tests：该目录包含测试程序源码，其中example目录为c语言程序例程源码，isa目录为RV32I指令测试源码； + +tools：该目录包含编译汇编和c语言程序所需GNU工具链和将二进制文件转成仿真所需的mem格式文件的工具BinToMem。BinToMem\_CLI.exe需要在cmd窗口下执行，BinToMem\_GUI.exe提供图形界面，双击即可运行； + +###3.如何使用 + +本项目运行在windows平台，编译仿真工具使用的是iverilog和vpp，波形查看工具使用的是gtkwave。 + +在使用之前需要安装以下工具： + +1)安装iverilog工具 + +可以在这里[http://bleyer.org/icarus/](http://bleyer.org/icarus/)下载，安装过程中记得同意把iverilog添加到环境变量中，当然也可以在安装完成后手动进行添加。安装完成后iverilog、vvp和gtkwave等工具也就安装好了。 + +2)安装GNU工具链 + +可以在通过百度云下载(链接: https://pan.baidu.com/s/1bYgslKxHMjtiZtIPsB2caQ 提取码: 9n3c)，下载完成后将压缩包解压到本项目的tools目录下。 + +3)安装make工具 + +可以通过百度云下载(链接: https://pan.baidu.com/s/1nFaUIwv171PDXuF7TziDFg 提取码: 9ntc)，下载完成后直接解压，然后将make所在的路径添加到环境变量里。 + +下面以add指令为例，说明如何使用本项目。 + +打开cmd窗口，进入到sim目录，执行以下命令： + +sim\_new\_nowave.bat ..\tests\isa\generated\rv32ui-p-add.bin inst.data + +如果运行成功的话就可以看到"PASS"的打印。其他指令使用方法类似。 + + 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HmnnIH2GR6Mv8U91GjB3X3TikosuuP0PL0h7BUjC3rv2zT/gwIWHv2nWrFnRXgHx1cOO7xk6dtFxps9jT2+nn/i/rG7SvoH4z9Vf2aV/j2nxZ/oVjzafL/Drr0wfuObh5pTwoyvG7XHmd4caCYbuOm2PaYvvXd9I8PDn94z/bHBsnOdvZjZ8ialrDv1Z/prn5naHpKChu0975V9G6rFatnwaudhpfn3L03A20dOh409yCHIaN/PHzER94/vzZaGPLN9n1kD8Wf4YKyYqY/V1swb2nR1/vry6Xl/3ow8MnHtP0qqSKRw+l8O2uYoft2c/JEs/4gQGF6KszvDEtHuWsWEdhn1iyyRAk20WyR2Fjf9Z+jp+AoFuIZCyZKCLsFkWbezd8pN1hoD4aTcK8PPmPQTWJYO40JbpgUhii8JJiC9d8yjTA+SnomlvuvBuvYinOIDW1y0fSiBd+kd/0oR+fLWhXt+Tgmz+nL6Q++cf8bw6AxHJGxmOJtuVK/7GZX00mc8+Y60fOvOd/pkUB1yx7HxWNB30nc7QeZ6FZ2/9kkwwNOYhttGXmJRtVoAtC5DKUSjAogF+pHalLZueNX3+8t1vpp/4v01RYuy3/s6/mn7AA7es/ePGYfo8+eO+RSseaqwrzH/HylM++0P+Z22/o5fVv/XYMw2X9cx/30rbKX77TOK7Nqz7z7F3nrn/nNq8Dw8/+eE3NGOOVt+WrDGnViyenlA/2nzMb83+0/M+863r1mxojQIEIUkwxOe3ufTWOH3o7sWv/ss7WbVaNBCSiYqxNPV67EqTHKuvvfy1PxkafnzoyatPWnrSVavjbrfuh++/5NUPDz+2Yfixh28/7vw3XbdmzoJzl333xgcJqRK8NM40VGgEWHosEihJca3whtpNl0+jTlzlKAYQ2CShQBwXtEYJrbqlmhQJQKDSBIwBQexHffcVtmRSAgIphjAFBKZYQUjfsmTA+CelpT2BQEzGDcdChJY/mUAl6qHn5VsOQ0tomTGR0jBn/M//8HfSh4cIkgkacx/syq2/Fq2LCivNyZPX+mt9/fX4Q1/iT5Lmzol7rBo3i8pi8j+29EKuAJ2nXxspecbGl6is+PFtbBWWVn/jP8lHJKOtofI8AEhCAfa3w6xAxP6Qgw50/LChvMVJ1Nfd93cn1FauXXHsbDbO115/TuTFG0P87PlnnHjeJfeubziGma89obb0pw8nF7g/Pe/dJ76r9tn7H4rTr1vz9ZW1Q14xq6WtGTu+xtm0uh+TxxO9miJ9/pEXrzzzG6tbog2hJOaq2dFM02jB2hglSS90VDVZdD0tRdS1+e+75rgYxZz9Fp9cW7U2dvZzjv7KTUfPjr3p7AP+/B21X61bV593zCdvO/E/1kgTbELNGvpb3LnMqmFoI32BQCK+MQFAPVqsYDI3wCg06SWxgl0+fgWBriRQTEBA6NSCsgYETU9t3xmQjIXCnAFXQ7N7IBnqaVxIbkdLntoa/0k/0kq35YhGFH4fG5cQjT6x11T2s1F62k9nOeIhqq8+Fn/i7JE+NDTTO38HBvonjKtPGtc3cbBOzyKeONg/aXzfxPH1iRPqEybWx0+sD04cmzCxNmFCbWLzs2rczEsv+jgr8RN/9w8HjT1P/7I/6Tz9KiauRdkn1gYn9pE0eolAJCcqon9CUmJU+uBAFGqkHeT6+SJFtGQbLcnaDvuvNh+ceEL63/oHV37r5FPmzxEdZJxz9dXT+q9+uFabfcCp77r15ocayzbRn7VVT8V/PnzvZ08683Mfv6z+i6c2RH9v+O23ahccHYURj145MHdFFB8M3bV47pl33rtiYO60/ugTn2Tyr5ken6HPm5c0dX34CnYyWqpYEXv0h6/YYxqtWcQF3LWYvj/Cvn9/8R5n3jlUW3ff+/r3nB5/3ncnqbHvgmW1T93D0kfZozmP/r3iz1/dte7RFf17/SXlSvzuo1/sf9UXV9c23PmRXftfFX8+8oN1v/li/6HvWVn79gmH0p93RzUlHf5kRj/7fHVNlJmmDV7zf+68/6r+18ygz3vuX1/7zVUDe8+MPh/9wTrxgpoipEdvuvW4xQfMlA2y4fe31Q7YbU69Pv/wC2uX/ni1eMH92JfYysLAPrOXPxbNJQyc+4M7aWUhOvOB7z5TW31tsvRw2o9oCiSuzjN3L96Xlh6iz9yzbkuu44XoYfV1bFVi9sB+0cJEjYrYdw5buYgWKfb7wHefjZeK/m23gfm79b/hFQNvuiZKxo5GJNDyZ3ReGz3JNcXfINCFBCzz/4kP143QllxNx98aAvgGBJw1L7/hSYy3GCRrAY3ggwcEYtFJGuVRIvSy3b7GVTV9ib7TxXdf/5w99jxnyecsn9322JNvgxZ2MEdX0PHFc7yzORbIPnvP2/+Tn/4Xy4cSsIv76BPrEH+hS/OB+riB/p0mD0ya3D8p/nfi5PqEnfom7NS/06Ta5An0qU+e0B99mVjbiT6T2OeggU28OPp+3MRN0plGyihXH2WfNIH+JVH1nSb0TZrUHxfRN7FZbn3cBHo1saUzcL9fX7NmDT13kG8bpEcM/dst39ZtG0yMdc/Kq8/96IdINIsbkqcFxUXRGfFPOnP557944umt2wbXLH/lUWPf3fix/aJrwWjAb4z+FAocUPvxyAfoCQoPL5/7z6/9r+vYNW7kjw+4/owHrzuuRl8e/+Tak586+7XXnvr4zW8ZWj73yLHvv0Ciao+sGPjTsQfWfvgNUeKTV56wcu2X3jYnknPkT6+jlLNXXzPtgAsu/i+afqA583vP3P1/f3NZlJHigCN/9n8fu+kt0QxFpMADK9de9acbmCbv3z9K+d5v1f6evs9bd+/7dr/l9LWfrX3swBvOeOBrxwmONvrpt0spPQlZd8/7dl95+toVfzonmTiiyGDfE970w5H/Q7+uv/PD+153yqNX1D4ZpfnCsY00FMHcvfiQG874+VdjsQ9f8eqja9959mPRrsb4+x3PfGzG3YsPW7zy7Tc9+flj51AQcMKna8fF3ynjEYsPv/2Zc/Yha6xZvvfCpZTpvPuGz5wnW59yvWPV7T+55rgZEdM7Pzbv8bOH4lyR45/7gdrtP76GV2rd/e+f+8HbTrn64RsXzFr9tVlv+ofaKV+Ovkcpzzr4vx49az6Ve9Tp9fgklXvFPsd8/Lgbn7y8uW2QQocD6/fuOCNSg3+Psn/ztCcvn3PTPm+pf2vdOa+lfQyzD6z9YMf/mlcfHXvo33Y7cOyuHaftG837RRsGhU98Zow/dIh/6cLxHlUCAQcCtklt22/muUBxyVKQoArj8ToP2Zm+4nnxp8b55P+a7GyCkAlJZAnf2cn4h713rX/ko+cuOXfpH5/dqr1wFbW1a84Zv2LmlK999ZolH/3wmt/TCq2mIqo17PB3mzHljpMPX/wPV/zutlsoJdt6Fd3DH+8TjCYQ4t2C/TS1H20hpO19LTsH1eKY6+WF0p9s8X84vpIfHquzfda0f5A8MP1EoyVtHoxyDQzMOfIt537i7775u6f/+AKdaFGcbRs86pA30BuJ6GmDzVkBpoGOr2Z2inn9KJaKA4K06YSkdo2Y8T/XrVfrO/8DG+M4gI79j/n7b5/wbZohiI9ZtGRA2wVq6x7++kqaA2DTBr8dqm14+j/HLjmG4gD5eOcdF1IcQFqRnHqUMppOGFv2/SgOoGPOMR+/jGV55P6ltUvOi+MAOuaftPKUO77+4Pra/CMuqX32h6tpAuOWby373o+Wffb+1fEMxCmnzp9DypzwrRMOnE57FXmxc+adfsrnlt1JJ8Zq0ffvnLr7XvGEQaTD7OM+cnHtwh+RhNrQr6/7zsXnLZw9Z784zaveF80WsEOM5h/9Ebnzpcfv2v9q+hxN33+2PiprrHbS7edT9FCr7XMUPd9q2V/F32e+/ozjav8ZJ6jV5p3zeLxX4FWXD7x25vLfCFzIc7/j/GXfZnEAHbNosWDpVfEMRG3Dg/9+28lXXyIGN9Hp4268/KhZVOr8wz5Xq1/4ycjl1+bsu/jksVVP0dRINPFw4+XxSSp38ZffIRRGX9fc8w+1sUuPYTMNFEmM0cIEZV9w8e1jp83d55iff/nX57wuTvaPtbF/fOvA6+f0v2G3N/1LbWx1lAwHCIBACoFsMwRsqDHN7monCdxnCMSlBHFME2YIkgV+eeNhXAbTik8P8DPJyYbSk6fuPDK8bacJ48eNGxwUPuPHDdInOTMYHewv8aAsUa7WY6CfpvIH+vsHxg8Oso+cTc5h/X3cIEmrjRs/MDhhcOq08VOnDe48bYA+U3cenLLzAH3oy7Sdx9FnypSBnaf2T4t+7Zs2jb64fwbiXJSdPoOxwOgzlWRGRYyjLztH5U6cMWd04tRpO09uNCa98Zn7bgkFDHGArVGyaQA+GaBKaE4ZMTH7H3N+/dZbVq+LLW1qk/OPvKR+wf0PJQVHvn/pTx4mZ7zsyChWmLP/X5xCvz7z+K0XLHhDy8wYryl78gVvXOIX8Xxrzbg2+9Gc/3n33PvQdXdc/Jb99n/L33/qnkcevuez7zxjv9mRa1/x/MgffnPGyn1ojSBZR5g5/4zjafNg7I9nHXvTE8+N/PL06w7epX8vWgugFQTy3CShtvq2U1eef9R8KmXmW2/6/bMjPz/9ukNojeCLq0VEiXYXPfjbZ0bo89/R58ajZzdXblqMKfATzs85+pLbo/iABSO1aCnhyJvO+DHNAbC/o6Rz9j3t5DtvfJDHIuGH3vqyb20Y/k3jk0wYzN79jVJJ9WW3Pj3866dHHnpq+FdPDf/jW+IYThwUFM2ag0V4pSERBCpGwOLag+8rFNHY7zJojjSsL7c8lahxpiEuqULjbgIxImkZxcdqW4fr+857/Q9+cPecGVOnUDgwIXLczIGPiz8NZ974Ip1nKVt9/bhxA3T09fe3hBa6oKElqlDig+YJEjieFukHBydPHZgyddzkyROmTB6cPGVw6pTxU6cMTplK5+lPctgUHIybEqUZP3kyJTN9BidT9uav9H2APiQnyrvzuMlTBkg4ySQ5U6dMiP+cMG3aTrNfMWPeG3777MaDDj7c4OiYIZIBVZ4VsORJvIiUQpgVkFYHeEJu6XiUn/+Om0/5zim7n31X4y5Jmsa/krx+Y69AnG2/d99+4nn3skV68v1zDqmv+pdLLjjpdbvGfmLmbofXf3Hp8vPe/eqZpkigVctoemDp55MS192zLNorQHKiZf7zDqANCrGGq287ZeUJf3FAdKFL7r+29L2nrvzMAvLcs179zqWLjlp6wunRTxvuuoLmAygguPI3dxxf+9nT9J3Szz7ury9euXL1urGxdfd+MZoPmHHsTb+45ZTaL9ZuoPY9b/HXTlr6hfddcuFJd5wwj9A30/zs5lNqv4zTNLwffYku+j99AG0RiLrG+v/4a4oVGgmS+CZOzPbUNL3mmuXn3E0KROcf/fcT76wdPovgjNUeoXWBX97+o6uPm9F6X/6Mt573yduue2RDbWzWAe96x60fOC9Sm2aZHvnSctr3wCTzD+/MUXFxJLHP4pPvPP3m3zCZD9/0wdtYb6e1gHHXEs/93vJ3Y0vfdRXTnJYblscp6cubfnXDkz+8YeyDr48mLSjZ34wtPeXLLBha96Ozlj/eCG6kaKAZLdlGvlaj4y8Q6BkC6QGBcNkgjcy6X4QoQhCtlpItIOCBgbQxkJXaMvKwsa4x0D23eey4Y49+aPWvv3nr9Tv1bXrtHrvsvecue9O/jc9r+Pe5u+wtfF4zdxf5s8culJg+UyZPnDhhcPqU8exP8fMnai7hDP2q/UzeaeLE8YNT5+419/Cj9jzsqD0OW7D7YQteQZ9DFsyhz6ELZhyyYNZhR8045KgZBx+160EL6DP9oIXTfD4zDlpIuWYcTJ+jZh521OxDSdqCOQfH8g9bMJc+hy8ct98bH3rmheu/sOzUiy97bovUEzQ2b9krsH79etorcP3K21Y/uErziKE4+z23GvcKxA4jWjjg2whor0D0iCH22tl4MSn5l1bQ9znhDqbeO++ItwVEy/ljbK9A7Bhonf6/P9748+Hlexy55HhayI9n/mki+ZrpB1xw0h3/dW2yn4D2Cryt9sCTf/WG9XctPvDrZzyQnI+Sjf0o2X+w55uXMACfuXjZ5z5FjxiKNhnQ3oIDT13JijzhlniNPz5ou9+iTy2jNLRgTzIPPrV27W9uOoaWEsboiQgHsEc/HH/L2ivjWfroePiKV172ul/QYv/DV7xqQbRgX6ud8tVHbloYrz7Q/DxtDHz7zdH+gEgH2hUYzfxHab6yJtrhT9sIPjrvhP+o1d5+09rl0Q6A9xyxmG6bpGPZ7UPRXDpJoCv7aKWf8q9Z/rpjat/eEF/l06r//tf9+cM30WT+b7408M7zmTZ0RR7/umb5PsewgpLjz25orujTPr6rXsP+jJ4RRFv/6IgT1OjPby5OUpLYP6/91yNnRY9vGvrB4gU3nfmjq/9shpCl9o5lf1tb+tDiJy976wZa+6/fs+O9tEVgw53nvv7E70Ui638XnYmKOLt2xw8been7/V/+s13W37n0DSd+P0728XijANsiEG0OaDxliGrMNgq0PGXIPKck1hffQaDXCFi3CkjrxS1sTBmb59veQ8AFSBsIhHuFmtsFtLsHxteHdxk//J2773/4Vw+se+qPKZUV9hlom0GjCNtLilOLUCVPWfW95xs388c7naNbFOLbC+MZdNqnmNw/TRsW41sOhH0UTS9NGRuRULJbIv6T6RqNkfF/8RG9xpX+ib9F/1CCOVN2ev38N73zn7708vDAdtqToFQj3itw0JsPnk97BegRQ86hQENBHgq4dDAeCiQRgBQQsBqJt4wJQslJv+nrZzBnr41bXRQQ0zQn2a05pWSmopvnk2+rv7rrAbX7R96XhDJJGcmPke+Pdv9RYNG8wG1RrsGita4tpbeq0nKh7MBCU5E1y/d7S+2b6+Nle+1h5h7KIhQ5sgbNHjjYjAMajn+EhQVsz2AcHyRXEggFHIyOJL1MwL67zUQmVEAgyVF3CwpneGDQdFh8q6AaEEwdX9+F7qHTeDdzZGNmkcHTq+gyh195t8/nNtde3t4YrVu19A8FWkd931Dg7Y0HD/OJgcj3CzFBPJGgBULX9Je8ml2Ls6MN/6ONA+zyXNywqPcG2uT//8777dnRboDWY/VXZ7zpwXjDv+rwVcVUrSxBjJTYorOKeIzm5D849/fnDEcX8dLRBmrHxh2XYH7wML99AA8edgSKZCCgI1B8QGC6xYCN/OxQpgeaP8ppWh/NwjI3szfEtZxRSklKNM9qmG5/EIka/JRcI30ztE6oZGi52SOYRk7PUEBxCRQKeOl93OJogSCZFWBBAH9AXqwTj/5SxLZxheri12xzBsIFqFZUdFJ7yU7L9lf1v4Mm7S988PGzk/cjqN5aP08Q4xC1srt5lzoywraUVinuRTi2EPYgCzYZQF+S6/5kGoCfTOYD+JQAwxJcGUedkQwEqkgg82WrNmPzpNXDpd52qAQEhukB1f1z3yEGFlKIoIYdYgyiLJW0Hw20ileaSehoIKU4SzONNfEJBXyGW+bR6V/KJPv++BYDFg1EqVpDAXZGPZqF+6ihkaNk950MsF+m66/LhbM8UNDIabhmzdyANrbQWdcSW3iMWcUGATwiYU6dbwIQ30sUf4+CBf4UgeZOSYQCHqZFUhBICIQNCJquyC0gkEo3zxCkBwSJKDUgEKIB0bOoswi8TZi0YglUYva5gXT3rJuxaKeBZpweqMuhgPkOAk8HzBxesqOB7QIVLu/EbV/JG+foTUp8EpiekCB86OWQ9GmeUR44wx8+QxIsH3rMQvSaJiWN+OwaVhb/ROn5ZyT5TprIaWKZ9D4o+miyj0Tl8k+UgKVkueKfdkSfseHoUxuOCxKz7GiVwLQSEwhC4vOUPv7EYjUp1bzNMyyvWb63QDcFxBoxRFF74F/iV5G2bBXkd0wgDmhn5EDeHiYQDcuWeUHzb6ZfkvOCXDUlv8tA+olf//DzjTONHPzWKq5zo+83y5V2Xwn3VUUeqeHFmkWw9NKlmtAkUveKiTdNaJtSiudUVGqzPXo66kZpSjb7zYR+SkZxADdV6yaveEyPNjfymCAZ9+MX0YremrvM6GSrD1b/FAMI6Tu9jUn9VXLbaqCQRAlxIMK1aqrEYovGh14DTR8pjIh8Kq+R4MIjzyc43RF65bZ8punvk6ChEW2YHHxUNCnQ0KEljmkoaQwCGtGDJQiwBRBu/j5VgmzTJBpothP2nmLMB/h1RaQGASuB9IBA52EsAUFSWiOFY0AgutUknGi6/3j1sHFJydw38+J8fZD9yp1O4uKlM4IqvE5JNCB4ZZGW5Oy1vta2oGyPt6yBSLZmmzEaaC0sTCggxlwtN4Y2Jgb45vDWmCC67JOcQYv/NswH2CcD2JW3mkYMMlSv2XKV3HD5ybxC7HHZpTPTNrkoH6vtaHhrfuHeTBCnZ5fUkS9v/hlPBsQCxStjShClYRf3je/JF5PfbchUYwV2Rn9B36FpAE1YwGcjWDOI3hM6Rv+yOKx56yDmA7KNEMgFAg4BgdGRGDx/4qFbJbecNF/4amcIpICAXc3Hvjbx9cmZuMREtrR/S4oPhIvSppQ4Z4urEryyCsG4T4tfV6d5YNvvwm9pYpwascFWTnlZogChgFQTHnDxxsHsSn82Z+abkwF8qiDyAcknumI2fsiP2n4dIS8rJ4jn4ZsnpQTSr1yNYUEf/p2+MFFcYOzXoz/ZhD/9uyPWgYuNimv+ORr91EifZBmJsyTrBYkcLpCfb/kSC4nKauQSf9WeTPQUCpKyGHPpitBrlSkls2bMM1kjEG8pTFpRa6Tv0cCRFARAII2AzZGYf9NfLvMZeGtAwDQSJahRAg8IEhUaEwbin0xCanyQpBFUaoYFjQqqFZWiAW24kDo9YGQvlBckGpB4ptlc/r3dUCC1NSRBgLx1oBkW8Mv35uS8dXOA9KIaaeFf/bW5I6ExA9GSpXW/gnjRz6bfpcmA6IywTBBd2YtbCpQlAzY/EU9IRIEO/1PcOiCuRLDzYhEtuwTS9gRknglIncnPI0FScbY1RNw7wleXhAnAUL3Ft4cgPQj0CIEMAYEpC/fW/DJcSum5gSDKnXh9ZbsA+0EKF1rO8Ov4xnjS/FUII9ToJEom7Fcw+drs0YAgsf3Leq3+7k03eyiQqro4K5As8DRmeqMHybGpAsnrxy5B+0m2lVmiBF1eKQ6QJIv7Frl86WRziyJbHWgokGxlEPYPCl4/cecNLx5f9bZsFIhFxWEEWxBhIUj0RTgpno+SxYl5SnlvREOCvEMijk4s2yYs+y2K+YkjTRpDo/vxySQEAe79GSlBoE0CfNzWyDEM+ikBgdnhuawXsCiArRfwdQPufcX4QPQ4fNAQsicViiUJ34UwwuRN21wsSPGVwgAXZKxLdc3aFmJ+2uAzmmcxzppM72Rus6W1ZGc1b1+kPS5TNW4SdzCDxjyNOFSU3JIsCV31ltVqm9oIUhNoyIa0VXhZfjUKXz4kggAItEHAZ+BOTat/gIExW3xPn/kmRvFuQ7GGJnkt57Pe75d6n6Ej61RWjnJYMrrW2vCSZqzde4bjg4eVUIDigDu/c/s9P/q5lx5IDAIgAAIgAAIg0BECbznq0OOOP1GNBrKHArtNqS/5209fv+LSjtQHhYIACIAACIBALxPYunXr0NAQvVWZ3oHc19dc32dvARRfDhw91q9ep/RLLrj8sn+86OlN8sSAFApk3yvQy/ZA3UEABEAABECgawi4hgJY1u0ak6MiIAACIAACPUUg1YM7hQKpUnqKKSoLAiAAAiAAAtUiYPfjKaFAttsSqgUI2oIACIAACIBA1xOwOHRbKIDJgK5vGaggCIAACIBATxHQenZjKIA4oKcaByoLAiAAAiBQUQL9/f10TwH966i/6t+d9go4SkcyEAABEAABEACBIglQBEA3Fh522GH0r3s0IGmIUKBIk6EsEAABEAABEAhGgHw/Hfvuu++ECRM++MEPZo4GEAoEMwkEgQAIgAAIgEBhBFgcsP/++8+bN+/YY4894IADli9fni0aQChQmNVQEAiAAAiAAAgEI0BxwJlnnnnqqaeefPLJBx98MAUEhx9++P333y8+iNCxMIQCjqCQDARAAARAAARKRGBkZOTaa6/9zGc+s3jx4kWLFi1YsOCQQw45+uijR+mtsp4HQgFPYEgOAiAAAiAAAiUgQKHA9vjYsWMH+5cddN5XO4QCvsSQHgRAAARAAAS6igBCga4yJyoDAiAAAiAAAr4EEAr4EkN6EAABEAABEOgqAggFusqcqAwIgAAIgAAI+BJAKOBLDOlBAARAAARAoKsIIBToKnOiMiAAAiAAAiDgSwChgC8xpAcBEAABEACBriLgGgrw9xzfpzsyI+HCMkuwZBQ1zUN+OWWyWpdTtyK1yptD3vJ9Wbnr455S1CFbLt9adH36XEe8rqdHFUQ7zGBl7r4teZ1CAfGFhgsXLmTi6As7UjUzeSZ2nkkI7r248Jzkp9ZaTRC8ju46BCk6iBB3nXlKS7mdUilDLdyz5F2p8vQIdyZdk9JlwCx46Cigf3k1aa/EGRpG3vIzqGTKElZV9cXEYrnpoYA9P/flTKgp5lWrJMYBvTM2hTWttgGp8VnAQgOK8uow2nLtyjjGqV5qiIlzlZ+Bs5c+GXqcl/zMVJGx4DiAj9v5lZuhMVuyBGmHGVQqvmXmoaTFm9fXrFmzZcuWzZs3b9y4cf369WvXrr1+5W2rH1z1+DOjLdnGaq+YWl/6t5++fsWl0tW8GOdy7aXgV8wiNj6ejCeQvoihhohGysjtpAq0N3FteqmCTAKllGqh1YfFQ6o+2lpLiXlBamIXlVz4pPL01d+UPpQdM3PTwtTaRWXLbR3E7ha7iC5Z7UfaTiTVy85fil2kvtBOe1bHKfv1rpReO2iojdOlO2udWTvyfe1l6e9a/2FC4dt/Azon0/isbT9e456lnXiNk5ZxyUsf03giypeGehe7OLY39/HExG3r1q1DQ0MDAwODg4PiO4fq9frY2Bj9y01G3+mg9EsuuHzZP1701ItjteaP0dfXzuibf8BBbz54/owZM6ZPn26cFZDiALXZka5adbVRm/tVCE/J5bBSeGPVipIS8zFFVdIuR62mOsDZ9UnV0+L+XSiJ8qUObCHPgIgJTHr66m9KH8qOoufT9kmpXrym2oFSbSem8dRkd5P8bDztpYv1tdhFa3eRm6ldiefzkK/tTZIyvv3R7v9U+2aQL7YodYgzhVMunVfyrFIWbbm8HartPGAooCpvKte3nfvKMfV3334njXiSHdX6msbV1PHQsT2njidqY+AoLB3crw0ITl2dHtCHAqlxgH3ANY3CWi/oVRlt/GEZT337p0UZKlo1p2gtMa9Fz4AqeaHTJjbpmbf+Xna0jA7tE0iVYLG7NLLz5m3qul5dWjs0SANTqvL2BGIoKRbnpWebOrDslvaQ6ozbVECVz5TxKtc3vaUzepXbZt1NDThVrFpf3/aTmt5xnLTIsdvRUX5q+/QaV1lTl/xIhvaWaiBjAnM0YN0r4LDv0KtWXvRN8YRjdMwba/uFiq7IcZTkSmqjh1AqZW8QjZwmPfPW3y7fEttxd9t+3R0lMGO52J2lCeIVtNFPWPliHMCLC6u/I2GO1wWyu8xsKbMFW9nas6hhtnKz1bH9/qWtr2/7TE3vOE5q5bjwdJSfoX1a2oM0nrjoGdbKNYNb14cCtJBQj1cWpI8pAnLXldMXzaCOSnaBAUdbd80tKU36WPR0aYU8jfbqLcPVg6+ebeqfyjaDHbXcMsgRddNyTlVeSuASeop6OhYqJhObQQbrax0PP+mivy8T3/RaPiw6YcOxr0BLenEgcpHvYi+1HYa94HNv56ZyU/Xx6l+iPi7txzc9N7qltbuU69gMKJmdsDt/VqJvepOe7ctRXTnz7+Jh3jY4NCppRtsGl/ztp99/6iJVY99eSnWT2pwoQTI8/0k8L50UpdnTMwvxKmjLFUcfU2IXOanjFxeurY44TGtFSUOY2mFUFCbOLudVuzM7pvJkGTPb0VSuaAJL+2FFi6xMQ7+aRtKc93BJJXUAdeRp0kSS78VZrS8Hpe0mUjNTq6xtV9q2ZxkHLPzt7ccxFAgoX+yVLtV0GSLUDm7q+xbzpY4nqikli6iFat2P+/js1c4l/S3cUtu/2EpTx5/UJsTrK3bwzOOVxU/ZxxNVT9Ve2bYNXsa2DbYer53Zsm3QOxSgOwi0rSfgScfxMWCJZRZlGYxKDqrk6qnDjftQW+YG01nd1LhBO/xlVjJv+ZkVQ8ZKE3C5VChDBUsRCuzWuJkwVyLuoWKuanRcuMulRpldV1XsWBU9O94goQAIdDeBSgwF2UIBupnw6eyzAs80FwjYzMIrpiTPFejuBoHagQAIgAAIgEAJCWQOBZ7aFLlxcX+A63MFOIXUpw2WkBdUAgEQAAEQAAEQEAlYvHnKg4cRB6AlgQAIgAAIgEB3EDD5dFsogDigO2yPWoAACIAACIAAI6D17ManDSIOQLsBARAAARAAge4joD5nyPyIIeX5QtITCUx0aB8mO4Lj45Il4abzdgVyUjK11iY+jtxSk4WqVyg5qUCkBKkV9BWI9CAAAiDQywQ0jxhq3UJIcNJfUuxLUH3MSJCwgN/3KT3OxXTeV+3C0psew2J5PIuom2OywqqTGm/5auJVwSBNy1dDpAcBEACBLiMQPhTQAmp/yCYP4eUkUu0UXGBqicUkCFWv9uW0b/TgcUYxJkApIAACIFAtAuanDQrPFWBVoucK0IOH6WmDpkcxSEO/+kxK7VMqLQ+FFZ8AJWJ1OS+mkdJ7PUqC5+W5UiMSXz4Wbi5xlcsDMrmcVOUppVb/VOOyIrTKSD+ZeoipCBd9TEW71LdaPRbaggAI9CyBbM8ViB48HD9XQDy8nyvAMzNJjhP1UqnSrL44cPOULheRfAHbtAzhMvRrr3f5ErX4hetJJ3kupqcpPcsiJVa5SbXOcAmuFmERoia29CUvOab2wA0h0rAUKskRU2p5WuRr0/fs2IGKgwAI9DgBl5sAXBcIxlqFcZfsjliNBlhe5mUd5ZhcmmmewFGs6L+5I7FrJSaTvB2PEtxLr25K0awZAhqXivvy9E3vogPSgAAIgEB1CUgeXK2IMRTgew7Z643Zn/xw9JdSedpogJ1sx4u0HwcENLDl6jZgKaUSxWyXITp0qYUvT9/0LjogDQiAAAhUl0DivgVXrt4PaJ4ViHMnjy2WAoEGkgyjv2luQAwy6Lu6EGAqS4wDMuhTcuuW/wJXspR2lUe1S9h6dZ/dS94soR4IgEDFCDQu7ps+vbUC1qcN6lYYuC+XrsXF83Z/L/2qOg9xGTg1RGAJVGdg0UdM7O5F1OhE2xRM5fqeN7Uzjt0eLbnXSy3Ii4+pPbCZHmYa/t3SeTLw0cp3b4cV68lQFwRAAARCENAuFmS5gyCEMlWS4ejMqlQl6AoCIAACIFA1Ah24g0B9PlHVoIXRl09aaKe+w5QBKSAAAiAAAiCQG4FUh+58B0FuKpZccLYNkiWvFNQDARAAARDoHQKp9xM6hQKpUnoHKGoKAiAAAiAAApUjYPfjDjcTNt5LVLmaQ2EQAAEQAAEQAAF+F2DzMQGtUNJuJpRWGEAUBEAABEAABECgQgQEPz5miAWMoYD6PuP4IQM4QAAEQAAEQAAEqkOg1XdrnLvlJcXydADigOrYHZqCAAiAAAiAQJNA45HB/gsEDRn0OILUxxeDOAiAAAiAAAiAQGkJ2F15yh0ECAJKa1coBgIgAAIgAAJeBEw+3XwHQb1WVz5eRSIxCIAACIAACIBAZwmorpzOSIf3Owg6WyWUDgIgAAIgAAIgkJmAdmLAHAq07jLIXCoyggAIgAAIgAAIdJaAeCuAej8gnjbYWeugdBAAARAAARDInUDGpw2KevEHFeWuLAoAARAAARAAARAISiDViZtmBep0tOwbrCnbDIIqCmEgAAIgAAIgAAL5EGhx6JF/b/XptqcNNhXC84XyMQ6kggAIgAAIgEARBAQ/rrr09NcR1eP9gzhAAARAAARAAAQqSiCaBxDuBpBq4bBtsF5LXmBQUQBQGwRAAARAAAR6mAAtCNj9uD4USPYJNBYTMCvQw00IVQcBEAABEKg2AVoRYH48uaUw3jkgHtZHDNWaNx8iGqh2Q4D2IAACIAACvUqAe3DtawmJSvojhnoVHeoNAiAAAiAAAl1FILlzQNk3aA4FGo8m4jcVdhUPVAYEQAAEQAAEeoNA048b3lJcX7NmzZYtWzZv3rxx48b169evXbv2+pW3/fpXD/z+uVFCxEMHemrx7Mm1c//m0+8/dZGKbuHChdl43nfffSxjZgmWcrnwnORnq3LeuVit8+CZt+Zh5efNIW/5vjTc9XFP6atD2PRB+q8oRDvUONJIlSPVXRLrWIovQBWRBVoQnr4a9mz6nCy+devWoaGhgYGBwcHBvr7mlTw9J2BsbCx+WkByRI8Gqtcp/ZILLr/8ny5a/1JzcwBL9Kpd+l7/xgPffPD8GTNmTJ8+PeUOAj6ZwJ9HwH0MfWFHqrHVXsSyiLBMaVKFmxJw4UzD4PIzKNZBHYIUHURIWG6dUilDLdyz5F2pUD3ComeQKjgOLxystlBpvGpnKBBFOVqTqRSEhlqidoizKJlBf8dqFpMs7/bma6mczGpvz9lQq35clZO2QMByGKYU2I9iNEB02CGVZDrD8oYam7JhKjJX3q2HwZTis4CFBhTlhV1brl0ZX0fipY+Ws68ES/oMnL3qG6rHZbBLQEom7+hVhCM3qU+5XAIxNTKY0kV/Hge4JO6aNLm2twyWsmRxbFd202RQSS+w8aTB5FfdU4iNCwT/8/woLQ80Fwhqtdk71T72N5++fsWlYiuk71IooMYHvD+oKfkZLlP6IoYaIhcpI6+/KtA+XmjTSxXkNZK6n1YfqfNrvbKWmL0KLiq58Enl6au/KX0oO4rjqRc3qR1KncrUFLVqt2l3i11El2zpHapTMaEw9QvR7rylte9OVAnq4KVVKVV/i5KmfqcdZ6ST2n5k6hQqNC0xx37HpTmmt0cbFttl+ynDOKllqx3/Q8Ui+bW3DO3W3t5UDkH8RbYFgitogeDl5qMCowWCeu2V0x0XCOIogEcPLLN4UMW0+LTRkPtVCE/J5bBSeCPQipISi71OUtIuR22yaoe065Oqp+Q7xRbjQkmUL3UMC3kGRExg0tNXf1P6UHYU+Wj7klQvXlPt6KO2E9MgZbK7SX42nvbSxfpa7KK1u0u7cmlv9kFclcC5BWlvJv9ksqOlRny8kjRss5249BdtkGcax7QRQyhX6i4ntV9r4wD3/uWuiZgyv/bm225N45Lv+CCNzJK3ar+HJvRoViD+1pwOyHAHAeXWvtTIMgCZepfWC3q1CW38YRlPg6GMYxHVPfAGIf1k0TOgSl7otIlNeuatv5cdLb2ufQKpEix2Nw1Spq7h1WWkdiL+6SXHUkEplExFkV+/di86lYOpf+XtpSyjkDagUa+j3CF4pWynIG0/lUwgKpOhX3vVhTlOdz+i6pPafiR9UtM76mORw5Q0mclRfirGxInztX7lSUEp7yCICojDB9MLibQuML9asf7sMhRKFwHt9AfRFbkUzdqrRc9Q1k01f2oCk5556+9uR5O7Ta1aqATMWC52Z2kCjoZSOwkrP0gc0JEoLZVDefqXJT5wHMccm7ElpneUYIrzvPTM1q99NXS3r1af1PajRgP2fu2oj7ZcafbFZAX36McEM/HgrZP9YuL0OwjYnEDd/LhBLy/LqYn4fEelgKOtbyvUps/p2pojEvlIJ73099Uz71g1gx21vS6DHG2E4dsORSEuoaeop9a4qjXFZKJ6Xp1OFWuqqekCxX7hwkIldbRq0y72vmYffx1HZ6/uEzxxO3zCVtBuX0nP1HboXq9i2puoj28/dUlvav++44OlgbVv7siDM1duKMa4bfCJjdG2QX7Q11k71c75RJjnChBf9YqHlyUNcyylNNBIJ0Vp9vQmOeJ5FgMyA4vKcMkWfSzyTSMyb0k8r7Yg6aSaWHUPKgpRiKlqlipLVWB2dJGj1pGJcrGjlpt7+xHtqG0nUsNTe53F7mItXDg4WrYdzmp9paZiiXh4FUxVVhuhqKp7v/Zthy6cLf1L/Ek7PnD5qp/LNp5IkE3uU9v+TeOAvYIWb+HepFPt4lsvVWepwUjjgDS0FtnexKE7lYO2Xup46NJuxU5n6ZtMvcMOOyzDcwWW//NFG4Rtg5FW9dpe01q2DRpDgT/QHQSNdYEoJBirzZochQJ0B4Hduu3/asfRvvxqSUjte/be0sHKVsuO1dK2g2ZF0UUSUON7re8sUiWU1UEC2e4gYKFAHAA0/93T9Q4Cvi7AphTMCwRhufCmb+oDYYsrrTSqPjtIQ9HZ8wC/5K6rKnY0cS5tw4BiPUWA+rv26CkIqGwQAsyP1w1PCTLPCtACATsa2wZnxgsEBcwKBKk2hIAACIAACIBANxHIPCswxBcIGlf1e7YuEOi3DUp3H5puH+gmxKgLCIAACIAACHQrAftNBLY7CKKAoLFMQF+KWiLoVkOgXiAAAiAAAiBQNAHmypveXFd++nMFEAEUbTeUBwIgAAIgAAKhCcjPHBTkp7yOKIkjits1GLrqkAcCIAACIAACvU2AP23QtG0w5RFDRK/epTsFxK3jYRsJlyzdBGE6by+d30cQVslUaSY+jtxSk4WqVyg5qUCkBKkV9BWI9CAAAiCQKwGLN09ZIOC3H0ShRImPDHceqrfjZxCiIuH3+EmP9TCdLy1U0+MKHB9j4JisJNXPYHqvCmaQXxIyUAMEQKALCDT3CogvJRIqZg4FGm8har6/oKzRQMBxtn1R7CbggE0nuMCAurUjKlS92pfTvtFT53XaAYW8IAACINAWgdh3i68iUq/t9c8VePhXDzz1ovC0wXiNYNdJtb/+ePRcAT500igsPuhGHFK5O5TGWdFN2tNLwkkBF/mUTFu0qVwxPS9Cm1hbWfHS3zTNYD+vAkzVX9smuBzROu4uyoWPxZQWlfhP9nr5CndsD+7tTdXTRM+kaqj22VafR2YQAIHuJZDtuQL/+i8XPbs5jgYaMQF9f8XUvv3feOCbD54/Y8aM6dOnO7yOiN+HEPMVJ7q1bkyaGGdG4ZdufLg0TZibHCcXIsnn6VkRkr9JLVdqM6ryFn0s7Y0vYLvHB6o0sTr8V75ELX7hAQ2dlKpsSm/iKdlFLFe0o3tfU02grZepnVgK8pKT2t6k9mOPA7RFixLUgEyVr03vDhYpQQAEQMCRAAUBYhyg5jI8YijOFuUUlglciuQu0CUxCyykayzR90h+lHs1R+F2+SYhajTAUjIv61i06v+4EO62HUVJybj/EL+k+kspF1fG117ZdC5DLtGslhiiHVV926dv+nZ0Q14QAIFeJtB83HDDubPIgB+2bYOUqPloArf7CR39Ey/ekp6N3ZJP9R3EffVhimmjAUmfDK1KnETJkD1sFtPVf9hSSiWNNYacoh9fnr7pS0USyoAACFSIQPI4ARYExHqrG/+MoYD4guKxMforOcHdpOlqnorxHW1905tsYJKTQb5pbkAMYsSa8gkDiw5ikGGhV6EWxlUt/wUut4vFsqrtwtYrQzusYmOAziAAAuUjQG686cfVRwTotw2ueeiBp18cbbyHKAkDpk+sfyTeNig6AO7emF+UPCU/KU3PsmSW9CyBukDAz0tX2FyUmEUrXyyXXSOqBUkVVCtlIuBYL6l2ovKiPmq4YF+hkNLbE1s4pOqjclP584qYfhK7iiTQbhSTdZgdVYBilGYypbb9SIjUcrXFqWr4yhHJ4DsIgAAIcAK0bfDXv/71E0888eyzz4pY6vU6eXr6l5+cNm3aa17zmrlz5y654PIv/MtFz2+J/Xnye5Rut6l9897Q3DZoDAXWRaGA+P6CWhQKLP30+09dxH2n45ANQxZDAOYohjNKAQEQAIGOEKBQ4I477jjssMN22WUXpkB8rV+j86Oj9H2U/hwZGdm+ffvGjS/89rf/76ijjopCgWVJKMAjBVoomNMaClgePEwhRuudiHHB0gJB6qVnR3j1YKH8urbLlh560JSoMgiAAAiYCAwNDbE4gLz+8PDIjuHh7dt3bN689eWXX9700ssvvLBp6Jln//jkU/39/evWr2NCWp4okLxlUF4iSNs2yN9MKOiVbS8eTJsrARglV7wQDgIgAAIlIRAt+9MMADtGRuNpgB3btm3fFh9btmxlJ0VtW94z7LNtMAoZWrYalvVRgyWxDdQAARAAARAAgWIIxKFAEg2MjIwOjwzTsWP7DooJ4lUCtklQOISHCzXOtiSwPniY34DodidhMQhQCgiAAAiAAAiAgDsB8vT0iRb9+UODWjMbHjEkrC5E0wOGzO56ICUIgAAIgAAIgEDxBKIbBpK3FLfsGxA1cXhJseFFRsXXByWCAAiAAAiAAAj4EhCCAX1WpzcT+paK9CAAAiAAAiAAAqUiYHnPsCkUiNcE4qPxf+HhBaWqHJQBARAAARAAARAwEIhvH5C8eWPBoJEFCwRoPiAAAiAAAiDQzQTEBQI5Cojr7XQHQTcTQt1AAARAAARAoAcIsDsA+BZCscaWlxQnCwT0v76+6CM+37gHoKGKIAACIAACIFB5AqITb/p1l5cUx28wolcQKJ/KM0EFQAAEQAAEQKCXCOi8ufQIIsusQC+RQl1BAARAAARAoDcIJCsFQmVt2wbFJxOxVxPhAAEQAAEQAAEQqBAB9gICy6MGqS7pdxA0K4xYoELGh6ogAAIgAALdS4DePTg4ODh+/OCECeOnTpmy885Tp0+ftssu0ydP3kmutIPvtr2ZUHqzYfciRc1AAARAAARAoEoE+vr6Fr3tTz92zjmXXnLx8isu+8K/Lv/mv9/60K8emDBhgloN+T3FSgrbzYTaWw6qhAq6ggAIgAAIgECXEpg3b96CBQsOP+II9tn/9a9/xe67p9Q1DgrUJwZa9wqw+w/xLqIubUaoFgiAAAiAQEUJjI6OXnb5FX/+7ncvXHjMIYccduCBB++99+tmzpyzdetWzaxA2nuGffYKVBQY1AYBEAABEACB7iLgtUCQWvX0vQJMhMO2g9SykAAEQAAEQAAEQCAMAfcFAu7BTa8oTJ8V4M8rRjQQxnqQAgIgAAIgAALtEXBfIGC+W/vqAa6CZdug8IDCxkuN2tMcuUEABEAABEAABAIQ8FggkJ255jUCxlCg5ZnDY9FBzyIm9e/THZmrxYVllmDJKGqah/xyymS1LqduRWqVN4e85fuyctfHntJdjq+GLL0qvzf7qS+9vO3iq0/B6XP1FAXXJWBxixYtOvHEE9+2aBH7HHLooa969as18iP/LXwSh96SUB8KUKYdI8JntLZjtDY6GuVcuHAhE0Bf2JFaMZNnYueZhODeiwvPSX5qrdUEwevorkOQooMIcdeZp7SU2ymVMtTCPUvelSpPjxBHEnc+SNn1BNQu4OJoyoMl7y7MakoLBEuWfvytxx574IEH7bvvvNe+dp/dd99j6tTp6h0EozqH7vQOgh2jY0+9GH3WCp+XtutRi0YyxW4qGjEOKNvYlF+TKqCJqPFZwEIDivKCrC3XroxjnOqlhpg4V/kZOHvpY+lxXnIy0MtbfgaVKpGld7hlaPylsmBh+o+MjGzfvn3btu1bt257cdOmF1548fnnNz733PMvvfSyBIR8t+jKmXMnLy8mq69Zs2bLli2bN2/euHHj+vXr165de/3K2x54YNXP/jBC6VjaaNPBWO11M+uf/vT516+4VLqal0IBHumLxYhZ2HnpDP9T+kIpuXwRsfakmlgbS1rkiEOkNFzSn1qd1fpq5WtrzTlIPkZNLDHnhWrPm6BJqpr09NJfqoJkFw4tsx0zc7NUVlRGaora5tem3b3am6m+Js52/tp2xU+61EttYI790b2/uJjYNMioA4tYZft3SzvXZrTbkf/qyMfUPt25efVfix1NlDLIZz3LpV25FOrehd2NbulHLiqp45t2ALH3O/FXk11M5+mK/2tf+9p73/temuMfGRmlaIDmBuifjS+8MLxjOD5YfLBt552n/PQ/f3zKyacsueDyCy+68LGhMX4fIFsLOHTPfppOePPB82fMmDF9+nTDXoF4YYGCBra8QF/Yd6kOavjDQlfVAVuuQiQD8JRcDiuFo9GKkhLzsZ5ySUra5aitQa2LXZ9UPaW2KDZ3F0qifKnLWcgzIGICk56++pvSh7KjyEc7NqlNTsuBy3GBzNuP2mk5SampZONpGn1UJS12sddX7AumvibBcRlY7XZ352Yff9V+bWn/WlFsBJCO1PFEFZV3OzeNM8W0N/f6+to983hrcSUuXThvu9t7rjreuvSpHNO07BSojcQOPbnQb5Rq2TYoKNYaBGQYOCzjkVf9Vdduya6OI15lqWO92l1NKCx6urTjdvT0ymvSM2/9vezIIfMR3KuObSYmVU12FyWLZjX5ZovPVpWU2omLfN+aSqGkb3ZmDjE+kyIAF24ZCvXKwj2K+EUajrzs4lV6hnbeqfbmMpC61F2rfwYOLmWl6ixZv02Zlc8u+HHVpac/V0CKHSQcUm/nsZiWWvteUOrPFtvwxtd+oaIrchw17HqGUqn9pmnSM2/93e1ocrft191RAjOWi91ZmoCjnhoNBJTffhzAsWjhuHNzNETwZMHtpY3neFN31N+dWwH6O+qsdlKpSWTr7xlKR5YUArqrepbFIRRIo2u6LLBHA+Iw5zsqBRxt0yrn9HtO19YckchHOumkXyORr55VmRtosz1oOXuBpcQuoaeop2OhYjKxGXh1OrUu7j3ORc82+Xuhbqf9iwW52MtLMUviPPi46J+hvWlrEUp/Xzm+6UPZK5QcVX/1UtnUv1z6XSg9mRzDtsFVq34abxsUpwT2mVk///zz33/qIlUDprf7wSeR+IgmSpCGOf6TeF46KQYW9vRs1Oaqastl116Uhn9h6aVqpspRs0iI1Oprx2jTwC2dV92DisLE2eW81qNYEIWyo6lc0ZSW9iPaUdtOuHyTr7XYXWwYGdqDo0tm/cVFPtdH2zZcqi/S1vYyCZfUNUxKSv3OxM2Fp9Ze7oOPXX+LHEf+2carNrk59l/H9sYguNQ3dbC1yHFBrbZArcvwsr4FtVZOKgfRX0joTEOH9rzqRlV7Zdw2eOGFv6Ftg/yInz54BG0bPKi5bdAaCrQuLewbhwJ0B4EX9wyJvdprBvnVypJhTC9JBatlx2ppWxITF6+GGq75XocE17nSLUe9fpBiu+C41DhDLKLj1sypvqHEZg4FHh0aa3l1QN09FHginhWIDxYSFBMK+IZsoRCXTY7jVUJpe05V7FgVPcvWPjuoT6lMViplOmgUFF0MgXZCAdJQjAaO2MtxVqARCvCpgWJCgWKAohQQAAEQAAEQqBaBNkMBMRqQQoEA2warhRLaggAIgAAIgAAIiARSQgHzrQfACAIgAAIgAAIgUCUCJp9uCwUQB1TJwtAVBEAABEAABNIIaD2729MG00TjdxAAARAAARAAgWIIxO8ZHqMXENAR/T96FwE7Rkbpz7H4PcLmI9PTBnOrGW2+5UduhQQQXBU9WVWZtgGqXU0RlWhR2dBma4deQCyJe7xdWUyWzS7Z2kAVc2XjY2pvXu25Ergy8GHvIopePRQd0euIhqOXEe0YHonfRzQyQgl8666fFfAW41tsnJ7fCJfTHXEZPKI2C6mXk4aZsCFTk4BqrxJaKu92aJfvDoTJER9D1N1NrbN2KT/bcvJxb895E+4UH3qLIL1GuF6v9fX19ff3DQz0jxs3MGnSxJ122mnq1CnTp+88Y9ddZs+aSe8nnLbzNPeJgS6/g8DLWl6J825nmeX3TuBSIXt5qeqVmE8FZW4wakZtE+rKduWF2itxHnYJaGJHUV5V9kqcyqcS7c2ryl6JLXz22muvH//4x9d//fobb7rh5ltuvmXlzStvveW737vzrru/d/fd3//BPXffe98P7v/hvf/934/PmjXL0dCUTP+0wVX04GHhEUNMHHuuAHvwsPgY1HbCNPFCxF1p95SqfG4P6WmRqdeX7qqKolwenGlJz2uqPuDT8rRLccaFvmvlm86rl4ap9s0gX2xCatUk/bXmtthL+smuf4b6ujc/njLvdqhtnCYOdnuZnn7K6qI1VjvtzQSzR+yijg+iD7A03V7jI41XqUNEt/Kh5woMDQ0NDAwMDg7SrADvPvV6nRYF6F/xDP1J6ZdccPmFF15ITxuU+ho9V+Ag4cHD3rMCfP6QR232YId+VY8Mg2m2LOpsp2mk4+dZvVL9X+oQJhVt4sabrKoqa+5aOWLpYnBjqZ0kx16uO22THNN5k4a++qTay7F9ute0nZR5t0NVvsRTDUq07YENuGoMYeoOKmTf9tAO1fbzdtwuYufl3k4b2LVf2QwSiucjDnrqKNfOyJyh+qlZOsInVatsCbxDAd9iuGcVv/gKaSe91sWyXpfZ37ejjzavOv6mFuGov1h9U0cK1cG85Gj1z8AhFVRJEuTdDk3yHdubFFq1CU0bT3BX59VO2tQkNXtH7KJt51JXTdW8mAQd4VNM1YKU0jV8cg8FguBuU4jWWuxkSUalDHGSu/5MeNm8rFb/DBzabBtFZs+7HbpHA3lz1sovZztkgwAPU3h7cO9fqU1IlZ83/1SVvBIUz8dLvY4n7g4+FQsF+FqDZH7Tealj29cyeOJOec08yuUyLX5CLJcnyzBLGUp/Xznu6dV2kq2+pW2H7tEAc36OPSLbaCvKt7fD3rSLxF/scZJdepOPe6sDH3dWppTZQwGpb2dQhTf3XMcjUzSgFmqaoNOOaKb6proWiVtqejXoYWdU/e0jr+TaLeWyn/jVkt2yJjmm8yaj+3KQLua4zrya7u3Tq74Z2rmURfLWwdshv5zlzl5t2CocS2cM0v4z29exHVbRLmLVxO7pGM91ZbuVIlQ1gqQzPc6n/aauleB9B8H1Ky6VnEpOmnWf2EpzM4VrfDzKyV6dKjen6kAsCIAACGQmkN8dBN6hALuZ0P2qMXOduyyj6NLydp9dhg7VAQEQAAEQIAL5hQLeCwTV2vBSntYDbuWxBTQBARAAARAQCXiHAsAHAiAAAiAAAiDQTQQQCnSTNVEXEAABEAABEPAmgFDAGxkygAAIgAAIgEA3EUAo0E3WRF1AAARAAARAwJtA9UIB6bkc3jVGhtAE+PM9ink+RGj1Ky8P/MOaMCxPjFehrJPNLlr+XJS7biY7ZhDlXmiRKasXChRJp7vLyuC5tVnYzREqqwzyuxu4VLsMfMDf0kLAs5zdp2x2EZ/vkkE3CXLX3BlevVDA5HjK2Q1KrpVXT/BKzCqeIUvJiYVVz4uPV+Le5O+FyCtxZp4Yr3zHgbB2sfD3Mo1X4rCjRDHSvB8xxJ82yPTTPvBV+5PlpCqHnRHDN6k9ibGY6ek92vNqSJga1mWQ76W/1tIZ9MzQYiTCImSJv9o/JW6qKC5NNRYXrjW9eNJUKa5PhnaiZlFL6W7+Xu3ThNrUL3qqPfuOS6n9SKLn286zyVcfTZ1hMLFkKX6cSbVL6rDPq+My/qcOWaHGkxI9YohXSXoQNP+TR08spSk9jwy0csRWJXYG1X4m+fZy3Ru6r3yThqH0cdfcJaUEX9ugpW7Mn5XUjnyS6dVO1LJ8OYv8tVGLS3WCp+kUf7V/ubRz7XCmViE4JXeBxfO09Gv79Sjva6rzFutraucsu9SJeEaWqzymKd4unI8ptCLsdvIizFS/495ES5uyoAUCd+5iLOYSuEnxrDaLpU96GcZLDvN2akN0bH9eirWT2DReaPXPUFCG8agrOZvQdYp/m+3Tpd9laC3tZymYZ2EcVHuxQbVs40nZ2rmkDx+TvQaZ9ptl+SUUFArwANbFuzNqPLBNzcKEl61XaPXPwKGANqQdPd35p2qYIRpIlaleAIntpJycvUbJvPm33z7L2e9MV8P58SyGg6S/NBvh3l86mLLS40wHuRVTdEGhAKtMHt6ay7T4G7FcnizDLHEo/VU5aoCfTU/ThULqBYSXt87AIW/52t5isbt2tka8wAJ/MSI3tViT3+2d9uwy/hQzlLuU0jt2caGRX5pQnPPTUJXsHQqkDpFS30hNrw7KPG7QjtdSVGGSbymXXz6mzjeII50UOpjkc3ciTdz5cuBFi19ybRmSt1YnHsUEIjrRT1iiBIl2Tu3Ebnd2AeeI0audOMq0JCuGf4b2yaBJ3NCeGQELB3u/cGyHLvaSWo4Yw7k0y65s59KVJ7eFiacFlNaOot21/FWBBXN2Mb2YJssdBKYyMlxn+6qbX3rV8/n2qPx06zLJXu0klF3EQr0U6DL4vtUBN19i2dKHaufZSkeuqvDP7w6CYKGAOrmK5gUCKoEOtpMOFl3plgBulTYflO8mAvmFAt4LBCasfBbRceKrm8yDurgT6GA76WDR7nxKmBLcSmgUqAQCYQkECwXCqgVpIAACIAACIAACxRBAKFAMZ5QCAiAAAiAAAiUlgFCgpIaBWiAAAiAAAiBQDAGEAsVwRikgAAIgAAIgUFICCAVKahioBQIgAAIgAALFEEAoUAxnlAICIAACIAACJSWAUKCkhoFaIAACIAACIFAMAYQCxXBGKSAAAiAAAiBQUgIIBUpqGKgFAiAAAiAAAsUQQChQDGeUAgIgAAIgAAIlJYBQoKSGgVogAAIgAAIgUAwBhALFcEYpIAACIAACIFBSAggFSmoYqAUCIAACIAACxRBAKFAMZ5QCAiAAAiAAAiUlgFCgpIaBWiAAAiAAAiBQDAGEAsVwRikgAAIgAAIgUFICCAVKahioBQIgAAIgAALFEEAoUAxnlAICIAACIAACJSWAUKCkhoFaIAACIAACIFAMAYQCxXBGKSAAAiAAAiBQUgLeocB9uiNz5biwzBIsGUVN85BfTpms1uXUrUit8uaQt3xfVu76uKf01QHpQQAEKkrAOxRYuHAhqyp9YUdqzU2eiZ1nEoJ7Ly48J/mptVYTBK+juw5Big4ixF1nntJSbqdUylAL9yx5V6o8PSKVSd4oUhVAAhDoEQLeoYDKRYwGTFf5apcW44AKjU1tNosChjY1PgtYaEBRXiS15dqVcYxTvdQQE+cqPwNnL30q0eMyQMhsTWQEgR4nUF+zZs2WLVs2b968cePG9evXr1279vqVt61ateqnT4xIaPadWT///POvX3GpdDUvhQJ8zkDMLmZh56Uz/E/pC582kGYOeKHSeCGd105aiFm06bXTFZRSq7NaX618ba2lSkmiVDWkEVxSyVIvyYeJyrSpv90uXMPMdszMTQuTc1AbrchWUrtNu3u1N1N9TZwd+4XIn0OwNzAJiNRnLf3UNKR6cVDjAPsEZOa68IJcJjh73Fug+h0nsHXr1qGhoYGBgcHBwb6+5pV8vV4fGxujf7mG9J0OSr/kgssvvPDCR4fGJOWP2Kv/oIMOevPB82fMmDF9+vTsswJsAkCSnqwZKKsG7lchPCW/ymGl8K6uFSUl5gOfqqRdjmppdYCw65Oqp8X9u1AS5UsuSntdyPWXTGPS01d/U/pQdhQ9utaXqE3Ocn2sthNT3zbZnTUt06+qfN/2ZqqvRY69vmJfUHurtjW6jHcm+9rjgAz8TUOKi5KWNL76t1kcsoNAyQlkDwUsA5C2zi5+LhWWNv6wjOZBCmXyqWjVAfCBW/rJomdAlVJxpSYw6Zm3/l52NHnH1NoFSWCxuyhfNKupa3h1GamduMj3ra8USvpmR3oQAIGuIZA9FBAHaI6DDfHqbEGo0ZxfIpi8sqQJ/RnK9TI5jqO5Xc9QKrXfCk165q2/ux1N7rb9ujtKcLc7q1SGKMcSy7IYVIw4Q8lHHODYAJAMBHqBQLuhgDhUufAS5+V4Xt9RKdRo6KKwS5qcrq05K5GPdNJFPTU8knLlpH+qbhnsqI2iMsjRRhi+7VAUwnWwxHminlrjqsTEZKJ6pmg7lTlLoNbUpI+jno7lZkum2le95Ciz/tlqjVwgUCQB722D7z91kWnActebT7qKVzyix1JHainm4LMC6vgo/cREibMI4jCqPc+u7VguU2KTPpbzKh+1+lpvZHJR0nnVPagovDhI3LT6WxBJ+tjtYrGjqVwRtale3Pou8k2+VhQu2VdsXantSuXpGHyw/uIiX1tfyfdbCnVsaawUk31N40Cq/mK/k4owmUB7XjopVT91nHEfx5ASBAomkN+2Qe9QgO4gyLvyjuNj3mqURL7W34uXnurAV07NS6KV3VGVFmYJ6VW9n1Zd/xI2CaiUN4H8QoEACwRhK88vHdRr3LAFlVwaVZ8d0qVkGSZsXdBVxY4mzi517OU0VbFv6hRFj48zvdyGUXeRQBlnBWAhEAABEAABEAABiUAPzQrA9iAAAiAAAiAAAkUSKN0CQZGVR1kgAAIgAAIgAAIIBdAGQAAEQAAEQKCnCSAU6Gnzo/IgAAIgAAIggFBAbgN83z4aBwiAAAiAAAj0AoGMoUCoO3BCyekFU6GOIAACIAACIJAHgSyhQCj/HUpOWC504z6eMxMWKaSBAAiAAAiUmYD3cwXUBw9ne9CvGgfYHTBPLz2dVHwIj/qdo9cqSb+mPojX8nRVk0pltjd0AwEQAAEQqCiBEj1XgPtOdvUsuVh+RnoYmXreJMdkIdNzxe0WVctl6bXnLfMB9nrhCaYV7VdQGwRAAARAgAhkWSCwgFP33ElPy29/7p2KaF8IbA8CIAACIAACIMAIBA4F+FSB6K3ZyVA785lkyxU8TAsCIAACIAACIOBOoK1QwOTdxfPSO3W0WwVDRQnu1W4/JZ/tsNRI/Ul8+Y2og+l8+3pCAgiAAAiAAAjYCWQJBaQ5f1aA5BrFrQD0qxQQSFl4douupjehieWKimUwvDaCscjhUyAZykIWEAABEAABECgJAe87CK5fcWlJVO+sGqY7FzqrFUoHARAAARDoVgIluoOgWxH71ss0C+IrB+lBAARAAARAoLMEsiwQdFbj8pSu3SNZHvWgCQiAAAiAAAi4EEAo4EIJaUAABEAABECgawkgFOha06JiIAACIAACIOBCAKGACyWkAQEQAAEQAIGuJYBQoGtNi4oVT6CKT8gonhJKBAEQKBsB75sJ2euI+GMDpMfvq0/jN712yJJRzOJYkDZL2Vjb9enxFxmI73bKz3DaUgI2ngKMmBMoF7Ha2hVQZW17cFE4W0MKUqPUgTGbbh3PlR92x6qFUiCIlVWdQ6nHJKvSqnEzofYpQOKzhhwfASQ9nii1iXCjOspPFYgEeRMwBYi5liu1E7Gzqa+byqCJ2P7VCmYQqM2S0ws4UsXmNHRKQ547pVSFRVFe5ujgMOKlpzurgCm9sAcsl4vquAL2dhVQPbHHFdAwgi0QZPPHvjVU09tHKPqVHXk0yrAye+etCgWYQ7W7qZ3Ysbu3H7H9d58pLb2s/crm3R4yyDdFA+7tIUOIk0HPsENQT0krf7sVo5+AEYbJygMdNz91AK962tN7iZLqLnZFdWGC/yr9xIRoT2rPU0ppYNWWS3m9zqshZCqKDPJZjRz11zYtXqjKUxo97fpnqG9HmrpYTUduLnbhdVH9h1f7FJuoJFPtAu79RXsNZ+lfYmv3aremSzQVgmP/FTVnjj9VH3u7UiXkwSF1/DGNJ5Z+ZGm6Yld176dcBzXSUvW3jzOpdrcYxc5fGs9NclLHMamylvG8I+OSWmj2WQF1DErtEtJQaBnOUkU54mOhn0tn5rpJzZT/yeWwlKb0vCVp5WhbsFZDk3x7uY5YLPrbOaj6++rDbWEyjcTZvUZiSpNwNrirTZeflJqKe/vh5pbkq20vtf2IhUojjqkxs1LEJpfaPqX0YmdUR2qtFSw9SzViartyRC3JMRlddGNilxTNoeVsb2+OSkpCxPaWEwepSbvzt7s6Jkc7btNJx3aiLSKVg+QdTHb3HX9Ys1d7pWncNvFJHcckPr56ih1fHa+yjYr2XNlDAZOBTXpr6ZtMkmoAS+nFgGMKaP2KnThvIqmDjuqwpSyWNu3VVrzkaPXPwMFLw1CJ1SHSdwiwaGJ3Le7cGMwgzTiDHN8u6Wga0W14tTdH+bwzunMLyDnbeOVeNYvDdq9v+8WJEnzbia+eAcfJsBV3lKbl494fpVDDsdB2knmHArxLa6NFeyfXRpG+TcqSXv0p797OR3/3WrCULqMhS+PeetppB+55tfpn4OBeYoaUoeweSg6zuGp3lZt09ZCh7tJ4LQYo2aRpu20GUbm2Z19uqel5ArGmGdqD+8iQGanLYJJBeGezVH2c1NIr2zgpKukdCuTRPnx7i5g+1DjVTr3y8NZcpqWCYrk8mXYIs9culP6+ctzTq0NwO/VVB/d2rM/ycg07yN9UC3fOJgnt9zLf9ixRbd9A3EYuojIY0SLWd3zztZdvehcCUv9yyWJyfow8u6ph0XBmaWpGl3YVsDitKF/+vunz1p/Jzz0UYOb3OngWx7yWVut+SZTqWqQ2l5peqrKlUmLLUFu21H8s5fI+5tLZTHJM5036+3LgY4FUL/6nRMBlhFXrq9rdt76sXK/2o+Xvy03UU3TApvOcjwQh1S5S+tS+pkYD2nZrsldqu3X0Exn4qBjFRsi8FHNXTHmLJu7toUgOvDqpnUXtXJZ2pa1sajtxHOrbGWdM/cKFA7OvaOvMNdK2K5O01P7o7i8cCfsm837E0PUrLvUto+rpHQepclbT3jTz07lT5eZXIxfJlW4qLhVEmh4hILZktOryGD2/RwwhFEixsujSXK62y9NooAkIgAAIZCaAoS8zuvwy5hcK5L5AkB+UYiTzWTLEAcUARykgAAJlIIChrwxWKEwHhAKFoUZBIAACIAACIFBGAggFymgV6AQCIAACIAAChRFAKFAYahQEAiAAAiAAAmUkgFCgjFaBTiAAAiAAAiBQGIHsdxCod5gE3HHKRRW2Wa/4EguzcbaCKg1E2xSl+xtTm5apPafKUW/EkkzAiw7YZbJZGblAAAQqRKAadxCwHaftY00dSUMVIcoJonn7iuUkIcNjNLoAiNggeaPiJ+1MxPRkFPGZJPSn+PQVSY5WrOnRNKG6TE7NBmJBAAR6hED2BYICRrGcisjgFyvdGnqtvqnGUoHQGXak5hUTaOV4SUBiEAABECgDgSyhAB83HYdO3/QmLlo54iDuMpqLl3em9NJ5L/0t+pjkaLOIOjjqY+LDeKrezkWf1DbqW1+xUKn9mER58XdRODUNv+63pDTFAdJsSk7hrEsVkAYEQAAEHAlkCQW8Rjc2YjrOyjKPJbouXg2THHUe2x6g8PSmOVvKLj5c2ld/kz4mOeJ5/j3VA6k8U/lI9XXRx6UNWfhbZtHt+oscfPln09nUGHiD1C6XiCe9bOeiJNKAAAiAQGEEsoQCGZSTrmstEiRX7V4Wd+HuWbQptYO+u/5i7KJ1k/ZIxVF5VR8xfHGP1TLUy6Shyl+dh3CsnZoslJ6+8E0O3iRH1FOd82AxcWYIyAgCIAACOREoKBTgV135DYVMsrsX9AKaQX+tPhnkmOIV9UKWnfHymqH04U5OutwPZY7gekpUtVGL/UJfasmqhr5zBl4NEolBAARAICCBgkIBprGXlwpYScuFrNdlYij985DDZYrTA1qHl981dzsm42pbLNI+N/dIVFqkkLRyl5ONScAJlWwKIBcIgEBPEcjyXAF1sDa5H/V86hgqCpcSa3+ypLcYkufiRUhnJE/ARQXXn0VIoqpalVz0cUGnXqqyorXn2RyD9KsaXpjgiEi5HLUiKlKp0AwmTm0q9kqpRhHT28MCS9GmmtpN0FPjESoLAiBgIZDfcwWyhAIwVU4EUv1uTuWWQaxLiFAGPaEDCIAACHSKQH6hQKELBJ3CV4ly+dWkZYa8EhXJpqS0QJA6+5KtFOQCARAAARBQCSAUKEurCLgzrixV8tQDBDyBITkIgAAIhCGAUCAMR0gBARAAARAAgYoSQChQUcNBbRAAARAAARAIQwChQBiOkAICIAACIAACFSWAUKCihoPaIAACIAACIBCGgHcoID7mRX3kC380irgfXj3porsq3JKrgEey5FqERbgLZBeeZUvjZd+yKd++Prk2J1G9wgpqk4mXnl6J21QM2UGgFwh4hwJ2f0y/qo+eZVksT8FrE7Tp8TttipWy53d7m6/+oZ7mG5YPpKV2DTFBfs2psHYb1uLuQHz7S1g9tdJC3QAcSk4BVUYRXUYgWCjg8ngcr2ggg8Nzz1LOqwqt/u6VqlbT7NZ6qVbA+J5TyyxJEwpl31BycqINsd1NwPtpg+8/dZF0iS86eG1o7/sgOcujW7kx1Afluj/VlYTwIlyuRaQuqtbXfpkipVeLNkVRWg6cgJrLnt7uojgHLtakpzjHI5I0nVefXmzS0+u8b6OSVNU+aJk3bKmFSKi9OKvju4Ra26RNxtL2NRduYtVMI5ql33EjahGZTkqFhtXTsb+LzdjlcsXUTkztzWRfUz/yldPd7ge18yXQW08btAT70uqD2G/Zhb7qKbVTEUyOexzgmFga1rVBg1QFrrOkPxtGXTRkhfIhRltfi2uR0vM/tXqq/HkEoJUjlisOyqZx3GRfU7nuHcnEx3TepKEvZy7H1OTarJpjvVJB2TnQr222h7B6sgbv0t9NdrTHQ+5GMdnX1I9M5aa2k1QLIgEItEMg2AJBO0q0k1fqQu2I6kjesPqr8UTYSmWQz7xIqhpS2KTN4hUbWUr0kqPVPwOHVALtJ/CqV/vFqf44VWb73DL3F8d2mFoFJACBriSQVyjQfp/PFTdTT7yqyLW4woTzS08X75tBqwzymSYuXoqlKZtdtPpn4JCBdvmz+HLwTR+QgHs7DFgoRIFAVQh4hwL86o3P+LGqild1pspLWarCqHJ65u1N85DPZVoakliuqR26GCuU/r5y3NOroapLfd3lu1ByT+Nbrm96d006mzJUvVQ53Xrp0ll7oXSRgPe2wetXXEr5TU5dvM7WjukuV6vqxTq7WJQCDlW+JFxVJpvtuRytGkwrrp5ERlWb6+Clvz3eShWlrbiJj8SfU9Wmb9MupnqJprTY0Su4dKmvvbJM2wztSmxCohDecnjblorQNmnHdm5qt/ZIXbSIWl9RT6/2YOHmpWdqY5D0b8dYFqNou7kpvUklaTwREZlM7DJ+ZhvlkKsSBPLbNpgxFKgEtbIp6eW3Oqh8VfRMjW/EBHmPoWr8qvrUDtq0naIr3R7aqXibecGtTYDIrhLILxTwXiCAebIR4K7C5DOyiQ2eqyp6miourkYXuTLdqXKDNwBJYNXbQ958TPLBrVPkUW42AggFsnHzzlWkW/JWTshQFT3bqSPyuhNAe3BnJc1CcXTZJCAXCBRJAKFAkbRRFgiAAAiAAAiUjgBCgdKZBAqBAAiAAAiAQJEEEAoUSRtlgQAIgAAIgEDpCCAUKJ1JoBAIgAAIgAAIFEkgy82E0k3S0i31pL14m7t65zTSl4SPtp2pNzhonw/B8lqeZ2CSY2rc9vTa+7K8nhNg6VRoz8yUVedQ5LiJskCgIwRKdDOhOCibng2C85KPdHk2ETWsIrlZ2jG/BV+8F188ybZGMwm8PVjCApd7+iX5Ig3tfVmmci36WEKf8tsL/U6MV1R7dWRcRqEg0DUEsi8QmC4Wcd50xVzO81JTlty2xYvbHby7HHtf8nXtmXsm2m0526evXTI3AGQEgV4mkGWBoJd59UjdLRPyfGiWljlSr7lT0akXvtrZFHu5eMRbKmckAAEQqCiBEi0QVJQg1A5FgHytukgvnWynLC7KZdZBLZcHCurmg3a0Ql4QAAEQ6GIC2RcIuhgKqmYhIG4U4FPKplncDCSZfCkO0IYaPJnk9U3nMyiDLCAAAiDQCwQQCvSClcPXUdw2qN3RFrZIS3AgRSHSpALmBsIaAtJAAAS6kgBCga40axGVgpctgjLKAAEQAIH8CSAUyJ9x1Uqw3LxHVWGX3TyNtDYvTuxr5ZhgeCUmIaZyLfpUzQ7QFwRAAAQKIoA7CAoCjWIYAdNcgn2TIOiBAAiAAAjgDgK0gS4hwHcFSl+6pHqoBgiAAAhUkAAWCCpoNKgMAiAAAiAAAuEIIBQIxxKSQAAEQAAEQKCCBBAKVNBoUBkEQAAEQAAEwhFAKBCOJSSBAAiAAAiAQAUJIBSooNGgMgiAAAiAAAiEI5DlZkL1nnLSh785hn2nf/lD6JAefNAe0C/yHgfCjYqQBAIlJVCimwm1T5nVvkFO9H/S02GRnjU0cAAHHiShPYixgu84U9KRG2qBQEUIZF8gML2BBue5exNHed4ewAd8xMEB7SFse6jIwAs1QaBcBLIsEJSrBtAGBEAABEAABHqAQIkWCHqANqoIAiAAAiAAAj1EIPsCQQ9BQlVBAARAAARAoHsJIBToXtuiZiAAAiAAAiDgQAChgAMkJAEBEAABEACB7iWAUKB7bYuagQAIgAAIgIADAYQCDpCQBARAAARAAAS6lwBCge61LWoGAiAAAiAAAg4EEAo4QEISEAABEAABEOheAggFute2qBkIgAAIgAAIOBBAKOAACUlAAARAAARAoHsJIBToXtuiZiAAAiAAAiDgQAChgAMkJAEBEAABEACB7iWQ5XVEeb93vFPyTVbm70sVX5xKifM+36lW51uvquhZtnr56uOb3t6e6VfxpYj8fdnVPd+pdohyQaAwAiV6HZHve8Srkr4wW6IgEOgggar0R189O4gURYNAFxDIvkDQre9Zl4zKpyikL3mf71Tb8q1XVfQsW7189fFNn2qXHum/qRyQAARAgAhkWSDoNXC+E7Oh0neKs6/+VdGzbPXy1cc3fafsgnJBAARyIlCiBYKcagixIAACIAACIAACHSGQfYGgI+qiUBAAARAAARAAgbAEEAqk8PRdow2VPqyZ3aX56u8uOWxKXz1904fVVpXmq49v+rz1h3wQAIFuIoBQIMWabHcVHdKXvM93qpH51qsqepatXr76+KbvlF1QLgiAQBUJIBSootWgMwiAAAiAAAgEI4A7CIKhhCAQAAEQAAEQyI8A7iDIjy0kgwAIgAAIgEBPE8ACQU+bH5UHARAAARAAAYQCaAMgAAIgAAIg0NMEEAr0tPlReRAAARAAARBAKIA2AAIgAAIgAAI9TQChQE+bH5UHARAAARAAgSw3E/IHn/XI+85Nr4HJu/XkXW4o+aHkmHjmLb/qdvTVv9f6ry8fpAeB0hIo0c2Evu8Rr0r60toeioFAQAJV6Y++egZEBFEg0IMEsi8Q9Mj7zk3Pfs+7reRdbij5oeTYpwToV7WgvE0QRH7efDIr2SP9NzMfZASBniKQZYGgpwBxJ0RDp3ilUgCEvCfGQ8kPJQcLBAU0KhQBAiBQXQIlWiCoLkRoDgIgAAIgAAIgoBLIvkAAmiAAAiAAAiAAAl1AAKFAihE7tdabd7mh5IeSY18d4Ms04pdKdL+8+VQCApQEARAoOQGEAikGMr0nPm+75l1uKPmh5Jh45i2/6nbMW3/IBwEQ6AUCCAV6wcqoIwiAAAiAAAgYCeAOAjQOEAABEAABEKgAAdxBUAEjQUUQAAEQAAEQqCIBLBBU0WrQGQRAAARAAASCEUAoEAwlBIEACIAACIBAFQkgFKii1aAzCIAACIAACAQjgFAgGEoIAgEQAAEQAIEqEkAoUEWrQWcQAAEQAAEQCEYgy82Evfa+87xft2MyZqhyQ8nxbXR5l2uSH+q8b31904fS05dzr/VfX7sgPQiUlkCJbib0fY94VdKX1vZQDAQCEqhKf/TVMyAiiAKBHiSQfYGgR9533qlnyIcqN5Qc376Rd7km+aHO+9bXN30oPTNz7pH+62sXpAeB3iSQZYGg10j5TsCG4hOq3FByfOuVd7mdmmD35eC7ABSqXqH0hBwQAIGSECjRAkFJiEANEAABEAABEACBIASyLxAEKR5CQAAEQAAEQAAEOksAoUAK/8xrsW3aNVS5oeT4Vifvcju+1u4LREpfdf3brD6ygwAIlIoAQoEUc7DdVXSoX3I1ZKhyQ8nxrWze5ZrkhzrvW1/f9KH0zJuzb72QHgRAoIoEEApU0WrQGQRAAARAAASCEcAdBMFQQhAIgAAIgAAI5EcAdxDkxxaSQQAEQAAEQKCnCWCBoKfNj8qDAAiAAAiAAEIBtAEQAAEQAAEQ6GkCCAV62vyoPAiAAAiAAAggFEAbAAEQAAEQAIGeJoBQoKfNj8qDAAiAAAiAQJabCXvtfeehXg/jKydU6/QtN+/0oeqVt5y8X6fUKf17rf/mzRnyQaAwAiW6mdD3PeJVSV+YLVEQCHSQQFX6o6+eHUSKokGgCwhkXyDokfed5/2s+Ko/q9+XT1X6TN52yZtDqv490n/z5gz5INAdBLIsEHRHzd1rkfeEed4T0Z3SP+96uVswW0ron40bcoEACOREoEQLBDnVEGJBAARAAARAAAQ6QiD7AkFH1EWhIAACIAACIAACYQkgFEjh6bsWHip9KDOH0ieUnFD1yltO6lp73gq0Kb/q+rdZfWQHARDwIoBQIAVX3u+Vz/t9853SP+96ebXyDImhfwZoyAICIFBRAggFKmo4qA0CIAACIAACYQjgDoIwHCEFBEAABEAABHIlgDsIcsUL4SAAAiAAAiDQuwSwQNC7tkfNQQAEQAAEQIAIIBRAMwABEAABEACBniaAUKCnzY/KgwAIgAAIgABCAbQBEAABEAABEOhpAggFetr8qDwIgAAIgAAIZLmZsNfed47X0mTrJ6G4hZLjW4tQ5YaSE0r/Xuu/vtyQHgRKS6BENxP6vke8KulLa3soBgIBCVSlP/rqGRARRIFADxLIvkDQI+87r/qz3Dulf6hyQ8nx7duhyg0lJ7j+PdJ/fbkhPQj0JoEsCwS9RqpTE7yhOHdK/1DlhpLjyzNUuaHkdEp/33KRHgRAICcCJVogyKmGEAsCIAACIAACINARAtkXCDqiLgoFARAAARAAARAISwChQArPTq31hjJzp/QPVW4oOb48Q5UbSk6n9PctF+lBAASqSAChQIrV8N76bM06FLdQcnxrEarcUHI6pb9vuUgPAiBQRQIIBapoNegMAiAAAiAAAsEI4A6CYCghCARAAARAAATyI4A7CPJjC8kgAAIgAAIg0NMEsEDQ0+ZH5UEABEAABEAAoQDaAAiAAAiAAAj0NAGEAj1tflQeBEAABEAABBAKoA2AAAiAAAiAQE8TQCjQ0+ZH5UEABEAABEAgy82Evfa+8069TiZU6+yU/nmXa5If6nwo/iY5ofT05dxr/TdvO0I+CBRGoEQ3E/q+R7wq6QuzJQoCgQ4SqEp/9NWzg0hRNAh0AYHsCwQ98r7zTj1DPlTb6pT+eZdrkh/qfCj+9ikB+lVSuDD9e6T/5m1HyAeB7iCQZYGgO2ruXgvfCVh3ycWk7JT+eZfbqQn2UFaruv6hOEAOCICAI4ESLRA4aoxkIAACIAACIAAClSCQfYGgEtWDkiAAAiAAAiAAAnYCCAVSWkjea955N9BO6Z93uaHW1PPW02Tfquufd7uFfBAAgSIJIBRIod2p982HagSd0j/vck3yQ50Pxd8kJ5SeeXPOmwPkgwAIlIEAQoEyWAE6gAAIgAAIgEDHCOAOgo6hR8EgAAIgAAIg4E4AdxC4s0JKEAABEAABEAABDwJYIPCAhaQgAAIgAAIg0H0EEAp0n01RIxAAARAAARDwIIBQwAMWkoIACIAACIBA9xFAKNB9NkWNQAAEQAAEQMCDAEIBD1hICgIgAAIgAALdRyDLzYTd+r5z1IvaNz2yBhzAgQhIb0tiTMp8vvtGZ9QIBCQCJbqZ0Pc94kgv+hXpzbDc7+I82gnaiRiD+rYH+AwQAIF2CGRfIOjW952jXqw9gQM4iCNLVdpDO6Mh8oJAzxLIskDQs7BQcRAAARAAARDoFIESLRB0CgHKBQEQAAEQAAEQyINA9gWCPLSBTBAAARAAARAAgYIJIBQoGDiKAwEQAAEQAIFyEUAoUC57QBsQAAEQAAEQKJgAQoGCgaM4EAABEAABECgXAYQC5bIHtAEBEAABEACBggkgFCgYOIoDARAAARAAgXIRQChQLntAGxAAARAAARAomABCgYKBozgQAAEQAAEQKBcBhALlsge0AQEQAAEQAIGCCSAUKBg4igMBEAABEACBchFAKFAue0AbEAABEAABECiYAEKBgoGjOBAAARAAARAoFwGEAuWyB7QBARAAARAAgYIJIBQoGDiKAwEQAAEQAIFyEUAoUC57QBsQAAEQAAEQKJgAQoGCgaM4EAABEAABECgXAYQC5bIHtAEBEAABEACBggkgFCgYOIoDARAAARAAgXIRQChQLntAGxAAARAAARAomABCgYKBozgQAAEQAAEQKBcBhALlsge0AQEQAAEQAIGCCSAUKBg4igMBEAABEACBchFAKFAue0AbEAABEAABECiYAEKBgoGjOBAAARAAARAoFwGEAuWyB7QBARAAARAAgYIJIBQoGDiKAwEQAAEQAIFyEUAoUC57QBsQAAEQAAEQKJiAdyhwn+7IrDQXllmCJaOoaR7yyymT1bqcuhWpVd4c8pbvy8pdH/eUvjogPQiAQEUJeIcCCxcuZFWlL+xIrbnJM7HzTEJw78WF5yQ/tdZqguB1dNchSNFBhLjrzFNayu2UShlq4Z4l70qVp0e4M0FKEACBXAl4hwKqNmI0YLrKV0c3MQ7onbEp71Geh2iimQIWGlCUV7PWlmtXxjFO9VJDTJyr/AycvfTpnR6X2b7ICAI9RaC+Zs2aLVu2bN68eePGjevXr1+7du31K29btWrVT58YkUDsO7N+/vnnX7/iUulqXgoFWC5ptkDMwhJIZ/if0hdRlDg+cvnSoCmd105aWOSIQ6Q0XNKfWp3V+mrla2vNOUg+Rk2snUGRVHLhk8pTUinVjqb0oeyYmZtkF1M7kZqiVu027e7V3kz1tdjF1+68sam9sqfGPlQWBCpHYOvWrUNDQwMDA4ODg319zSv5er0+NjZG//Ia0Xc6KP2SCy6/8MILHx0akyp7xF79Bx100JsPnj9jxozp06dnnxVgEwCSdNOqgftVCE/Jr3JYKXzY0oqSEnOHpyppl6O2DDWYsOuTqqfF/btQEuVLQ7n2upDrL5nGpKev/qb0oewoenStz1ObnOX6WG0nprHAZHfWtEy/qvJ925upvhY59vqKfUHtrdrWWLnxEQqDAAi0SSB7KGAZgLQ6ufi51Mpo4w/LaB6kUH6hpjoAPnCrV89qnGQa5VNrnV8CE08L5yBIvezYWW6kqsnuol1ELKau4dVlJM4u8n3bCWYFfIkhPQh0K4HsoYA4QHM6bIjPzwvyS8DU0ZmrEcR18Usrx9HcrmcoldpvlCY989bf3Y4md9t+3R0lMGO52J2lyRDlWGJZ8ao9rHzEAY4NAMlAoBcItBsKiEOVCy/uBUV36DsqBRxtXXROTZPTtTVHJPKRTqbqJibw1TPXqI61HFPU6OgdWbIMcrQRhm871LK1xHminlrjqrUWk4nq+XKTJLdTU68mh8QgAAKVIOC9bfD9py4yDVjuFeaTrnxEE6/ypWGO/ySel05K06fcQ3CVTPK159m1HeXlX5gcMbEUA7nIV/mo1deO0aaBWzqvugcVnYueWs5a4zI7mtKHsqOWm+RxLe1HtKO2nXD5Jl9rsbvYMFw4aEVJJ031dZHP9dG2DXv13fsvUoIACHSEQH7bBr1DAbqDIG8EuGQRCVd3TK+WHaulbd59EPJBAARKSCC/UCDAAkFYXvzSp80p0LBaFS+NTSar/slxYrl4haUSq2JHE+eOA4QCIAACIFAYgTLOChRWeRQEAiAAAiAAAlUh0EOzAlUxCfQEARAAARAAge4gULoFgu7AilqAAAiAAAiAQFUIIBSoiqWgJwiAAAiAAAjkQgChQC5YIRQEQAAEQAAEqkIAoUBVLAU9QQAEQAAEQCAXAggFcsEKoSAAAiAAAiBQFQIIBapiKegJAiAAAiAAArkQQCiQC1YIBQEQAAEQAIGqEEAoUBVLQU8QAAEQAAEQyIUAQoFcsEIoCIAACIAACFSFAEKBqlgKeoIACIAACIBALgQQCuSCFUJBAARAAARAoCoEEApUxVLQEwRAAARAAARyIYBQIBesEAoCIAACIAACVSGAUKAqloKeIAACIAACIJALAYQCuWCFUBAAARAAARCoCgGEAlWxFPQEARAAARAAgVwIIBTIBSuEggAIgAAIgEBVCCAUqIqloCcIgAAIgAAI5EIAoUAuWCEUBEAABEAABKpCAKFAVSwFPUEABEAABEAgFwIIBXLBCqEgAAIgAAIgUBUCCAWqYinoCQIgAAIgAAK5EEAokAtWCAUBEAABEACBqhBAKFAVS0FPEAABEAABEMiFAEKBXLBCKAiAAAiAAAhUhQBCgapYCnqCAAiAAAiAQC4EEArkghVCQQAEQAAEQKAqBBAKVMVS0BMEQAAEQAAEciGAUCAXrBAKAiAAAiAAAlUhgFCgKpaCniAAAiAAAiCQCwGEArlghVAQAAEQAAEQqAoBhAJVsRT0BAEQAAEQAIFcCCAUyAUrhIIACIAACIBAVQggFKiKpaAnCIAACIAACORCAKFALlghFARAAARAAASqQgChQFUsBT1BAARAAARAIBcCCAVywQqhIAACIAACIJArgf7+/sH4GDduHPuXHXTet1yEAr7EkB4EQAAEQAAEOk+AXP6RRx75xvg48MADFy1adO65537xi1/s6/P27N4ZOl97aAACIAACIAACPU9gZGTkJz/5CcUBRxxxxLve9a4PfehDp512Gv07OjrqywahgC8xpAcBEAABEACBzhOgUICOa6+9dtasWRQQvO51rzvkkEMoDqCTvsohFPAlhvQgAAIgAAIg0DECdeEgx0/HBRdcQIsF++67b7Y4gGoihwJjY2Mdqx8KBgEQAAEQAAEQsBIgry9FA+S43/72t9O/FAqIP7mDxKyAOyukBAEQAAEQAIEOE6BQgDYGStHA8PBw5jhAMyvQ4SqieBAAARAAARAAATMBFgeIv7M/s80HMDnyrIBUAMwBAiAAAiAAAiBQHgLSlIAYAUjf3XXGAoE7K6QEARAAARAAgQ4TUEMBNiXQjlotoUCbstrRA3lBAARAAARAAARSCWx2PlJFcadfX7NmzZYtW0jyxo0bN2zYsHbt2n+75durVq366RPyjYl/smvf9//jtp///Bep0pEABEAABEAABECg4wQOPfSQt739Hb99Vn7o0BF79R900EFHHfKGGTNmTJs2rf7II4+wUOD555+3hwK7TqpPm1gf7MPdhh03LhQAARAAARAAgXQC20frG7eMPbtZdtxiKDB9+vRmKMBmBZ566qnrbvrmL37xy58/OYpHDKRjRgoQAAEQAAEQqBSB/r7aQbv3HXrIwQsOfSPNClAo0Lw3kW5VZEelagRlQQAEQAAEQAAEshDgjyhIQgHakUjHQHxMHV+79ZYbJw+2tR0xi1LIAwIgAAIgAAIgkDOBSePq37jlRvL1LBSIDtpAyP+lOGD8+PH0VoPLL1u2x8456wLxIAACIAACIAAChRMg/05efvbs2ePiIwkIWDRAccDg4OCECRNoM+HwaP2u226auzOeOlC4iVAgCIAACIAACORGgDw7+Xfy8lOnTiWPT64/CgUoDuC7BCg6oB922223Yxcc+ulPfern37txv1n1qROwUpCbTSAYBEAABEAABAohMHV8nXw6eXby7/P23nP33XendQCaAiDXX//973+/detWup+QjpdeeumFF16guwqfeeaZJ5988u4f/nygb+zcJUtPXXx6IXqiEBAAARAAARAAgVwI3HLTDbQuQPMBFAfstddebFZgp512mjRpUv2JJ57Ytm0biwZejo9NmzZRNED3Fv7hD3+gyGDVrx/PRSkIBQEQAAEQAAEQKJDAn8ydSRHA3LlzJ0+eTEEArQ5MnDgxCgXo6p9CAYoDKBqgBw3xaIBmCCgmoD/pJCXYvn37SHzQG5HpIM3ZvzhAAARAAARAAARKS4C9o4jvCKRFAXL/dNCUAP+3/vTTT5OnZ9EAO5j7Z19YiEBxAB30OmQKBeiNyAgFSmtyKAYCIAACIAACIgEeCtC+QHbLAAUBtEWAYgL6wiKD+vr165mnZ16f7xtgf7IoYceOHdpQgGICvMEIbQ4EQAAEQAAESkuAuWmaFWC3CLC7BflB0QAd9aGhIebp2Y4B9i87WBxAP1ECmhKgg6YE+BoBWylAKFBa80MxEAABEAABEGCzAuxuQf4sQZobYBMDbG6g/txzz5Gn59EAc//8YBMGPBRgCwR0EFyEAmhhIAACIAACIFByAnxWgE0MsMcKs1CARwP/HwcHzXs6f0BCAAAAAElFTkSuQmCC) + +###4.未来计划 + +4.1支持乘、除法指令； + +4.2在真实的FPGA平台(xilinx artix-7)上跑起来； + +4.3…… diff --git a/rtl/defines.v b/rtl/defines.v new file mode 100644 index 0000000..3718549 --- /dev/null +++ b/rtl/defines.v @@ -0,0 +1,98 @@ + /* + Copyright 2019 Blue Liang, liangkangnan@163.com + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + +`define RstEnable 1'b0 +`define RstDisable 1'b1 +`define ZeroWord 32'h00000000 +`define WriteEnable 1'b1 +`define WriteDisable 1'b0 +`define ReadEnable 1'b1 +`define ReadDisable 1'b0 +`define InstValid 1'b1 +`define InstInvalid 1'b0 +`define True 1'b1 +`define False 1'b0 +`define ChipEnable 1'b1 +`define ChipDisable 1'b0 +`define JumpEnable 1'b1 +`define JumpDisable 1'b0 + +// I type inst +`define INST_TYPE_I 7'b0010011 +`define INST_ADDI 3'b000 +`define INST_SLTI 3'b010 +`define INST_SLTIU 3'b011 +`define INST_XORI 3'b100 +`define INST_ORI 3'b110 +`define INST_ANDI 3'b111 +`define INST_SLLI 3'b001 +`define INST_SRI 3'b101 + +// L type inst +`define INST_TYPE_L 7'b0000011 +`define INST_LB 3'b000 +`define INST_LH 3'b001 +`define INST_LW 3'b010 +`define INST_LBU 3'b100 +`define INST_LHU 3'b101 + +// S type inst +`define INST_TYPE_S 7'b0100011 +`define INST_SB 3'b000 +`define INST_SH 3'b001 +`define INST_SW 3'b010 + +// R type inst +`define INST_TYPE_R 7'b0110011 +`define INST_ADD_SUB 3'b000 +`define INST_SLL 3'b001 +`define INST_SLT 3'b010 +`define INST_SLTU 3'b011 +`define INST_XOR 3'b100 +`define INST_SR 3'b101 +`define INST_OR 3'b110 +`define INST_AND 3'b111 + +// J type inst +`define INST_JAL 7'b1101111 +`define INST_JALR 7'b1100111 + +`define INST_LUI 7'b0110111 +`define INST_AUIPC 7'b0010111 +`define INST_NOP 32'h00000001 + +`define INST_FENCE 7'b0001111 + +// J type inst +`define INST_TYPE_B 7'b1100011 +`define INST_BEQ 3'b000 +`define INST_BNE 3'b001 +`define INST_BLT 3'b100 +`define INST_BGE 3'b101 +`define INST_BLTU 3'b110 +`define INST_BGEU 3'b111 + +// SIM RAM +`define SramMemNum 2048 // memory depth(how many words) +`define SramBus 31:0 +`define SramAddrBus 31:0 + +// common regs +`define RegAddrBus 4:0 +`define RegBus 31:0 +`define RegWidth 32 +`define RegNum 32 // reg count +`define RegNumLog2 5 diff --git a/rtl/ex.v b/rtl/ex.v new file mode 100644 index 0000000..cc7e333 --- /dev/null +++ b/rtl/ex.v @@ -0,0 +1,478 @@ + /* + Copyright 2019 Blue Liang, liangkangnan@163.com + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + +`include "defines.v" + +// excute and writeback module +module ex ( + + input wire clk, + input wire rst, + + // from id + input wire[`SramBus] inst_i, // inst content + input wire inst_valid_i, + input wire[`SramAddrBus] inst_addr_i, // inst addr + + // from regs + input wire[`RegBus] reg1_rdata_i, // reg1 read data + input wire[`RegBus] reg2_rdata_i, // reg2 read data + + // from sram + input wire[`SramBus] sram_rdata_i, // ram read data + + // to sram + output reg[`SramBus] sram_wdata_o, // ram write data + output reg[`SramAddrBus] sram_raddr_o, // ram read addr + output reg[`SramAddrBus] sram_waddr_o, // ram write addr + + // to regs + output reg[`RegBus] reg_wdata_o, // reg write data + + // to pc_reg + output reg jump_flag_o, // if jump or not flag + output reg[`RegBus] jump_addr_o // jump dest addr + +); + + wire[31:0] sign_extend_tmp; + wire[4:0] shift_bits; + reg[1:0] sram_raddr_index; + reg[1:0] sram_waddr_index; + + wire[6:0] opcode = inst_i[6:0]; + wire[2:0] funct3 = inst_i[14:12]; + + assign sign_extend_tmp = {{20{inst_i[31]}}, inst_i[31:20]}; + assign shift_bits = inst_i[24:20]; + + always @ (posedge clk) begin + if (rst == `RstEnable) begin + sram_raddr_o <= `ZeroWord; + jump_flag_o <= `JumpDisable; + sram_raddr_index <= 2'b0; + sram_waddr_index <= 2'b0; + end + end + + always @ (*) begin + if (inst_valid_i == `InstValid) begin + case (opcode) + `INST_TYPE_I: begin + case (funct3) + `INST_ADDI: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + end + `INST_SLTI: begin + jump_flag_o <= `JumpDisable; + if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin + if (reg1_rdata_i < sign_extend_tmp) begin + reg_wdata_o <= 32'h00000001; + end else begin + reg_wdata_o <= 32'h00000000; + end + end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin + reg_wdata_o <= 32'h00000001; + end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin + reg_wdata_o <= 32'h00000000; + end else begin + if (reg1_rdata_i < sign_extend_tmp) begin + reg_wdata_o <= 32'h00000001; + end else begin + reg_wdata_o <= 32'h00000000; + end + end + end + `INST_SLTIU: begin + jump_flag_o <= `JumpDisable; + if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b1) begin + if (reg1_rdata_i < sign_extend_tmp) begin + reg_wdata_o <= 32'h00000001; + end else begin + reg_wdata_o <= 32'h00000000; + end + end else if (reg1_rdata_i[31] == 1'b1 && sign_extend_tmp[31] == 1'b0) begin + reg_wdata_o <= 32'h00000000; + end else if (reg1_rdata_i[31] == 1'b0 && sign_extend_tmp[31] == 1'b1) begin + reg_wdata_o <= 32'h00000001; + end else begin + if (reg1_rdata_i < sign_extend_tmp) begin + reg_wdata_o <= 32'h00000001; + end else begin + reg_wdata_o <= 32'h00000000; + end + end + end + `INST_XORI: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= reg1_rdata_i ^ {{20{inst_i[31]}}, inst_i[31:20]}; + end + `INST_ORI: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= reg1_rdata_i | {{20{inst_i[31]}}, inst_i[31:20]}; + end + `INST_ANDI: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= reg1_rdata_i & {{20{inst_i[31]}}, inst_i[31:20]}; + end + `INST_SLLI: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= reg1_rdata_i << shift_bits; + end + `INST_SRI: begin + jump_flag_o <= `JumpDisable; + if (inst_i[30] == 1'b1) begin + reg_wdata_o <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, shift_bits})) | (reg1_rdata_i >> shift_bits); + end else begin + reg_wdata_o <= reg1_rdata_i >> shift_bits; + end + end + endcase + end + `INST_TYPE_R: begin + case (funct3) + `INST_ADD_SUB: begin + jump_flag_o <= `JumpDisable; + if (inst_i[30] == 1'b0) begin + reg_wdata_o <= reg1_rdata_i + reg2_rdata_i; + end else begin + reg_wdata_o <= reg1_rdata_i - reg2_rdata_i; + end + end + `INST_SLL: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= reg1_rdata_i << reg2_rdata_i[4:0]; + end + `INST_SLT: begin + jump_flag_o <= `JumpDisable; + if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin + if (reg1_rdata_i < reg2_rdata_i) begin + reg_wdata_o <= 32'h00000001; + end else begin + reg_wdata_o <= 32'h00000000; + end + end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin + reg_wdata_o <= 32'h00000001; + end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin + reg_wdata_o <= 32'h00000000; + end else begin + if (reg1_rdata_i < reg2_rdata_i) begin + reg_wdata_o <= 32'h00000001; + end else begin + reg_wdata_o <= 32'h00000000; + end + end + end + `INST_SLTU: begin + jump_flag_o <= `JumpDisable; + if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin + if (reg1_rdata_i < reg2_rdata_i) begin + reg_wdata_o <= 32'h00000001; + end else begin + reg_wdata_o <= 32'h00000000; + end + end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin + reg_wdata_o <= 32'h00000000; + end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin + reg_wdata_o <= 32'h00000001; + end else begin + if (reg1_rdata_i < reg2_rdata_i) begin + reg_wdata_o <= 32'h00000001; + end else begin + reg_wdata_o <= 32'h00000000; + end + end + end + `INST_XOR: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= reg1_rdata_i ^ reg2_rdata_i; + end + `INST_SR: begin + jump_flag_o <= `JumpDisable; + if (inst_i[30] == 1'b1) begin + reg_wdata_o <= ({32{reg1_rdata_i[31]}} << (6'd32 - {1'b0, reg2_rdata_i[4:0]})) | (reg1_rdata_i >> reg2_rdata_i[4:0]); + end else begin + reg_wdata_o <= reg1_rdata_i >> reg2_rdata_i[4:0]; + end + end + `INST_OR: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= reg1_rdata_i | reg2_rdata_i; + end + `INST_AND: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= reg1_rdata_i & reg2_rdata_i; + end + endcase + end + `INST_TYPE_L: begin + case (funct3) + `INST_LB: begin + jump_flag_o <= `JumpDisable; + sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11; + end + `INST_LH: begin + jump_flag_o <= `JumpDisable; + sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11; + end + `INST_LW: begin + jump_flag_o <= `JumpDisable; + sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11; + end + `INST_LBU: begin + jump_flag_o <= `JumpDisable; + sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11; + end + `INST_LHU: begin + jump_flag_o <= `JumpDisable; + sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}; + sram_raddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) - ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & 32'hfffffffc)) & 2'b11; + end + endcase + end + `INST_TYPE_S: begin + case (funct3) + `INST_SB: begin + jump_flag_o <= `JumpDisable; + sram_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + sram_waddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11; + end + `INST_SH: begin + jump_flag_o <= `JumpDisable; + sram_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + sram_raddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + sram_waddr_index <= ((reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}) - (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]} & 32'hfffffffc)) & 2'b11; + end + `INST_SW: begin + jump_flag_o <= `JumpDisable; + sram_waddr_o <= reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:25], inst_i[11:7]}; + sram_wdata_o <= reg2_rdata_i; + end + endcase + end + `INST_TYPE_B: begin + case (funct3) + `INST_BEQ: begin + if (reg1_rdata_i == reg2_rdata_i) begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end else begin + jump_flag_o <= `JumpDisable; + end + end + `INST_BNE: begin + if (reg1_rdata_i != reg2_rdata_i) begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end else begin + jump_flag_o <= `JumpDisable; + end + end + `INST_BLT: begin + if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin + if (reg1_rdata_i >= reg2_rdata_i) begin + jump_flag_o <= `JumpDisable; + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin + if (reg1_rdata_i >= reg2_rdata_i) begin + jump_flag_o <= `JumpDisable; + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end else begin + jump_flag_o <= `JumpDisable; + end + end + `INST_BGE: begin + if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin + if (reg1_rdata_i < reg2_rdata_i) begin + jump_flag_o <= `JumpDisable; + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin + if (reg1_rdata_i < reg2_rdata_i) begin + jump_flag_o <= `JumpDisable; + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end else begin + jump_flag_o <= `JumpDisable; + end + end + `INST_BLTU: begin + if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b0) begin + jump_flag_o <= `JumpDisable; + end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin + if (reg1_rdata_i >= reg2_rdata_i) begin + jump_flag_o <= `JumpDisable; + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin + if (reg1_rdata_i >= reg2_rdata_i) begin + jump_flag_o <= `JumpDisable; + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end + `INST_BGEU: begin + if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b1) begin + jump_flag_o <= `JumpDisable; + end else if (reg1_rdata_i[31] == 1'b1 && reg2_rdata_i[31] == 1'b1) begin + if (reg1_rdata_i < reg2_rdata_i) begin + jump_flag_o <= `JumpDisable; + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end else if (reg1_rdata_i[31] == 1'b0 && reg2_rdata_i[31] == 1'b0) begin + if (reg1_rdata_i < reg2_rdata_i) begin + jump_flag_o <= `JumpDisable; + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end else begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{20{inst_i[31]}}, inst_i[7], inst_i[30:25], inst_i[11:8], 1'b0}; + end + end + endcase + end + `INST_JAL: begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + {{12{inst_i[31]}}, inst_i[19:12], inst_i[20], inst_i[30:21], 1'b0}; + reg_wdata_o <= inst_addr_i + 4'h4; + end + `INST_JALR: begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= (reg1_rdata_i + {{20{inst_i[31]}}, inst_i[31:20]}) & (32'hfffffffe); + reg_wdata_o <= inst_addr_i + 4'h4; + end + `INST_LUI: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= {inst_i[31:12], 12'b0}; + end + `INST_AUIPC: begin + jump_flag_o <= `JumpDisable; + reg_wdata_o <= {inst_i[31:12], 12'b0} + inst_addr_i; + end + `INST_NOP: begin + jump_flag_o <= `JumpDisable; + end + `INST_FENCE: begin + jump_flag_o <= `JumpEnable; + jump_addr_o <= inst_addr_i + 4'h4; + end + default: begin + + end + endcase + end + end + + always @ (*) begin + if (inst_valid_i == `InstValid) begin + case (opcode) + `INST_TYPE_L: begin + case (funct3) + `INST_LB: begin + if (sram_raddr_index == 2'b0) + reg_wdata_o <= {{24{sram_rdata_i[7]}}, sram_rdata_i[7:0]}; + else if (sram_raddr_index == 2'b01) + reg_wdata_o <= {{24{sram_rdata_i[15]}}, sram_rdata_i[15:8]}; + else if (sram_raddr_index == 2'b10) + reg_wdata_o <= {{24{sram_rdata_i[23]}}, sram_rdata_i[23:16]}; + else + reg_wdata_o <= {{24{sram_rdata_i[31]}}, sram_rdata_i[31:24]}; + end + `INST_LH: begin + if (sram_raddr_index == 2'b0) + reg_wdata_o <= {{16{sram_rdata_i[15]}}, sram_rdata_i[15:0]}; + else + reg_wdata_o <= {{16{sram_rdata_i[31]}}, sram_rdata_i[31:16]}; + end + `INST_LW: begin + reg_wdata_o <= sram_rdata_i; + end + `INST_LBU: begin + if (sram_raddr_index == 2'b0) + reg_wdata_o <= {24'h0, sram_rdata_i[7:0]}; + else if (sram_raddr_index == 2'b01) + reg_wdata_o <= {24'h0, sram_rdata_i[15:8]}; + else if (sram_raddr_index == 2'b10) + reg_wdata_o <= {24'h0, sram_rdata_i[23:16]}; + else + reg_wdata_o <= {24'h0, sram_rdata_i[31:24]}; + end + `INST_LHU: begin + if (sram_raddr_index == 2'b0) + reg_wdata_o <= {16'h0, sram_rdata_i[15:0]}; + else + reg_wdata_o <= {16'h0, sram_rdata_i[31:16]}; + end + endcase + end + `INST_TYPE_S: begin + case (funct3) + `INST_SB: begin + if (sram_waddr_index == 2'b00) + sram_wdata_o <= {sram_rdata_i[31:8], reg2_rdata_i[7:0]}; + else if (sram_waddr_index == 2'b01) + sram_wdata_o <= {sram_rdata_i[31:16], reg2_rdata_i[7:0], sram_rdata_i[7:0]}; + else if (sram_waddr_index == 2'b10) + sram_wdata_o <= {sram_rdata_i[31:24], reg2_rdata_i[7:0], sram_rdata_i[15:0]}; + else + sram_wdata_o <= {reg2_rdata_i[7:0], sram_rdata_i[23:0]}; + end + `INST_SH: begin + if (sram_waddr_index == 2'b00) + sram_wdata_o <= {sram_rdata_i[31:16], reg2_rdata_i[15:0]}; + else + sram_wdata_o <= {reg2_rdata_i[15:0], sram_rdata_i[15:0]}; + end + endcase + end + endcase + end + end + +endmodule diff --git a/rtl/id.v b/rtl/id.v new file mode 100644 index 0000000..f546638 --- /dev/null +++ b/rtl/id.v @@ -0,0 +1,425 @@ + /* + Copyright 2019 Blue Liang, liangkangnan@163.com + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + +`include "defines.v" + +// identify module +module id ( + + input wire clk, + input wire rst, + input wire[`SramBus] inst_i, // inst content + input wire[`SramAddrBus] inst_addr_i, // inst addr + input wire jump_flag_ex_i, + + // to regs + output reg reg1_re_o, // reg1 read enable + output reg[`RegAddrBus] reg1_raddr_o, // reg1 read addr + output reg reg2_re_o, // reg2 read enable + output reg[`RegAddrBus] reg2_raddr_o, // reg2 read addr + output reg reg_we_o, // reg write enable + output reg[`RegAddrBus] reg_waddr_o, // reg write addr + + // to ex + output reg[`SramBus] inst_o, + output reg inst_valid_o, // inst is valid flag + output reg[`SramAddrBus] inst_addr_o, + + // to sram + output reg sram_re_o, // ram read enable + output reg sram_we_o // ram write enable + +); + + wire[6:0] opcode = inst_i[6:0]; + wire[2:0] funct3 = inst_i[14:12]; + wire[4:0] rd = inst_i[11:7]; + wire[4:0] rs1 = inst_i[19:15]; + wire[4:0] rs2 = inst_i[24:20]; + + + always @ (posedge clk) begin + if (rst == `RstEnable) begin + inst_o <= `ZeroWord; + reg_we_o <= `WriteDisable; + sram_we_o <= `WriteDisable; + reg1_re_o <= `ReadDisable; + reg2_re_o <= `ReadDisable; + sram_re_o <= `ReadDisable; + inst_valid_o <= `InstInvalid; + end else if (jump_flag_ex_i == `JumpEnable && inst_i != `INST_NOP) begin + inst_valid_o <= `InstValid; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + inst_o <= `INST_NOP; + end else begin + inst_o <= inst_i; + inst_addr_o <= inst_addr_i; + + case (opcode) + `INST_TYPE_I: begin + case (funct3) + `INST_ADDI: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + sram_we_o <= `WriteDisable; + end + `INST_SLTI: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + sram_we_o <= `WriteDisable; + end + `INST_SLTIU: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + sram_we_o <= `WriteDisable; + end + `INST_XORI: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + sram_we_o <= `WriteDisable; + end + `INST_ORI: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + sram_we_o <= `WriteDisable; + end + `INST_ANDI: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + sram_we_o <= `WriteDisable; + end + `INST_SLLI: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + sram_we_o <= `WriteDisable; + end + `INST_SRI: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + sram_we_o <= `WriteDisable; + end + default: begin + inst_valid_o <= `InstInvalid; + end + endcase + end + `INST_TYPE_R: begin + case (funct3) + `INST_ADD_SUB: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_SLL: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_SLT: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_SLTU: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_XOR: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_SR: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_OR: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + `INST_AND: begin + inst_valid_o <= `InstValid; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + end + default: begin + inst_valid_o <= `InstInvalid; + end + endcase + end + `INST_TYPE_L: begin + case (funct3) + `INST_LB: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + sram_re_o <= `ReadEnable; + sram_we_o <= `WriteDisable; + end + `INST_LH: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + sram_re_o <= `ReadEnable; + sram_we_o <= `WriteDisable; + end + `INST_LW: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + sram_re_o <= `ReadEnable; + sram_we_o <= `WriteDisable; + end + `INST_LBU: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + sram_re_o <= `ReadEnable; + sram_we_o <= `WriteDisable; + end + `INST_LHU: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + sram_re_o <= `ReadEnable; + sram_we_o <= `WriteDisable; + end + default: begin + inst_valid_o <= `InstInvalid; + end + endcase + end + `INST_TYPE_S: begin + case (funct3) + `INST_SB: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteEnable; + sram_re_o <= `ReadEnable; + reg_we_o <= `WriteDisable; + end + `INST_SH: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteEnable; + sram_re_o <= `ReadEnable; + reg_we_o <= `WriteDisable; + end + `INST_SW: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_re_o <= `ReadEnable; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteEnable; + reg_we_o <= `WriteDisable; + end + default: begin + inst_valid_o <= `InstInvalid; + end + endcase + end + `INST_TYPE_B: begin + case (funct3) + `INST_BEQ: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg2_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + end + `INST_BNE: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg2_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + end + `INST_BLT: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg2_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + end + `INST_BGE: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg2_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + end + `INST_BLTU: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg2_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + end + `INST_BGEU: begin + inst_valid_o <= `InstValid; + reg1_re_o <= `ReadEnable; + reg2_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg2_raddr_o <= rs2; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + end + default: begin + inst_valid_o <= `InstInvalid; + end + endcase + end + `INST_JAL: begin + inst_valid_o <= `InstValid; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + end + `INST_JALR: begin + inst_valid_o <= `InstValid; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteEnable; + reg1_re_o <= `ReadEnable; + reg1_raddr_o <= rs1; + reg_waddr_o <= rd; + end + `INST_LUI: begin + inst_valid_o <= `InstValid; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + end + `INST_AUIPC: begin + inst_valid_o <= `InstValid; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteEnable; + reg_waddr_o <= rd; + end + `INST_NOP: begin + inst_valid_o <= `InstValid; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + end + `INST_FENCE: begin + inst_valid_o <= `InstValid; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + end + default: begin + inst_valid_o <= `InstInvalid; + sram_we_o <= `WriteDisable; + reg_we_o <= `WriteDisable; + end + endcase + end + end + +endmodule diff --git a/rtl/if_id.v b/rtl/if_id.v new file mode 100644 index 0000000..2d24d72 --- /dev/null +++ b/rtl/if_id.v @@ -0,0 +1,48 @@ + /* + Copyright 2019 Blue Liang, liangkangnan@163.com + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + +`include "defines.v" + +// inst fetch module +module if_id ( + + input wire clk, + input wire rst, + + input wire[`SramBus] inst_i, // inst content + input wire[`SramAddrBus] inst_addr_i, // inst addr + + input wire jump_flag_ex_i, + + output reg[`SramBus] inst_o, + output reg[`SramAddrBus] inst_addr_o + +); + + always @ (posedge clk) begin + if (rst == `RstEnable) begin + inst_o <= `ZeroWord; + inst_addr_o <= `ZeroWord; + end else if (jump_flag_ex_i == `JumpEnable) begin + inst_o <= `INST_NOP; + inst_addr_o <= `ZeroWord; + end else begin + inst_o <= inst_i; + inst_addr_o <= inst_addr_i; + end + end + +endmodule diff --git a/rtl/openriscv_core.v b/rtl/openriscv_core.v new file mode 100644 index 0000000..418f04f --- /dev/null +++ b/rtl/openriscv_core.v @@ -0,0 +1,148 @@ + /* + Copyright 2019 Blue Liang, liangkangnan@163.com + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + +`include "defines.v" + +// CPU core module +module openriscv_core ( + + input wire clk, + input wire rst + +); + + // pc_reg + wire[`SramAddrBus] pc_pc_o; + wire pc_re_o; + + // if_id + wire[`SramBus] if_inst_o; + wire[`SramAddrBus] if_inst_addr_o; + + // id + wire id_reg1_re_o; + wire[`RegAddrBus] id_reg1_raddr_o; + wire id_reg2_re_o; + wire[`RegAddrBus] id_reg2_raddr_o; + wire[`SramBus] id_inst_o; + wire id_inst_valid_o; + wire id_reg_we_o; + wire[`RegAddrBus] id_reg_waddr_o; + wire id_sram_re_o; + wire id_sram_we_o; + wire[`SramAddrBus] id_pc_o; + wire[`SramAddrBus] id_inst_addr_o; + + // ex + wire[`RegBus] ex_reg_wdata_o; + wire[`SramBus] ex_sram_wdata_o; + wire[`SramAddrBus] ex_sram_raddr_o; + wire[`SramAddrBus] ex_sram_waddr_o; + wire ex_jump_flag_o; + wire[`RegBus] ex_jump_addr_o; + + // regs + wire[`RegBus] regs_rdata1_o; + wire[`RegBus] regs_rdata2_o; + + // sim_ram + wire[`SramBus] ram_pc_rdata_o; + wire[`SramBus] ram_ex_rdata_o; + + sim_ram u_sim_ram( + .clk(clk), + .rst(rst), + .we_i(id_sram_we_o), + .waddr_i(ex_sram_waddr_o), + .wdata_i(ex_sram_wdata_o), + .pc_re_i(pc_re_o), + .pc_raddr_i(pc_pc_o), + .pc_rdata_o(ram_pc_rdata_o), + .ex_re_i(id_sram_re_o), + .ex_raddr_i(ex_sram_raddr_o), + .ex_rdata_o(ram_ex_rdata_o) + ); + + pc_reg u_pc_reg( + .clk(clk), + .rst(rst), + .pc_o(pc_pc_o), + .re_o(pc_re_o), + .jump_flag_ex_i(ex_jump_flag_o), + .jump_addr_ex_i(ex_jump_addr_o) + ); + + regs u_regs( + .clk(clk), + .rst(rst), + .we(id_reg_we_o), + .waddr(id_reg_waddr_o), + .wdata(ex_reg_wdata_o), + .re1(id_reg1_re_o), + .raddr1(id_reg1_raddr_o), + .rdata1(regs_rdata1_o), + .re2(id_reg2_re_o), + .raddr2(id_reg2_raddr_o), + .rdata2(regs_rdata2_o) + ); + + if_id u_if_id( + .clk(clk), + .rst(rst), + .inst_i(ram_pc_rdata_o), + .inst_addr_i(pc_pc_o), + .inst_o(if_inst_o), + .inst_addr_o(if_inst_addr_o), + .jump_flag_ex_i(ex_jump_flag_o) + ); + + id u_id( + .clk(clk), + .rst(rst), + .inst_i(if_inst_o), + .inst_addr_o(id_inst_addr_o), + .inst_addr_i(if_inst_addr_o), + .jump_flag_ex_i(ex_jump_flag_o), + .reg1_re_o(id_reg1_re_o), + .reg1_raddr_o(id_reg1_raddr_o), + .reg2_re_o(id_reg2_re_o), + .reg2_raddr_o(id_reg2_raddr_o), + .inst_o(id_inst_o), + .inst_valid_o(id_inst_valid_o), + .reg_we_o(id_reg_we_o), + .reg_waddr_o(id_reg_waddr_o), + .sram_re_o(id_sram_re_o), + .sram_we_o(id_sram_we_o) + ); + + ex u_ex( + .clk(clk), + .rst(rst), + .inst_i(id_inst_o), + .inst_addr_i(id_inst_addr_o), + .inst_valid_i(id_inst_valid_o), + .reg1_rdata_i(regs_rdata1_o), + .reg2_rdata_i(regs_rdata2_o), + .reg_wdata_o(ex_reg_wdata_o), + .sram_rdata_i(ram_ex_rdata_o), + .sram_wdata_o(ex_sram_wdata_o), + .sram_raddr_o(ex_sram_raddr_o), + .sram_waddr_o(ex_sram_waddr_o), + .jump_flag_o(ex_jump_flag_o), + .jump_addr_o(ex_jump_addr_o) + ); + +endmodule diff --git a/rtl/pc_reg.v b/rtl/pc_reg.v new file mode 100644 index 0000000..5bc0c29 --- /dev/null +++ b/rtl/pc_reg.v @@ -0,0 +1,56 @@ + /* + Copyright 2019 Blue Liang, liangkangnan@163.com + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + +`include "defines.v" + +// pc reg module +module pc_reg ( + + input wire clk, + input wire rst, + + input wire jump_flag_ex_i, + input wire[`RegBus] jump_addr_ex_i, + + output reg[`SramAddrBus] pc_o, + output reg re_o + +); + + reg[`SramAddrBus] offset; + + always @ (posedge clk) begin + if (rst == `RstEnable) begin + pc_o <= `ZeroWord; + offset <= `ZeroWord; + end else if (jump_flag_ex_i == `JumpEnable) begin + pc_o <= jump_addr_ex_i; + offset <= jump_addr_ex_i + 4'h4; + end else begin + pc_o <= offset; + offset <= offset + 4'h4; + end + end + + always @ (posedge clk) begin + if (rst == `RstEnable) begin + re_o <= `ReadDisable; + end else begin + re_o <= `ReadEnable; + end + end + +endmodule diff --git a/rtl/regs.v b/rtl/regs.v new file mode 100644 index 0000000..a10bb1c --- /dev/null +++ b/rtl/regs.v @@ -0,0 +1,73 @@ + /* + Copyright 2019 Blue Liang, liangkangnan@163.com + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + +`include "defines.v" + +// common reg module +module regs ( + + input wire clk, + input wire rst, + + input wire we, // reg write enable + input wire[`RegAddrBus] waddr, // reg write addr + input wire[`RegBus] wdata, // reg write data + + input wire re1, // reg1 read enable + input wire[`RegAddrBus] raddr1, // reg1 read addr + output reg[`RegBus] rdata1, // reg1 read data + + input wire re2, // reg2 read enable + input wire[`RegAddrBus] raddr2, // reg2 read addr + output reg[`RegBus] rdata2 // reg2 read data + +); + + reg[`RegBus] regs[0:`RegNum - 1]; + + always @ (posedge clk) begin + if (rst == `RstDisable) begin + if((we == `WriteEnable) && (waddr != `RegNumLog2'h0)) begin + regs[waddr] <= wdata; + end + end + end + + always @ (*) begin + if(rst == `RstEnable) begin + rdata1 <= `ZeroWord; + end else if(raddr1 == `RegNumLog2'h0) begin + rdata1 <= `ZeroWord; + end else if(re1 == `ReadEnable) begin + rdata1 <= regs[raddr1]; + end else begin + rdata1 <= `ZeroWord; + end + end + + always @ (*) begin + if(rst == `RstEnable) begin + rdata2 <= `ZeroWord; + end else if(raddr2 == `RegNumLog2'h0) begin + rdata2 <= `ZeroWord; + end else if(re2 == `ReadEnable) begin + rdata2 <= regs[raddr2]; + end else begin + rdata2 <= `ZeroWord; + end + end + +endmodule diff --git a/rtl/sim_ram.v b/rtl/sim_ram.v new file mode 100644 index 0000000..1d4775b --- /dev/null +++ b/rtl/sim_ram.v @@ -0,0 +1,71 @@ + /* + Copyright 2019 Blue Liang, liangkangnan@163.com + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + */ + +`include "defines.v" + +// simulation ram module +module sim_ram ( + + input wire clk, + input wire rst, + + input wire we_i, // write enable + input wire[`SramAddrBus] waddr_i, // write addr + input wire[`SramBus] wdata_i, // write data + + input wire pc_re_i, // pc read enable + input wire[`SramAddrBus] pc_raddr_i, // pc read addr + output reg[`SramBus] pc_rdata_o, // pc read data + + input wire ex_re_i, // ex read enable + input wire[`SramAddrBus] ex_raddr_i, // ex read addr + output reg[`SramBus] ex_rdata_o // ex read data + +); + + reg[`SramBus] ram[0:`SramMemNum - 1]; + + always @ (posedge clk) begin + if (rst == `RstDisable) begin + if(we_i == `WriteEnable) begin + ram[waddr_i[13:2]] <= wdata_i; + end + end + end + + always @ (*) begin + if(rst == `RstEnable) begin + pc_rdata_o <= `ZeroWord; + end else if((pc_raddr_i == waddr_i) && (pc_re_i == `ReadEnable)) begin + pc_rdata_o <= wdata_i; + end else if(pc_re_i == `ReadEnable) begin + pc_rdata_o <= ram[pc_raddr_i >> 2]; + end else begin + pc_rdata_o <= `ZeroWord; + end + end + + always @ (*) begin + if(rst == `RstEnable) begin + ex_rdata_o <= `ZeroWord; + end else if(ex_re_i == `ReadEnable) begin + ex_rdata_o <= ram[ex_raddr_i[13:2]]; + end else begin + ex_rdata_o <= `ZeroWord; + end + end + +endmodule diff --git a/sim/inst.data b/sim/inst.data new file mode 100644 index 0000000..bf20995 --- /dev/null +++ b/sim/inst.data @@ -0,0 +1,354 @@ +00000d13 +00000d93 +00000093 +00000113 +00208f33 +00000e93 +00200193 +4ddf1663 +00100093 +00100113 +00208f33 +00200e93 +00300193 +4bdf1a63 +00300093 +00700113 +00208f33 +00a00e93 +00400193 +49df1e63 +00000093 +ffff8137 +00208f33 +ffff8eb7 +00500193 +49df1263 +800000b7 +00000113 +00208f33 +80000eb7 +00600193 +47df1663 +800000b7 +ffff8137 +00208f33 +7fff8eb7 +00700193 +45df1a63 +00000093 +00008137 +fff10113 +00208f33 +00008eb7 +fffe8e93 +00800193 +43df1a63 +800000b7 +fff08093 +00000113 +00208f33 +80000eb7 +fffe8e93 +00900193 +41df1a63 +800000b7 +fff08093 +00008137 +fff10113 +00208f33 +80008eb7 +ffee8e93 +00a00193 +3fdf1863 +800000b7 +00008137 +fff10113 +00208f33 +80008eb7 +fffe8e93 +00b00193 +3ddf1863 +800000b7 +fff08093 +ffff8137 +00208f33 +7fff8eb7 +fffe8e93 +00c00193 +3bdf1863 +00000093 +fff00113 +00208f33 +fff00e93 +00d00193 +39df1c63 +fff00093 +00100113 +00208f33 +00000e93 +00e00193 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+01a00e93 +02200193 +05df1c63 +00f00093 +00100133 +00f00e93 +02300193 +05d11263 +02000093 +00008133 +02000e93 +02400193 +03d11863 +000000b3 +00000e93 +02500193 +03d09063 +01000093 +01e00113 +00208033 +00000e93 +02600193 +01d01463 +00301863 +00100d13 +00000d93 +0000006f +00100d13 +00100d93 +0000006f +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 diff --git a/sim/openriscv_core_tb.v b/sim/openriscv_core_tb.v new file mode 100644 index 0000000..52a94c8 --- /dev/null +++ b/sim/openriscv_core_tb.v @@ -0,0 +1,77 @@ +`timescale 1 ns / 1 ps + +`include "defines.v" + +// top module +module openriscv_core_tb; + + reg clk; + reg rst; + + always #10 clk = ~clk; // 50MHz + + wire[`RegBus] x3 = u_openriscv_core.u_regs.regs[3]; + wire[`RegBus] x26 = u_openriscv_core.u_regs.regs[26]; + wire[`RegBus] x27 = u_openriscv_core.u_regs.regs[27]; + + integer r; + initial begin + clk = 0; + rst = `RstEnable; + $display("test running..."); + #40 + rst = `RstDisable; + #100 + wait(x26 == 32'b1) // wait sim end, when x26 == 1 + #100 + if (x27 == 32'b1) begin + $display("~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~"); + $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); + $display("~~~~~~~~~ ##### ## #### #### ~~~~~~~~~"); + $display("~~~~~~~~~ # # # # # # ~~~~~~~~~"); + $display("~~~~~~~~~ # # # # #### #### ~~~~~~~~~"); + $display("~~~~~~~~~ ##### ###### # #~~~~~~~~~"); + $display("~~~~~~~~~ # # # # # # #~~~~~~~~~"); + $display("~~~~~~~~~ # # # #### #### ~~~~~~~~~"); + $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); + end else begin + $display("~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~"); + $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); + $display("~~~~~~~~~~###### ## # # ~~~~~~~~~~"); + $display("~~~~~~~~~~# # # # # ~~~~~~~~~~"); + $display("~~~~~~~~~~##### # # # # ~~~~~~~~~~"); + $display("~~~~~~~~~~# ###### # # ~~~~~~~~~~"); + $display("~~~~~~~~~~# # # # # ~~~~~~~~~~"); + $display("~~~~~~~~~~# # # # ######~~~~~~~~~~"); + $display("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~"); + $display("fail testnum = %2d", x3); + for (r = 0; r < 32; r++) + $display("x%2d = 0x%x", r, u_openriscv_core.u_regs.regs[r]); + end + $finish; + end + + // sim timeout + initial begin + #100000 + $display("Time Out."); + $finish; + end + + // read mem data + initial begin + $readmemh ("inst.data", u_openriscv_core.u_sim_ram.ram); + end + + // generate wave file, use by gtkwave + initial begin + $dumpfile("openriscv_core_tb.vcd"); + $dumpvars(0, openriscv_core_tb); + end + + openriscv_core u_openriscv_core( + .clk(clk), + .rst(rst) + ); + +endmodule diff --git a/sim/openriscv_core_tb.vcd b/sim/openriscv_core_tb.vcd new file mode 100644 index 0000000..48c75b2 --- /dev/null +++ b/sim/openriscv_core_tb.vcd @@ -0,0 +1,19055 @@ +$date + Tue Dec 03 18:22:42 2019 +$end +$version + Icarus Verilog +$end +$timescale + 1ps +$end +$scope module openriscv_core_tb $end +$var wire 32 ! x26 [31:0] $end +$var wire 32 " x27 [31:0] $end +$var wire 32 # x3 [31:0] $end +$var reg 1 $ clk $end +$var reg 1 % rst $end +$var integer 32 & r [31:0] $end +$scope module u_openriscv_core $end +$var wire 1 $ clk $end +$var wire 1 % rst $end +$var wire 32 ' regs_rdata2_o [31:0] $end +$var wire 32 ( regs_rdata1_o [31:0] $end +$var wire 32 ) ram_pc_rdata_o [31:0] $end +$var wire 32 * ram_ex_rdata_o [31:0] $end +$var wire 1 + pc_re_o $end +$var wire 32 , pc_pc_o [31:0] $end +$var wire 32 - if_inst_o [31:0] $end +$var wire 32 . if_inst_addr_o [31:0] $end +$var wire 1 / id_sram_we_o $end +$var wire 1 0 id_sram_re_o $end +$var wire 1 1 id_reg_we_o $end +$var wire 5 2 id_reg_waddr_o [4:0] $end +$var wire 1 3 id_reg2_re_o $end +$var wire 5 4 id_reg2_raddr_o [4:0] $end +$var wire 1 5 id_reg1_re_o $end +$var wire 5 6 id_reg1_raddr_o [4:0] $end +$var wire 1 7 id_inst_valid_o $end +$var wire 32 8 id_inst_o [31:0] $end +$var wire 32 9 id_inst_addr_o [31:0] $end +$var wire 32 : ex_sram_wdata_o [31:0] $end +$var wire 32 ; ex_sram_waddr_o [31:0] $end +$var wire 32 < ex_sram_raddr_o [31:0] $end +$var wire 32 = ex_reg_wdata_o [31:0] $end +$var wire 1 > ex_jump_flag_o $end +$var wire 32 ? ex_jump_addr_o [31:0] $end +$scope module u_ex $end +$var wire 1 $ clk $end +$var wire 1 % rst $end +$var wire 32 @ sram_rdata_i [31:0] $end +$var wire 32 A sign_extend_tmp [31:0] $end +$var wire 5 B shift_bits [4:0] $end +$var wire 32 C reg2_rdata_i [31:0] $end +$var wire 32 D reg1_rdata_i [31:0] $end +$var wire 7 E opcode [6:0] $end +$var wire 1 7 inst_valid_i $end +$var wire 32 F inst_i [31:0] $end +$var wire 32 G inst_addr_i [31:0] $end +$var wire 3 H funct3 [2:0] $end +$var reg 32 I jump_addr_o [31:0] $end +$var reg 1 > jump_flag_o $end +$var reg 32 J reg_wdata_o [31:0] $end +$var reg 2 K sram_raddr_index [1:0] $end +$var reg 32 L sram_raddr_o [31:0] $end +$var reg 2 M sram_waddr_index [1:0] $end +$var reg 32 N sram_waddr_o [31:0] $end +$var reg 32 O sram_wdata_o [31:0] $end +$upscope $end +$scope module u_id $end +$var wire 1 $ clk $end +$var wire 1 > jump_flag_ex_i $end +$var wire 1 % rst $end +$var wire 5 P rs2 [4:0] $end +$var wire 5 Q rs1 [4:0] $end +$var wire 5 R rd [4:0] $end +$var wire 7 S opcode [6:0] $end +$var wire 32 T inst_i [31:0] $end +$var wire 32 U inst_addr_i [31:0] $end +$var wire 3 V funct3 [2:0] $end +$var reg 32 W inst_addr_o [31:0] $end +$var reg 32 X inst_o [31:0] $end +$var reg 1 7 inst_valid_o $end +$var reg 5 Y reg1_raddr_o [4:0] $end +$var reg 1 5 reg1_re_o $end +$var reg 5 Z reg2_raddr_o [4:0] $end +$var reg 1 3 reg2_re_o $end +$var reg 5 [ reg_waddr_o [4:0] $end +$var reg 1 1 reg_we_o $end +$var reg 1 0 sram_re_o $end +$var reg 1 / sram_we_o $end +$upscope $end +$scope module u_if_id $end +$var wire 1 $ clk $end +$var wire 1 > jump_flag_ex_i $end +$var wire 1 % rst $end +$var wire 32 \ inst_i [31:0] $end +$var wire 32 ] inst_addr_i [31:0] $end +$var reg 32 ^ inst_addr_o [31:0] $end +$var reg 32 _ inst_o [31:0] $end +$upscope $end +$scope module u_pc_reg $end +$var wire 1 $ clk $end +$var wire 32 ` jump_addr_ex_i [31:0] $end +$var wire 1 > jump_flag_ex_i $end +$var wire 1 % rst $end +$var reg 32 a offset [31:0] $end +$var reg 32 b pc_o [31:0] $end +$var reg 1 + re_o $end +$upscope $end +$scope module u_regs $end +$var wire 1 $ clk $end +$var wire 5 c raddr1 [4:0] $end +$var wire 5 d raddr2 [4:0] $end +$var wire 1 5 re1 $end +$var wire 1 3 re2 $end +$var wire 1 % rst $end +$var wire 5 e waddr [4:0] $end +$var wire 32 f wdata [31:0] $end +$var wire 1 1 we $end +$var reg 32 g rdata1 [31:0] $end +$var reg 32 h rdata2 [31:0] $end +$upscope $end +$scope module u_sim_ram $end +$var wire 1 $ clk $end +$var wire 32 i ex_raddr_i [31:0] $end +$var wire 1 0 ex_re_i $end +$var wire 32 j pc_raddr_i [31:0] $end +$var wire 1 + pc_re_i $end +$var wire 1 % rst $end +$var wire 32 k waddr_i [31:0] $end +$var wire 32 l wdata_i [31:0] $end +$var wire 1 / we_i $end +$var reg 32 m ex_rdata_o [31:0] $end +$var reg 32 n pc_rdata_o [31:0] $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b0 n +b0 m +bx l +bx k +bx j +bx i +b0 h +b0 g +bx f +bx e +bx d +bx c +bx b +bx a +bx ` +bx _ +bx ^ +bx ] +b0 \ +bx [ +bx Z +bx Y +bx X +bx W +bx V +bx U +bx T +bx S +bx R +bx Q +bx P +bx O +bx N +bx M +bx L +bx K +bx J +bx I +bx H +bx G +bx F +bx E +b0 D +b0 C +bx B +bx A +b0 @ +bx ? +x> +bx = +bx < +bx ; +bx : +bx 9 +bx 8 +x7 +bx 6 +x5 +bx 4 +x3 +bx 2 +x1 +x0 +x/ +bx . +bx - +bx , +x+ +b0 * +b0 ) +b0 ( +b0 ' +bx & +0% +0$ +bx # +bx " +bx ! +$end +#10000 +b0 P +b0 Q +b0 R +b0 V +b0 S +b0 B +b0 A +b0 H +b0 E +b0 a +b0 , +b0 ] +b0 b +b0 j +0+ +b0 . +b0 U +b0 ^ +b0 - +b0 T +b0 _ +07 +00 +03 +05 +0/ +01 +b0 8 +b0 F +b0 X +b0 M +b0 K +0> +b0 < +b0 L +b0 i +1$ +#20000 +0$ +#30000 +1$ +#40000 +0$ +1% +#50000 +b110100010011 ) +b110100010011 \ +b110100010011 n +b100 a +1+ +b0 9 +b0 G +b0 W +1$ +#60000 +0$ +#70000 +b110110010011 ) +b110110010011 \ +b110110010011 n +b11010 R +b10011 S +b110100010011 - +b110100010011 T +b110100010011 _ +b1000 a +b100 , +b100 ] +b100 b +b100 j +1$ +#80000 +0$ +#90000 +b0 = +b0 J +b0 f +b10010011 ) +b10010011 \ +b10010011 n +b11011 R +b10011 E +b1100 a +b1000 , +b1000 ] +b1000 b +b1000 j +b100 . +b100 U +b100 ^ +b110110010011 - +b110110010011 T +b110110010011 _ +b0 6 +b0 Y +b0 c +15 +b11010 2 +b11010 [ +b11010 e +11 +17 +b110100010011 8 +b110100010011 F +b110100010011 X +1$ +#100000 +0$ +#110000 +b100010011 ) +b100010011 \ +b100010011 n +b1 R +b11011 2 +b11011 [ +b11011 e +b100 9 +b100 G +b100 W +b110110010011 8 +b110110010011 F +b110110010011 X +b1000 . +b1000 U +b1000 ^ +b10010011 - +b10010011 T +b10010011 _ +b0 ! +b10000 a +b1100 , +b1100 ] +b1100 b +b1100 j +1$ +#120000 +0$ +#130000 +b1000001000111100110011 ) +b1000001000111100110011 \ +b1000001000111100110011 n +b10 R +b10100 a +b10000 , +b10000 ] +b10000 b +b10000 j +b0 " +b1100 . +b1100 U +b1100 ^ +b100010011 - +b100010011 T +b100010011 _ +b1 2 +b1 [ +b1 e +b1000 9 +b1000 G +b1000 W +b10010011 8 +b10010011 F +b10010011 X +1$ +#140000 +0$ +#150000 +b111010010011 ) +b111010010011 \ +b111010010011 n +b10 P +b1 Q +b11110 R +b110011 S +b10 2 +b10 [ +b10 e +b1100 9 +b1100 G +b1100 W +b100010011 8 +b100010011 F +b100010011 X +b10000 . +b10000 U +b10000 ^ +b1000001000111100110011 - +b1000001000111100110011 T +b1000001000111100110011 _ +b11000 a +b10100 , +b10100 ] +b10100 b +b10100 j +1$ +#160000 +0$ +#170000 +b1000000000000110010011 ) +b1000000000000110010011 \ +b1000000000000110010011 n +b0 = +b0 J +b0 f +b0 P +b0 Q +b11101 R +b10011 S +b10 B +b10 A +b110011 E +b11100 a +b11000 , +b11000 ] +b11000 b +b11000 j +b10100 . +b10100 U +b10100 ^ +b111010010011 - +b111010010011 T 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+b1110001100 ] +b1110001100 b +b1110001100 j +1$ +#6320000 +0$ +#6330000 +b1000001000111100110011 ) +b1000001000111100110011 \ +b1000001000111100110011 n +b1011 = +b1011 J +b1011 f +b1101 P +b1 R +b1011 B +b1011 A +b1110010100 a +b1110010000 , +b1110010000 ] +b1110010000 b +b1110010000 j +b1110001100 . +b1110001100 U +b1110001100 ^ +b110100000000000010010011 - +b110100000000000010010011 T +b110100000000000010010011 _ +b10 2 +b10 [ +b10 e +b1110001000 9 +b1110001000 G +b1110001000 W +b101100000000000100010011 8 +b101100000000000100010011 F +b101100000000000100010011 X +1$ +#6340000 +0$ +#6350000 +b1101 = +b1101 J +b1101 f +b100100000001000010011 ) +b100100000001000010011 \ +b100100000001000010011 n +b1101 B +b1101 A +b10 P +b1 Q +b11110 R +b110011 S +b1 2 +b1 [ +b1 e +b1110001100 9 +b1110001100 G +b1110001100 W +b110100000000000010010011 8 +b110100000000000010010011 F +b110100000000000010010011 X +b1110010000 . +b1110010000 U +b1110010000 ^ +b1000001000111100110011 - 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+b1 E +b1110001100 a +b1110001000 , +b1110001000 ] +b1110001000 b +b1110001000 j +b0 . +b0 U +b0 ^ +b1 - +b1 T +b1 _ +b1 8 +b1 F +b1 X +1$ +#6460000 +0$ +#6470000 +b110100000000000010010011 ) +b110100000000000010010011 \ +b110100000000000010010011 n +b1011 P +b10 R +b10011 S +b0 9 +b0 G +b0 W +b1110001000 . +b1110001000 U +b1110001000 ^ +b101100000000000100010011 - +b101100000000000100010011 T +b101100000000000100010011 _ +b1110010000 a +b1110001100 , +b1110001100 ] +b1110001100 b +b1110001100 j +1$ +#6480000 +0$ +#6490000 +b1011 = +b1011 J +b1011 f +b1000001000111100110011 ) +b1000001000111100110011 \ +b1000001000111100110011 n +b0 ( +b0 D +b0 g +b1101 P +b1 R +b1011 B +b1011 A +b10011 E +b1110010100 a +b1110010000 , +b1110010000 ] +b1110010000 b +b1110010000 j +b1110001100 . +b1110001100 U +b1110001100 ^ +b110100000000000010010011 - +b110100000000000010010011 T +b110100000000000010010011 _ +b0 6 +b0 Y +b0 c +b10 2 +b10 [ +b10 e +11 +b1110001000 9 +b1110001000 G +b1110001000 W +b101100000000000100010011 8 +b101100000000000100010011 F +b101100000000000100010011 X +1$ +#6500000 +0$ +#6510000 +b1101 = +b1101 J +b1101 f +b100100000001000010011 ) +b100100000001000010011 \ +b100100000001000010011 n +b1101 B +b1101 A +b10 P +b1 Q +b11110 R +b110011 S +b1 2 +b1 [ +b1 e +b1110001100 9 +b1110001100 G +b1110001100 W +b110100000000000010010011 8 +b110100000000000010010011 F +b110100000000000010010011 X +b1110010000 . +b1110010000 U +b1110010000 ^ +b1000001000111100110011 - +b1000001000111100110011 T +b1000001000111100110011 _ +b1110011000 a +b1110010100 , +b1110010100 ] +b1110010100 b +b1110010100 j +1$ +#6520000 +0$ +#6530000 +b1000000000001010010011 ) +b1000000000001010010011 \ +b1000000000001010010011 n +b1011 ' +b1011 C +b1011 h +b1101 ( +b1101 D +b1101 g +b11000 = +b11000 J +b11000 f +b1 P +b100 Q +b100 R +b10011 S +b10 B +b10 A +b110011 E +b1110011100 a +b1110011000 , +b1110011000 ] +b1110011000 b +b1110011000 j +b1110010100 . +b1110010100 U +b1110010100 ^ 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g +b10 = +b10 J +b10 f +b101 P +b100 Q +b1101 R +b1 V +b1100011 S +b10 B +b10 A +b1110100100 a +b1110100000 , +b1110100000 ] +b1110100000 b +b1110100000 j +b1110011100 . +b1110011100 U +b1110011100 ^ +b11111110010100100001011011100011 - +b11111110010100100001011011100011 T +b11111110010100100001011011100011 _ +b0 6 +b0 Y +b0 c +b101 2 +b101 [ +b101 e +b1110011000 9 +b1110011000 G +b1110011000 W +b1000000000001010010011 8 +b1000000000001010010011 F +b1000000000001010010011 X +1$ +#6580000 +0$ +#6590000 +b1110001000 ? +b1110001000 I +b1110001000 ` +0> +b10 ' +b10 C +b10 h +b10 ( +b10 D +b10 g +b11111111111111111111111111100101 = +b11111111111111111111111111100101 J +b11111111111111111111111111100101 f +b1110100000000000110010011 ) +b1110100000000000110010011 \ +b1110100000000000110010011 n +b101 B +b11111111111111111111111111100101 A +b1 H +b1100011 E +b11000 P +b0 Q +b11101 R +b0 V +b10011 S +01 +b101 4 +b101 Z +b101 d +b100 6 +b100 Y +b100 c +b1110011100 9 +b1110011100 G +b1110011100 W +b11111110010100100001011011100011 8 +b11111110010100100001011011100011 F +b11111110010100100001011011100011 X +b1110100000 . +b1110100000 U +b1110100000 ^ +b1100000000000111010010011 - +b1100000000000111010010011 T +b1100000000000111010010011 _ +b1110101000 a +b1110100100 , +b1110100100 ] +b1110100100 b +b1110100100 j +1$ +#6600000 +0$ +#6610000 +b11000 = +b11000 J +b11000 f +b10101110111110001000001100011 ) +b10101110111110001000001100011 \ +b10101110111110001000001100011 n +b0 ( +b0 D +b0 g +b11101 P +b11 R +b11000 B +b11000 A +b0 H +b10011 E +b1110101100 a +b1110101000 , +b1110101000 ] +b1110101000 b +b1110101000 j +b1110100100 . +b1110100100 U +b1110100100 ^ +b1110100000000000110010011 - +b1110100000000000110010011 T +b1110100000000000110010011 _ +b0 6 +b0 Y +b0 c +b11101 2 +b11101 [ +b11101 e +11 +b1110100000 9 +b1110100000 G +b1110100000 W +b1100000000000111010010011 8 +b1100000000000111010010011 F +b1100000000000111010010011 X +1$ +#6620000 +0$ +#6630000 +b11101 = +b11101 J +b11101 f +b1000010011 ) +b1000010011 \ +b1000010011 n +b11101 B +b11101 A +b11110 Q +b0 R +b1 V +b1100011 S +b11 2 +b11 [ +b11 e +b1110100100 9 +b1110100100 G +b1110100100 W +b1110100000000000110010011 8 +b1110100000000000110010011 F +b1110100000000000110010011 X +b1110101000 . +b1110101000 U +b1110101000 ^ +b10101110111110001000001100011 - +b10101110111110001000001100011 T +b10101110111110001000001100011 _ +b1110110000 a +b1110101100 , +b1110101100 ] +b1110101100 b +b1110101100 j +1$ +#6640000 +0$ +#6650000 +b10011101000 ? +b10011101000 I +b10011101000 ` +0> +b101100000000000100010011 ) +b101100000000000100010011 \ +b101100000000000100010011 n +b11000 ' +b11000 C +b11000 h +b11000 ( +b11000 D +b11000 g +b101011101 = +b101011101 J +b101011101 f +b0 P +b0 Q +b100 R +b0 V +b10011 S +b101011101 A +b1 H +b1100011 E +b1110110100 a +b1110110000 , +b1110110000 ] +b1110110000 b +b1110110000 j +b11101 # +b1110101100 . +b1110101100 U +b1110101100 ^ +b1000010011 - +b1000010011 T +b1000010011 _ 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+#9070000 +b10000 = +b10000 J +b10000 f +b1000001000000000110011 ) +b1000001000000000110011 \ +b1000001000000000110011 n +b10000 B +b10000 A +b0 H +b10011 E +b11110 P +b10 R +b0 6 +b0 Y +b0 c +b1 2 +b1 [ +b1 e +11 +b10011001100 9 +b10011001100 G +b10011001100 W +b1000000000000000010010011 8 +b1000000000000000010010011 F +b1000000000000000010010011 X +b10011010000 . +b10011010000 U +b10011010000 ^ +b1111000000000000100010011 - +b1111000000000000100010011 T +b1111000000000000100010011 _ +b10011011000 a +b10011010100 , +b10011010100 ] +b10011010100 b +b10011010100 j +1$ +#9080000 +0$ +#9090000 +b111010010011 ) +b111010010011 \ +b111010010011 n +b11110 = +b11110 J +b11110 f +b10 P +b1 Q +b0 R +b110011 S +b11110 B +b11110 A +b10011011100 a +b10011011000 , +b10011011000 ] +b10011011000 b +b10011011000 j +b10011010100 . +b10011010100 U +b10011010100 ^ +b1000001000000000110011 - +b1000001000000000110011 T +b1000001000000000110011 _ +b10 2 +b10 [ +b10 e +b10011010000 9 +b10011010000 G +b10011010000 W +b1111000000000000100010011 8 +b1111000000000000100010011 F +b1111000000000000100010011 X +1$ +#9100000 +0$ +#9110000 +b101110 = +b101110 J +b101110 f +b11110 ' +b11110 C +b11110 h +b10000 ( +b10000 D +b10000 g +b10011000000000000110010011 ) +b10011000000000000110010011 \ +b10011000000000000110010011 n +b10 B +b10 A +b110011 E +b0 P +b0 Q +b11101 R +b10011 S +b10 4 +b10 Z +b10 d +b1 6 +b1 Y +b1 c +b0 2 +b0 [ +b0 e +b10011010100 9 +b10011010100 G +b10011010100 W +b1000001000000000110011 8 +b1000001000000000110011 F +b1000001000000000110011 X +b10011011000 . +b10011011000 U +b10011011000 ^ +b111010010011 - +b111010010011 T +b111010010011 _ +b10011100000 a +b10011011100 , +b10011011100 ] +b10011011100 b +b10011011100 j +1$ +#9120000 +0$ +#9130000 +b0 = +b0 J +b0 f +b1110100000001010001100011 ) +b1110100000001010001100011 \ +b1110100000001010001100011 n +b0 ( +b0 D +b0 g +b110 P +b11 R +b0 B +b0 A +b10011 E +b10011100100 a +b10011100000 , +b10011100000 ] +b10011100000 b +b10011100000 j +b10011011100 . +b10011011100 U +b10011011100 ^ +b10011000000000000110010011 - +b10011000000000000110010011 T +b10011000000000000110010011 _ +b0 6 +b0 Y +b0 c +b11101 2 +b11101 [ +b11101 e +b10011011000 9 +b10011011000 G +b10011011000 W +b111010010011 8 +b111010010011 F +b111010010011 X +1$ +#9140000 +0$ +#9150000 +b100110 = +b100110 J +b100110 f +b1100000001100001100011 ) +b1100000001100001100011 \ +b1100000001100001100011 n +b110 B +b100110 A +b11101 P +b1000 R +b1 V +b1100011 S +b11 2 +b11 [ +b11 e +b10011011100 9 +b10011011100 G +b10011011100 W +b10011000000000000110010011 8 +b10011000000000000110010011 F +b10011000000000000110010011 X +b10011100000 . +b10011100000 U +b10011100000 ^ +b1110100000001010001100011 - +b1110100000001010001100011 T +b1110100000001010001100011 _ +b10011101000 a +b10011100100 , +b10011100100 ] +b10011100100 b +b10011100100 j +1$ +#9160000 +0$ +#9170000 +0> +b100000000110100010011 ) +b100000000110100010011 \ +b100000000110100010011 n +b0 ' +b0 C +b0 h +b11101 = +b11101 J +b11101 f +b11 P +b10000 R +b11101 B +b11101 A +b1 H +b1100011 E +b10011101100 a +b10011101000 , +b10011101000 ] +b10011101000 b +b10011101000 j +b100110 # +b10011100100 . +b10011100100 U +b10011100100 ^ +b1100000001100001100011 - +b1100000001100001100011 T +b1100000001100001100011 _ +01 +b11101 4 +b11101 Z +b11101 d +b10011100000 9 +b10011100000 G +b10011100000 W +b1110100000001010001100011 8 +b1110100000001010001100011 F +b1110100000001010001100011 X +1$ +#9180000 +0$ +#9190000 +b10011110100 ? +b10011110100 I +b10011110100 ` +1> +b100110 ' +b100110 C +b100110 h +b110110010011 ) +b110110010011 \ +b110110010011 n +b11 B +b11 A +b1 P +b11010 R +b0 V +b10011 S +b11 4 +b11 Z +b11 d +b10011100100 9 +b10011100100 G +b10011100100 W +b1100000001100001100011 8 +b1100000001100001100011 F +b1100000001100001100011 X +b10011101000 . +b10011101000 U +b10011101000 ^ +b100000000110100010011 - +b100000000110100010011 T +b100000000110100010011 _ +b10011110000 a +b10011101100 , +b10011101100 ] +b10011101100 b +b10011101100 j +1$ +#9200000 +0$ +#9210000 +0> +b100000000110100010011 ) +b100000000110100010011 \ +b100000000110100010011 n +b10011100100 ? +b10011100100 I +b10011100100 ` +b0 P +b0 R +b1 S +b0 B +b0 A +b0 H +b1 E +b10011111000 a +b10011110100 , +b10011110100 ] +b10011110100 b +b10011110100 j +b0 . +b0 U +b0 ^ +b1 - +b1 T +b1 _ +b1 8 +b1 F +b1 X +1$ +#9220000 +0$ +#9230000 +b100000000110110010011 ) +b100000000110110010011 \ +b100000000110110010011 n +b1 P +b11010 R +b10011 S +b0 9 +b0 G +b0 W +b10011110100 . +b10011110100 U +b10011110100 ^ +b100000000110100010011 - +b100000000110100010011 T +b100000000110100010011 _ +b10011111100 a +b10011111000 , +b10011111000 ] +b10011111000 b +b10011111000 j +1$ +#9240000 +0$ +#9250000 +b1 = +b1 J +b1 f +b1101111 ) +b1101111 \ +b1101111 n +b11011 R +b1 B +b1 A +b10011 E +b10100000000 a +b10011111100 , +b10011111100 ] +b10011111100 b +b10011111100 j +b10011111000 . +b10011111000 U +b10011111000 ^ +b100000000110110010011 - +b100000000110110010011 T +b100000000110110010011 _ +b11010 2 +b11010 [ +b11010 e +11 +b10011110100 9 +b10011110100 G +b10011110100 W +b100000000110100010011 8 +b100000000110100010011 F +b100000000110100010011 X +1$ +#9260000 +0$ +#9270000 +b0 ) +b0 \ +b0 n +b0 P +b0 R +b1101111 S +b11011 2 +b11011 [ +b11011 e +b10011111000 9 +b10011111000 G +b10011111000 W +b100000000110110010011 8 +b100000000110110010011 F +b100000000110110010011 X +b10011111100 . +b10011111100 U +b10011111100 ^ +b1101111 - +b1101111 T +b1101111 _ +b1 ! +b10100000100 a +b10100000000 , +b10100000000 ] +b10100000000 b +b10100000000 j +1$ +#9280000 +0$ +#9290000 +b10011111100 ? +b10011111100 I +b10011111100 ` +1> +b10100000000 = +b10100000000 J +b10100000000 f +b0 S +b0 B +b0 A +b1101111 E +b10100001000 a +b10100000100 , +b10100000100 ] +b10100000100 b +b10100000100 j +b1 " +b10100000000 . +b10100000000 U +b10100000000 ^ +b0 - +b0 T +b0 _ +b0 2 +b0 [ +b0 e +b10011111100 9 +b10011111100 G +b10011111100 W +b1101111 8 +b1101111 F +b1101111 X +1$ +#9300000 +0$ +#9310000 +0> +b1101111 ) +b1101111 \ +b1101111 n +b1 E +b1 S +b1 8 +b1 F +b1 X +01 +b0 . +b0 U +b0 ^ +b1 - +b1 T +b1 _ +b10100000000 a +b10011111100 , +b10011111100 ] +b10011111100 b +b10011111100 j +1$ +#9320000 +0$ +#9330000 +b0 ) +b0 \ +b0 n +b1101111 S +b10100000100 a +b10100000000 , +b10100000000 ] +b10100000000 b +b10100000000 j +b10011111100 . +b10011111100 U +b10011111100 ^ +b1101111 - +b1101111 T +b1101111 _ +b0 9 +b0 G +b0 W +1$ +#9340000 +0$ +#9350000 +1> +b1101111 E +b0 S +11 +b10011111100 9 +b10011111100 G +b10011111100 W +b1101111 8 +b1101111 F +b1101111 X +b10100000000 . +b10100000000 U +b10100000000 ^ +b0 - +b0 T +b0 _ +b10100001000 a +b10100000100 , +b10100000100 ] +b10100000100 b +b10100000100 j +1$ +#9360000 +0$ +#9370000 +0> +b1101111 ) +b1101111 \ +b1101111 n +b1 S +b1 E +b10100000000 a +b10011111100 , +b10011111100 ] +b10011111100 b +b10011111100 j +b0 . +b0 U +b0 ^ +b1 - +b1 T +b1 _ +b1 8 +b1 F +b1 X +01 +1$ diff --git a/sim/out.vvp b/sim/out.vvp new file mode 100644 index 0000000..9650bdd --- /dev/null +++ b/sim/out.vvp @@ -0,0 +1,6456 @@ +#! /usr/local/iverilog/bin/vvp +:ivl_version "11.0 (devel)" "(s20150603-642-g3bdb50da)"; +:ivl_delay_selection "TYPICAL"; +:vpi_time_precision - 12; +:vpi_module "system"; +:vpi_module "vhdl_sys"; +:vpi_module "vhdl_textio"; +:vpi_module "v2005_math"; +:vpi_module "va_math"; +S_00000000007cdc30 .scope module, "openriscv_core_tb" "openriscv_core_tb" 2 6; + .timescale -9 -12; +v0000000000bda3d0_3 .array/port v0000000000bda3d0, 3; +L_0000000000ac5e80 .functor BUFZ 32, v0000000000bda3d0_3, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0000000000bda3d0_26 .array/port v0000000000bda3d0, 26; +L_0000000000ac5d30 .functor BUFZ 32, v0000000000bda3d0_26, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0000000000bda3d0_27 .array/port v0000000000bda3d0, 27; +L_0000000000ac5da0 .functor BUFZ 32, v0000000000bda3d0_27, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>; +v0000000000bf4070_0 .var "clk", 0 0; +v0000000000bf4110_0 .var/i "r", 31 0; +v0000000000bf41b0_0 .var "rst", 0 0; +v0000000000bf4250_0 .net "x26", 31 0, L_0000000000ac5d30; 1 drivers +v0000000000bf42f0_0 .net "x27", 31 0, L_0000000000ac5da0; 1 drivers +v0000000000bf4390_0 .net "x3", 31 0, L_0000000000ac5e80; 1 drivers +E_00000000006a1d90 .event edge, v0000000000bf4250_0; +S_0000000000b88750 .scope module, "u_openriscv_core" "openriscv_core" 2 72, 3 20 0, S_00000000007cdc30; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; +v0000000000bf2f90_0 .net "clk", 0 0, v0000000000bf4070_0; 1 drivers +v0000000000bf3030_0 .net "ex_jump_addr_o", 31 0, v0000000000b24c60_0; 1 drivers +v0000000000bf30d0_0 .net "ex_jump_flag_o", 0 0, v0000000000b24d00_0; 1 drivers +v0000000000bf3170_0 .net "ex_reg_wdata_o", 31 0, v0000000000b24f80_0; 1 drivers +v0000000000bf3210_0 .net "ex_sram_raddr_o", 31 0, v0000000000b252a0_0; 1 drivers +v0000000000bf32b0_0 .net "ex_sram_waddr_o", 31 0, v0000000000b25480_0; 1 drivers +v0000000000bf3350_0 .net "ex_sram_wdata_o", 31 0, v0000000000b25520_0; 1 drivers +v0000000000bf33f0_0 .net "id_inst_addr_o", 31 0, v0000000000b257a0_0; 1 drivers +v0000000000bf3490_0 .net "id_inst_o", 31 0, v0000000000b258e0_0; 1 drivers +v0000000000bf3530_0 .net "id_inst_valid_o", 0 0, v0000000000b25980_0; 1 drivers +v0000000000bf35d0_0 .net "id_reg1_raddr_o", 4 0, v0000000000bd8fd0_0; 1 drivers +v0000000000bf3670_0 .net "id_reg1_re_o", 0 0, v0000000000bd9070_0; 1 drivers +v0000000000bf3710_0 .net "id_reg2_raddr_o", 4 0, v0000000000bd9110_0; 1 drivers +v0000000000bf37b0_0 .net "id_reg2_re_o", 0 0, v0000000000bd91b0_0; 1 drivers +v0000000000bf3850_0 .net "id_reg_waddr_o", 4 0, v0000000000bd9250_0; 1 drivers +v0000000000bf38f0_0 .net "id_reg_we_o", 0 0, v0000000000bd92f0_0; 1 drivers +v0000000000bf3990_0 .net "id_sram_re_o", 0 0, v0000000000bd9570_0; 1 drivers +v0000000000bf3a30_0 .net "id_sram_we_o", 0 0, v0000000000bd9610_0; 1 drivers +v0000000000bf3ad0_0 .net "if_inst_addr_o", 31 0, v0000000000bd97f0_0; 1 drivers +v0000000000bf3b70_0 .net "if_inst_o", 31 0, v0000000000bd9930_0; 1 drivers +v0000000000bf3c10_0 .net "pc_pc_o", 31 0, v0000000000bd9d90_0; 1 drivers +v0000000000bf3cb0_0 .net "pc_re_o", 0 0, v0000000000bd9e30_0; 1 drivers +v0000000000bf3d50_0 .net "ram_ex_rdata_o", 31 0, v0000000000bda830_0; 1 drivers +v0000000000bf3df0_0 .net "ram_pc_rdata_o", 31 0, v0000000000bdaa10_0; 1 drivers +v0000000000bf3e90_0 .net "regs_rdata1_o", 31 0, v0000000000bda150_0; 1 drivers +v0000000000bf3f30_0 .net "regs_rdata2_o", 31 0, v0000000000bda1f0_0; 1 drivers +v0000000000bf3fd0_0 .net "rst", 0 0, v0000000000bf41b0_0; 1 drivers +S_0000000000b8cea0 .scope module, "u_ex" "ex" 3 131, 4 20 0, S_0000000000b88750; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 32 "inst_i"; + .port_info 3 /INPUT 1 "inst_valid_i"; + .port_info 4 /INPUT 32 "inst_addr_i"; + .port_info 5 /INPUT 32 "reg1_rdata_i"; + .port_info 6 /INPUT 32 "reg2_rdata_i"; + .port_info 7 /INPUT 32 "sram_rdata_i"; + .port_info 8 /OUTPUT 32 "sram_wdata_o"; + .port_info 9 /OUTPUT 32 "sram_raddr_o"; + .port_info 10 /OUTPUT 32 "sram_waddr_o"; + .port_info 11 /OUTPUT 32 "reg_wdata_o"; + .port_info 12 /OUTPUT 1 "jump_flag_o"; + .port_info 13 /OUTPUT 32 "jump_addr_o"; +v0000000000b23c20_0 .net *"_s5", 0 0, L_0000000000bf4890; 1 drivers +v0000000000b23e00_0 .net *"_s6", 19 0, L_0000000000bf4930; 1 drivers +v0000000000b24300_0 .net *"_s9", 11 0, L_0000000000bf49d0; 1 drivers +v0000000000b24940_0 .net "clk", 0 0, v0000000000bf4070_0; alias, 1 drivers +v0000000000b249e0_0 .net "funct3", 2 0, L_0000000000bf47f0; 1 drivers +v0000000000b24a80_0 .net "inst_addr_i", 31 0, v0000000000b257a0_0; alias, 1 drivers +v0000000000b24b20_0 .net "inst_i", 31 0, v0000000000b258e0_0; alias, 1 drivers +v0000000000b24bc0_0 .net "inst_valid_i", 0 0, v0000000000b25980_0; alias, 1 drivers +v0000000000b24c60_0 .var "jump_addr_o", 31 0; +v0000000000b24d00_0 .var "jump_flag_o", 0 0; +v0000000000b24da0_0 .net "opcode", 6 0, L_0000000000bf4750; 1 drivers +v0000000000b24e40_0 .net "reg1_rdata_i", 31 0, v0000000000bda150_0; alias, 1 drivers +v0000000000b24ee0_0 .net "reg2_rdata_i", 31 0, v0000000000bda1f0_0; alias, 1 drivers +v0000000000b24f80_0 .var "reg_wdata_o", 31 0; +v0000000000b25020_0 .net "rst", 0 0, v0000000000bf41b0_0; alias, 1 drivers +v0000000000b250c0_0 .net "shift_bits", 4 0, L_0000000000bf4b10; 1 drivers +v0000000000b25160_0 .net "sign_extend_tmp", 31 0, L_0000000000bf4a70; 1 drivers +v0000000000b25200_0 .var "sram_raddr_index", 1 0; +v0000000000b252a0_0 .var "sram_raddr_o", 31 0; +v0000000000b25340_0 .net "sram_rdata_i", 31 0, v0000000000bda830_0; alias, 1 drivers +v0000000000b253e0_0 .var "sram_waddr_index", 1 0; +v0000000000b25480_0 .var "sram_waddr_o", 31 0; +v0000000000b25520_0 .var "sram_wdata_o", 31 0; +E_00000000006a1d50/0 .event edge, v0000000000b24bc0_0, v0000000000b24da0_0, v0000000000b249e0_0, v0000000000b25200_0; +E_00000000006a1d50/1 .event edge, v0000000000b25340_0, v0000000000b253e0_0, v0000000000b24ee0_0; +E_00000000006a1d50 .event/or E_00000000006a1d50/0, E_00000000006a1d50/1; +E_00000000006a1c50/0 .event edge, v0000000000b24bc0_0, v0000000000b24da0_0, v0000000000b249e0_0, v0000000000b24e40_0; +E_00000000006a1c50/1 .event edge, v0000000000b24b20_0, v0000000000b25160_0, v0000000000b250c0_0, v0000000000b24ee0_0; +E_00000000006a1c50/2 .event edge, v0000000000b24a80_0; +E_00000000006a1c50 .event/or E_00000000006a1c50/0, E_00000000006a1c50/1, E_00000000006a1c50/2; +E_00000000006a1b90 .event posedge, v0000000000b24940_0; +L_0000000000bf4750 .part v0000000000b258e0_0, 0, 7; +L_0000000000bf47f0 .part v0000000000b258e0_0, 12, 3; +L_0000000000bf4890 .part v0000000000b258e0_0, 31, 1; +LS_0000000000bf4930_0_0 .concat [ 1 1 1 1], L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890; +LS_0000000000bf4930_0_4 .concat [ 1 1 1 1], L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890; +LS_0000000000bf4930_0_8 .concat [ 1 1 1 1], L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890; +LS_0000000000bf4930_0_12 .concat [ 1 1 1 1], L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890; +LS_0000000000bf4930_0_16 .concat [ 1 1 1 1], L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890, L_0000000000bf4890; +LS_0000000000bf4930_1_0 .concat [ 4 4 4 4], LS_0000000000bf4930_0_0, LS_0000000000bf4930_0_4, LS_0000000000bf4930_0_8, LS_0000000000bf4930_0_12; +LS_0000000000bf4930_1_4 .concat [ 4 0 0 0], LS_0000000000bf4930_0_16; +L_0000000000bf4930 .concat [ 16 4 0 0], LS_0000000000bf4930_1_0, LS_0000000000bf4930_1_4; +L_0000000000bf49d0 .part v0000000000b258e0_0, 20, 12; +L_0000000000bf4a70 .concat [ 12 20 0 0], L_0000000000bf49d0, L_0000000000bf4930; +L_0000000000bf4b10 .part v0000000000b258e0_0, 20, 5; +S_0000000000ac0200 .scope module, "u_id" "id" 3 112, 5 20 0, S_0000000000b88750; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 32 "inst_i"; + .port_info 3 /INPUT 32 "inst_addr_i"; + .port_info 4 /INPUT 1 "jump_flag_ex_i"; + .port_info 5 /OUTPUT 1 "reg1_re_o"; + .port_info 6 /OUTPUT 5 "reg1_raddr_o"; + .port_info 7 /OUTPUT 1 "reg2_re_o"; + .port_info 8 /OUTPUT 5 "reg2_raddr_o"; + .port_info 9 /OUTPUT 1 "reg_we_o"; + .port_info 10 /OUTPUT 5 "reg_waddr_o"; + .port_info 11 /OUTPUT 32 "inst_o"; + .port_info 12 /OUTPUT 1 "inst_valid_o"; + .port_info 13 /OUTPUT 32 "inst_addr_o"; + .port_info 14 /OUTPUT 1 "sram_re_o"; + .port_info 15 /OUTPUT 1 "sram_we_o"; +v0000000000b255c0_0 .net "clk", 0 0, v0000000000bf4070_0; alias, 1 drivers +v0000000000b25660_0 .net "funct3", 2 0, L_0000000000bf44d0; 1 drivers +v0000000000b25700_0 .net "inst_addr_i", 31 0, v0000000000bd97f0_0; alias, 1 drivers +v0000000000b257a0_0 .var "inst_addr_o", 31 0; +v0000000000b25840_0 .net "inst_i", 31 0, v0000000000bd9930_0; alias, 1 drivers +v0000000000b258e0_0 .var "inst_o", 31 0; +v0000000000b25980_0 .var "inst_valid_o", 0 0; +v0000000000b25a20_0 .net "jump_flag_ex_i", 0 0, v0000000000b24d00_0; alias, 1 drivers +v0000000000b25ac0_0 .net "opcode", 6 0, L_0000000000bf4430; 1 drivers +v0000000000bd8f30_0 .net "rd", 4 0, L_0000000000bf4570; 1 drivers +v0000000000bd8fd0_0 .var "reg1_raddr_o", 4 0; +v0000000000bd9070_0 .var "reg1_re_o", 0 0; +v0000000000bd9110_0 .var "reg2_raddr_o", 4 0; +v0000000000bd91b0_0 .var "reg2_re_o", 0 0; +v0000000000bd9250_0 .var "reg_waddr_o", 4 0; +v0000000000bd92f0_0 .var "reg_we_o", 0 0; +v0000000000bd9390_0 .net "rs1", 4 0, L_0000000000bf4610; 1 drivers +v0000000000bd9430_0 .net "rs2", 4 0, L_0000000000bf46b0; 1 drivers +v0000000000bd94d0_0 .net "rst", 0 0, v0000000000bf41b0_0; alias, 1 drivers +v0000000000bd9570_0 .var "sram_re_o", 0 0; +v0000000000bd9610_0 .var "sram_we_o", 0 0; +L_0000000000bf4430 .part v0000000000bd9930_0, 0, 7; +L_0000000000bf44d0 .part v0000000000bd9930_0, 12, 3; +L_0000000000bf4570 .part v0000000000bd9930_0, 7, 5; +L_0000000000bf4610 .part v0000000000bd9930_0, 15, 5; +L_0000000000bf46b0 .part v0000000000bd9930_0, 20, 5; +S_0000000000ab3dc0 .scope module, "u_if_id" "if_id" 3 102, 6 20 0, S_0000000000b88750; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 32 "inst_i"; + .port_info 3 /INPUT 32 "inst_addr_i"; + .port_info 4 /INPUT 1 "jump_flag_ex_i"; + .port_info 5 /OUTPUT 32 "inst_o"; + .port_info 6 /OUTPUT 32 "inst_addr_o"; +v0000000000bd96b0_0 .net "clk", 0 0, v0000000000bf4070_0; alias, 1 drivers +v0000000000bd9750_0 .net "inst_addr_i", 31 0, v0000000000bd9d90_0; alias, 1 drivers +v0000000000bd97f0_0 .var "inst_addr_o", 31 0; +v0000000000bd9890_0 .net "inst_i", 31 0, v0000000000bdaa10_0; alias, 1 drivers +v0000000000bd9930_0 .var "inst_o", 31 0; +v0000000000bd99d0_0 .net "jump_flag_ex_i", 0 0, v0000000000b24d00_0; alias, 1 drivers +v0000000000bd9a70_0 .net "rst", 0 0, v0000000000bf41b0_0; alias, 1 drivers +S_0000000000aad080 .scope module, "u_pc_reg" "pc_reg" 3 79, 7 20 0, S_0000000000b88750; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "jump_flag_ex_i"; + .port_info 3 /INPUT 32 "jump_addr_ex_i"; + .port_info 4 /OUTPUT 32 "pc_o"; + .port_info 5 /OUTPUT 1 "re_o"; +v0000000000bd9b10_0 .net "clk", 0 0, v0000000000bf4070_0; alias, 1 drivers +v0000000000bd9bb0_0 .net "jump_addr_ex_i", 31 0, v0000000000b24c60_0; alias, 1 drivers +v0000000000bd9c50_0 .net "jump_flag_ex_i", 0 0, v0000000000b24d00_0; alias, 1 drivers +v0000000000bd9cf0_0 .var "offset", 31 0; +v0000000000bd9d90_0 .var "pc_o", 31 0; +v0000000000bd9e30_0 .var "re_o", 0 0; +v0000000000bd9ed0_0 .net "rst", 0 0, v0000000000bf41b0_0; alias, 1 drivers +S_0000000000aad210 .scope module, "u_regs" "regs" 3 88, 8 20 0, S_0000000000b88750; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "we"; + .port_info 3 /INPUT 5 "waddr"; + .port_info 4 /INPUT 32 "wdata"; + .port_info 5 /INPUT 1 "re1"; + .port_info 6 /INPUT 5 "raddr1"; + .port_info 7 /OUTPUT 32 "rdata1"; + .port_info 8 /INPUT 1 "re2"; + .port_info 9 /INPUT 5 "raddr2"; + .port_info 10 /OUTPUT 32 "rdata2"; +v0000000000bd9f70_0 .net "clk", 0 0, v0000000000bf4070_0; alias, 1 drivers +v0000000000bda010_0 .net "raddr1", 4 0, v0000000000bd8fd0_0; alias, 1 drivers +v0000000000bda0b0_0 .net "raddr2", 4 0, v0000000000bd9110_0; alias, 1 drivers +v0000000000bda150_0 .var "rdata1", 31 0; +v0000000000bda1f0_0 .var "rdata2", 31 0; +v0000000000bda290_0 .net "re1", 0 0, v0000000000bd9070_0; alias, 1 drivers +v0000000000bda330_0 .net "re2", 0 0, v0000000000bd91b0_0; alias, 1 drivers +v0000000000bda3d0 .array "regs", 31 0, 31 0; +v0000000000bda470_0 .net "rst", 0 0, v0000000000bf41b0_0; alias, 1 drivers +v0000000000bda510_0 .net "waddr", 4 0, v0000000000bd9250_0; alias, 1 drivers +v0000000000bda5b0_0 .net "wdata", 31 0, v0000000000b24f80_0; alias, 1 drivers +v0000000000bda650_0 .net "we", 0 0, v0000000000bd92f0_0; alias, 1 drivers +v0000000000bda3d0_0 .array/port v0000000000bda3d0, 0; +E_00000000006a1b50/0 .event edge, v0000000000b25020_0, v0000000000bd9110_0, v0000000000bd91b0_0, v0000000000bda3d0_0; +v0000000000bda3d0_1 .array/port v0000000000bda3d0, 1; +v0000000000bda3d0_2 .array/port v0000000000bda3d0, 2; +v0000000000bda3d0_4 .array/port v0000000000bda3d0, 4; +E_00000000006a1b50/1 .event edge, v0000000000bda3d0_1, v0000000000bda3d0_2, v0000000000bda3d0_3, v0000000000bda3d0_4; +v0000000000bda3d0_5 .array/port v0000000000bda3d0, 5; +v0000000000bda3d0_6 .array/port v0000000000bda3d0, 6; +v0000000000bda3d0_7 .array/port v0000000000bda3d0, 7; +v0000000000bda3d0_8 .array/port v0000000000bda3d0, 8; +E_00000000006a1b50/2 .event edge, v0000000000bda3d0_5, v0000000000bda3d0_6, v0000000000bda3d0_7, v0000000000bda3d0_8; +v0000000000bda3d0_9 .array/port v0000000000bda3d0, 9; +v0000000000bda3d0_10 .array/port v0000000000bda3d0, 10; +v0000000000bda3d0_11 .array/port v0000000000bda3d0, 11; +v0000000000bda3d0_12 .array/port v0000000000bda3d0, 12; +E_00000000006a1b50/3 .event edge, v0000000000bda3d0_9, v0000000000bda3d0_10, v0000000000bda3d0_11, v0000000000bda3d0_12; +v0000000000bda3d0_13 .array/port v0000000000bda3d0, 13; +v0000000000bda3d0_14 .array/port v0000000000bda3d0, 14; +v0000000000bda3d0_15 .array/port v0000000000bda3d0, 15; +v0000000000bda3d0_16 .array/port v0000000000bda3d0, 16; +E_00000000006a1b50/4 .event edge, v0000000000bda3d0_13, v0000000000bda3d0_14, v0000000000bda3d0_15, v0000000000bda3d0_16; +v0000000000bda3d0_17 .array/port v0000000000bda3d0, 17; +v0000000000bda3d0_18 .array/port v0000000000bda3d0, 18; +v0000000000bda3d0_19 .array/port v0000000000bda3d0, 19; +v0000000000bda3d0_20 .array/port v0000000000bda3d0, 20; +E_00000000006a1b50/5 .event edge, v0000000000bda3d0_17, v0000000000bda3d0_18, v0000000000bda3d0_19, v0000000000bda3d0_20; +v0000000000bda3d0_21 .array/port v0000000000bda3d0, 21; +v0000000000bda3d0_22 .array/port v0000000000bda3d0, 22; +v0000000000bda3d0_23 .array/port v0000000000bda3d0, 23; +v0000000000bda3d0_24 .array/port v0000000000bda3d0, 24; +E_00000000006a1b50/6 .event edge, v0000000000bda3d0_21, v0000000000bda3d0_22, v0000000000bda3d0_23, v0000000000bda3d0_24; +v0000000000bda3d0_25 .array/port v0000000000bda3d0, 25; +v0000000000bda3d0_28 .array/port v0000000000bda3d0, 28; +E_00000000006a1b50/7 .event edge, v0000000000bda3d0_25, v0000000000bda3d0_26, v0000000000bda3d0_27, v0000000000bda3d0_28; +v0000000000bda3d0_29 .array/port v0000000000bda3d0, 29; +v0000000000bda3d0_30 .array/port v0000000000bda3d0, 30; +v0000000000bda3d0_31 .array/port v0000000000bda3d0, 31; +E_00000000006a1b50/8 .event edge, v0000000000bda3d0_29, v0000000000bda3d0_30, v0000000000bda3d0_31; +E_00000000006a1b50 .event/or E_00000000006a1b50/0, E_00000000006a1b50/1, E_00000000006a1b50/2, E_00000000006a1b50/3, E_00000000006a1b50/4, E_00000000006a1b50/5, E_00000000006a1b50/6, E_00000000006a1b50/7, E_00000000006a1b50/8; +E_00000000006a3110/0 .event edge, v0000000000b25020_0, v0000000000bd8fd0_0, v0000000000bd9070_0, v0000000000bda3d0_0; +E_00000000006a3110/1 .event edge, v0000000000bda3d0_1, v0000000000bda3d0_2, v0000000000bda3d0_3, v0000000000bda3d0_4; +E_00000000006a3110/2 .event edge, v0000000000bda3d0_5, v0000000000bda3d0_6, v0000000000bda3d0_7, v0000000000bda3d0_8; +E_00000000006a3110/3 .event edge, v0000000000bda3d0_9, v0000000000bda3d0_10, v0000000000bda3d0_11, v0000000000bda3d0_12; +E_00000000006a3110/4 .event edge, v0000000000bda3d0_13, v0000000000bda3d0_14, v0000000000bda3d0_15, v0000000000bda3d0_16; +E_00000000006a3110/5 .event edge, v0000000000bda3d0_17, v0000000000bda3d0_18, v0000000000bda3d0_19, v0000000000bda3d0_20; +E_00000000006a3110/6 .event edge, v0000000000bda3d0_21, v0000000000bda3d0_22, v0000000000bda3d0_23, v0000000000bda3d0_24; +E_00000000006a3110/7 .event edge, v0000000000bda3d0_25, v0000000000bda3d0_26, v0000000000bda3d0_27, v0000000000bda3d0_28; +E_00000000006a3110/8 .event edge, v0000000000bda3d0_29, v0000000000bda3d0_30, v0000000000bda3d0_31; +E_00000000006a3110 .event/or E_00000000006a3110/0, E_00000000006a3110/1, E_00000000006a3110/2, E_00000000006a3110/3, E_00000000006a3110/4, E_00000000006a3110/5, E_00000000006a3110/6, E_00000000006a3110/7, E_00000000006a3110/8; +S_0000000000ac6910 .scope module, "u_sim_ram" "sim_ram" 3 65, 9 20 0, S_0000000000b88750; + .timescale -9 -12; + .port_info 0 /INPUT 1 "clk"; + .port_info 1 /INPUT 1 "rst"; + .port_info 2 /INPUT 1 "we_i"; + .port_info 3 /INPUT 32 "waddr_i"; + .port_info 4 /INPUT 32 "wdata_i"; + .port_info 5 /INPUT 1 "pc_re_i"; + .port_info 6 /INPUT 32 "pc_raddr_i"; + .port_info 7 /OUTPUT 32 "pc_rdata_o"; + .port_info 8 /INPUT 1 "ex_re_i"; + .port_info 9 /INPUT 32 "ex_raddr_i"; + .port_info 10 /OUTPUT 32 "ex_rdata_o"; +v0000000000bda6f0_0 .net "clk", 0 0, v0000000000bf4070_0; alias, 1 drivers +v0000000000bda790_0 .net "ex_raddr_i", 31 0, v0000000000b252a0_0; alias, 1 drivers +v0000000000bda830_0 .var "ex_rdata_o", 31 0; +v0000000000bda8d0_0 .net "ex_re_i", 0 0, v0000000000bd9570_0; alias, 1 drivers +v0000000000bda970_0 .net "pc_raddr_i", 31 0, v0000000000bd9d90_0; alias, 1 drivers +v0000000000bdaa10_0 .var "pc_rdata_o", 31 0; +v0000000000bdaab0_0 .net "pc_re_i", 0 0, v0000000000bd9e30_0; alias, 1 drivers +v0000000000bdab50 .array "ram", 2047 0, 31 0; +v0000000000bdabf0_0 .net "rst", 0 0, v0000000000bf41b0_0; alias, 1 drivers +v0000000000bdac90_0 .net "waddr_i", 31 0, v0000000000b25480_0; alias, 1 drivers +v0000000000bdad30_0 .net "wdata_i", 31 0, v0000000000b25520_0; alias, 1 drivers +v0000000000bdadd0_0 .net "we_i", 0 0, v0000000000bd9610_0; alias, 1 drivers +v0000000000bdab50_0 .array/port v0000000000bdab50, 0; +E_00000000006a3090/0 .event edge, v0000000000b25020_0, v0000000000bd9570_0, v0000000000b252a0_0, v0000000000bdab50_0; +v0000000000bdab50_1 .array/port v0000000000bdab50, 1; +v0000000000bdab50_2 .array/port v0000000000bdab50, 2; +v0000000000bdab50_3 .array/port v0000000000bdab50, 3; +v0000000000bdab50_4 .array/port v0000000000bdab50, 4; +E_00000000006a3090/1 .event edge, v0000000000bdab50_1, v0000000000bdab50_2, v0000000000bdab50_3, v0000000000bdab50_4; +v0000000000bdab50_5 .array/port v0000000000bdab50, 5; +v0000000000bdab50_6 .array/port v0000000000bdab50, 6; +v0000000000bdab50_7 .array/port v0000000000bdab50, 7; +v0000000000bdab50_8 .array/port v0000000000bdab50, 8; +E_00000000006a3090/2 .event edge, v0000000000bdab50_5, v0000000000bdab50_6, v0000000000bdab50_7, v0000000000bdab50_8; +v0000000000bdab50_9 .array/port v0000000000bdab50, 9; +v0000000000bdab50_10 .array/port v0000000000bdab50, 10; +v0000000000bdab50_11 .array/port v0000000000bdab50, 11; +v0000000000bdab50_12 .array/port v0000000000bdab50, 12; +E_00000000006a3090/3 .event edge, v0000000000bdab50_9, v0000000000bdab50_10, v0000000000bdab50_11, v0000000000bdab50_12; +v0000000000bdab50_13 .array/port v0000000000bdab50, 13; +v0000000000bdab50_14 .array/port v0000000000bdab50, 14; +v0000000000bdab50_15 .array/port v0000000000bdab50, 15; +v0000000000bdab50_16 .array/port v0000000000bdab50, 16; +E_00000000006a3090/4 .event edge, v0000000000bdab50_13, v0000000000bdab50_14, v0000000000bdab50_15, v0000000000bdab50_16; +v0000000000bdab50_17 .array/port v0000000000bdab50, 17; +v0000000000bdab50_18 .array/port v0000000000bdab50, 18; +v0000000000bdab50_19 .array/port v0000000000bdab50, 19; +v0000000000bdab50_20 .array/port v0000000000bdab50, 20; +E_00000000006a3090/5 .event edge, v0000000000bdab50_17, v0000000000bdab50_18, v0000000000bdab50_19, v0000000000bdab50_20; +v0000000000bdab50_21 .array/port v0000000000bdab50, 21; +v0000000000bdab50_22 .array/port v0000000000bdab50, 22; +v0000000000bdab50_23 .array/port v0000000000bdab50, 23; +v0000000000bdab50_24 .array/port v0000000000bdab50, 24; +E_00000000006a3090/6 .event edge, v0000000000bdab50_21, v0000000000bdab50_22, v0000000000bdab50_23, v0000000000bdab50_24; +v0000000000bdab50_25 .array/port v0000000000bdab50, 25; +v0000000000bdab50_26 .array/port v0000000000bdab50, 26; +v0000000000bdab50_27 .array/port v0000000000bdab50, 27; +v0000000000bdab50_28 .array/port v0000000000bdab50, 28; +E_00000000006a3090/7 .event edge, v0000000000bdab50_25, v0000000000bdab50_26, v0000000000bdab50_27, v0000000000bdab50_28; +v0000000000bdab50_29 .array/port v0000000000bdab50, 29; +v0000000000bdab50_30 .array/port v0000000000bdab50, 30; +v0000000000bdab50_31 .array/port v0000000000bdab50, 31; +v0000000000bdab50_32 .array/port v0000000000bdab50, 32; +E_00000000006a3090/8 .event edge, v0000000000bdab50_29, v0000000000bdab50_30, v0000000000bdab50_31, v0000000000bdab50_32; +v0000000000bdab50_33 .array/port v0000000000bdab50, 33; +v0000000000bdab50_34 .array/port v0000000000bdab50, 34; +v0000000000bdab50_35 .array/port v0000000000bdab50, 35; +v0000000000bdab50_36 .array/port v0000000000bdab50, 36; +E_00000000006a3090/9 .event edge, v0000000000bdab50_33, v0000000000bdab50_34, v0000000000bdab50_35, v0000000000bdab50_36; +v0000000000bdab50_37 .array/port v0000000000bdab50, 37; +v0000000000bdab50_38 .array/port v0000000000bdab50, 38; +v0000000000bdab50_39 .array/port v0000000000bdab50, 39; +v0000000000bdab50_40 .array/port v0000000000bdab50, 40; +E_00000000006a3090/10 .event edge, v0000000000bdab50_37, v0000000000bdab50_38, v0000000000bdab50_39, v0000000000bdab50_40; +v0000000000bdab50_41 .array/port v0000000000bdab50, 41; +v0000000000bdab50_42 .array/port v0000000000bdab50, 42; +v0000000000bdab50_43 .array/port v0000000000bdab50, 43; +v0000000000bdab50_44 .array/port v0000000000bdab50, 44; +E_00000000006a3090/11 .event edge, v0000000000bdab50_41, v0000000000bdab50_42, v0000000000bdab50_43, v0000000000bdab50_44; +v0000000000bdab50_45 .array/port v0000000000bdab50, 45; +v0000000000bdab50_46 .array/port v0000000000bdab50, 46; +v0000000000bdab50_47 .array/port v0000000000bdab50, 47; +v0000000000bdab50_48 .array/port v0000000000bdab50, 48; +E_00000000006a3090/12 .event edge, v0000000000bdab50_45, v0000000000bdab50_46, v0000000000bdab50_47, v0000000000bdab50_48; +v0000000000bdab50_49 .array/port v0000000000bdab50, 49; +v0000000000bdab50_50 .array/port v0000000000bdab50, 50; +v0000000000bdab50_51 .array/port v0000000000bdab50, 51; +v0000000000bdab50_52 .array/port v0000000000bdab50, 52; +E_00000000006a3090/13 .event edge, v0000000000bdab50_49, v0000000000bdab50_50, v0000000000bdab50_51, v0000000000bdab50_52; +v0000000000bdab50_53 .array/port v0000000000bdab50, 53; +v0000000000bdab50_54 .array/port v0000000000bdab50, 54; +v0000000000bdab50_55 .array/port v0000000000bdab50, 55; +v0000000000bdab50_56 .array/port v0000000000bdab50, 56; +E_00000000006a3090/14 .event edge, v0000000000bdab50_53, v0000000000bdab50_54, v0000000000bdab50_55, v0000000000bdab50_56; +v0000000000bdab50_57 .array/port v0000000000bdab50, 57; +v0000000000bdab50_58 .array/port v0000000000bdab50, 58; +v0000000000bdab50_59 .array/port v0000000000bdab50, 59; +v0000000000bdab50_60 .array/port v0000000000bdab50, 60; +E_00000000006a3090/15 .event edge, v0000000000bdab50_57, v0000000000bdab50_58, v0000000000bdab50_59, v0000000000bdab50_60; +v0000000000bdab50_61 .array/port v0000000000bdab50, 61; +v0000000000bdab50_62 .array/port v0000000000bdab50, 62; +v0000000000bdab50_63 .array/port v0000000000bdab50, 63; +v0000000000bdab50_64 .array/port v0000000000bdab50, 64; +E_00000000006a3090/16 .event edge, v0000000000bdab50_61, v0000000000bdab50_62, v0000000000bdab50_63, v0000000000bdab50_64; +v0000000000bdab50_65 .array/port v0000000000bdab50, 65; +v0000000000bdab50_66 .array/port v0000000000bdab50, 66; +v0000000000bdab50_67 .array/port v0000000000bdab50, 67; +v0000000000bdab50_68 .array/port v0000000000bdab50, 68; +E_00000000006a3090/17 .event edge, v0000000000bdab50_65, v0000000000bdab50_66, v0000000000bdab50_67, v0000000000bdab50_68; +v0000000000bdab50_69 .array/port v0000000000bdab50, 69; +v0000000000bdab50_70 .array/port v0000000000bdab50, 70; +v0000000000bdab50_71 .array/port v0000000000bdab50, 71; +v0000000000bdab50_72 .array/port v0000000000bdab50, 72; +E_00000000006a3090/18 .event edge, v0000000000bdab50_69, v0000000000bdab50_70, v0000000000bdab50_71, v0000000000bdab50_72; +v0000000000bdab50_73 .array/port v0000000000bdab50, 73; +v0000000000bdab50_74 .array/port v0000000000bdab50, 74; +v0000000000bdab50_75 .array/port v0000000000bdab50, 75; +v0000000000bdab50_76 .array/port v0000000000bdab50, 76; +E_00000000006a3090/19 .event edge, v0000000000bdab50_73, v0000000000bdab50_74, v0000000000bdab50_75, v0000000000bdab50_76; +v0000000000bdab50_77 .array/port v0000000000bdab50, 77; +v0000000000bdab50_78 .array/port v0000000000bdab50, 78; +v0000000000bdab50_79 .array/port v0000000000bdab50, 79; +v0000000000bdab50_80 .array/port v0000000000bdab50, 80; +E_00000000006a3090/20 .event edge, v0000000000bdab50_77, v0000000000bdab50_78, v0000000000bdab50_79, v0000000000bdab50_80; +v0000000000bdab50_81 .array/port v0000000000bdab50, 81; +v0000000000bdab50_82 .array/port v0000000000bdab50, 82; +v0000000000bdab50_83 .array/port v0000000000bdab50, 83; +v0000000000bdab50_84 .array/port v0000000000bdab50, 84; +E_00000000006a3090/21 .event edge, v0000000000bdab50_81, v0000000000bdab50_82, v0000000000bdab50_83, v0000000000bdab50_84; +v0000000000bdab50_85 .array/port v0000000000bdab50, 85; +v0000000000bdab50_86 .array/port v0000000000bdab50, 86; +v0000000000bdab50_87 .array/port v0000000000bdab50, 87; +v0000000000bdab50_88 .array/port v0000000000bdab50, 88; +E_00000000006a3090/22 .event edge, v0000000000bdab50_85, v0000000000bdab50_86, v0000000000bdab50_87, v0000000000bdab50_88; +v0000000000bdab50_89 .array/port v0000000000bdab50, 89; +v0000000000bdab50_90 .array/port v0000000000bdab50, 90; +v0000000000bdab50_91 .array/port v0000000000bdab50, 91; +v0000000000bdab50_92 .array/port v0000000000bdab50, 92; +E_00000000006a3090/23 .event edge, v0000000000bdab50_89, v0000000000bdab50_90, v0000000000bdab50_91, v0000000000bdab50_92; +v0000000000bdab50_93 .array/port v0000000000bdab50, 93; +v0000000000bdab50_94 .array/port v0000000000bdab50, 94; +v0000000000bdab50_95 .array/port v0000000000bdab50, 95; +v0000000000bdab50_96 .array/port v0000000000bdab50, 96; +E_00000000006a3090/24 .event edge, v0000000000bdab50_93, v0000000000bdab50_94, v0000000000bdab50_95, v0000000000bdab50_96; +v0000000000bdab50_97 .array/port v0000000000bdab50, 97; +v0000000000bdab50_98 .array/port v0000000000bdab50, 98; +v0000000000bdab50_99 .array/port v0000000000bdab50, 99; +v0000000000bdab50_100 .array/port v0000000000bdab50, 100; +E_00000000006a3090/25 .event edge, v0000000000bdab50_97, v0000000000bdab50_98, v0000000000bdab50_99, v0000000000bdab50_100; +v0000000000bdab50_101 .array/port v0000000000bdab50, 101; +v0000000000bdab50_102 .array/port v0000000000bdab50, 102; +v0000000000bdab50_103 .array/port v0000000000bdab50, 103; +v0000000000bdab50_104 .array/port v0000000000bdab50, 104; +E_00000000006a3090/26 .event edge, v0000000000bdab50_101, v0000000000bdab50_102, v0000000000bdab50_103, v0000000000bdab50_104; +v0000000000bdab50_105 .array/port v0000000000bdab50, 105; +v0000000000bdab50_106 .array/port v0000000000bdab50, 106; +v0000000000bdab50_107 .array/port v0000000000bdab50, 107; +v0000000000bdab50_108 .array/port v0000000000bdab50, 108; +E_00000000006a3090/27 .event edge, v0000000000bdab50_105, v0000000000bdab50_106, v0000000000bdab50_107, v0000000000bdab50_108; +v0000000000bdab50_109 .array/port v0000000000bdab50, 109; +v0000000000bdab50_110 .array/port v0000000000bdab50, 110; +v0000000000bdab50_111 .array/port v0000000000bdab50, 111; +v0000000000bdab50_112 .array/port v0000000000bdab50, 112; +E_00000000006a3090/28 .event edge, v0000000000bdab50_109, v0000000000bdab50_110, v0000000000bdab50_111, v0000000000bdab50_112; +v0000000000bdab50_113 .array/port v0000000000bdab50, 113; +v0000000000bdab50_114 .array/port v0000000000bdab50, 114; +v0000000000bdab50_115 .array/port v0000000000bdab50, 115; +v0000000000bdab50_116 .array/port v0000000000bdab50, 116; +E_00000000006a3090/29 .event edge, v0000000000bdab50_113, v0000000000bdab50_114, v0000000000bdab50_115, v0000000000bdab50_116; +v0000000000bdab50_117 .array/port v0000000000bdab50, 117; +v0000000000bdab50_118 .array/port v0000000000bdab50, 118; +v0000000000bdab50_119 .array/port v0000000000bdab50, 119; +v0000000000bdab50_120 .array/port v0000000000bdab50, 120; +E_00000000006a3090/30 .event edge, v0000000000bdab50_117, v0000000000bdab50_118, v0000000000bdab50_119, v0000000000bdab50_120; +v0000000000bdab50_121 .array/port v0000000000bdab50, 121; +v0000000000bdab50_122 .array/port v0000000000bdab50, 122; +v0000000000bdab50_123 .array/port v0000000000bdab50, 123; +v0000000000bdab50_124 .array/port v0000000000bdab50, 124; +E_00000000006a3090/31 .event edge, v0000000000bdab50_121, v0000000000bdab50_122, v0000000000bdab50_123, v0000000000bdab50_124; +v0000000000bdab50_125 .array/port v0000000000bdab50, 125; +v0000000000bdab50_126 .array/port v0000000000bdab50, 126; +v0000000000bdab50_127 .array/port v0000000000bdab50, 127; +v0000000000bdab50_128 .array/port v0000000000bdab50, 128; +E_00000000006a3090/32 .event edge, v0000000000bdab50_125, v0000000000bdab50_126, v0000000000bdab50_127, v0000000000bdab50_128; +v0000000000bdab50_129 .array/port v0000000000bdab50, 129; +v0000000000bdab50_130 .array/port v0000000000bdab50, 130; +v0000000000bdab50_131 .array/port v0000000000bdab50, 131; +v0000000000bdab50_132 .array/port v0000000000bdab50, 132; +E_00000000006a3090/33 .event edge, v0000000000bdab50_129, v0000000000bdab50_130, v0000000000bdab50_131, v0000000000bdab50_132; +v0000000000bdab50_133 .array/port v0000000000bdab50, 133; +v0000000000bdab50_134 .array/port v0000000000bdab50, 134; +v0000000000bdab50_135 .array/port v0000000000bdab50, 135; +v0000000000bdab50_136 .array/port v0000000000bdab50, 136; +E_00000000006a3090/34 .event edge, v0000000000bdab50_133, v0000000000bdab50_134, v0000000000bdab50_135, v0000000000bdab50_136; +v0000000000bdab50_137 .array/port v0000000000bdab50, 137; +v0000000000bdab50_138 .array/port v0000000000bdab50, 138; +v0000000000bdab50_139 .array/port v0000000000bdab50, 139; +v0000000000bdab50_140 .array/port v0000000000bdab50, 140; +E_00000000006a3090/35 .event edge, v0000000000bdab50_137, v0000000000bdab50_138, v0000000000bdab50_139, v0000000000bdab50_140; +v0000000000bdab50_141 .array/port v0000000000bdab50, 141; +v0000000000bdab50_142 .array/port v0000000000bdab50, 142; +v0000000000bdab50_143 .array/port v0000000000bdab50, 143; +v0000000000bdab50_144 .array/port v0000000000bdab50, 144; +E_00000000006a3090/36 .event edge, v0000000000bdab50_141, v0000000000bdab50_142, v0000000000bdab50_143, v0000000000bdab50_144; +v0000000000bdab50_145 .array/port v0000000000bdab50, 145; +v0000000000bdab50_146 .array/port v0000000000bdab50, 146; +v0000000000bdab50_147 .array/port v0000000000bdab50, 147; +v0000000000bdab50_148 .array/port v0000000000bdab50, 148; +E_00000000006a3090/37 .event edge, v0000000000bdab50_145, v0000000000bdab50_146, v0000000000bdab50_147, v0000000000bdab50_148; +v0000000000bdab50_149 .array/port v0000000000bdab50, 149; +v0000000000bdab50_150 .array/port v0000000000bdab50, 150; +v0000000000bdab50_151 .array/port v0000000000bdab50, 151; +v0000000000bdab50_152 .array/port v0000000000bdab50, 152; +E_00000000006a3090/38 .event edge, v0000000000bdab50_149, v0000000000bdab50_150, v0000000000bdab50_151, v0000000000bdab50_152; +v0000000000bdab50_153 .array/port v0000000000bdab50, 153; +v0000000000bdab50_154 .array/port v0000000000bdab50, 154; +v0000000000bdab50_155 .array/port v0000000000bdab50, 155; +v0000000000bdab50_156 .array/port v0000000000bdab50, 156; +E_00000000006a3090/39 .event edge, v0000000000bdab50_153, v0000000000bdab50_154, v0000000000bdab50_155, v0000000000bdab50_156; +v0000000000bdab50_157 .array/port v0000000000bdab50, 157; +v0000000000bdab50_158 .array/port v0000000000bdab50, 158; +v0000000000bdab50_159 .array/port v0000000000bdab50, 159; +v0000000000bdab50_160 .array/port v0000000000bdab50, 160; +E_00000000006a3090/40 .event edge, v0000000000bdab50_157, v0000000000bdab50_158, v0000000000bdab50_159, v0000000000bdab50_160; +v0000000000bdab50_161 .array/port v0000000000bdab50, 161; +v0000000000bdab50_162 .array/port v0000000000bdab50, 162; +v0000000000bdab50_163 .array/port v0000000000bdab50, 163; +v0000000000bdab50_164 .array/port v0000000000bdab50, 164; +E_00000000006a3090/41 .event edge, v0000000000bdab50_161, v0000000000bdab50_162, v0000000000bdab50_163, v0000000000bdab50_164; +v0000000000bdab50_165 .array/port v0000000000bdab50, 165; +v0000000000bdab50_166 .array/port v0000000000bdab50, 166; +v0000000000bdab50_167 .array/port v0000000000bdab50, 167; +v0000000000bdab50_168 .array/port v0000000000bdab50, 168; +E_00000000006a3090/42 .event edge, v0000000000bdab50_165, v0000000000bdab50_166, v0000000000bdab50_167, v0000000000bdab50_168; +v0000000000bdab50_169 .array/port v0000000000bdab50, 169; +v0000000000bdab50_170 .array/port v0000000000bdab50, 170; +v0000000000bdab50_171 .array/port v0000000000bdab50, 171; +v0000000000bdab50_172 .array/port v0000000000bdab50, 172; +E_00000000006a3090/43 .event edge, v0000000000bdab50_169, v0000000000bdab50_170, v0000000000bdab50_171, v0000000000bdab50_172; +v0000000000bdab50_173 .array/port v0000000000bdab50, 173; +v0000000000bdab50_174 .array/port v0000000000bdab50, 174; +v0000000000bdab50_175 .array/port v0000000000bdab50, 175; +v0000000000bdab50_176 .array/port v0000000000bdab50, 176; +E_00000000006a3090/44 .event edge, v0000000000bdab50_173, v0000000000bdab50_174, v0000000000bdab50_175, v0000000000bdab50_176; +v0000000000bdab50_177 .array/port v0000000000bdab50, 177; +v0000000000bdab50_178 .array/port v0000000000bdab50, 178; +v0000000000bdab50_179 .array/port v0000000000bdab50, 179; +v0000000000bdab50_180 .array/port v0000000000bdab50, 180; +E_00000000006a3090/45 .event edge, v0000000000bdab50_177, v0000000000bdab50_178, v0000000000bdab50_179, v0000000000bdab50_180; +v0000000000bdab50_181 .array/port v0000000000bdab50, 181; +v0000000000bdab50_182 .array/port v0000000000bdab50, 182; +v0000000000bdab50_183 .array/port v0000000000bdab50, 183; +v0000000000bdab50_184 .array/port v0000000000bdab50, 184; +E_00000000006a3090/46 .event edge, v0000000000bdab50_181, v0000000000bdab50_182, v0000000000bdab50_183, v0000000000bdab50_184; +v0000000000bdab50_185 .array/port v0000000000bdab50, 185; +v0000000000bdab50_186 .array/port v0000000000bdab50, 186; +v0000000000bdab50_187 .array/port v0000000000bdab50, 187; +v0000000000bdab50_188 .array/port v0000000000bdab50, 188; +E_00000000006a3090/47 .event edge, v0000000000bdab50_185, v0000000000bdab50_186, v0000000000bdab50_187, v0000000000bdab50_188; +v0000000000bdab50_189 .array/port v0000000000bdab50, 189; +v0000000000bdab50_190 .array/port v0000000000bdab50, 190; +v0000000000bdab50_191 .array/port v0000000000bdab50, 191; +v0000000000bdab50_192 .array/port v0000000000bdab50, 192; +E_00000000006a3090/48 .event edge, v0000000000bdab50_189, v0000000000bdab50_190, v0000000000bdab50_191, v0000000000bdab50_192; +v0000000000bdab50_193 .array/port v0000000000bdab50, 193; +v0000000000bdab50_194 .array/port v0000000000bdab50, 194; +v0000000000bdab50_195 .array/port v0000000000bdab50, 195; +v0000000000bdab50_196 .array/port v0000000000bdab50, 196; +E_00000000006a3090/49 .event edge, v0000000000bdab50_193, v0000000000bdab50_194, v0000000000bdab50_195, v0000000000bdab50_196; +v0000000000bdab50_197 .array/port v0000000000bdab50, 197; +v0000000000bdab50_198 .array/port v0000000000bdab50, 198; +v0000000000bdab50_199 .array/port v0000000000bdab50, 199; +v0000000000bdab50_200 .array/port v0000000000bdab50, 200; +E_00000000006a3090/50 .event edge, v0000000000bdab50_197, v0000000000bdab50_198, v0000000000bdab50_199, v0000000000bdab50_200; +v0000000000bdab50_201 .array/port v0000000000bdab50, 201; +v0000000000bdab50_202 .array/port v0000000000bdab50, 202; +v0000000000bdab50_203 .array/port v0000000000bdab50, 203; +v0000000000bdab50_204 .array/port v0000000000bdab50, 204; +E_00000000006a3090/51 .event edge, v0000000000bdab50_201, v0000000000bdab50_202, v0000000000bdab50_203, v0000000000bdab50_204; +v0000000000bdab50_205 .array/port v0000000000bdab50, 205; +v0000000000bdab50_206 .array/port v0000000000bdab50, 206; +v0000000000bdab50_207 .array/port v0000000000bdab50, 207; +v0000000000bdab50_208 .array/port v0000000000bdab50, 208; +E_00000000006a3090/52 .event edge, v0000000000bdab50_205, v0000000000bdab50_206, v0000000000bdab50_207, v0000000000bdab50_208; +v0000000000bdab50_209 .array/port v0000000000bdab50, 209; +v0000000000bdab50_210 .array/port v0000000000bdab50, 210; +v0000000000bdab50_211 .array/port v0000000000bdab50, 211; +v0000000000bdab50_212 .array/port v0000000000bdab50, 212; +E_00000000006a3090/53 .event edge, v0000000000bdab50_209, v0000000000bdab50_210, v0000000000bdab50_211, v0000000000bdab50_212; +v0000000000bdab50_213 .array/port v0000000000bdab50, 213; +v0000000000bdab50_214 .array/port v0000000000bdab50, 214; +v0000000000bdab50_215 .array/port v0000000000bdab50, 215; +v0000000000bdab50_216 .array/port v0000000000bdab50, 216; +E_00000000006a3090/54 .event edge, v0000000000bdab50_213, v0000000000bdab50_214, v0000000000bdab50_215, v0000000000bdab50_216; +v0000000000bdab50_217 .array/port v0000000000bdab50, 217; +v0000000000bdab50_218 .array/port v0000000000bdab50, 218; +v0000000000bdab50_219 .array/port v0000000000bdab50, 219; +v0000000000bdab50_220 .array/port v0000000000bdab50, 220; +E_00000000006a3090/55 .event edge, v0000000000bdab50_217, v0000000000bdab50_218, v0000000000bdab50_219, v0000000000bdab50_220; +v0000000000bdab50_221 .array/port v0000000000bdab50, 221; +v0000000000bdab50_222 .array/port v0000000000bdab50, 222; +v0000000000bdab50_223 .array/port v0000000000bdab50, 223; +v0000000000bdab50_224 .array/port v0000000000bdab50, 224; +E_00000000006a3090/56 .event edge, v0000000000bdab50_221, v0000000000bdab50_222, v0000000000bdab50_223, v0000000000bdab50_224; +v0000000000bdab50_225 .array/port v0000000000bdab50, 225; +v0000000000bdab50_226 .array/port v0000000000bdab50, 226; +v0000000000bdab50_227 .array/port v0000000000bdab50, 227; +v0000000000bdab50_228 .array/port v0000000000bdab50, 228; +E_00000000006a3090/57 .event edge, v0000000000bdab50_225, v0000000000bdab50_226, v0000000000bdab50_227, v0000000000bdab50_228; +v0000000000bdab50_229 .array/port v0000000000bdab50, 229; +v0000000000bdab50_230 .array/port v0000000000bdab50, 230; +v0000000000bdab50_231 .array/port v0000000000bdab50, 231; +v0000000000bdab50_232 .array/port v0000000000bdab50, 232; +E_00000000006a3090/58 .event edge, v0000000000bdab50_229, v0000000000bdab50_230, v0000000000bdab50_231, v0000000000bdab50_232; +v0000000000bdab50_233 .array/port v0000000000bdab50, 233; +v0000000000bdab50_234 .array/port v0000000000bdab50, 234; +v0000000000bdab50_235 .array/port v0000000000bdab50, 235; +v0000000000bdab50_236 .array/port v0000000000bdab50, 236; +E_00000000006a3090/59 .event edge, v0000000000bdab50_233, v0000000000bdab50_234, v0000000000bdab50_235, v0000000000bdab50_236; +v0000000000bdab50_237 .array/port v0000000000bdab50, 237; +v0000000000bdab50_238 .array/port v0000000000bdab50, 238; +v0000000000bdab50_239 .array/port v0000000000bdab50, 239; +v0000000000bdab50_240 .array/port v0000000000bdab50, 240; +E_00000000006a3090/60 .event edge, v0000000000bdab50_237, v0000000000bdab50_238, v0000000000bdab50_239, v0000000000bdab50_240; +v0000000000bdab50_241 .array/port v0000000000bdab50, 241; +v0000000000bdab50_242 .array/port v0000000000bdab50, 242; +v0000000000bdab50_243 .array/port v0000000000bdab50, 243; +v0000000000bdab50_244 .array/port v0000000000bdab50, 244; +E_00000000006a3090/61 .event edge, v0000000000bdab50_241, v0000000000bdab50_242, v0000000000bdab50_243, v0000000000bdab50_244; +v0000000000bdab50_245 .array/port v0000000000bdab50, 245; +v0000000000bdab50_246 .array/port v0000000000bdab50, 246; +v0000000000bdab50_247 .array/port v0000000000bdab50, 247; +v0000000000bdab50_248 .array/port v0000000000bdab50, 248; +E_00000000006a3090/62 .event edge, v0000000000bdab50_245, v0000000000bdab50_246, v0000000000bdab50_247, v0000000000bdab50_248; +v0000000000bdab50_249 .array/port v0000000000bdab50, 249; +v0000000000bdab50_250 .array/port v0000000000bdab50, 250; +v0000000000bdab50_251 .array/port v0000000000bdab50, 251; +v0000000000bdab50_252 .array/port v0000000000bdab50, 252; +E_00000000006a3090/63 .event edge, v0000000000bdab50_249, v0000000000bdab50_250, v0000000000bdab50_251, v0000000000bdab50_252; +v0000000000bdab50_253 .array/port v0000000000bdab50, 253; +v0000000000bdab50_254 .array/port v0000000000bdab50, 254; +v0000000000bdab50_255 .array/port v0000000000bdab50, 255; +v0000000000bdab50_256 .array/port v0000000000bdab50, 256; +E_00000000006a3090/64 .event edge, v0000000000bdab50_253, v0000000000bdab50_254, v0000000000bdab50_255, v0000000000bdab50_256; +v0000000000bdab50_257 .array/port v0000000000bdab50, 257; +v0000000000bdab50_258 .array/port v0000000000bdab50, 258; +v0000000000bdab50_259 .array/port v0000000000bdab50, 259; +v0000000000bdab50_260 .array/port v0000000000bdab50, 260; +E_00000000006a3090/65 .event edge, v0000000000bdab50_257, v0000000000bdab50_258, v0000000000bdab50_259, v0000000000bdab50_260; +v0000000000bdab50_261 .array/port v0000000000bdab50, 261; +v0000000000bdab50_262 .array/port v0000000000bdab50, 262; +v0000000000bdab50_263 .array/port v0000000000bdab50, 263; +v0000000000bdab50_264 .array/port v0000000000bdab50, 264; +E_00000000006a3090/66 .event edge, v0000000000bdab50_261, v0000000000bdab50_262, v0000000000bdab50_263, v0000000000bdab50_264; +v0000000000bdab50_265 .array/port v0000000000bdab50, 265; +v0000000000bdab50_266 .array/port v0000000000bdab50, 266; +v0000000000bdab50_267 .array/port v0000000000bdab50, 267; +v0000000000bdab50_268 .array/port v0000000000bdab50, 268; +E_00000000006a3090/67 .event edge, v0000000000bdab50_265, v0000000000bdab50_266, v0000000000bdab50_267, v0000000000bdab50_268; +v0000000000bdab50_269 .array/port v0000000000bdab50, 269; +v0000000000bdab50_270 .array/port v0000000000bdab50, 270; +v0000000000bdab50_271 .array/port v0000000000bdab50, 271; +v0000000000bdab50_272 .array/port v0000000000bdab50, 272; +E_00000000006a3090/68 .event edge, v0000000000bdab50_269, v0000000000bdab50_270, v0000000000bdab50_271, v0000000000bdab50_272; +v0000000000bdab50_273 .array/port v0000000000bdab50, 273; +v0000000000bdab50_274 .array/port v0000000000bdab50, 274; +v0000000000bdab50_275 .array/port v0000000000bdab50, 275; +v0000000000bdab50_276 .array/port v0000000000bdab50, 276; +E_00000000006a3090/69 .event edge, v0000000000bdab50_273, v0000000000bdab50_274, v0000000000bdab50_275, v0000000000bdab50_276; +v0000000000bdab50_277 .array/port v0000000000bdab50, 277; +v0000000000bdab50_278 .array/port v0000000000bdab50, 278; +v0000000000bdab50_279 .array/port v0000000000bdab50, 279; +v0000000000bdab50_280 .array/port v0000000000bdab50, 280; +E_00000000006a3090/70 .event edge, v0000000000bdab50_277, v0000000000bdab50_278, v0000000000bdab50_279, v0000000000bdab50_280; +v0000000000bdab50_281 .array/port v0000000000bdab50, 281; +v0000000000bdab50_282 .array/port v0000000000bdab50, 282; +v0000000000bdab50_283 .array/port v0000000000bdab50, 283; +v0000000000bdab50_284 .array/port v0000000000bdab50, 284; +E_00000000006a3090/71 .event edge, v0000000000bdab50_281, v0000000000bdab50_282, v0000000000bdab50_283, v0000000000bdab50_284; +v0000000000bdab50_285 .array/port v0000000000bdab50, 285; +v0000000000bdab50_286 .array/port v0000000000bdab50, 286; +v0000000000bdab50_287 .array/port v0000000000bdab50, 287; +v0000000000bdab50_288 .array/port v0000000000bdab50, 288; +E_00000000006a3090/72 .event edge, v0000000000bdab50_285, v0000000000bdab50_286, v0000000000bdab50_287, v0000000000bdab50_288; +v0000000000bdab50_289 .array/port v0000000000bdab50, 289; +v0000000000bdab50_290 .array/port v0000000000bdab50, 290; +v0000000000bdab50_291 .array/port v0000000000bdab50, 291; +v0000000000bdab50_292 .array/port v0000000000bdab50, 292; +E_00000000006a3090/73 .event edge, v0000000000bdab50_289, v0000000000bdab50_290, v0000000000bdab50_291, v0000000000bdab50_292; +v0000000000bdab50_293 .array/port v0000000000bdab50, 293; +v0000000000bdab50_294 .array/port v0000000000bdab50, 294; +v0000000000bdab50_295 .array/port v0000000000bdab50, 295; +v0000000000bdab50_296 .array/port v0000000000bdab50, 296; +E_00000000006a3090/74 .event edge, v0000000000bdab50_293, v0000000000bdab50_294, v0000000000bdab50_295, v0000000000bdab50_296; +v0000000000bdab50_297 .array/port v0000000000bdab50, 297; +v0000000000bdab50_298 .array/port v0000000000bdab50, 298; +v0000000000bdab50_299 .array/port v0000000000bdab50, 299; +v0000000000bdab50_300 .array/port v0000000000bdab50, 300; +E_00000000006a3090/75 .event edge, v0000000000bdab50_297, v0000000000bdab50_298, v0000000000bdab50_299, v0000000000bdab50_300; +v0000000000bdab50_301 .array/port v0000000000bdab50, 301; +v0000000000bdab50_302 .array/port v0000000000bdab50, 302; +v0000000000bdab50_303 .array/port v0000000000bdab50, 303; +v0000000000bdab50_304 .array/port v0000000000bdab50, 304; +E_00000000006a3090/76 .event edge, v0000000000bdab50_301, v0000000000bdab50_302, v0000000000bdab50_303, v0000000000bdab50_304; +v0000000000bdab50_305 .array/port v0000000000bdab50, 305; +v0000000000bdab50_306 .array/port v0000000000bdab50, 306; +v0000000000bdab50_307 .array/port v0000000000bdab50, 307; +v0000000000bdab50_308 .array/port v0000000000bdab50, 308; +E_00000000006a3090/77 .event edge, v0000000000bdab50_305, v0000000000bdab50_306, v0000000000bdab50_307, v0000000000bdab50_308; +v0000000000bdab50_309 .array/port v0000000000bdab50, 309; +v0000000000bdab50_310 .array/port v0000000000bdab50, 310; +v0000000000bdab50_311 .array/port v0000000000bdab50, 311; +v0000000000bdab50_312 .array/port v0000000000bdab50, 312; +E_00000000006a3090/78 .event edge, v0000000000bdab50_309, v0000000000bdab50_310, v0000000000bdab50_311, v0000000000bdab50_312; +v0000000000bdab50_313 .array/port v0000000000bdab50, 313; +v0000000000bdab50_314 .array/port v0000000000bdab50, 314; +v0000000000bdab50_315 .array/port v0000000000bdab50, 315; +v0000000000bdab50_316 .array/port v0000000000bdab50, 316; +E_00000000006a3090/79 .event edge, v0000000000bdab50_313, v0000000000bdab50_314, v0000000000bdab50_315, v0000000000bdab50_316; +v0000000000bdab50_317 .array/port v0000000000bdab50, 317; +v0000000000bdab50_318 .array/port v0000000000bdab50, 318; +v0000000000bdab50_319 .array/port v0000000000bdab50, 319; +v0000000000bdab50_320 .array/port v0000000000bdab50, 320; +E_00000000006a3090/80 .event edge, v0000000000bdab50_317, v0000000000bdab50_318, v0000000000bdab50_319, v0000000000bdab50_320; +v0000000000bdab50_321 .array/port v0000000000bdab50, 321; +v0000000000bdab50_322 .array/port v0000000000bdab50, 322; +v0000000000bdab50_323 .array/port v0000000000bdab50, 323; +v0000000000bdab50_324 .array/port v0000000000bdab50, 324; +E_00000000006a3090/81 .event edge, v0000000000bdab50_321, v0000000000bdab50_322, v0000000000bdab50_323, v0000000000bdab50_324; +v0000000000bdab50_325 .array/port v0000000000bdab50, 325; +v0000000000bdab50_326 .array/port v0000000000bdab50, 326; +v0000000000bdab50_327 .array/port v0000000000bdab50, 327; +v0000000000bdab50_328 .array/port v0000000000bdab50, 328; +E_00000000006a3090/82 .event edge, v0000000000bdab50_325, v0000000000bdab50_326, v0000000000bdab50_327, v0000000000bdab50_328; +v0000000000bdab50_329 .array/port v0000000000bdab50, 329; +v0000000000bdab50_330 .array/port v0000000000bdab50, 330; +v0000000000bdab50_331 .array/port v0000000000bdab50, 331; +v0000000000bdab50_332 .array/port v0000000000bdab50, 332; +E_00000000006a3090/83 .event edge, v0000000000bdab50_329, v0000000000bdab50_330, v0000000000bdab50_331, v0000000000bdab50_332; +v0000000000bdab50_333 .array/port v0000000000bdab50, 333; +v0000000000bdab50_334 .array/port v0000000000bdab50, 334; +v0000000000bdab50_335 .array/port v0000000000bdab50, 335; +v0000000000bdab50_336 .array/port v0000000000bdab50, 336; +E_00000000006a3090/84 .event edge, v0000000000bdab50_333, v0000000000bdab50_334, v0000000000bdab50_335, v0000000000bdab50_336; +v0000000000bdab50_337 .array/port v0000000000bdab50, 337; +v0000000000bdab50_338 .array/port v0000000000bdab50, 338; +v0000000000bdab50_339 .array/port v0000000000bdab50, 339; +v0000000000bdab50_340 .array/port v0000000000bdab50, 340; +E_00000000006a3090/85 .event edge, v0000000000bdab50_337, v0000000000bdab50_338, v0000000000bdab50_339, v0000000000bdab50_340; +v0000000000bdab50_341 .array/port v0000000000bdab50, 341; +v0000000000bdab50_342 .array/port v0000000000bdab50, 342; +v0000000000bdab50_343 .array/port v0000000000bdab50, 343; +v0000000000bdab50_344 .array/port v0000000000bdab50, 344; +E_00000000006a3090/86 .event edge, v0000000000bdab50_341, v0000000000bdab50_342, v0000000000bdab50_343, v0000000000bdab50_344; +v0000000000bdab50_345 .array/port v0000000000bdab50, 345; +v0000000000bdab50_346 .array/port v0000000000bdab50, 346; +v0000000000bdab50_347 .array/port v0000000000bdab50, 347; +v0000000000bdab50_348 .array/port v0000000000bdab50, 348; +E_00000000006a3090/87 .event edge, v0000000000bdab50_345, v0000000000bdab50_346, v0000000000bdab50_347, v0000000000bdab50_348; +v0000000000bdab50_349 .array/port v0000000000bdab50, 349; +v0000000000bdab50_350 .array/port v0000000000bdab50, 350; +v0000000000bdab50_351 .array/port v0000000000bdab50, 351; +v0000000000bdab50_352 .array/port v0000000000bdab50, 352; +E_00000000006a3090/88 .event edge, v0000000000bdab50_349, v0000000000bdab50_350, v0000000000bdab50_351, v0000000000bdab50_352; +v0000000000bdab50_353 .array/port v0000000000bdab50, 353; +v0000000000bdab50_354 .array/port v0000000000bdab50, 354; +v0000000000bdab50_355 .array/port v0000000000bdab50, 355; +v0000000000bdab50_356 .array/port v0000000000bdab50, 356; +E_00000000006a3090/89 .event edge, v0000000000bdab50_353, v0000000000bdab50_354, v0000000000bdab50_355, v0000000000bdab50_356; +v0000000000bdab50_357 .array/port v0000000000bdab50, 357; +v0000000000bdab50_358 .array/port v0000000000bdab50, 358; +v0000000000bdab50_359 .array/port v0000000000bdab50, 359; +v0000000000bdab50_360 .array/port v0000000000bdab50, 360; +E_00000000006a3090/90 .event edge, v0000000000bdab50_357, v0000000000bdab50_358, v0000000000bdab50_359, v0000000000bdab50_360; +v0000000000bdab50_361 .array/port v0000000000bdab50, 361; +v0000000000bdab50_362 .array/port v0000000000bdab50, 362; +v0000000000bdab50_363 .array/port v0000000000bdab50, 363; +v0000000000bdab50_364 .array/port v0000000000bdab50, 364; +E_00000000006a3090/91 .event edge, v0000000000bdab50_361, v0000000000bdab50_362, v0000000000bdab50_363, v0000000000bdab50_364; +v0000000000bdab50_365 .array/port v0000000000bdab50, 365; +v0000000000bdab50_366 .array/port v0000000000bdab50, 366; +v0000000000bdab50_367 .array/port v0000000000bdab50, 367; +v0000000000bdab50_368 .array/port v0000000000bdab50, 368; +E_00000000006a3090/92 .event edge, v0000000000bdab50_365, v0000000000bdab50_366, v0000000000bdab50_367, v0000000000bdab50_368; +v0000000000bdab50_369 .array/port v0000000000bdab50, 369; +v0000000000bdab50_370 .array/port v0000000000bdab50, 370; +v0000000000bdab50_371 .array/port v0000000000bdab50, 371; +v0000000000bdab50_372 .array/port v0000000000bdab50, 372; +E_00000000006a3090/93 .event edge, v0000000000bdab50_369, v0000000000bdab50_370, v0000000000bdab50_371, v0000000000bdab50_372; +v0000000000bdab50_373 .array/port v0000000000bdab50, 373; +v0000000000bdab50_374 .array/port v0000000000bdab50, 374; +v0000000000bdab50_375 .array/port v0000000000bdab50, 375; +v0000000000bdab50_376 .array/port v0000000000bdab50, 376; +E_00000000006a3090/94 .event edge, v0000000000bdab50_373, v0000000000bdab50_374, v0000000000bdab50_375, v0000000000bdab50_376; +v0000000000bdab50_377 .array/port v0000000000bdab50, 377; +v0000000000bdab50_378 .array/port v0000000000bdab50, 378; +v0000000000bdab50_379 .array/port v0000000000bdab50, 379; +v0000000000bdab50_380 .array/port v0000000000bdab50, 380; +E_00000000006a3090/95 .event edge, v0000000000bdab50_377, v0000000000bdab50_378, v0000000000bdab50_379, v0000000000bdab50_380; +v0000000000bdab50_381 .array/port v0000000000bdab50, 381; +v0000000000bdab50_382 .array/port v0000000000bdab50, 382; +v0000000000bdab50_383 .array/port v0000000000bdab50, 383; +v0000000000bdab50_384 .array/port v0000000000bdab50, 384; +E_00000000006a3090/96 .event edge, v0000000000bdab50_381, v0000000000bdab50_382, v0000000000bdab50_383, v0000000000bdab50_384; +v0000000000bdab50_385 .array/port v0000000000bdab50, 385; +v0000000000bdab50_386 .array/port v0000000000bdab50, 386; +v0000000000bdab50_387 .array/port v0000000000bdab50, 387; +v0000000000bdab50_388 .array/port v0000000000bdab50, 388; +E_00000000006a3090/97 .event edge, v0000000000bdab50_385, v0000000000bdab50_386, v0000000000bdab50_387, v0000000000bdab50_388; +v0000000000bdab50_389 .array/port v0000000000bdab50, 389; +v0000000000bdab50_390 .array/port v0000000000bdab50, 390; +v0000000000bdab50_391 .array/port v0000000000bdab50, 391; +v0000000000bdab50_392 .array/port v0000000000bdab50, 392; +E_00000000006a3090/98 .event edge, v0000000000bdab50_389, v0000000000bdab50_390, v0000000000bdab50_391, v0000000000bdab50_392; +v0000000000bdab50_393 .array/port v0000000000bdab50, 393; +v0000000000bdab50_394 .array/port v0000000000bdab50, 394; +v0000000000bdab50_395 .array/port v0000000000bdab50, 395; +v0000000000bdab50_396 .array/port v0000000000bdab50, 396; +E_00000000006a3090/99 .event edge, v0000000000bdab50_393, v0000000000bdab50_394, v0000000000bdab50_395, v0000000000bdab50_396; +v0000000000bdab50_397 .array/port v0000000000bdab50, 397; +v0000000000bdab50_398 .array/port v0000000000bdab50, 398; +v0000000000bdab50_399 .array/port v0000000000bdab50, 399; +v0000000000bdab50_400 .array/port v0000000000bdab50, 400; +E_00000000006a3090/100 .event edge, v0000000000bdab50_397, v0000000000bdab50_398, v0000000000bdab50_399, v0000000000bdab50_400; +v0000000000bdab50_401 .array/port v0000000000bdab50, 401; +v0000000000bdab50_402 .array/port v0000000000bdab50, 402; +v0000000000bdab50_403 .array/port v0000000000bdab50, 403; +v0000000000bdab50_404 .array/port v0000000000bdab50, 404; +E_00000000006a3090/101 .event edge, v0000000000bdab50_401, v0000000000bdab50_402, v0000000000bdab50_403, v0000000000bdab50_404; +v0000000000bdab50_405 .array/port v0000000000bdab50, 405; +v0000000000bdab50_406 .array/port v0000000000bdab50, 406; +v0000000000bdab50_407 .array/port v0000000000bdab50, 407; +v0000000000bdab50_408 .array/port v0000000000bdab50, 408; +E_00000000006a3090/102 .event edge, v0000000000bdab50_405, v0000000000bdab50_406, v0000000000bdab50_407, v0000000000bdab50_408; +v0000000000bdab50_409 .array/port v0000000000bdab50, 409; +v0000000000bdab50_410 .array/port v0000000000bdab50, 410; +v0000000000bdab50_411 .array/port v0000000000bdab50, 411; +v0000000000bdab50_412 .array/port v0000000000bdab50, 412; +E_00000000006a3090/103 .event edge, v0000000000bdab50_409, v0000000000bdab50_410, v0000000000bdab50_411, v0000000000bdab50_412; +v0000000000bdab50_413 .array/port v0000000000bdab50, 413; +v0000000000bdab50_414 .array/port v0000000000bdab50, 414; +v0000000000bdab50_415 .array/port v0000000000bdab50, 415; +v0000000000bdab50_416 .array/port v0000000000bdab50, 416; +E_00000000006a3090/104 .event edge, v0000000000bdab50_413, v0000000000bdab50_414, v0000000000bdab50_415, v0000000000bdab50_416; +v0000000000bdab50_417 .array/port v0000000000bdab50, 417; +v0000000000bdab50_418 .array/port v0000000000bdab50, 418; +v0000000000bdab50_419 .array/port v0000000000bdab50, 419; +v0000000000bdab50_420 .array/port v0000000000bdab50, 420; +E_00000000006a3090/105 .event edge, v0000000000bdab50_417, v0000000000bdab50_418, v0000000000bdab50_419, v0000000000bdab50_420; +v0000000000bdab50_421 .array/port v0000000000bdab50, 421; +v0000000000bdab50_422 .array/port v0000000000bdab50, 422; +v0000000000bdab50_423 .array/port v0000000000bdab50, 423; +v0000000000bdab50_424 .array/port v0000000000bdab50, 424; +E_00000000006a3090/106 .event edge, v0000000000bdab50_421, v0000000000bdab50_422, v0000000000bdab50_423, v0000000000bdab50_424; +v0000000000bdab50_425 .array/port v0000000000bdab50, 425; +v0000000000bdab50_426 .array/port v0000000000bdab50, 426; +v0000000000bdab50_427 .array/port v0000000000bdab50, 427; +v0000000000bdab50_428 .array/port v0000000000bdab50, 428; +E_00000000006a3090/107 .event edge, v0000000000bdab50_425, v0000000000bdab50_426, v0000000000bdab50_427, v0000000000bdab50_428; +v0000000000bdab50_429 .array/port v0000000000bdab50, 429; +v0000000000bdab50_430 .array/port v0000000000bdab50, 430; +v0000000000bdab50_431 .array/port v0000000000bdab50, 431; +v0000000000bdab50_432 .array/port v0000000000bdab50, 432; +E_00000000006a3090/108 .event edge, v0000000000bdab50_429, v0000000000bdab50_430, v0000000000bdab50_431, v0000000000bdab50_432; +v0000000000bdab50_433 .array/port v0000000000bdab50, 433; +v0000000000bdab50_434 .array/port v0000000000bdab50, 434; +v0000000000bdab50_435 .array/port v0000000000bdab50, 435; +v0000000000bdab50_436 .array/port v0000000000bdab50, 436; +E_00000000006a3090/109 .event edge, v0000000000bdab50_433, v0000000000bdab50_434, v0000000000bdab50_435, v0000000000bdab50_436; +v0000000000bdab50_437 .array/port v0000000000bdab50, 437; +v0000000000bdab50_438 .array/port v0000000000bdab50, 438; +v0000000000bdab50_439 .array/port v0000000000bdab50, 439; +v0000000000bdab50_440 .array/port v0000000000bdab50, 440; +E_00000000006a3090/110 .event edge, v0000000000bdab50_437, v0000000000bdab50_438, v0000000000bdab50_439, v0000000000bdab50_440; +v0000000000bdab50_441 .array/port v0000000000bdab50, 441; +v0000000000bdab50_442 .array/port v0000000000bdab50, 442; +v0000000000bdab50_443 .array/port v0000000000bdab50, 443; +v0000000000bdab50_444 .array/port v0000000000bdab50, 444; +E_00000000006a3090/111 .event edge, v0000000000bdab50_441, v0000000000bdab50_442, v0000000000bdab50_443, v0000000000bdab50_444; +v0000000000bdab50_445 .array/port v0000000000bdab50, 445; +v0000000000bdab50_446 .array/port v0000000000bdab50, 446; +v0000000000bdab50_447 .array/port v0000000000bdab50, 447; +v0000000000bdab50_448 .array/port v0000000000bdab50, 448; +E_00000000006a3090/112 .event edge, v0000000000bdab50_445, v0000000000bdab50_446, v0000000000bdab50_447, v0000000000bdab50_448; +v0000000000bdab50_449 .array/port v0000000000bdab50, 449; +v0000000000bdab50_450 .array/port v0000000000bdab50, 450; +v0000000000bdab50_451 .array/port v0000000000bdab50, 451; +v0000000000bdab50_452 .array/port v0000000000bdab50, 452; +E_00000000006a3090/113 .event edge, v0000000000bdab50_449, v0000000000bdab50_450, v0000000000bdab50_451, v0000000000bdab50_452; +v0000000000bdab50_453 .array/port v0000000000bdab50, 453; +v0000000000bdab50_454 .array/port v0000000000bdab50, 454; +v0000000000bdab50_455 .array/port v0000000000bdab50, 455; +v0000000000bdab50_456 .array/port v0000000000bdab50, 456; +E_00000000006a3090/114 .event edge, v0000000000bdab50_453, v0000000000bdab50_454, v0000000000bdab50_455, v0000000000bdab50_456; +v0000000000bdab50_457 .array/port v0000000000bdab50, 457; +v0000000000bdab50_458 .array/port v0000000000bdab50, 458; +v0000000000bdab50_459 .array/port v0000000000bdab50, 459; +v0000000000bdab50_460 .array/port v0000000000bdab50, 460; +E_00000000006a3090/115 .event edge, v0000000000bdab50_457, v0000000000bdab50_458, v0000000000bdab50_459, v0000000000bdab50_460; +v0000000000bdab50_461 .array/port v0000000000bdab50, 461; +v0000000000bdab50_462 .array/port v0000000000bdab50, 462; +v0000000000bdab50_463 .array/port v0000000000bdab50, 463; +v0000000000bdab50_464 .array/port v0000000000bdab50, 464; +E_00000000006a3090/116 .event edge, v0000000000bdab50_461, v0000000000bdab50_462, v0000000000bdab50_463, v0000000000bdab50_464; +v0000000000bdab50_465 .array/port v0000000000bdab50, 465; +v0000000000bdab50_466 .array/port v0000000000bdab50, 466; +v0000000000bdab50_467 .array/port v0000000000bdab50, 467; +v0000000000bdab50_468 .array/port v0000000000bdab50, 468; +E_00000000006a3090/117 .event edge, v0000000000bdab50_465, v0000000000bdab50_466, v0000000000bdab50_467, v0000000000bdab50_468; +v0000000000bdab50_469 .array/port v0000000000bdab50, 469; +v0000000000bdab50_470 .array/port v0000000000bdab50, 470; +v0000000000bdab50_471 .array/port v0000000000bdab50, 471; +v0000000000bdab50_472 .array/port v0000000000bdab50, 472; +E_00000000006a3090/118 .event edge, v0000000000bdab50_469, v0000000000bdab50_470, v0000000000bdab50_471, v0000000000bdab50_472; +v0000000000bdab50_473 .array/port v0000000000bdab50, 473; +v0000000000bdab50_474 .array/port v0000000000bdab50, 474; +v0000000000bdab50_475 .array/port v0000000000bdab50, 475; +v0000000000bdab50_476 .array/port v0000000000bdab50, 476; +E_00000000006a3090/119 .event edge, v0000000000bdab50_473, v0000000000bdab50_474, v0000000000bdab50_475, v0000000000bdab50_476; +v0000000000bdab50_477 .array/port v0000000000bdab50, 477; +v0000000000bdab50_478 .array/port v0000000000bdab50, 478; +v0000000000bdab50_479 .array/port v0000000000bdab50, 479; +v0000000000bdab50_480 .array/port v0000000000bdab50, 480; +E_00000000006a3090/120 .event edge, v0000000000bdab50_477, v0000000000bdab50_478, v0000000000bdab50_479, v0000000000bdab50_480; +v0000000000bdab50_481 .array/port v0000000000bdab50, 481; +v0000000000bdab50_482 .array/port v0000000000bdab50, 482; +v0000000000bdab50_483 .array/port v0000000000bdab50, 483; +v0000000000bdab50_484 .array/port v0000000000bdab50, 484; +E_00000000006a3090/121 .event edge, v0000000000bdab50_481, v0000000000bdab50_482, v0000000000bdab50_483, v0000000000bdab50_484; +v0000000000bdab50_485 .array/port v0000000000bdab50, 485; +v0000000000bdab50_486 .array/port v0000000000bdab50, 486; +v0000000000bdab50_487 .array/port v0000000000bdab50, 487; +v0000000000bdab50_488 .array/port v0000000000bdab50, 488; +E_00000000006a3090/122 .event edge, v0000000000bdab50_485, v0000000000bdab50_486, v0000000000bdab50_487, v0000000000bdab50_488; +v0000000000bdab50_489 .array/port v0000000000bdab50, 489; +v0000000000bdab50_490 .array/port v0000000000bdab50, 490; +v0000000000bdab50_491 .array/port v0000000000bdab50, 491; +v0000000000bdab50_492 .array/port v0000000000bdab50, 492; +E_00000000006a3090/123 .event edge, v0000000000bdab50_489, v0000000000bdab50_490, v0000000000bdab50_491, v0000000000bdab50_492; +v0000000000bdab50_493 .array/port v0000000000bdab50, 493; +v0000000000bdab50_494 .array/port v0000000000bdab50, 494; +v0000000000bdab50_495 .array/port v0000000000bdab50, 495; +v0000000000bdab50_496 .array/port v0000000000bdab50, 496; +E_00000000006a3090/124 .event edge, v0000000000bdab50_493, v0000000000bdab50_494, v0000000000bdab50_495, v0000000000bdab50_496; +v0000000000bdab50_497 .array/port v0000000000bdab50, 497; +v0000000000bdab50_498 .array/port v0000000000bdab50, 498; +v0000000000bdab50_499 .array/port v0000000000bdab50, 499; +v0000000000bdab50_500 .array/port v0000000000bdab50, 500; +E_00000000006a3090/125 .event edge, v0000000000bdab50_497, v0000000000bdab50_498, v0000000000bdab50_499, v0000000000bdab50_500; +v0000000000bdab50_501 .array/port v0000000000bdab50, 501; +v0000000000bdab50_502 .array/port v0000000000bdab50, 502; +v0000000000bdab50_503 .array/port v0000000000bdab50, 503; +v0000000000bdab50_504 .array/port v0000000000bdab50, 504; +E_00000000006a3090/126 .event edge, v0000000000bdab50_501, v0000000000bdab50_502, v0000000000bdab50_503, v0000000000bdab50_504; +v0000000000bdab50_505 .array/port v0000000000bdab50, 505; +v0000000000bdab50_506 .array/port v0000000000bdab50, 506; +v0000000000bdab50_507 .array/port v0000000000bdab50, 507; +v0000000000bdab50_508 .array/port v0000000000bdab50, 508; +E_00000000006a3090/127 .event edge, v0000000000bdab50_505, v0000000000bdab50_506, v0000000000bdab50_507, v0000000000bdab50_508; +v0000000000bdab50_509 .array/port v0000000000bdab50, 509; +v0000000000bdab50_510 .array/port v0000000000bdab50, 510; +v0000000000bdab50_511 .array/port v0000000000bdab50, 511; +v0000000000bdab50_512 .array/port v0000000000bdab50, 512; +E_00000000006a3090/128 .event edge, v0000000000bdab50_509, v0000000000bdab50_510, v0000000000bdab50_511, v0000000000bdab50_512; +v0000000000bdab50_513 .array/port v0000000000bdab50, 513; +v0000000000bdab50_514 .array/port v0000000000bdab50, 514; +v0000000000bdab50_515 .array/port v0000000000bdab50, 515; +v0000000000bdab50_516 .array/port v0000000000bdab50, 516; +E_00000000006a3090/129 .event edge, v0000000000bdab50_513, v0000000000bdab50_514, v0000000000bdab50_515, v0000000000bdab50_516; +v0000000000bdab50_517 .array/port v0000000000bdab50, 517; +v0000000000bdab50_518 .array/port v0000000000bdab50, 518; +v0000000000bdab50_519 .array/port v0000000000bdab50, 519; +v0000000000bdab50_520 .array/port v0000000000bdab50, 520; +E_00000000006a3090/130 .event edge, v0000000000bdab50_517, v0000000000bdab50_518, v0000000000bdab50_519, v0000000000bdab50_520; +v0000000000bdab50_521 .array/port v0000000000bdab50, 521; +v0000000000bdab50_522 .array/port v0000000000bdab50, 522; +v0000000000bdab50_523 .array/port v0000000000bdab50, 523; +v0000000000bdab50_524 .array/port v0000000000bdab50, 524; +E_00000000006a3090/131 .event edge, v0000000000bdab50_521, v0000000000bdab50_522, v0000000000bdab50_523, v0000000000bdab50_524; +v0000000000bdab50_525 .array/port v0000000000bdab50, 525; +v0000000000bdab50_526 .array/port v0000000000bdab50, 526; +v0000000000bdab50_527 .array/port v0000000000bdab50, 527; +v0000000000bdab50_528 .array/port v0000000000bdab50, 528; +E_00000000006a3090/132 .event edge, v0000000000bdab50_525, v0000000000bdab50_526, v0000000000bdab50_527, v0000000000bdab50_528; +v0000000000bdab50_529 .array/port v0000000000bdab50, 529; +v0000000000bdab50_530 .array/port v0000000000bdab50, 530; +v0000000000bdab50_531 .array/port v0000000000bdab50, 531; +v0000000000bdab50_532 .array/port v0000000000bdab50, 532; +E_00000000006a3090/133 .event edge, v0000000000bdab50_529, v0000000000bdab50_530, v0000000000bdab50_531, v0000000000bdab50_532; +v0000000000bdab50_533 .array/port v0000000000bdab50, 533; +v0000000000bdab50_534 .array/port v0000000000bdab50, 534; +v0000000000bdab50_535 .array/port v0000000000bdab50, 535; +v0000000000bdab50_536 .array/port v0000000000bdab50, 536; +E_00000000006a3090/134 .event edge, v0000000000bdab50_533, v0000000000bdab50_534, v0000000000bdab50_535, v0000000000bdab50_536; +v0000000000bdab50_537 .array/port v0000000000bdab50, 537; +v0000000000bdab50_538 .array/port v0000000000bdab50, 538; +v0000000000bdab50_539 .array/port v0000000000bdab50, 539; +v0000000000bdab50_540 .array/port v0000000000bdab50, 540; +E_00000000006a3090/135 .event edge, v0000000000bdab50_537, v0000000000bdab50_538, v0000000000bdab50_539, v0000000000bdab50_540; +v0000000000bdab50_541 .array/port v0000000000bdab50, 541; +v0000000000bdab50_542 .array/port v0000000000bdab50, 542; +v0000000000bdab50_543 .array/port v0000000000bdab50, 543; +v0000000000bdab50_544 .array/port v0000000000bdab50, 544; +E_00000000006a3090/136 .event edge, v0000000000bdab50_541, v0000000000bdab50_542, v0000000000bdab50_543, v0000000000bdab50_544; +v0000000000bdab50_545 .array/port v0000000000bdab50, 545; +v0000000000bdab50_546 .array/port v0000000000bdab50, 546; +v0000000000bdab50_547 .array/port v0000000000bdab50, 547; +v0000000000bdab50_548 .array/port v0000000000bdab50, 548; +E_00000000006a3090/137 .event edge, v0000000000bdab50_545, v0000000000bdab50_546, v0000000000bdab50_547, v0000000000bdab50_548; +v0000000000bdab50_549 .array/port v0000000000bdab50, 549; +v0000000000bdab50_550 .array/port v0000000000bdab50, 550; +v0000000000bdab50_551 .array/port v0000000000bdab50, 551; +v0000000000bdab50_552 .array/port v0000000000bdab50, 552; +E_00000000006a3090/138 .event edge, v0000000000bdab50_549, v0000000000bdab50_550, v0000000000bdab50_551, v0000000000bdab50_552; +v0000000000bdab50_553 .array/port v0000000000bdab50, 553; +v0000000000bdab50_554 .array/port v0000000000bdab50, 554; +v0000000000bdab50_555 .array/port v0000000000bdab50, 555; +v0000000000bdab50_556 .array/port v0000000000bdab50, 556; +E_00000000006a3090/139 .event edge, v0000000000bdab50_553, v0000000000bdab50_554, v0000000000bdab50_555, v0000000000bdab50_556; +v0000000000bdab50_557 .array/port v0000000000bdab50, 557; +v0000000000bdab50_558 .array/port v0000000000bdab50, 558; +v0000000000bdab50_559 .array/port v0000000000bdab50, 559; +v0000000000bdab50_560 .array/port v0000000000bdab50, 560; +E_00000000006a3090/140 .event edge, v0000000000bdab50_557, v0000000000bdab50_558, v0000000000bdab50_559, v0000000000bdab50_560; +v0000000000bdab50_561 .array/port v0000000000bdab50, 561; +v0000000000bdab50_562 .array/port v0000000000bdab50, 562; +v0000000000bdab50_563 .array/port v0000000000bdab50, 563; +v0000000000bdab50_564 .array/port v0000000000bdab50, 564; +E_00000000006a3090/141 .event edge, v0000000000bdab50_561, v0000000000bdab50_562, v0000000000bdab50_563, v0000000000bdab50_564; +v0000000000bdab50_565 .array/port v0000000000bdab50, 565; +v0000000000bdab50_566 .array/port v0000000000bdab50, 566; +v0000000000bdab50_567 .array/port v0000000000bdab50, 567; +v0000000000bdab50_568 .array/port v0000000000bdab50, 568; +E_00000000006a3090/142 .event edge, v0000000000bdab50_565, v0000000000bdab50_566, v0000000000bdab50_567, v0000000000bdab50_568; +v0000000000bdab50_569 .array/port v0000000000bdab50, 569; +v0000000000bdab50_570 .array/port v0000000000bdab50, 570; +v0000000000bdab50_571 .array/port v0000000000bdab50, 571; +v0000000000bdab50_572 .array/port v0000000000bdab50, 572; +E_00000000006a3090/143 .event edge, v0000000000bdab50_569, v0000000000bdab50_570, v0000000000bdab50_571, v0000000000bdab50_572; +v0000000000bdab50_573 .array/port v0000000000bdab50, 573; +v0000000000bdab50_574 .array/port v0000000000bdab50, 574; +v0000000000bdab50_575 .array/port v0000000000bdab50, 575; +v0000000000bdab50_576 .array/port v0000000000bdab50, 576; +E_00000000006a3090/144 .event edge, v0000000000bdab50_573, v0000000000bdab50_574, v0000000000bdab50_575, v0000000000bdab50_576; +v0000000000bdab50_577 .array/port v0000000000bdab50, 577; +v0000000000bdab50_578 .array/port v0000000000bdab50, 578; +v0000000000bdab50_579 .array/port v0000000000bdab50, 579; +v0000000000bdab50_580 .array/port v0000000000bdab50, 580; +E_00000000006a3090/145 .event edge, v0000000000bdab50_577, v0000000000bdab50_578, v0000000000bdab50_579, v0000000000bdab50_580; +v0000000000bdab50_581 .array/port v0000000000bdab50, 581; +v0000000000bdab50_582 .array/port v0000000000bdab50, 582; +v0000000000bdab50_583 .array/port v0000000000bdab50, 583; +v0000000000bdab50_584 .array/port v0000000000bdab50, 584; +E_00000000006a3090/146 .event edge, v0000000000bdab50_581, v0000000000bdab50_582, v0000000000bdab50_583, v0000000000bdab50_584; +v0000000000bdab50_585 .array/port v0000000000bdab50, 585; +v0000000000bdab50_586 .array/port v0000000000bdab50, 586; +v0000000000bdab50_587 .array/port v0000000000bdab50, 587; +v0000000000bdab50_588 .array/port v0000000000bdab50, 588; +E_00000000006a3090/147 .event edge, v0000000000bdab50_585, v0000000000bdab50_586, v0000000000bdab50_587, v0000000000bdab50_588; +v0000000000bdab50_589 .array/port v0000000000bdab50, 589; +v0000000000bdab50_590 .array/port v0000000000bdab50, 590; +v0000000000bdab50_591 .array/port v0000000000bdab50, 591; +v0000000000bdab50_592 .array/port v0000000000bdab50, 592; +E_00000000006a3090/148 .event edge, v0000000000bdab50_589, v0000000000bdab50_590, v0000000000bdab50_591, v0000000000bdab50_592; +v0000000000bdab50_593 .array/port v0000000000bdab50, 593; +v0000000000bdab50_594 .array/port v0000000000bdab50, 594; +v0000000000bdab50_595 .array/port v0000000000bdab50, 595; +v0000000000bdab50_596 .array/port v0000000000bdab50, 596; +E_00000000006a3090/149 .event edge, v0000000000bdab50_593, v0000000000bdab50_594, v0000000000bdab50_595, v0000000000bdab50_596; +v0000000000bdab50_597 .array/port v0000000000bdab50, 597; +v0000000000bdab50_598 .array/port v0000000000bdab50, 598; +v0000000000bdab50_599 .array/port v0000000000bdab50, 599; +v0000000000bdab50_600 .array/port v0000000000bdab50, 600; +E_00000000006a3090/150 .event edge, v0000000000bdab50_597, v0000000000bdab50_598, v0000000000bdab50_599, v0000000000bdab50_600; +v0000000000bdab50_601 .array/port v0000000000bdab50, 601; +v0000000000bdab50_602 .array/port v0000000000bdab50, 602; +v0000000000bdab50_603 .array/port v0000000000bdab50, 603; +v0000000000bdab50_604 .array/port v0000000000bdab50, 604; +E_00000000006a3090/151 .event edge, v0000000000bdab50_601, v0000000000bdab50_602, v0000000000bdab50_603, v0000000000bdab50_604; +v0000000000bdab50_605 .array/port v0000000000bdab50, 605; +v0000000000bdab50_606 .array/port v0000000000bdab50, 606; +v0000000000bdab50_607 .array/port v0000000000bdab50, 607; +v0000000000bdab50_608 .array/port v0000000000bdab50, 608; +E_00000000006a3090/152 .event edge, v0000000000bdab50_605, v0000000000bdab50_606, v0000000000bdab50_607, v0000000000bdab50_608; +v0000000000bdab50_609 .array/port v0000000000bdab50, 609; +v0000000000bdab50_610 .array/port v0000000000bdab50, 610; +v0000000000bdab50_611 .array/port v0000000000bdab50, 611; +v0000000000bdab50_612 .array/port v0000000000bdab50, 612; +E_00000000006a3090/153 .event edge, v0000000000bdab50_609, v0000000000bdab50_610, v0000000000bdab50_611, v0000000000bdab50_612; +v0000000000bdab50_613 .array/port v0000000000bdab50, 613; +v0000000000bdab50_614 .array/port v0000000000bdab50, 614; +v0000000000bdab50_615 .array/port v0000000000bdab50, 615; +v0000000000bdab50_616 .array/port v0000000000bdab50, 616; +E_00000000006a3090/154 .event edge, v0000000000bdab50_613, v0000000000bdab50_614, v0000000000bdab50_615, v0000000000bdab50_616; +v0000000000bdab50_617 .array/port v0000000000bdab50, 617; +v0000000000bdab50_618 .array/port v0000000000bdab50, 618; +v0000000000bdab50_619 .array/port v0000000000bdab50, 619; +v0000000000bdab50_620 .array/port v0000000000bdab50, 620; +E_00000000006a3090/155 .event edge, v0000000000bdab50_617, v0000000000bdab50_618, v0000000000bdab50_619, v0000000000bdab50_620; +v0000000000bdab50_621 .array/port v0000000000bdab50, 621; +v0000000000bdab50_622 .array/port v0000000000bdab50, 622; +v0000000000bdab50_623 .array/port v0000000000bdab50, 623; +v0000000000bdab50_624 .array/port v0000000000bdab50, 624; +E_00000000006a3090/156 .event edge, v0000000000bdab50_621, v0000000000bdab50_622, v0000000000bdab50_623, v0000000000bdab50_624; +v0000000000bdab50_625 .array/port v0000000000bdab50, 625; +v0000000000bdab50_626 .array/port v0000000000bdab50, 626; +v0000000000bdab50_627 .array/port v0000000000bdab50, 627; +v0000000000bdab50_628 .array/port v0000000000bdab50, 628; +E_00000000006a3090/157 .event edge, v0000000000bdab50_625, v0000000000bdab50_626, v0000000000bdab50_627, v0000000000bdab50_628; +v0000000000bdab50_629 .array/port v0000000000bdab50, 629; +v0000000000bdab50_630 .array/port v0000000000bdab50, 630; +v0000000000bdab50_631 .array/port v0000000000bdab50, 631; +v0000000000bdab50_632 .array/port v0000000000bdab50, 632; +E_00000000006a3090/158 .event edge, v0000000000bdab50_629, v0000000000bdab50_630, v0000000000bdab50_631, v0000000000bdab50_632; +v0000000000bdab50_633 .array/port v0000000000bdab50, 633; +v0000000000bdab50_634 .array/port v0000000000bdab50, 634; +v0000000000bdab50_635 .array/port v0000000000bdab50, 635; +v0000000000bdab50_636 .array/port v0000000000bdab50, 636; +E_00000000006a3090/159 .event edge, v0000000000bdab50_633, v0000000000bdab50_634, v0000000000bdab50_635, v0000000000bdab50_636; +v0000000000bdab50_637 .array/port v0000000000bdab50, 637; +v0000000000bdab50_638 .array/port v0000000000bdab50, 638; +v0000000000bdab50_639 .array/port v0000000000bdab50, 639; +v0000000000bdab50_640 .array/port v0000000000bdab50, 640; +E_00000000006a3090/160 .event edge, v0000000000bdab50_637, v0000000000bdab50_638, v0000000000bdab50_639, v0000000000bdab50_640; +v0000000000bdab50_641 .array/port v0000000000bdab50, 641; +v0000000000bdab50_642 .array/port v0000000000bdab50, 642; +v0000000000bdab50_643 .array/port v0000000000bdab50, 643; +v0000000000bdab50_644 .array/port v0000000000bdab50, 644; +E_00000000006a3090/161 .event edge, v0000000000bdab50_641, v0000000000bdab50_642, v0000000000bdab50_643, v0000000000bdab50_644; +v0000000000bdab50_645 .array/port v0000000000bdab50, 645; +v0000000000bdab50_646 .array/port v0000000000bdab50, 646; +v0000000000bdab50_647 .array/port v0000000000bdab50, 647; +v0000000000bdab50_648 .array/port v0000000000bdab50, 648; +E_00000000006a3090/162 .event edge, v0000000000bdab50_645, v0000000000bdab50_646, v0000000000bdab50_647, v0000000000bdab50_648; +v0000000000bdab50_649 .array/port v0000000000bdab50, 649; +v0000000000bdab50_650 .array/port v0000000000bdab50, 650; +v0000000000bdab50_651 .array/port v0000000000bdab50, 651; +v0000000000bdab50_652 .array/port v0000000000bdab50, 652; +E_00000000006a3090/163 .event edge, v0000000000bdab50_649, v0000000000bdab50_650, v0000000000bdab50_651, v0000000000bdab50_652; +v0000000000bdab50_653 .array/port v0000000000bdab50, 653; +v0000000000bdab50_654 .array/port v0000000000bdab50, 654; +v0000000000bdab50_655 .array/port v0000000000bdab50, 655; +v0000000000bdab50_656 .array/port v0000000000bdab50, 656; +E_00000000006a3090/164 .event edge, v0000000000bdab50_653, v0000000000bdab50_654, v0000000000bdab50_655, v0000000000bdab50_656; +v0000000000bdab50_657 .array/port v0000000000bdab50, 657; +v0000000000bdab50_658 .array/port v0000000000bdab50, 658; +v0000000000bdab50_659 .array/port v0000000000bdab50, 659; +v0000000000bdab50_660 .array/port v0000000000bdab50, 660; +E_00000000006a3090/165 .event edge, v0000000000bdab50_657, v0000000000bdab50_658, v0000000000bdab50_659, v0000000000bdab50_660; +v0000000000bdab50_661 .array/port v0000000000bdab50, 661; +v0000000000bdab50_662 .array/port v0000000000bdab50, 662; +v0000000000bdab50_663 .array/port v0000000000bdab50, 663; +v0000000000bdab50_664 .array/port v0000000000bdab50, 664; +E_00000000006a3090/166 .event edge, v0000000000bdab50_661, v0000000000bdab50_662, v0000000000bdab50_663, v0000000000bdab50_664; +v0000000000bdab50_665 .array/port v0000000000bdab50, 665; +v0000000000bdab50_666 .array/port v0000000000bdab50, 666; +v0000000000bdab50_667 .array/port v0000000000bdab50, 667; +v0000000000bdab50_668 .array/port v0000000000bdab50, 668; +E_00000000006a3090/167 .event edge, v0000000000bdab50_665, v0000000000bdab50_666, v0000000000bdab50_667, v0000000000bdab50_668; +v0000000000bdab50_669 .array/port v0000000000bdab50, 669; +v0000000000bdab50_670 .array/port v0000000000bdab50, 670; +v0000000000bdab50_671 .array/port v0000000000bdab50, 671; +v0000000000bdab50_672 .array/port v0000000000bdab50, 672; +E_00000000006a3090/168 .event edge, v0000000000bdab50_669, v0000000000bdab50_670, v0000000000bdab50_671, v0000000000bdab50_672; +v0000000000bdab50_673 .array/port v0000000000bdab50, 673; +v0000000000bdab50_674 .array/port v0000000000bdab50, 674; +v0000000000bdab50_675 .array/port v0000000000bdab50, 675; +v0000000000bdab50_676 .array/port v0000000000bdab50, 676; +E_00000000006a3090/169 .event edge, v0000000000bdab50_673, v0000000000bdab50_674, v0000000000bdab50_675, v0000000000bdab50_676; +v0000000000bdab50_677 .array/port v0000000000bdab50, 677; +v0000000000bdab50_678 .array/port v0000000000bdab50, 678; +v0000000000bdab50_679 .array/port v0000000000bdab50, 679; +v0000000000bdab50_680 .array/port v0000000000bdab50, 680; +E_00000000006a3090/170 .event edge, v0000000000bdab50_677, v0000000000bdab50_678, v0000000000bdab50_679, v0000000000bdab50_680; +v0000000000bdab50_681 .array/port v0000000000bdab50, 681; +v0000000000bdab50_682 .array/port v0000000000bdab50, 682; +v0000000000bdab50_683 .array/port v0000000000bdab50, 683; +v0000000000bdab50_684 .array/port v0000000000bdab50, 684; +E_00000000006a3090/171 .event edge, v0000000000bdab50_681, v0000000000bdab50_682, v0000000000bdab50_683, v0000000000bdab50_684; +v0000000000bdab50_685 .array/port v0000000000bdab50, 685; +v0000000000bdab50_686 .array/port v0000000000bdab50, 686; +v0000000000bdab50_687 .array/port v0000000000bdab50, 687; +v0000000000bdab50_688 .array/port v0000000000bdab50, 688; +E_00000000006a3090/172 .event edge, v0000000000bdab50_685, v0000000000bdab50_686, v0000000000bdab50_687, v0000000000bdab50_688; +v0000000000bdab50_689 .array/port v0000000000bdab50, 689; +v0000000000bdab50_690 .array/port v0000000000bdab50, 690; +v0000000000bdab50_691 .array/port v0000000000bdab50, 691; +v0000000000bdab50_692 .array/port v0000000000bdab50, 692; +E_00000000006a3090/173 .event edge, v0000000000bdab50_689, v0000000000bdab50_690, v0000000000bdab50_691, v0000000000bdab50_692; +v0000000000bdab50_693 .array/port v0000000000bdab50, 693; +v0000000000bdab50_694 .array/port v0000000000bdab50, 694; +v0000000000bdab50_695 .array/port v0000000000bdab50, 695; +v0000000000bdab50_696 .array/port v0000000000bdab50, 696; +E_00000000006a3090/174 .event edge, v0000000000bdab50_693, v0000000000bdab50_694, v0000000000bdab50_695, v0000000000bdab50_696; +v0000000000bdab50_697 .array/port v0000000000bdab50, 697; +v0000000000bdab50_698 .array/port v0000000000bdab50, 698; +v0000000000bdab50_699 .array/port v0000000000bdab50, 699; +v0000000000bdab50_700 .array/port v0000000000bdab50, 700; +E_00000000006a3090/175 .event edge, v0000000000bdab50_697, v0000000000bdab50_698, v0000000000bdab50_699, v0000000000bdab50_700; +v0000000000bdab50_701 .array/port v0000000000bdab50, 701; +v0000000000bdab50_702 .array/port v0000000000bdab50, 702; +v0000000000bdab50_703 .array/port v0000000000bdab50, 703; +v0000000000bdab50_704 .array/port v0000000000bdab50, 704; +E_00000000006a3090/176 .event edge, v0000000000bdab50_701, v0000000000bdab50_702, v0000000000bdab50_703, v0000000000bdab50_704; +v0000000000bdab50_705 .array/port v0000000000bdab50, 705; +v0000000000bdab50_706 .array/port v0000000000bdab50, 706; +v0000000000bdab50_707 .array/port v0000000000bdab50, 707; +v0000000000bdab50_708 .array/port v0000000000bdab50, 708; +E_00000000006a3090/177 .event edge, v0000000000bdab50_705, v0000000000bdab50_706, v0000000000bdab50_707, v0000000000bdab50_708; +v0000000000bdab50_709 .array/port v0000000000bdab50, 709; +v0000000000bdab50_710 .array/port v0000000000bdab50, 710; +v0000000000bdab50_711 .array/port v0000000000bdab50, 711; +v0000000000bdab50_712 .array/port v0000000000bdab50, 712; +E_00000000006a3090/178 .event edge, v0000000000bdab50_709, v0000000000bdab50_710, v0000000000bdab50_711, v0000000000bdab50_712; +v0000000000bdab50_713 .array/port v0000000000bdab50, 713; +v0000000000bdab50_714 .array/port v0000000000bdab50, 714; +v0000000000bdab50_715 .array/port v0000000000bdab50, 715; +v0000000000bdab50_716 .array/port v0000000000bdab50, 716; +E_00000000006a3090/179 .event edge, v0000000000bdab50_713, v0000000000bdab50_714, v0000000000bdab50_715, v0000000000bdab50_716; +v0000000000bdab50_717 .array/port v0000000000bdab50, 717; +v0000000000bdab50_718 .array/port v0000000000bdab50, 718; +v0000000000bdab50_719 .array/port v0000000000bdab50, 719; +v0000000000bdab50_720 .array/port v0000000000bdab50, 720; +E_00000000006a3090/180 .event edge, v0000000000bdab50_717, v0000000000bdab50_718, v0000000000bdab50_719, v0000000000bdab50_720; +v0000000000bdab50_721 .array/port v0000000000bdab50, 721; +v0000000000bdab50_722 .array/port v0000000000bdab50, 722; +v0000000000bdab50_723 .array/port v0000000000bdab50, 723; +v0000000000bdab50_724 .array/port v0000000000bdab50, 724; +E_00000000006a3090/181 .event edge, v0000000000bdab50_721, v0000000000bdab50_722, v0000000000bdab50_723, v0000000000bdab50_724; +v0000000000bdab50_725 .array/port v0000000000bdab50, 725; +v0000000000bdab50_726 .array/port v0000000000bdab50, 726; +v0000000000bdab50_727 .array/port v0000000000bdab50, 727; +v0000000000bdab50_728 .array/port v0000000000bdab50, 728; +E_00000000006a3090/182 .event edge, v0000000000bdab50_725, v0000000000bdab50_726, v0000000000bdab50_727, v0000000000bdab50_728; +v0000000000bdab50_729 .array/port v0000000000bdab50, 729; +v0000000000bdab50_730 .array/port v0000000000bdab50, 730; +v0000000000bdab50_731 .array/port v0000000000bdab50, 731; +v0000000000bdab50_732 .array/port v0000000000bdab50, 732; +E_00000000006a3090/183 .event edge, v0000000000bdab50_729, v0000000000bdab50_730, v0000000000bdab50_731, v0000000000bdab50_732; +v0000000000bdab50_733 .array/port v0000000000bdab50, 733; +v0000000000bdab50_734 .array/port v0000000000bdab50, 734; +v0000000000bdab50_735 .array/port v0000000000bdab50, 735; +v0000000000bdab50_736 .array/port v0000000000bdab50, 736; +E_00000000006a3090/184 .event edge, v0000000000bdab50_733, v0000000000bdab50_734, v0000000000bdab50_735, v0000000000bdab50_736; +v0000000000bdab50_737 .array/port v0000000000bdab50, 737; +v0000000000bdab50_738 .array/port v0000000000bdab50, 738; +v0000000000bdab50_739 .array/port v0000000000bdab50, 739; +v0000000000bdab50_740 .array/port v0000000000bdab50, 740; +E_00000000006a3090/185 .event edge, v0000000000bdab50_737, v0000000000bdab50_738, v0000000000bdab50_739, v0000000000bdab50_740; +v0000000000bdab50_741 .array/port v0000000000bdab50, 741; +v0000000000bdab50_742 .array/port v0000000000bdab50, 742; +v0000000000bdab50_743 .array/port v0000000000bdab50, 743; +v0000000000bdab50_744 .array/port v0000000000bdab50, 744; +E_00000000006a3090/186 .event edge, v0000000000bdab50_741, v0000000000bdab50_742, v0000000000bdab50_743, v0000000000bdab50_744; +v0000000000bdab50_745 .array/port v0000000000bdab50, 745; +v0000000000bdab50_746 .array/port v0000000000bdab50, 746; +v0000000000bdab50_747 .array/port v0000000000bdab50, 747; +v0000000000bdab50_748 .array/port v0000000000bdab50, 748; +E_00000000006a3090/187 .event edge, v0000000000bdab50_745, v0000000000bdab50_746, v0000000000bdab50_747, v0000000000bdab50_748; +v0000000000bdab50_749 .array/port v0000000000bdab50, 749; +v0000000000bdab50_750 .array/port v0000000000bdab50, 750; +v0000000000bdab50_751 .array/port v0000000000bdab50, 751; +v0000000000bdab50_752 .array/port v0000000000bdab50, 752; +E_00000000006a3090/188 .event edge, v0000000000bdab50_749, v0000000000bdab50_750, v0000000000bdab50_751, v0000000000bdab50_752; +v0000000000bdab50_753 .array/port v0000000000bdab50, 753; +v0000000000bdab50_754 .array/port v0000000000bdab50, 754; +v0000000000bdab50_755 .array/port v0000000000bdab50, 755; +v0000000000bdab50_756 .array/port v0000000000bdab50, 756; +E_00000000006a3090/189 .event edge, v0000000000bdab50_753, v0000000000bdab50_754, v0000000000bdab50_755, v0000000000bdab50_756; +v0000000000bdab50_757 .array/port v0000000000bdab50, 757; +v0000000000bdab50_758 .array/port v0000000000bdab50, 758; +v0000000000bdab50_759 .array/port v0000000000bdab50, 759; +v0000000000bdab50_760 .array/port v0000000000bdab50, 760; +E_00000000006a3090/190 .event edge, v0000000000bdab50_757, v0000000000bdab50_758, v0000000000bdab50_759, v0000000000bdab50_760; +v0000000000bdab50_761 .array/port v0000000000bdab50, 761; +v0000000000bdab50_762 .array/port v0000000000bdab50, 762; +v0000000000bdab50_763 .array/port v0000000000bdab50, 763; +v0000000000bdab50_764 .array/port v0000000000bdab50, 764; +E_00000000006a3090/191 .event edge, v0000000000bdab50_761, v0000000000bdab50_762, v0000000000bdab50_763, v0000000000bdab50_764; +v0000000000bdab50_765 .array/port v0000000000bdab50, 765; +v0000000000bdab50_766 .array/port v0000000000bdab50, 766; +v0000000000bdab50_767 .array/port v0000000000bdab50, 767; +v0000000000bdab50_768 .array/port v0000000000bdab50, 768; +E_00000000006a3090/192 .event edge, v0000000000bdab50_765, v0000000000bdab50_766, v0000000000bdab50_767, v0000000000bdab50_768; +v0000000000bdab50_769 .array/port v0000000000bdab50, 769; +v0000000000bdab50_770 .array/port v0000000000bdab50, 770; +v0000000000bdab50_771 .array/port v0000000000bdab50, 771; +v0000000000bdab50_772 .array/port v0000000000bdab50, 772; +E_00000000006a3090/193 .event edge, v0000000000bdab50_769, v0000000000bdab50_770, v0000000000bdab50_771, v0000000000bdab50_772; +v0000000000bdab50_773 .array/port v0000000000bdab50, 773; +v0000000000bdab50_774 .array/port v0000000000bdab50, 774; +v0000000000bdab50_775 .array/port v0000000000bdab50, 775; +v0000000000bdab50_776 .array/port v0000000000bdab50, 776; +E_00000000006a3090/194 .event edge, v0000000000bdab50_773, v0000000000bdab50_774, v0000000000bdab50_775, v0000000000bdab50_776; +v0000000000bdab50_777 .array/port v0000000000bdab50, 777; +v0000000000bdab50_778 .array/port v0000000000bdab50, 778; +v0000000000bdab50_779 .array/port v0000000000bdab50, 779; +v0000000000bdab50_780 .array/port v0000000000bdab50, 780; +E_00000000006a3090/195 .event edge, v0000000000bdab50_777, v0000000000bdab50_778, v0000000000bdab50_779, v0000000000bdab50_780; +v0000000000bdab50_781 .array/port v0000000000bdab50, 781; +v0000000000bdab50_782 .array/port v0000000000bdab50, 782; +v0000000000bdab50_783 .array/port v0000000000bdab50, 783; +v0000000000bdab50_784 .array/port v0000000000bdab50, 784; +E_00000000006a3090/196 .event edge, v0000000000bdab50_781, v0000000000bdab50_782, v0000000000bdab50_783, v0000000000bdab50_784; +v0000000000bdab50_785 .array/port v0000000000bdab50, 785; +v0000000000bdab50_786 .array/port v0000000000bdab50, 786; +v0000000000bdab50_787 .array/port v0000000000bdab50, 787; +v0000000000bdab50_788 .array/port v0000000000bdab50, 788; +E_00000000006a3090/197 .event edge, v0000000000bdab50_785, v0000000000bdab50_786, v0000000000bdab50_787, v0000000000bdab50_788; +v0000000000bdab50_789 .array/port v0000000000bdab50, 789; +v0000000000bdab50_790 .array/port v0000000000bdab50, 790; +v0000000000bdab50_791 .array/port v0000000000bdab50, 791; +v0000000000bdab50_792 .array/port v0000000000bdab50, 792; +E_00000000006a3090/198 .event edge, v0000000000bdab50_789, v0000000000bdab50_790, v0000000000bdab50_791, v0000000000bdab50_792; +v0000000000bdab50_793 .array/port v0000000000bdab50, 793; +v0000000000bdab50_794 .array/port v0000000000bdab50, 794; +v0000000000bdab50_795 .array/port v0000000000bdab50, 795; +v0000000000bdab50_796 .array/port v0000000000bdab50, 796; +E_00000000006a3090/199 .event edge, v0000000000bdab50_793, v0000000000bdab50_794, v0000000000bdab50_795, v0000000000bdab50_796; +v0000000000bdab50_797 .array/port v0000000000bdab50, 797; +v0000000000bdab50_798 .array/port v0000000000bdab50, 798; +v0000000000bdab50_799 .array/port v0000000000bdab50, 799; +v0000000000bdab50_800 .array/port v0000000000bdab50, 800; +E_00000000006a3090/200 .event edge, v0000000000bdab50_797, v0000000000bdab50_798, v0000000000bdab50_799, v0000000000bdab50_800; +v0000000000bdab50_801 .array/port v0000000000bdab50, 801; +v0000000000bdab50_802 .array/port v0000000000bdab50, 802; +v0000000000bdab50_803 .array/port v0000000000bdab50, 803; +v0000000000bdab50_804 .array/port v0000000000bdab50, 804; +E_00000000006a3090/201 .event edge, v0000000000bdab50_801, v0000000000bdab50_802, v0000000000bdab50_803, v0000000000bdab50_804; +v0000000000bdab50_805 .array/port v0000000000bdab50, 805; +v0000000000bdab50_806 .array/port v0000000000bdab50, 806; +v0000000000bdab50_807 .array/port v0000000000bdab50, 807; +v0000000000bdab50_808 .array/port v0000000000bdab50, 808; +E_00000000006a3090/202 .event edge, v0000000000bdab50_805, v0000000000bdab50_806, v0000000000bdab50_807, v0000000000bdab50_808; +v0000000000bdab50_809 .array/port v0000000000bdab50, 809; +v0000000000bdab50_810 .array/port v0000000000bdab50, 810; +v0000000000bdab50_811 .array/port v0000000000bdab50, 811; +v0000000000bdab50_812 .array/port v0000000000bdab50, 812; +E_00000000006a3090/203 .event edge, v0000000000bdab50_809, v0000000000bdab50_810, v0000000000bdab50_811, v0000000000bdab50_812; +v0000000000bdab50_813 .array/port v0000000000bdab50, 813; +v0000000000bdab50_814 .array/port v0000000000bdab50, 814; +v0000000000bdab50_815 .array/port v0000000000bdab50, 815; +v0000000000bdab50_816 .array/port v0000000000bdab50, 816; +E_00000000006a3090/204 .event edge, v0000000000bdab50_813, v0000000000bdab50_814, v0000000000bdab50_815, v0000000000bdab50_816; +v0000000000bdab50_817 .array/port v0000000000bdab50, 817; +v0000000000bdab50_818 .array/port v0000000000bdab50, 818; +v0000000000bdab50_819 .array/port v0000000000bdab50, 819; +v0000000000bdab50_820 .array/port v0000000000bdab50, 820; +E_00000000006a3090/205 .event edge, v0000000000bdab50_817, v0000000000bdab50_818, v0000000000bdab50_819, v0000000000bdab50_820; +v0000000000bdab50_821 .array/port v0000000000bdab50, 821; +v0000000000bdab50_822 .array/port v0000000000bdab50, 822; +v0000000000bdab50_823 .array/port v0000000000bdab50, 823; +v0000000000bdab50_824 .array/port v0000000000bdab50, 824; +E_00000000006a3090/206 .event edge, v0000000000bdab50_821, v0000000000bdab50_822, v0000000000bdab50_823, v0000000000bdab50_824; +v0000000000bdab50_825 .array/port v0000000000bdab50, 825; +v0000000000bdab50_826 .array/port v0000000000bdab50, 826; +v0000000000bdab50_827 .array/port v0000000000bdab50, 827; +v0000000000bdab50_828 .array/port v0000000000bdab50, 828; +E_00000000006a3090/207 .event edge, v0000000000bdab50_825, v0000000000bdab50_826, v0000000000bdab50_827, v0000000000bdab50_828; +v0000000000bdab50_829 .array/port v0000000000bdab50, 829; +v0000000000bdab50_830 .array/port v0000000000bdab50, 830; +v0000000000bdab50_831 .array/port v0000000000bdab50, 831; +v0000000000bdab50_832 .array/port v0000000000bdab50, 832; +E_00000000006a3090/208 .event edge, v0000000000bdab50_829, v0000000000bdab50_830, v0000000000bdab50_831, v0000000000bdab50_832; +v0000000000bdab50_833 .array/port v0000000000bdab50, 833; +v0000000000bdab50_834 .array/port v0000000000bdab50, 834; +v0000000000bdab50_835 .array/port v0000000000bdab50, 835; +v0000000000bdab50_836 .array/port v0000000000bdab50, 836; +E_00000000006a3090/209 .event edge, v0000000000bdab50_833, v0000000000bdab50_834, v0000000000bdab50_835, v0000000000bdab50_836; +v0000000000bdab50_837 .array/port v0000000000bdab50, 837; +v0000000000bdab50_838 .array/port v0000000000bdab50, 838; +v0000000000bdab50_839 .array/port v0000000000bdab50, 839; +v0000000000bdab50_840 .array/port v0000000000bdab50, 840; +E_00000000006a3090/210 .event edge, v0000000000bdab50_837, v0000000000bdab50_838, v0000000000bdab50_839, v0000000000bdab50_840; +v0000000000bdab50_841 .array/port v0000000000bdab50, 841; +v0000000000bdab50_842 .array/port v0000000000bdab50, 842; +v0000000000bdab50_843 .array/port v0000000000bdab50, 843; +v0000000000bdab50_844 .array/port v0000000000bdab50, 844; +E_00000000006a3090/211 .event edge, v0000000000bdab50_841, v0000000000bdab50_842, v0000000000bdab50_843, v0000000000bdab50_844; +v0000000000bdab50_845 .array/port v0000000000bdab50, 845; +v0000000000bdab50_846 .array/port v0000000000bdab50, 846; +v0000000000bdab50_847 .array/port v0000000000bdab50, 847; +v0000000000bdab50_848 .array/port v0000000000bdab50, 848; +E_00000000006a3090/212 .event edge, v0000000000bdab50_845, v0000000000bdab50_846, v0000000000bdab50_847, v0000000000bdab50_848; +v0000000000bdab50_849 .array/port v0000000000bdab50, 849; +v0000000000bdab50_850 .array/port v0000000000bdab50, 850; +v0000000000bdab50_851 .array/port v0000000000bdab50, 851; +v0000000000bdab50_852 .array/port v0000000000bdab50, 852; +E_00000000006a3090/213 .event edge, v0000000000bdab50_849, v0000000000bdab50_850, v0000000000bdab50_851, v0000000000bdab50_852; +v0000000000bdab50_853 .array/port v0000000000bdab50, 853; +v0000000000bdab50_854 .array/port v0000000000bdab50, 854; +v0000000000bdab50_855 .array/port v0000000000bdab50, 855; +v0000000000bdab50_856 .array/port v0000000000bdab50, 856; +E_00000000006a3090/214 .event edge, v0000000000bdab50_853, v0000000000bdab50_854, v0000000000bdab50_855, v0000000000bdab50_856; +v0000000000bdab50_857 .array/port v0000000000bdab50, 857; +v0000000000bdab50_858 .array/port v0000000000bdab50, 858; +v0000000000bdab50_859 .array/port v0000000000bdab50, 859; +v0000000000bdab50_860 .array/port v0000000000bdab50, 860; +E_00000000006a3090/215 .event edge, v0000000000bdab50_857, v0000000000bdab50_858, v0000000000bdab50_859, v0000000000bdab50_860; +v0000000000bdab50_861 .array/port v0000000000bdab50, 861; +v0000000000bdab50_862 .array/port v0000000000bdab50, 862; +v0000000000bdab50_863 .array/port v0000000000bdab50, 863; +v0000000000bdab50_864 .array/port v0000000000bdab50, 864; +E_00000000006a3090/216 .event edge, v0000000000bdab50_861, v0000000000bdab50_862, v0000000000bdab50_863, v0000000000bdab50_864; +v0000000000bdab50_865 .array/port v0000000000bdab50, 865; +v0000000000bdab50_866 .array/port v0000000000bdab50, 866; +v0000000000bdab50_867 .array/port v0000000000bdab50, 867; +v0000000000bdab50_868 .array/port v0000000000bdab50, 868; +E_00000000006a3090/217 .event edge, v0000000000bdab50_865, v0000000000bdab50_866, v0000000000bdab50_867, v0000000000bdab50_868; +v0000000000bdab50_869 .array/port v0000000000bdab50, 869; +v0000000000bdab50_870 .array/port v0000000000bdab50, 870; +v0000000000bdab50_871 .array/port v0000000000bdab50, 871; +v0000000000bdab50_872 .array/port v0000000000bdab50, 872; +E_00000000006a3090/218 .event edge, v0000000000bdab50_869, v0000000000bdab50_870, v0000000000bdab50_871, v0000000000bdab50_872; +v0000000000bdab50_873 .array/port v0000000000bdab50, 873; +v0000000000bdab50_874 .array/port v0000000000bdab50, 874; +v0000000000bdab50_875 .array/port v0000000000bdab50, 875; +v0000000000bdab50_876 .array/port v0000000000bdab50, 876; +E_00000000006a3090/219 .event edge, v0000000000bdab50_873, v0000000000bdab50_874, v0000000000bdab50_875, v0000000000bdab50_876; +v0000000000bdab50_877 .array/port v0000000000bdab50, 877; +v0000000000bdab50_878 .array/port v0000000000bdab50, 878; +v0000000000bdab50_879 .array/port v0000000000bdab50, 879; +v0000000000bdab50_880 .array/port v0000000000bdab50, 880; +E_00000000006a3090/220 .event edge, v0000000000bdab50_877, v0000000000bdab50_878, v0000000000bdab50_879, v0000000000bdab50_880; +v0000000000bdab50_881 .array/port v0000000000bdab50, 881; +v0000000000bdab50_882 .array/port v0000000000bdab50, 882; +v0000000000bdab50_883 .array/port v0000000000bdab50, 883; +v0000000000bdab50_884 .array/port v0000000000bdab50, 884; +E_00000000006a3090/221 .event edge, v0000000000bdab50_881, v0000000000bdab50_882, v0000000000bdab50_883, v0000000000bdab50_884; +v0000000000bdab50_885 .array/port v0000000000bdab50, 885; +v0000000000bdab50_886 .array/port v0000000000bdab50, 886; +v0000000000bdab50_887 .array/port v0000000000bdab50, 887; +v0000000000bdab50_888 .array/port v0000000000bdab50, 888; +E_00000000006a3090/222 .event edge, v0000000000bdab50_885, v0000000000bdab50_886, v0000000000bdab50_887, v0000000000bdab50_888; +v0000000000bdab50_889 .array/port v0000000000bdab50, 889; +v0000000000bdab50_890 .array/port v0000000000bdab50, 890; +v0000000000bdab50_891 .array/port v0000000000bdab50, 891; +v0000000000bdab50_892 .array/port v0000000000bdab50, 892; +E_00000000006a3090/223 .event edge, v0000000000bdab50_889, v0000000000bdab50_890, v0000000000bdab50_891, v0000000000bdab50_892; +v0000000000bdab50_893 .array/port v0000000000bdab50, 893; +v0000000000bdab50_894 .array/port v0000000000bdab50, 894; +v0000000000bdab50_895 .array/port v0000000000bdab50, 895; +v0000000000bdab50_896 .array/port v0000000000bdab50, 896; +E_00000000006a3090/224 .event edge, v0000000000bdab50_893, v0000000000bdab50_894, v0000000000bdab50_895, v0000000000bdab50_896; +v0000000000bdab50_897 .array/port v0000000000bdab50, 897; +v0000000000bdab50_898 .array/port v0000000000bdab50, 898; +v0000000000bdab50_899 .array/port v0000000000bdab50, 899; +v0000000000bdab50_900 .array/port v0000000000bdab50, 900; +E_00000000006a3090/225 .event edge, v0000000000bdab50_897, v0000000000bdab50_898, v0000000000bdab50_899, v0000000000bdab50_900; +v0000000000bdab50_901 .array/port v0000000000bdab50, 901; +v0000000000bdab50_902 .array/port v0000000000bdab50, 902; +v0000000000bdab50_903 .array/port v0000000000bdab50, 903; +v0000000000bdab50_904 .array/port v0000000000bdab50, 904; +E_00000000006a3090/226 .event edge, v0000000000bdab50_901, v0000000000bdab50_902, v0000000000bdab50_903, v0000000000bdab50_904; +v0000000000bdab50_905 .array/port v0000000000bdab50, 905; +v0000000000bdab50_906 .array/port v0000000000bdab50, 906; +v0000000000bdab50_907 .array/port v0000000000bdab50, 907; +v0000000000bdab50_908 .array/port v0000000000bdab50, 908; +E_00000000006a3090/227 .event edge, v0000000000bdab50_905, v0000000000bdab50_906, v0000000000bdab50_907, v0000000000bdab50_908; +v0000000000bdab50_909 .array/port v0000000000bdab50, 909; +v0000000000bdab50_910 .array/port v0000000000bdab50, 910; +v0000000000bdab50_911 .array/port v0000000000bdab50, 911; +v0000000000bdab50_912 .array/port v0000000000bdab50, 912; +E_00000000006a3090/228 .event edge, v0000000000bdab50_909, v0000000000bdab50_910, v0000000000bdab50_911, v0000000000bdab50_912; +v0000000000bdab50_913 .array/port v0000000000bdab50, 913; +v0000000000bdab50_914 .array/port v0000000000bdab50, 914; +v0000000000bdab50_915 .array/port v0000000000bdab50, 915; +v0000000000bdab50_916 .array/port v0000000000bdab50, 916; +E_00000000006a3090/229 .event edge, v0000000000bdab50_913, v0000000000bdab50_914, v0000000000bdab50_915, v0000000000bdab50_916; +v0000000000bdab50_917 .array/port v0000000000bdab50, 917; +v0000000000bdab50_918 .array/port v0000000000bdab50, 918; +v0000000000bdab50_919 .array/port v0000000000bdab50, 919; +v0000000000bdab50_920 .array/port v0000000000bdab50, 920; +E_00000000006a3090/230 .event edge, v0000000000bdab50_917, v0000000000bdab50_918, v0000000000bdab50_919, v0000000000bdab50_920; +v0000000000bdab50_921 .array/port v0000000000bdab50, 921; +v0000000000bdab50_922 .array/port v0000000000bdab50, 922; +v0000000000bdab50_923 .array/port v0000000000bdab50, 923; +v0000000000bdab50_924 .array/port v0000000000bdab50, 924; +E_00000000006a3090/231 .event edge, v0000000000bdab50_921, v0000000000bdab50_922, v0000000000bdab50_923, v0000000000bdab50_924; +v0000000000bdab50_925 .array/port v0000000000bdab50, 925; +v0000000000bdab50_926 .array/port v0000000000bdab50, 926; +v0000000000bdab50_927 .array/port v0000000000bdab50, 927; +v0000000000bdab50_928 .array/port v0000000000bdab50, 928; +E_00000000006a3090/232 .event edge, v0000000000bdab50_925, v0000000000bdab50_926, v0000000000bdab50_927, v0000000000bdab50_928; +v0000000000bdab50_929 .array/port v0000000000bdab50, 929; +v0000000000bdab50_930 .array/port v0000000000bdab50, 930; +v0000000000bdab50_931 .array/port v0000000000bdab50, 931; +v0000000000bdab50_932 .array/port v0000000000bdab50, 932; +E_00000000006a3090/233 .event edge, v0000000000bdab50_929, v0000000000bdab50_930, v0000000000bdab50_931, v0000000000bdab50_932; +v0000000000bdab50_933 .array/port v0000000000bdab50, 933; +v0000000000bdab50_934 .array/port v0000000000bdab50, 934; +v0000000000bdab50_935 .array/port v0000000000bdab50, 935; +v0000000000bdab50_936 .array/port v0000000000bdab50, 936; +E_00000000006a3090/234 .event edge, v0000000000bdab50_933, v0000000000bdab50_934, v0000000000bdab50_935, v0000000000bdab50_936; +v0000000000bdab50_937 .array/port v0000000000bdab50, 937; +v0000000000bdab50_938 .array/port v0000000000bdab50, 938; +v0000000000bdab50_939 .array/port v0000000000bdab50, 939; +v0000000000bdab50_940 .array/port v0000000000bdab50, 940; +E_00000000006a3090/235 .event edge, v0000000000bdab50_937, v0000000000bdab50_938, v0000000000bdab50_939, v0000000000bdab50_940; +v0000000000bdab50_941 .array/port v0000000000bdab50, 941; +v0000000000bdab50_942 .array/port v0000000000bdab50, 942; +v0000000000bdab50_943 .array/port v0000000000bdab50, 943; +v0000000000bdab50_944 .array/port v0000000000bdab50, 944; +E_00000000006a3090/236 .event edge, v0000000000bdab50_941, v0000000000bdab50_942, v0000000000bdab50_943, v0000000000bdab50_944; +v0000000000bdab50_945 .array/port v0000000000bdab50, 945; +v0000000000bdab50_946 .array/port v0000000000bdab50, 946; +v0000000000bdab50_947 .array/port v0000000000bdab50, 947; +v0000000000bdab50_948 .array/port v0000000000bdab50, 948; +E_00000000006a3090/237 .event edge, v0000000000bdab50_945, v0000000000bdab50_946, v0000000000bdab50_947, v0000000000bdab50_948; +v0000000000bdab50_949 .array/port v0000000000bdab50, 949; +v0000000000bdab50_950 .array/port v0000000000bdab50, 950; +v0000000000bdab50_951 .array/port v0000000000bdab50, 951; +v0000000000bdab50_952 .array/port v0000000000bdab50, 952; +E_00000000006a3090/238 .event edge, v0000000000bdab50_949, v0000000000bdab50_950, v0000000000bdab50_951, v0000000000bdab50_952; +v0000000000bdab50_953 .array/port v0000000000bdab50, 953; +v0000000000bdab50_954 .array/port v0000000000bdab50, 954; +v0000000000bdab50_955 .array/port v0000000000bdab50, 955; +v0000000000bdab50_956 .array/port v0000000000bdab50, 956; +E_00000000006a3090/239 .event edge, v0000000000bdab50_953, v0000000000bdab50_954, v0000000000bdab50_955, v0000000000bdab50_956; +v0000000000bdab50_957 .array/port v0000000000bdab50, 957; +v0000000000bdab50_958 .array/port v0000000000bdab50, 958; +v0000000000bdab50_959 .array/port v0000000000bdab50, 959; +v0000000000bdab50_960 .array/port v0000000000bdab50, 960; +E_00000000006a3090/240 .event edge, v0000000000bdab50_957, v0000000000bdab50_958, v0000000000bdab50_959, v0000000000bdab50_960; +v0000000000bdab50_961 .array/port v0000000000bdab50, 961; +v0000000000bdab50_962 .array/port v0000000000bdab50, 962; +v0000000000bdab50_963 .array/port v0000000000bdab50, 963; +v0000000000bdab50_964 .array/port v0000000000bdab50, 964; +E_00000000006a3090/241 .event edge, v0000000000bdab50_961, v0000000000bdab50_962, v0000000000bdab50_963, v0000000000bdab50_964; +v0000000000bdab50_965 .array/port v0000000000bdab50, 965; +v0000000000bdab50_966 .array/port v0000000000bdab50, 966; +v0000000000bdab50_967 .array/port v0000000000bdab50, 967; +v0000000000bdab50_968 .array/port v0000000000bdab50, 968; +E_00000000006a3090/242 .event edge, v0000000000bdab50_965, v0000000000bdab50_966, v0000000000bdab50_967, v0000000000bdab50_968; +v0000000000bdab50_969 .array/port v0000000000bdab50, 969; +v0000000000bdab50_970 .array/port v0000000000bdab50, 970; +v0000000000bdab50_971 .array/port v0000000000bdab50, 971; +v0000000000bdab50_972 .array/port v0000000000bdab50, 972; +E_00000000006a3090/243 .event edge, v0000000000bdab50_969, v0000000000bdab50_970, v0000000000bdab50_971, v0000000000bdab50_972; +v0000000000bdab50_973 .array/port v0000000000bdab50, 973; +v0000000000bdab50_974 .array/port v0000000000bdab50, 974; +v0000000000bdab50_975 .array/port v0000000000bdab50, 975; +v0000000000bdab50_976 .array/port v0000000000bdab50, 976; +E_00000000006a3090/244 .event edge, v0000000000bdab50_973, v0000000000bdab50_974, v0000000000bdab50_975, v0000000000bdab50_976; +v0000000000bdab50_977 .array/port v0000000000bdab50, 977; +v0000000000bdab50_978 .array/port v0000000000bdab50, 978; +v0000000000bdab50_979 .array/port v0000000000bdab50, 979; +v0000000000bdab50_980 .array/port v0000000000bdab50, 980; +E_00000000006a3090/245 .event edge, v0000000000bdab50_977, v0000000000bdab50_978, v0000000000bdab50_979, v0000000000bdab50_980; +v0000000000bdab50_981 .array/port v0000000000bdab50, 981; +v0000000000bdab50_982 .array/port v0000000000bdab50, 982; +v0000000000bdab50_983 .array/port v0000000000bdab50, 983; +v0000000000bdab50_984 .array/port v0000000000bdab50, 984; +E_00000000006a3090/246 .event edge, v0000000000bdab50_981, v0000000000bdab50_982, v0000000000bdab50_983, v0000000000bdab50_984; +v0000000000bdab50_985 .array/port v0000000000bdab50, 985; +v0000000000bdab50_986 .array/port v0000000000bdab50, 986; +v0000000000bdab50_987 .array/port v0000000000bdab50, 987; +v0000000000bdab50_988 .array/port v0000000000bdab50, 988; +E_00000000006a3090/247 .event edge, v0000000000bdab50_985, v0000000000bdab50_986, v0000000000bdab50_987, v0000000000bdab50_988; +v0000000000bdab50_989 .array/port v0000000000bdab50, 989; +v0000000000bdab50_990 .array/port v0000000000bdab50, 990; +v0000000000bdab50_991 .array/port v0000000000bdab50, 991; +v0000000000bdab50_992 .array/port v0000000000bdab50, 992; +E_00000000006a3090/248 .event edge, v0000000000bdab50_989, v0000000000bdab50_990, v0000000000bdab50_991, v0000000000bdab50_992; +v0000000000bdab50_993 .array/port v0000000000bdab50, 993; +v0000000000bdab50_994 .array/port v0000000000bdab50, 994; +v0000000000bdab50_995 .array/port v0000000000bdab50, 995; +v0000000000bdab50_996 .array/port v0000000000bdab50, 996; +E_00000000006a3090/249 .event edge, v0000000000bdab50_993, v0000000000bdab50_994, v0000000000bdab50_995, v0000000000bdab50_996; +v0000000000bdab50_997 .array/port v0000000000bdab50, 997; +v0000000000bdab50_998 .array/port v0000000000bdab50, 998; +v0000000000bdab50_999 .array/port v0000000000bdab50, 999; +v0000000000bdab50_1000 .array/port v0000000000bdab50, 1000; +E_00000000006a3090/250 .event edge, v0000000000bdab50_997, v0000000000bdab50_998, v0000000000bdab50_999, v0000000000bdab50_1000; +v0000000000bdab50_1001 .array/port v0000000000bdab50, 1001; +v0000000000bdab50_1002 .array/port v0000000000bdab50, 1002; +v0000000000bdab50_1003 .array/port v0000000000bdab50, 1003; +v0000000000bdab50_1004 .array/port v0000000000bdab50, 1004; +E_00000000006a3090/251 .event edge, v0000000000bdab50_1001, v0000000000bdab50_1002, v0000000000bdab50_1003, v0000000000bdab50_1004; +v0000000000bdab50_1005 .array/port v0000000000bdab50, 1005; +v0000000000bdab50_1006 .array/port v0000000000bdab50, 1006; +v0000000000bdab50_1007 .array/port v0000000000bdab50, 1007; +v0000000000bdab50_1008 .array/port v0000000000bdab50, 1008; +E_00000000006a3090/252 .event edge, v0000000000bdab50_1005, v0000000000bdab50_1006, v0000000000bdab50_1007, v0000000000bdab50_1008; +v0000000000bdab50_1009 .array/port v0000000000bdab50, 1009; +v0000000000bdab50_1010 .array/port v0000000000bdab50, 1010; +v0000000000bdab50_1011 .array/port v0000000000bdab50, 1011; +v0000000000bdab50_1012 .array/port v0000000000bdab50, 1012; +E_00000000006a3090/253 .event edge, v0000000000bdab50_1009, v0000000000bdab50_1010, v0000000000bdab50_1011, v0000000000bdab50_1012; +v0000000000bdab50_1013 .array/port v0000000000bdab50, 1013; +v0000000000bdab50_1014 .array/port v0000000000bdab50, 1014; +v0000000000bdab50_1015 .array/port v0000000000bdab50, 1015; +v0000000000bdab50_1016 .array/port v0000000000bdab50, 1016; +E_00000000006a3090/254 .event edge, v0000000000bdab50_1013, v0000000000bdab50_1014, v0000000000bdab50_1015, v0000000000bdab50_1016; +v0000000000bdab50_1017 .array/port v0000000000bdab50, 1017; +v0000000000bdab50_1018 .array/port v0000000000bdab50, 1018; +v0000000000bdab50_1019 .array/port v0000000000bdab50, 1019; +v0000000000bdab50_1020 .array/port v0000000000bdab50, 1020; +E_00000000006a3090/255 .event edge, v0000000000bdab50_1017, v0000000000bdab50_1018, v0000000000bdab50_1019, v0000000000bdab50_1020; +v0000000000bdab50_1021 .array/port v0000000000bdab50, 1021; +v0000000000bdab50_1022 .array/port v0000000000bdab50, 1022; +v0000000000bdab50_1023 .array/port v0000000000bdab50, 1023; +v0000000000bdab50_1024 .array/port v0000000000bdab50, 1024; +E_00000000006a3090/256 .event edge, v0000000000bdab50_1021, v0000000000bdab50_1022, v0000000000bdab50_1023, v0000000000bdab50_1024; +v0000000000bdab50_1025 .array/port v0000000000bdab50, 1025; +v0000000000bdab50_1026 .array/port v0000000000bdab50, 1026; +v0000000000bdab50_1027 .array/port v0000000000bdab50, 1027; +v0000000000bdab50_1028 .array/port v0000000000bdab50, 1028; +E_00000000006a3090/257 .event edge, v0000000000bdab50_1025, v0000000000bdab50_1026, v0000000000bdab50_1027, v0000000000bdab50_1028; +v0000000000bdab50_1029 .array/port v0000000000bdab50, 1029; +v0000000000bdab50_1030 .array/port v0000000000bdab50, 1030; +v0000000000bdab50_1031 .array/port v0000000000bdab50, 1031; +v0000000000bdab50_1032 .array/port v0000000000bdab50, 1032; +E_00000000006a3090/258 .event edge, v0000000000bdab50_1029, v0000000000bdab50_1030, v0000000000bdab50_1031, v0000000000bdab50_1032; +v0000000000bdab50_1033 .array/port v0000000000bdab50, 1033; +v0000000000bdab50_1034 .array/port v0000000000bdab50, 1034; +v0000000000bdab50_1035 .array/port v0000000000bdab50, 1035; +v0000000000bdab50_1036 .array/port v0000000000bdab50, 1036; +E_00000000006a3090/259 .event edge, v0000000000bdab50_1033, v0000000000bdab50_1034, v0000000000bdab50_1035, v0000000000bdab50_1036; +v0000000000bdab50_1037 .array/port v0000000000bdab50, 1037; +v0000000000bdab50_1038 .array/port v0000000000bdab50, 1038; +v0000000000bdab50_1039 .array/port v0000000000bdab50, 1039; +v0000000000bdab50_1040 .array/port v0000000000bdab50, 1040; +E_00000000006a3090/260 .event edge, v0000000000bdab50_1037, v0000000000bdab50_1038, v0000000000bdab50_1039, v0000000000bdab50_1040; +v0000000000bdab50_1041 .array/port v0000000000bdab50, 1041; +v0000000000bdab50_1042 .array/port v0000000000bdab50, 1042; +v0000000000bdab50_1043 .array/port v0000000000bdab50, 1043; +v0000000000bdab50_1044 .array/port v0000000000bdab50, 1044; +E_00000000006a3090/261 .event edge, v0000000000bdab50_1041, v0000000000bdab50_1042, v0000000000bdab50_1043, v0000000000bdab50_1044; +v0000000000bdab50_1045 .array/port v0000000000bdab50, 1045; +v0000000000bdab50_1046 .array/port v0000000000bdab50, 1046; +v0000000000bdab50_1047 .array/port v0000000000bdab50, 1047; +v0000000000bdab50_1048 .array/port v0000000000bdab50, 1048; +E_00000000006a3090/262 .event edge, v0000000000bdab50_1045, v0000000000bdab50_1046, v0000000000bdab50_1047, v0000000000bdab50_1048; +v0000000000bdab50_1049 .array/port v0000000000bdab50, 1049; +v0000000000bdab50_1050 .array/port v0000000000bdab50, 1050; +v0000000000bdab50_1051 .array/port v0000000000bdab50, 1051; +v0000000000bdab50_1052 .array/port v0000000000bdab50, 1052; +E_00000000006a3090/263 .event edge, v0000000000bdab50_1049, v0000000000bdab50_1050, v0000000000bdab50_1051, v0000000000bdab50_1052; +v0000000000bdab50_1053 .array/port v0000000000bdab50, 1053; +v0000000000bdab50_1054 .array/port v0000000000bdab50, 1054; +v0000000000bdab50_1055 .array/port v0000000000bdab50, 1055; +v0000000000bdab50_1056 .array/port v0000000000bdab50, 1056; +E_00000000006a3090/264 .event edge, v0000000000bdab50_1053, v0000000000bdab50_1054, v0000000000bdab50_1055, v0000000000bdab50_1056; +v0000000000bdab50_1057 .array/port v0000000000bdab50, 1057; +v0000000000bdab50_1058 .array/port v0000000000bdab50, 1058; +v0000000000bdab50_1059 .array/port v0000000000bdab50, 1059; +v0000000000bdab50_1060 .array/port v0000000000bdab50, 1060; +E_00000000006a3090/265 .event edge, v0000000000bdab50_1057, v0000000000bdab50_1058, v0000000000bdab50_1059, v0000000000bdab50_1060; +v0000000000bdab50_1061 .array/port v0000000000bdab50, 1061; +v0000000000bdab50_1062 .array/port v0000000000bdab50, 1062; +v0000000000bdab50_1063 .array/port v0000000000bdab50, 1063; +v0000000000bdab50_1064 .array/port v0000000000bdab50, 1064; +E_00000000006a3090/266 .event edge, v0000000000bdab50_1061, v0000000000bdab50_1062, v0000000000bdab50_1063, v0000000000bdab50_1064; +v0000000000bdab50_1065 .array/port v0000000000bdab50, 1065; +v0000000000bdab50_1066 .array/port v0000000000bdab50, 1066; +v0000000000bdab50_1067 .array/port v0000000000bdab50, 1067; +v0000000000bdab50_1068 .array/port v0000000000bdab50, 1068; +E_00000000006a3090/267 .event edge, v0000000000bdab50_1065, v0000000000bdab50_1066, v0000000000bdab50_1067, v0000000000bdab50_1068; +v0000000000bdab50_1069 .array/port v0000000000bdab50, 1069; +v0000000000bdab50_1070 .array/port v0000000000bdab50, 1070; +v0000000000bdab50_1071 .array/port v0000000000bdab50, 1071; +v0000000000bdab50_1072 .array/port v0000000000bdab50, 1072; +E_00000000006a3090/268 .event edge, v0000000000bdab50_1069, v0000000000bdab50_1070, v0000000000bdab50_1071, v0000000000bdab50_1072; +v0000000000bdab50_1073 .array/port v0000000000bdab50, 1073; +v0000000000bdab50_1074 .array/port v0000000000bdab50, 1074; +v0000000000bdab50_1075 .array/port v0000000000bdab50, 1075; +v0000000000bdab50_1076 .array/port v0000000000bdab50, 1076; +E_00000000006a3090/269 .event edge, v0000000000bdab50_1073, v0000000000bdab50_1074, v0000000000bdab50_1075, v0000000000bdab50_1076; +v0000000000bdab50_1077 .array/port v0000000000bdab50, 1077; +v0000000000bdab50_1078 .array/port v0000000000bdab50, 1078; +v0000000000bdab50_1079 .array/port v0000000000bdab50, 1079; +v0000000000bdab50_1080 .array/port v0000000000bdab50, 1080; +E_00000000006a3090/270 .event edge, v0000000000bdab50_1077, v0000000000bdab50_1078, v0000000000bdab50_1079, v0000000000bdab50_1080; +v0000000000bdab50_1081 .array/port v0000000000bdab50, 1081; +v0000000000bdab50_1082 .array/port v0000000000bdab50, 1082; +v0000000000bdab50_1083 .array/port v0000000000bdab50, 1083; +v0000000000bdab50_1084 .array/port v0000000000bdab50, 1084; +E_00000000006a3090/271 .event edge, v0000000000bdab50_1081, v0000000000bdab50_1082, v0000000000bdab50_1083, v0000000000bdab50_1084; +v0000000000bdab50_1085 .array/port v0000000000bdab50, 1085; +v0000000000bdab50_1086 .array/port v0000000000bdab50, 1086; +v0000000000bdab50_1087 .array/port v0000000000bdab50, 1087; +v0000000000bdab50_1088 .array/port v0000000000bdab50, 1088; +E_00000000006a3090/272 .event edge, v0000000000bdab50_1085, v0000000000bdab50_1086, v0000000000bdab50_1087, v0000000000bdab50_1088; +v0000000000bdab50_1089 .array/port v0000000000bdab50, 1089; +v0000000000bdab50_1090 .array/port v0000000000bdab50, 1090; +v0000000000bdab50_1091 .array/port v0000000000bdab50, 1091; +v0000000000bdab50_1092 .array/port v0000000000bdab50, 1092; +E_00000000006a3090/273 .event edge, v0000000000bdab50_1089, v0000000000bdab50_1090, v0000000000bdab50_1091, v0000000000bdab50_1092; +v0000000000bdab50_1093 .array/port v0000000000bdab50, 1093; +v0000000000bdab50_1094 .array/port v0000000000bdab50, 1094; +v0000000000bdab50_1095 .array/port v0000000000bdab50, 1095; +v0000000000bdab50_1096 .array/port v0000000000bdab50, 1096; +E_00000000006a3090/274 .event edge, v0000000000bdab50_1093, v0000000000bdab50_1094, v0000000000bdab50_1095, v0000000000bdab50_1096; +v0000000000bdab50_1097 .array/port v0000000000bdab50, 1097; +v0000000000bdab50_1098 .array/port v0000000000bdab50, 1098; +v0000000000bdab50_1099 .array/port v0000000000bdab50, 1099; +v0000000000bdab50_1100 .array/port v0000000000bdab50, 1100; +E_00000000006a3090/275 .event edge, v0000000000bdab50_1097, v0000000000bdab50_1098, v0000000000bdab50_1099, v0000000000bdab50_1100; +v0000000000bdab50_1101 .array/port v0000000000bdab50, 1101; +v0000000000bdab50_1102 .array/port v0000000000bdab50, 1102; +v0000000000bdab50_1103 .array/port v0000000000bdab50, 1103; +v0000000000bdab50_1104 .array/port v0000000000bdab50, 1104; +E_00000000006a3090/276 .event edge, v0000000000bdab50_1101, v0000000000bdab50_1102, v0000000000bdab50_1103, v0000000000bdab50_1104; +v0000000000bdab50_1105 .array/port v0000000000bdab50, 1105; +v0000000000bdab50_1106 .array/port v0000000000bdab50, 1106; +v0000000000bdab50_1107 .array/port v0000000000bdab50, 1107; +v0000000000bdab50_1108 .array/port v0000000000bdab50, 1108; +E_00000000006a3090/277 .event edge, v0000000000bdab50_1105, v0000000000bdab50_1106, v0000000000bdab50_1107, v0000000000bdab50_1108; +v0000000000bdab50_1109 .array/port v0000000000bdab50, 1109; +v0000000000bdab50_1110 .array/port v0000000000bdab50, 1110; +v0000000000bdab50_1111 .array/port v0000000000bdab50, 1111; +v0000000000bdab50_1112 .array/port v0000000000bdab50, 1112; +E_00000000006a3090/278 .event edge, v0000000000bdab50_1109, v0000000000bdab50_1110, v0000000000bdab50_1111, v0000000000bdab50_1112; +v0000000000bdab50_1113 .array/port v0000000000bdab50, 1113; +v0000000000bdab50_1114 .array/port v0000000000bdab50, 1114; +v0000000000bdab50_1115 .array/port v0000000000bdab50, 1115; +v0000000000bdab50_1116 .array/port v0000000000bdab50, 1116; +E_00000000006a3090/279 .event edge, v0000000000bdab50_1113, v0000000000bdab50_1114, v0000000000bdab50_1115, v0000000000bdab50_1116; +v0000000000bdab50_1117 .array/port v0000000000bdab50, 1117; +v0000000000bdab50_1118 .array/port v0000000000bdab50, 1118; +v0000000000bdab50_1119 .array/port v0000000000bdab50, 1119; +v0000000000bdab50_1120 .array/port v0000000000bdab50, 1120; +E_00000000006a3090/280 .event edge, v0000000000bdab50_1117, v0000000000bdab50_1118, v0000000000bdab50_1119, v0000000000bdab50_1120; +v0000000000bdab50_1121 .array/port v0000000000bdab50, 1121; +v0000000000bdab50_1122 .array/port v0000000000bdab50, 1122; +v0000000000bdab50_1123 .array/port v0000000000bdab50, 1123; +v0000000000bdab50_1124 .array/port v0000000000bdab50, 1124; +E_00000000006a3090/281 .event edge, v0000000000bdab50_1121, v0000000000bdab50_1122, v0000000000bdab50_1123, v0000000000bdab50_1124; +v0000000000bdab50_1125 .array/port v0000000000bdab50, 1125; +v0000000000bdab50_1126 .array/port v0000000000bdab50, 1126; +v0000000000bdab50_1127 .array/port v0000000000bdab50, 1127; +v0000000000bdab50_1128 .array/port v0000000000bdab50, 1128; +E_00000000006a3090/282 .event edge, v0000000000bdab50_1125, v0000000000bdab50_1126, v0000000000bdab50_1127, v0000000000bdab50_1128; +v0000000000bdab50_1129 .array/port v0000000000bdab50, 1129; +v0000000000bdab50_1130 .array/port v0000000000bdab50, 1130; +v0000000000bdab50_1131 .array/port v0000000000bdab50, 1131; +v0000000000bdab50_1132 .array/port v0000000000bdab50, 1132; +E_00000000006a3090/283 .event edge, v0000000000bdab50_1129, v0000000000bdab50_1130, v0000000000bdab50_1131, v0000000000bdab50_1132; +v0000000000bdab50_1133 .array/port v0000000000bdab50, 1133; +v0000000000bdab50_1134 .array/port v0000000000bdab50, 1134; +v0000000000bdab50_1135 .array/port v0000000000bdab50, 1135; +v0000000000bdab50_1136 .array/port v0000000000bdab50, 1136; +E_00000000006a3090/284 .event edge, v0000000000bdab50_1133, v0000000000bdab50_1134, v0000000000bdab50_1135, v0000000000bdab50_1136; +v0000000000bdab50_1137 .array/port v0000000000bdab50, 1137; +v0000000000bdab50_1138 .array/port v0000000000bdab50, 1138; +v0000000000bdab50_1139 .array/port v0000000000bdab50, 1139; +v0000000000bdab50_1140 .array/port v0000000000bdab50, 1140; +E_00000000006a3090/285 .event edge, v0000000000bdab50_1137, v0000000000bdab50_1138, v0000000000bdab50_1139, v0000000000bdab50_1140; +v0000000000bdab50_1141 .array/port v0000000000bdab50, 1141; +v0000000000bdab50_1142 .array/port v0000000000bdab50, 1142; +v0000000000bdab50_1143 .array/port v0000000000bdab50, 1143; +v0000000000bdab50_1144 .array/port v0000000000bdab50, 1144; +E_00000000006a3090/286 .event edge, v0000000000bdab50_1141, v0000000000bdab50_1142, v0000000000bdab50_1143, v0000000000bdab50_1144; +v0000000000bdab50_1145 .array/port v0000000000bdab50, 1145; +v0000000000bdab50_1146 .array/port v0000000000bdab50, 1146; +v0000000000bdab50_1147 .array/port v0000000000bdab50, 1147; +v0000000000bdab50_1148 .array/port v0000000000bdab50, 1148; +E_00000000006a3090/287 .event edge, v0000000000bdab50_1145, v0000000000bdab50_1146, v0000000000bdab50_1147, v0000000000bdab50_1148; +v0000000000bdab50_1149 .array/port v0000000000bdab50, 1149; +v0000000000bdab50_1150 .array/port v0000000000bdab50, 1150; +v0000000000bdab50_1151 .array/port v0000000000bdab50, 1151; +v0000000000bdab50_1152 .array/port v0000000000bdab50, 1152; +E_00000000006a3090/288 .event edge, v0000000000bdab50_1149, v0000000000bdab50_1150, v0000000000bdab50_1151, v0000000000bdab50_1152; +v0000000000bdab50_1153 .array/port v0000000000bdab50, 1153; +v0000000000bdab50_1154 .array/port v0000000000bdab50, 1154; +v0000000000bdab50_1155 .array/port v0000000000bdab50, 1155; +v0000000000bdab50_1156 .array/port v0000000000bdab50, 1156; +E_00000000006a3090/289 .event edge, v0000000000bdab50_1153, v0000000000bdab50_1154, v0000000000bdab50_1155, v0000000000bdab50_1156; +v0000000000bdab50_1157 .array/port v0000000000bdab50, 1157; +v0000000000bdab50_1158 .array/port v0000000000bdab50, 1158; +v0000000000bdab50_1159 .array/port v0000000000bdab50, 1159; +v0000000000bdab50_1160 .array/port v0000000000bdab50, 1160; +E_00000000006a3090/290 .event edge, v0000000000bdab50_1157, v0000000000bdab50_1158, v0000000000bdab50_1159, v0000000000bdab50_1160; +v0000000000bdab50_1161 .array/port v0000000000bdab50, 1161; +v0000000000bdab50_1162 .array/port v0000000000bdab50, 1162; +v0000000000bdab50_1163 .array/port v0000000000bdab50, 1163; +v0000000000bdab50_1164 .array/port v0000000000bdab50, 1164; +E_00000000006a3090/291 .event edge, v0000000000bdab50_1161, v0000000000bdab50_1162, v0000000000bdab50_1163, v0000000000bdab50_1164; +v0000000000bdab50_1165 .array/port v0000000000bdab50, 1165; +v0000000000bdab50_1166 .array/port v0000000000bdab50, 1166; +v0000000000bdab50_1167 .array/port v0000000000bdab50, 1167; +v0000000000bdab50_1168 .array/port v0000000000bdab50, 1168; +E_00000000006a3090/292 .event edge, v0000000000bdab50_1165, v0000000000bdab50_1166, v0000000000bdab50_1167, v0000000000bdab50_1168; +v0000000000bdab50_1169 .array/port v0000000000bdab50, 1169; +v0000000000bdab50_1170 .array/port v0000000000bdab50, 1170; +v0000000000bdab50_1171 .array/port v0000000000bdab50, 1171; +v0000000000bdab50_1172 .array/port v0000000000bdab50, 1172; +E_00000000006a3090/293 .event edge, v0000000000bdab50_1169, v0000000000bdab50_1170, v0000000000bdab50_1171, v0000000000bdab50_1172; +v0000000000bdab50_1173 .array/port v0000000000bdab50, 1173; +v0000000000bdab50_1174 .array/port v0000000000bdab50, 1174; +v0000000000bdab50_1175 .array/port v0000000000bdab50, 1175; +v0000000000bdab50_1176 .array/port v0000000000bdab50, 1176; +E_00000000006a3090/294 .event edge, v0000000000bdab50_1173, v0000000000bdab50_1174, v0000000000bdab50_1175, v0000000000bdab50_1176; +v0000000000bdab50_1177 .array/port v0000000000bdab50, 1177; +v0000000000bdab50_1178 .array/port v0000000000bdab50, 1178; +v0000000000bdab50_1179 .array/port v0000000000bdab50, 1179; +v0000000000bdab50_1180 .array/port v0000000000bdab50, 1180; +E_00000000006a3090/295 .event edge, v0000000000bdab50_1177, v0000000000bdab50_1178, v0000000000bdab50_1179, v0000000000bdab50_1180; +v0000000000bdab50_1181 .array/port v0000000000bdab50, 1181; +v0000000000bdab50_1182 .array/port v0000000000bdab50, 1182; +v0000000000bdab50_1183 .array/port v0000000000bdab50, 1183; +v0000000000bdab50_1184 .array/port v0000000000bdab50, 1184; +E_00000000006a3090/296 .event edge, v0000000000bdab50_1181, v0000000000bdab50_1182, v0000000000bdab50_1183, v0000000000bdab50_1184; +v0000000000bdab50_1185 .array/port v0000000000bdab50, 1185; +v0000000000bdab50_1186 .array/port v0000000000bdab50, 1186; +v0000000000bdab50_1187 .array/port v0000000000bdab50, 1187; +v0000000000bdab50_1188 .array/port v0000000000bdab50, 1188; +E_00000000006a3090/297 .event edge, v0000000000bdab50_1185, v0000000000bdab50_1186, v0000000000bdab50_1187, v0000000000bdab50_1188; +v0000000000bdab50_1189 .array/port v0000000000bdab50, 1189; +v0000000000bdab50_1190 .array/port v0000000000bdab50, 1190; +v0000000000bdab50_1191 .array/port v0000000000bdab50, 1191; +v0000000000bdab50_1192 .array/port v0000000000bdab50, 1192; +E_00000000006a3090/298 .event edge, v0000000000bdab50_1189, v0000000000bdab50_1190, v0000000000bdab50_1191, v0000000000bdab50_1192; +v0000000000bdab50_1193 .array/port v0000000000bdab50, 1193; +v0000000000bdab50_1194 .array/port v0000000000bdab50, 1194; +v0000000000bdab50_1195 .array/port v0000000000bdab50, 1195; +v0000000000bdab50_1196 .array/port v0000000000bdab50, 1196; +E_00000000006a3090/299 .event edge, v0000000000bdab50_1193, v0000000000bdab50_1194, v0000000000bdab50_1195, v0000000000bdab50_1196; +v0000000000bdab50_1197 .array/port v0000000000bdab50, 1197; +v0000000000bdab50_1198 .array/port v0000000000bdab50, 1198; +v0000000000bdab50_1199 .array/port v0000000000bdab50, 1199; +v0000000000bdab50_1200 .array/port v0000000000bdab50, 1200; +E_00000000006a3090/300 .event edge, v0000000000bdab50_1197, v0000000000bdab50_1198, v0000000000bdab50_1199, v0000000000bdab50_1200; +v0000000000bdab50_1201 .array/port v0000000000bdab50, 1201; +v0000000000bdab50_1202 .array/port v0000000000bdab50, 1202; +v0000000000bdab50_1203 .array/port v0000000000bdab50, 1203; +v0000000000bdab50_1204 .array/port v0000000000bdab50, 1204; +E_00000000006a3090/301 .event edge, v0000000000bdab50_1201, v0000000000bdab50_1202, v0000000000bdab50_1203, v0000000000bdab50_1204; +v0000000000bdab50_1205 .array/port v0000000000bdab50, 1205; +v0000000000bdab50_1206 .array/port v0000000000bdab50, 1206; +v0000000000bdab50_1207 .array/port v0000000000bdab50, 1207; +v0000000000bdab50_1208 .array/port v0000000000bdab50, 1208; +E_00000000006a3090/302 .event edge, v0000000000bdab50_1205, v0000000000bdab50_1206, v0000000000bdab50_1207, v0000000000bdab50_1208; +v0000000000bdab50_1209 .array/port v0000000000bdab50, 1209; +v0000000000bdab50_1210 .array/port v0000000000bdab50, 1210; +v0000000000bdab50_1211 .array/port v0000000000bdab50, 1211; +v0000000000bdab50_1212 .array/port v0000000000bdab50, 1212; +E_00000000006a3090/303 .event edge, v0000000000bdab50_1209, v0000000000bdab50_1210, v0000000000bdab50_1211, v0000000000bdab50_1212; +v0000000000bdab50_1213 .array/port v0000000000bdab50, 1213; +v0000000000bdab50_1214 .array/port v0000000000bdab50, 1214; +v0000000000bdab50_1215 .array/port v0000000000bdab50, 1215; +v0000000000bdab50_1216 .array/port v0000000000bdab50, 1216; +E_00000000006a3090/304 .event edge, v0000000000bdab50_1213, v0000000000bdab50_1214, v0000000000bdab50_1215, v0000000000bdab50_1216; +v0000000000bdab50_1217 .array/port v0000000000bdab50, 1217; +v0000000000bdab50_1218 .array/port v0000000000bdab50, 1218; +v0000000000bdab50_1219 .array/port v0000000000bdab50, 1219; +v0000000000bdab50_1220 .array/port v0000000000bdab50, 1220; +E_00000000006a3090/305 .event edge, v0000000000bdab50_1217, v0000000000bdab50_1218, v0000000000bdab50_1219, v0000000000bdab50_1220; +v0000000000bdab50_1221 .array/port v0000000000bdab50, 1221; +v0000000000bdab50_1222 .array/port v0000000000bdab50, 1222; +v0000000000bdab50_1223 .array/port v0000000000bdab50, 1223; +v0000000000bdab50_1224 .array/port v0000000000bdab50, 1224; +E_00000000006a3090/306 .event edge, v0000000000bdab50_1221, v0000000000bdab50_1222, v0000000000bdab50_1223, v0000000000bdab50_1224; +v0000000000bdab50_1225 .array/port v0000000000bdab50, 1225; +v0000000000bdab50_1226 .array/port v0000000000bdab50, 1226; +v0000000000bdab50_1227 .array/port v0000000000bdab50, 1227; +v0000000000bdab50_1228 .array/port v0000000000bdab50, 1228; +E_00000000006a3090/307 .event edge, v0000000000bdab50_1225, v0000000000bdab50_1226, v0000000000bdab50_1227, v0000000000bdab50_1228; +v0000000000bdab50_1229 .array/port v0000000000bdab50, 1229; +v0000000000bdab50_1230 .array/port v0000000000bdab50, 1230; +v0000000000bdab50_1231 .array/port v0000000000bdab50, 1231; +v0000000000bdab50_1232 .array/port v0000000000bdab50, 1232; +E_00000000006a3090/308 .event edge, v0000000000bdab50_1229, v0000000000bdab50_1230, v0000000000bdab50_1231, v0000000000bdab50_1232; +v0000000000bdab50_1233 .array/port v0000000000bdab50, 1233; +v0000000000bdab50_1234 .array/port v0000000000bdab50, 1234; +v0000000000bdab50_1235 .array/port v0000000000bdab50, 1235; +v0000000000bdab50_1236 .array/port v0000000000bdab50, 1236; +E_00000000006a3090/309 .event edge, v0000000000bdab50_1233, v0000000000bdab50_1234, v0000000000bdab50_1235, v0000000000bdab50_1236; +v0000000000bdab50_1237 .array/port v0000000000bdab50, 1237; +v0000000000bdab50_1238 .array/port v0000000000bdab50, 1238; +v0000000000bdab50_1239 .array/port v0000000000bdab50, 1239; +v0000000000bdab50_1240 .array/port v0000000000bdab50, 1240; +E_00000000006a3090/310 .event edge, v0000000000bdab50_1237, v0000000000bdab50_1238, v0000000000bdab50_1239, v0000000000bdab50_1240; +v0000000000bdab50_1241 .array/port v0000000000bdab50, 1241; +v0000000000bdab50_1242 .array/port v0000000000bdab50, 1242; +v0000000000bdab50_1243 .array/port v0000000000bdab50, 1243; +v0000000000bdab50_1244 .array/port v0000000000bdab50, 1244; +E_00000000006a3090/311 .event edge, v0000000000bdab50_1241, v0000000000bdab50_1242, v0000000000bdab50_1243, v0000000000bdab50_1244; +v0000000000bdab50_1245 .array/port v0000000000bdab50, 1245; +v0000000000bdab50_1246 .array/port v0000000000bdab50, 1246; +v0000000000bdab50_1247 .array/port v0000000000bdab50, 1247; +v0000000000bdab50_1248 .array/port v0000000000bdab50, 1248; +E_00000000006a3090/312 .event edge, v0000000000bdab50_1245, v0000000000bdab50_1246, v0000000000bdab50_1247, v0000000000bdab50_1248; +v0000000000bdab50_1249 .array/port v0000000000bdab50, 1249; +v0000000000bdab50_1250 .array/port v0000000000bdab50, 1250; +v0000000000bdab50_1251 .array/port v0000000000bdab50, 1251; +v0000000000bdab50_1252 .array/port v0000000000bdab50, 1252; +E_00000000006a3090/313 .event edge, v0000000000bdab50_1249, v0000000000bdab50_1250, v0000000000bdab50_1251, v0000000000bdab50_1252; +v0000000000bdab50_1253 .array/port v0000000000bdab50, 1253; +v0000000000bdab50_1254 .array/port v0000000000bdab50, 1254; +v0000000000bdab50_1255 .array/port v0000000000bdab50, 1255; +v0000000000bdab50_1256 .array/port v0000000000bdab50, 1256; +E_00000000006a3090/314 .event edge, v0000000000bdab50_1253, v0000000000bdab50_1254, v0000000000bdab50_1255, v0000000000bdab50_1256; +v0000000000bdab50_1257 .array/port v0000000000bdab50, 1257; +v0000000000bdab50_1258 .array/port v0000000000bdab50, 1258; +v0000000000bdab50_1259 .array/port v0000000000bdab50, 1259; +v0000000000bdab50_1260 .array/port v0000000000bdab50, 1260; +E_00000000006a3090/315 .event edge, v0000000000bdab50_1257, v0000000000bdab50_1258, v0000000000bdab50_1259, v0000000000bdab50_1260; +v0000000000bdab50_1261 .array/port v0000000000bdab50, 1261; +v0000000000bdab50_1262 .array/port v0000000000bdab50, 1262; +v0000000000bdab50_1263 .array/port v0000000000bdab50, 1263; +v0000000000bdab50_1264 .array/port v0000000000bdab50, 1264; +E_00000000006a3090/316 .event edge, v0000000000bdab50_1261, v0000000000bdab50_1262, v0000000000bdab50_1263, v0000000000bdab50_1264; +v0000000000bdab50_1265 .array/port v0000000000bdab50, 1265; +v0000000000bdab50_1266 .array/port v0000000000bdab50, 1266; +v0000000000bdab50_1267 .array/port v0000000000bdab50, 1267; +v0000000000bdab50_1268 .array/port v0000000000bdab50, 1268; +E_00000000006a3090/317 .event edge, v0000000000bdab50_1265, v0000000000bdab50_1266, v0000000000bdab50_1267, v0000000000bdab50_1268; +v0000000000bdab50_1269 .array/port v0000000000bdab50, 1269; +v0000000000bdab50_1270 .array/port v0000000000bdab50, 1270; +v0000000000bdab50_1271 .array/port v0000000000bdab50, 1271; +v0000000000bdab50_1272 .array/port v0000000000bdab50, 1272; +E_00000000006a3090/318 .event edge, v0000000000bdab50_1269, v0000000000bdab50_1270, v0000000000bdab50_1271, v0000000000bdab50_1272; +v0000000000bdab50_1273 .array/port v0000000000bdab50, 1273; +v0000000000bdab50_1274 .array/port v0000000000bdab50, 1274; +v0000000000bdab50_1275 .array/port v0000000000bdab50, 1275; +v0000000000bdab50_1276 .array/port v0000000000bdab50, 1276; +E_00000000006a3090/319 .event edge, v0000000000bdab50_1273, v0000000000bdab50_1274, v0000000000bdab50_1275, v0000000000bdab50_1276; +v0000000000bdab50_1277 .array/port v0000000000bdab50, 1277; +v0000000000bdab50_1278 .array/port v0000000000bdab50, 1278; +v0000000000bdab50_1279 .array/port v0000000000bdab50, 1279; +v0000000000bdab50_1280 .array/port v0000000000bdab50, 1280; +E_00000000006a3090/320 .event edge, v0000000000bdab50_1277, v0000000000bdab50_1278, v0000000000bdab50_1279, v0000000000bdab50_1280; +v0000000000bdab50_1281 .array/port v0000000000bdab50, 1281; +v0000000000bdab50_1282 .array/port v0000000000bdab50, 1282; +v0000000000bdab50_1283 .array/port v0000000000bdab50, 1283; +v0000000000bdab50_1284 .array/port v0000000000bdab50, 1284; +E_00000000006a3090/321 .event edge, v0000000000bdab50_1281, v0000000000bdab50_1282, v0000000000bdab50_1283, v0000000000bdab50_1284; +v0000000000bdab50_1285 .array/port v0000000000bdab50, 1285; +v0000000000bdab50_1286 .array/port v0000000000bdab50, 1286; +v0000000000bdab50_1287 .array/port v0000000000bdab50, 1287; +v0000000000bdab50_1288 .array/port v0000000000bdab50, 1288; +E_00000000006a3090/322 .event edge, v0000000000bdab50_1285, v0000000000bdab50_1286, v0000000000bdab50_1287, v0000000000bdab50_1288; +v0000000000bdab50_1289 .array/port v0000000000bdab50, 1289; +v0000000000bdab50_1290 .array/port v0000000000bdab50, 1290; +v0000000000bdab50_1291 .array/port v0000000000bdab50, 1291; +v0000000000bdab50_1292 .array/port v0000000000bdab50, 1292; +E_00000000006a3090/323 .event edge, v0000000000bdab50_1289, v0000000000bdab50_1290, v0000000000bdab50_1291, v0000000000bdab50_1292; +v0000000000bdab50_1293 .array/port v0000000000bdab50, 1293; +v0000000000bdab50_1294 .array/port v0000000000bdab50, 1294; +v0000000000bdab50_1295 .array/port v0000000000bdab50, 1295; +v0000000000bdab50_1296 .array/port v0000000000bdab50, 1296; +E_00000000006a3090/324 .event edge, v0000000000bdab50_1293, v0000000000bdab50_1294, v0000000000bdab50_1295, v0000000000bdab50_1296; +v0000000000bdab50_1297 .array/port v0000000000bdab50, 1297; +v0000000000bdab50_1298 .array/port v0000000000bdab50, 1298; +v0000000000bdab50_1299 .array/port v0000000000bdab50, 1299; +v0000000000bdab50_1300 .array/port v0000000000bdab50, 1300; +E_00000000006a3090/325 .event edge, v0000000000bdab50_1297, v0000000000bdab50_1298, v0000000000bdab50_1299, v0000000000bdab50_1300; +v0000000000bdab50_1301 .array/port v0000000000bdab50, 1301; +v0000000000bdab50_1302 .array/port v0000000000bdab50, 1302; +v0000000000bdab50_1303 .array/port v0000000000bdab50, 1303; +v0000000000bdab50_1304 .array/port v0000000000bdab50, 1304; +E_00000000006a3090/326 .event edge, v0000000000bdab50_1301, v0000000000bdab50_1302, v0000000000bdab50_1303, v0000000000bdab50_1304; +v0000000000bdab50_1305 .array/port v0000000000bdab50, 1305; +v0000000000bdab50_1306 .array/port v0000000000bdab50, 1306; +v0000000000bdab50_1307 .array/port v0000000000bdab50, 1307; +v0000000000bdab50_1308 .array/port v0000000000bdab50, 1308; +E_00000000006a3090/327 .event edge, v0000000000bdab50_1305, v0000000000bdab50_1306, v0000000000bdab50_1307, v0000000000bdab50_1308; +v0000000000bdab50_1309 .array/port v0000000000bdab50, 1309; +v0000000000bdab50_1310 .array/port v0000000000bdab50, 1310; +v0000000000bdab50_1311 .array/port v0000000000bdab50, 1311; +v0000000000bdab50_1312 .array/port v0000000000bdab50, 1312; +E_00000000006a3090/328 .event edge, v0000000000bdab50_1309, v0000000000bdab50_1310, v0000000000bdab50_1311, v0000000000bdab50_1312; +v0000000000bdab50_1313 .array/port v0000000000bdab50, 1313; +v0000000000bdab50_1314 .array/port v0000000000bdab50, 1314; +v0000000000bdab50_1315 .array/port v0000000000bdab50, 1315; +v0000000000bdab50_1316 .array/port v0000000000bdab50, 1316; +E_00000000006a3090/329 .event edge, v0000000000bdab50_1313, v0000000000bdab50_1314, v0000000000bdab50_1315, v0000000000bdab50_1316; +v0000000000bdab50_1317 .array/port v0000000000bdab50, 1317; +v0000000000bdab50_1318 .array/port v0000000000bdab50, 1318; +v0000000000bdab50_1319 .array/port v0000000000bdab50, 1319; +v0000000000bdab50_1320 .array/port v0000000000bdab50, 1320; +E_00000000006a3090/330 .event edge, v0000000000bdab50_1317, v0000000000bdab50_1318, v0000000000bdab50_1319, v0000000000bdab50_1320; +v0000000000bdab50_1321 .array/port v0000000000bdab50, 1321; +v0000000000bdab50_1322 .array/port v0000000000bdab50, 1322; +v0000000000bdab50_1323 .array/port v0000000000bdab50, 1323; +v0000000000bdab50_1324 .array/port v0000000000bdab50, 1324; +E_00000000006a3090/331 .event edge, v0000000000bdab50_1321, v0000000000bdab50_1322, v0000000000bdab50_1323, v0000000000bdab50_1324; +v0000000000bdab50_1325 .array/port v0000000000bdab50, 1325; +v0000000000bdab50_1326 .array/port v0000000000bdab50, 1326; +v0000000000bdab50_1327 .array/port v0000000000bdab50, 1327; +v0000000000bdab50_1328 .array/port v0000000000bdab50, 1328; +E_00000000006a3090/332 .event edge, v0000000000bdab50_1325, v0000000000bdab50_1326, v0000000000bdab50_1327, v0000000000bdab50_1328; +v0000000000bdab50_1329 .array/port v0000000000bdab50, 1329; +v0000000000bdab50_1330 .array/port v0000000000bdab50, 1330; +v0000000000bdab50_1331 .array/port v0000000000bdab50, 1331; +v0000000000bdab50_1332 .array/port v0000000000bdab50, 1332; +E_00000000006a3090/333 .event edge, v0000000000bdab50_1329, v0000000000bdab50_1330, v0000000000bdab50_1331, v0000000000bdab50_1332; +v0000000000bdab50_1333 .array/port v0000000000bdab50, 1333; +v0000000000bdab50_1334 .array/port v0000000000bdab50, 1334; +v0000000000bdab50_1335 .array/port v0000000000bdab50, 1335; +v0000000000bdab50_1336 .array/port v0000000000bdab50, 1336; +E_00000000006a3090/334 .event edge, v0000000000bdab50_1333, v0000000000bdab50_1334, v0000000000bdab50_1335, v0000000000bdab50_1336; +v0000000000bdab50_1337 .array/port v0000000000bdab50, 1337; +v0000000000bdab50_1338 .array/port v0000000000bdab50, 1338; +v0000000000bdab50_1339 .array/port v0000000000bdab50, 1339; +v0000000000bdab50_1340 .array/port v0000000000bdab50, 1340; +E_00000000006a3090/335 .event edge, v0000000000bdab50_1337, v0000000000bdab50_1338, v0000000000bdab50_1339, v0000000000bdab50_1340; +v0000000000bdab50_1341 .array/port v0000000000bdab50, 1341; +v0000000000bdab50_1342 .array/port v0000000000bdab50, 1342; +v0000000000bdab50_1343 .array/port v0000000000bdab50, 1343; +v0000000000bdab50_1344 .array/port v0000000000bdab50, 1344; +E_00000000006a3090/336 .event edge, v0000000000bdab50_1341, v0000000000bdab50_1342, v0000000000bdab50_1343, v0000000000bdab50_1344; +v0000000000bdab50_1345 .array/port v0000000000bdab50, 1345; +v0000000000bdab50_1346 .array/port v0000000000bdab50, 1346; +v0000000000bdab50_1347 .array/port v0000000000bdab50, 1347; +v0000000000bdab50_1348 .array/port v0000000000bdab50, 1348; +E_00000000006a3090/337 .event edge, v0000000000bdab50_1345, v0000000000bdab50_1346, v0000000000bdab50_1347, v0000000000bdab50_1348; +v0000000000bdab50_1349 .array/port v0000000000bdab50, 1349; +v0000000000bdab50_1350 .array/port v0000000000bdab50, 1350; +v0000000000bdab50_1351 .array/port v0000000000bdab50, 1351; +v0000000000bdab50_1352 .array/port v0000000000bdab50, 1352; +E_00000000006a3090/338 .event edge, v0000000000bdab50_1349, v0000000000bdab50_1350, v0000000000bdab50_1351, v0000000000bdab50_1352; +v0000000000bdab50_1353 .array/port v0000000000bdab50, 1353; +v0000000000bdab50_1354 .array/port v0000000000bdab50, 1354; +v0000000000bdab50_1355 .array/port v0000000000bdab50, 1355; +v0000000000bdab50_1356 .array/port v0000000000bdab50, 1356; +E_00000000006a3090/339 .event edge, v0000000000bdab50_1353, v0000000000bdab50_1354, v0000000000bdab50_1355, v0000000000bdab50_1356; +v0000000000bdab50_1357 .array/port v0000000000bdab50, 1357; +v0000000000bdab50_1358 .array/port v0000000000bdab50, 1358; +v0000000000bdab50_1359 .array/port v0000000000bdab50, 1359; +v0000000000bdab50_1360 .array/port v0000000000bdab50, 1360; +E_00000000006a3090/340 .event edge, v0000000000bdab50_1357, v0000000000bdab50_1358, v0000000000bdab50_1359, v0000000000bdab50_1360; +v0000000000bdab50_1361 .array/port v0000000000bdab50, 1361; +v0000000000bdab50_1362 .array/port v0000000000bdab50, 1362; +v0000000000bdab50_1363 .array/port v0000000000bdab50, 1363; +v0000000000bdab50_1364 .array/port v0000000000bdab50, 1364; +E_00000000006a3090/341 .event edge, v0000000000bdab50_1361, v0000000000bdab50_1362, v0000000000bdab50_1363, v0000000000bdab50_1364; +v0000000000bdab50_1365 .array/port v0000000000bdab50, 1365; +v0000000000bdab50_1366 .array/port v0000000000bdab50, 1366; +v0000000000bdab50_1367 .array/port v0000000000bdab50, 1367; +v0000000000bdab50_1368 .array/port v0000000000bdab50, 1368; +E_00000000006a3090/342 .event edge, v0000000000bdab50_1365, v0000000000bdab50_1366, v0000000000bdab50_1367, v0000000000bdab50_1368; +v0000000000bdab50_1369 .array/port v0000000000bdab50, 1369; +v0000000000bdab50_1370 .array/port v0000000000bdab50, 1370; +v0000000000bdab50_1371 .array/port v0000000000bdab50, 1371; +v0000000000bdab50_1372 .array/port v0000000000bdab50, 1372; +E_00000000006a3090/343 .event edge, v0000000000bdab50_1369, v0000000000bdab50_1370, v0000000000bdab50_1371, v0000000000bdab50_1372; +v0000000000bdab50_1373 .array/port v0000000000bdab50, 1373; +v0000000000bdab50_1374 .array/port v0000000000bdab50, 1374; +v0000000000bdab50_1375 .array/port v0000000000bdab50, 1375; +v0000000000bdab50_1376 .array/port v0000000000bdab50, 1376; +E_00000000006a3090/344 .event edge, v0000000000bdab50_1373, v0000000000bdab50_1374, v0000000000bdab50_1375, v0000000000bdab50_1376; +v0000000000bdab50_1377 .array/port v0000000000bdab50, 1377; +v0000000000bdab50_1378 .array/port v0000000000bdab50, 1378; +v0000000000bdab50_1379 .array/port v0000000000bdab50, 1379; +v0000000000bdab50_1380 .array/port v0000000000bdab50, 1380; +E_00000000006a3090/345 .event edge, v0000000000bdab50_1377, v0000000000bdab50_1378, v0000000000bdab50_1379, v0000000000bdab50_1380; +v0000000000bdab50_1381 .array/port v0000000000bdab50, 1381; +v0000000000bdab50_1382 .array/port v0000000000bdab50, 1382; +v0000000000bdab50_1383 .array/port v0000000000bdab50, 1383; +v0000000000bdab50_1384 .array/port v0000000000bdab50, 1384; +E_00000000006a3090/346 .event edge, v0000000000bdab50_1381, v0000000000bdab50_1382, v0000000000bdab50_1383, v0000000000bdab50_1384; +v0000000000bdab50_1385 .array/port v0000000000bdab50, 1385; +v0000000000bdab50_1386 .array/port v0000000000bdab50, 1386; +v0000000000bdab50_1387 .array/port v0000000000bdab50, 1387; +v0000000000bdab50_1388 .array/port v0000000000bdab50, 1388; +E_00000000006a3090/347 .event edge, v0000000000bdab50_1385, v0000000000bdab50_1386, v0000000000bdab50_1387, v0000000000bdab50_1388; +v0000000000bdab50_1389 .array/port v0000000000bdab50, 1389; +v0000000000bdab50_1390 .array/port v0000000000bdab50, 1390; +v0000000000bdab50_1391 .array/port v0000000000bdab50, 1391; +v0000000000bdab50_1392 .array/port v0000000000bdab50, 1392; +E_00000000006a3090/348 .event edge, v0000000000bdab50_1389, v0000000000bdab50_1390, v0000000000bdab50_1391, v0000000000bdab50_1392; +v0000000000bdab50_1393 .array/port v0000000000bdab50, 1393; +v0000000000bdab50_1394 .array/port v0000000000bdab50, 1394; +v0000000000bdab50_1395 .array/port v0000000000bdab50, 1395; +v0000000000bdab50_1396 .array/port v0000000000bdab50, 1396; +E_00000000006a3090/349 .event edge, v0000000000bdab50_1393, v0000000000bdab50_1394, v0000000000bdab50_1395, v0000000000bdab50_1396; +v0000000000bdab50_1397 .array/port v0000000000bdab50, 1397; +v0000000000bdab50_1398 .array/port v0000000000bdab50, 1398; +v0000000000bdab50_1399 .array/port v0000000000bdab50, 1399; +v0000000000bdab50_1400 .array/port v0000000000bdab50, 1400; +E_00000000006a3090/350 .event edge, v0000000000bdab50_1397, v0000000000bdab50_1398, v0000000000bdab50_1399, v0000000000bdab50_1400; +v0000000000bdab50_1401 .array/port v0000000000bdab50, 1401; +v0000000000bdab50_1402 .array/port v0000000000bdab50, 1402; +v0000000000bdab50_1403 .array/port v0000000000bdab50, 1403; +v0000000000bdab50_1404 .array/port v0000000000bdab50, 1404; +E_00000000006a3090/351 .event edge, v0000000000bdab50_1401, v0000000000bdab50_1402, v0000000000bdab50_1403, v0000000000bdab50_1404; +v0000000000bdab50_1405 .array/port v0000000000bdab50, 1405; +v0000000000bdab50_1406 .array/port v0000000000bdab50, 1406; +v0000000000bdab50_1407 .array/port v0000000000bdab50, 1407; +v0000000000bdab50_1408 .array/port v0000000000bdab50, 1408; +E_00000000006a3090/352 .event edge, v0000000000bdab50_1405, v0000000000bdab50_1406, v0000000000bdab50_1407, v0000000000bdab50_1408; +v0000000000bdab50_1409 .array/port v0000000000bdab50, 1409; +v0000000000bdab50_1410 .array/port v0000000000bdab50, 1410; +v0000000000bdab50_1411 .array/port v0000000000bdab50, 1411; +v0000000000bdab50_1412 .array/port v0000000000bdab50, 1412; +E_00000000006a3090/353 .event edge, v0000000000bdab50_1409, v0000000000bdab50_1410, v0000000000bdab50_1411, v0000000000bdab50_1412; +v0000000000bdab50_1413 .array/port v0000000000bdab50, 1413; +v0000000000bdab50_1414 .array/port v0000000000bdab50, 1414; +v0000000000bdab50_1415 .array/port v0000000000bdab50, 1415; +v0000000000bdab50_1416 .array/port v0000000000bdab50, 1416; +E_00000000006a3090/354 .event edge, v0000000000bdab50_1413, v0000000000bdab50_1414, v0000000000bdab50_1415, v0000000000bdab50_1416; +v0000000000bdab50_1417 .array/port v0000000000bdab50, 1417; +v0000000000bdab50_1418 .array/port v0000000000bdab50, 1418; +v0000000000bdab50_1419 .array/port v0000000000bdab50, 1419; +v0000000000bdab50_1420 .array/port v0000000000bdab50, 1420; +E_00000000006a3090/355 .event edge, v0000000000bdab50_1417, v0000000000bdab50_1418, v0000000000bdab50_1419, v0000000000bdab50_1420; +v0000000000bdab50_1421 .array/port v0000000000bdab50, 1421; +v0000000000bdab50_1422 .array/port v0000000000bdab50, 1422; +v0000000000bdab50_1423 .array/port v0000000000bdab50, 1423; +v0000000000bdab50_1424 .array/port v0000000000bdab50, 1424; +E_00000000006a3090/356 .event edge, v0000000000bdab50_1421, v0000000000bdab50_1422, v0000000000bdab50_1423, v0000000000bdab50_1424; +v0000000000bdab50_1425 .array/port v0000000000bdab50, 1425; +v0000000000bdab50_1426 .array/port v0000000000bdab50, 1426; +v0000000000bdab50_1427 .array/port v0000000000bdab50, 1427; +v0000000000bdab50_1428 .array/port v0000000000bdab50, 1428; +E_00000000006a3090/357 .event edge, v0000000000bdab50_1425, v0000000000bdab50_1426, v0000000000bdab50_1427, v0000000000bdab50_1428; +v0000000000bdab50_1429 .array/port v0000000000bdab50, 1429; +v0000000000bdab50_1430 .array/port v0000000000bdab50, 1430; +v0000000000bdab50_1431 .array/port v0000000000bdab50, 1431; +v0000000000bdab50_1432 .array/port v0000000000bdab50, 1432; +E_00000000006a3090/358 .event edge, v0000000000bdab50_1429, v0000000000bdab50_1430, v0000000000bdab50_1431, v0000000000bdab50_1432; +v0000000000bdab50_1433 .array/port v0000000000bdab50, 1433; +v0000000000bdab50_1434 .array/port v0000000000bdab50, 1434; +v0000000000bdab50_1435 .array/port v0000000000bdab50, 1435; +v0000000000bdab50_1436 .array/port v0000000000bdab50, 1436; +E_00000000006a3090/359 .event edge, v0000000000bdab50_1433, v0000000000bdab50_1434, v0000000000bdab50_1435, v0000000000bdab50_1436; +v0000000000bdab50_1437 .array/port v0000000000bdab50, 1437; +v0000000000bdab50_1438 .array/port v0000000000bdab50, 1438; +v0000000000bdab50_1439 .array/port v0000000000bdab50, 1439; +v0000000000bdab50_1440 .array/port v0000000000bdab50, 1440; +E_00000000006a3090/360 .event edge, v0000000000bdab50_1437, v0000000000bdab50_1438, v0000000000bdab50_1439, v0000000000bdab50_1440; +v0000000000bdab50_1441 .array/port v0000000000bdab50, 1441; +v0000000000bdab50_1442 .array/port v0000000000bdab50, 1442; +v0000000000bdab50_1443 .array/port v0000000000bdab50, 1443; +v0000000000bdab50_1444 .array/port v0000000000bdab50, 1444; +E_00000000006a3090/361 .event edge, v0000000000bdab50_1441, v0000000000bdab50_1442, v0000000000bdab50_1443, v0000000000bdab50_1444; +v0000000000bdab50_1445 .array/port v0000000000bdab50, 1445; +v0000000000bdab50_1446 .array/port v0000000000bdab50, 1446; +v0000000000bdab50_1447 .array/port v0000000000bdab50, 1447; +v0000000000bdab50_1448 .array/port v0000000000bdab50, 1448; +E_00000000006a3090/362 .event edge, v0000000000bdab50_1445, v0000000000bdab50_1446, v0000000000bdab50_1447, v0000000000bdab50_1448; +v0000000000bdab50_1449 .array/port v0000000000bdab50, 1449; +v0000000000bdab50_1450 .array/port v0000000000bdab50, 1450; +v0000000000bdab50_1451 .array/port v0000000000bdab50, 1451; +v0000000000bdab50_1452 .array/port v0000000000bdab50, 1452; +E_00000000006a3090/363 .event edge, v0000000000bdab50_1449, v0000000000bdab50_1450, v0000000000bdab50_1451, v0000000000bdab50_1452; +v0000000000bdab50_1453 .array/port v0000000000bdab50, 1453; +v0000000000bdab50_1454 .array/port v0000000000bdab50, 1454; +v0000000000bdab50_1455 .array/port v0000000000bdab50, 1455; +v0000000000bdab50_1456 .array/port v0000000000bdab50, 1456; +E_00000000006a3090/364 .event edge, v0000000000bdab50_1453, v0000000000bdab50_1454, v0000000000bdab50_1455, v0000000000bdab50_1456; +v0000000000bdab50_1457 .array/port v0000000000bdab50, 1457; +v0000000000bdab50_1458 .array/port v0000000000bdab50, 1458; +v0000000000bdab50_1459 .array/port v0000000000bdab50, 1459; +v0000000000bdab50_1460 .array/port v0000000000bdab50, 1460; +E_00000000006a3090/365 .event edge, v0000000000bdab50_1457, v0000000000bdab50_1458, v0000000000bdab50_1459, v0000000000bdab50_1460; +v0000000000bdab50_1461 .array/port v0000000000bdab50, 1461; +v0000000000bdab50_1462 .array/port v0000000000bdab50, 1462; +v0000000000bdab50_1463 .array/port v0000000000bdab50, 1463; +v0000000000bdab50_1464 .array/port v0000000000bdab50, 1464; +E_00000000006a3090/366 .event edge, v0000000000bdab50_1461, v0000000000bdab50_1462, v0000000000bdab50_1463, v0000000000bdab50_1464; +v0000000000bdab50_1465 .array/port v0000000000bdab50, 1465; +v0000000000bdab50_1466 .array/port v0000000000bdab50, 1466; +v0000000000bdab50_1467 .array/port v0000000000bdab50, 1467; +v0000000000bdab50_1468 .array/port v0000000000bdab50, 1468; +E_00000000006a3090/367 .event edge, v0000000000bdab50_1465, v0000000000bdab50_1466, v0000000000bdab50_1467, v0000000000bdab50_1468; +v0000000000bdab50_1469 .array/port v0000000000bdab50, 1469; +v0000000000bdab50_1470 .array/port v0000000000bdab50, 1470; +v0000000000bdab50_1471 .array/port v0000000000bdab50, 1471; +v0000000000bdab50_1472 .array/port v0000000000bdab50, 1472; +E_00000000006a3090/368 .event edge, v0000000000bdab50_1469, v0000000000bdab50_1470, v0000000000bdab50_1471, v0000000000bdab50_1472; +v0000000000bdab50_1473 .array/port v0000000000bdab50, 1473; +v0000000000bdab50_1474 .array/port v0000000000bdab50, 1474; +v0000000000bdab50_1475 .array/port v0000000000bdab50, 1475; +v0000000000bdab50_1476 .array/port v0000000000bdab50, 1476; +E_00000000006a3090/369 .event edge, v0000000000bdab50_1473, v0000000000bdab50_1474, v0000000000bdab50_1475, v0000000000bdab50_1476; +v0000000000bdab50_1477 .array/port v0000000000bdab50, 1477; +v0000000000bdab50_1478 .array/port v0000000000bdab50, 1478; +v0000000000bdab50_1479 .array/port v0000000000bdab50, 1479; +v0000000000bdab50_1480 .array/port v0000000000bdab50, 1480; +E_00000000006a3090/370 .event edge, v0000000000bdab50_1477, v0000000000bdab50_1478, v0000000000bdab50_1479, v0000000000bdab50_1480; +v0000000000bdab50_1481 .array/port v0000000000bdab50, 1481; +v0000000000bdab50_1482 .array/port v0000000000bdab50, 1482; +v0000000000bdab50_1483 .array/port v0000000000bdab50, 1483; +v0000000000bdab50_1484 .array/port v0000000000bdab50, 1484; +E_00000000006a3090/371 .event edge, v0000000000bdab50_1481, v0000000000bdab50_1482, v0000000000bdab50_1483, v0000000000bdab50_1484; +v0000000000bdab50_1485 .array/port v0000000000bdab50, 1485; +v0000000000bdab50_1486 .array/port v0000000000bdab50, 1486; +v0000000000bdab50_1487 .array/port v0000000000bdab50, 1487; +v0000000000bdab50_1488 .array/port v0000000000bdab50, 1488; +E_00000000006a3090/372 .event edge, v0000000000bdab50_1485, v0000000000bdab50_1486, v0000000000bdab50_1487, v0000000000bdab50_1488; +v0000000000bdab50_1489 .array/port v0000000000bdab50, 1489; +v0000000000bdab50_1490 .array/port v0000000000bdab50, 1490; +v0000000000bdab50_1491 .array/port v0000000000bdab50, 1491; +v0000000000bdab50_1492 .array/port v0000000000bdab50, 1492; +E_00000000006a3090/373 .event edge, v0000000000bdab50_1489, v0000000000bdab50_1490, v0000000000bdab50_1491, v0000000000bdab50_1492; +v0000000000bdab50_1493 .array/port v0000000000bdab50, 1493; +v0000000000bdab50_1494 .array/port v0000000000bdab50, 1494; +v0000000000bdab50_1495 .array/port v0000000000bdab50, 1495; +v0000000000bdab50_1496 .array/port v0000000000bdab50, 1496; +E_00000000006a3090/374 .event edge, v0000000000bdab50_1493, v0000000000bdab50_1494, v0000000000bdab50_1495, v0000000000bdab50_1496; +v0000000000bdab50_1497 .array/port v0000000000bdab50, 1497; +v0000000000bdab50_1498 .array/port v0000000000bdab50, 1498; +v0000000000bdab50_1499 .array/port v0000000000bdab50, 1499; +v0000000000bdab50_1500 .array/port v0000000000bdab50, 1500; +E_00000000006a3090/375 .event edge, v0000000000bdab50_1497, v0000000000bdab50_1498, v0000000000bdab50_1499, v0000000000bdab50_1500; +v0000000000bdab50_1501 .array/port v0000000000bdab50, 1501; +v0000000000bdab50_1502 .array/port v0000000000bdab50, 1502; +v0000000000bdab50_1503 .array/port v0000000000bdab50, 1503; +v0000000000bdab50_1504 .array/port v0000000000bdab50, 1504; +E_00000000006a3090/376 .event edge, v0000000000bdab50_1501, v0000000000bdab50_1502, v0000000000bdab50_1503, v0000000000bdab50_1504; +v0000000000bdab50_1505 .array/port v0000000000bdab50, 1505; +v0000000000bdab50_1506 .array/port v0000000000bdab50, 1506; +v0000000000bdab50_1507 .array/port v0000000000bdab50, 1507; +v0000000000bdab50_1508 .array/port v0000000000bdab50, 1508; +E_00000000006a3090/377 .event edge, v0000000000bdab50_1505, v0000000000bdab50_1506, v0000000000bdab50_1507, v0000000000bdab50_1508; +v0000000000bdab50_1509 .array/port v0000000000bdab50, 1509; +v0000000000bdab50_1510 .array/port v0000000000bdab50, 1510; +v0000000000bdab50_1511 .array/port v0000000000bdab50, 1511; +v0000000000bdab50_1512 .array/port v0000000000bdab50, 1512; +E_00000000006a3090/378 .event edge, v0000000000bdab50_1509, v0000000000bdab50_1510, v0000000000bdab50_1511, v0000000000bdab50_1512; +v0000000000bdab50_1513 .array/port v0000000000bdab50, 1513; +v0000000000bdab50_1514 .array/port v0000000000bdab50, 1514; +v0000000000bdab50_1515 .array/port v0000000000bdab50, 1515; +v0000000000bdab50_1516 .array/port v0000000000bdab50, 1516; +E_00000000006a3090/379 .event edge, v0000000000bdab50_1513, v0000000000bdab50_1514, v0000000000bdab50_1515, v0000000000bdab50_1516; +v0000000000bdab50_1517 .array/port v0000000000bdab50, 1517; +v0000000000bdab50_1518 .array/port v0000000000bdab50, 1518; +v0000000000bdab50_1519 .array/port v0000000000bdab50, 1519; +v0000000000bdab50_1520 .array/port v0000000000bdab50, 1520; +E_00000000006a3090/380 .event edge, v0000000000bdab50_1517, v0000000000bdab50_1518, v0000000000bdab50_1519, v0000000000bdab50_1520; +v0000000000bdab50_1521 .array/port v0000000000bdab50, 1521; +v0000000000bdab50_1522 .array/port v0000000000bdab50, 1522; +v0000000000bdab50_1523 .array/port v0000000000bdab50, 1523; +v0000000000bdab50_1524 .array/port v0000000000bdab50, 1524; +E_00000000006a3090/381 .event edge, v0000000000bdab50_1521, v0000000000bdab50_1522, v0000000000bdab50_1523, v0000000000bdab50_1524; +v0000000000bdab50_1525 .array/port v0000000000bdab50, 1525; +v0000000000bdab50_1526 .array/port v0000000000bdab50, 1526; +v0000000000bdab50_1527 .array/port v0000000000bdab50, 1527; +v0000000000bdab50_1528 .array/port v0000000000bdab50, 1528; +E_00000000006a3090/382 .event edge, v0000000000bdab50_1525, v0000000000bdab50_1526, v0000000000bdab50_1527, v0000000000bdab50_1528; +v0000000000bdab50_1529 .array/port v0000000000bdab50, 1529; +v0000000000bdab50_1530 .array/port v0000000000bdab50, 1530; +v0000000000bdab50_1531 .array/port v0000000000bdab50, 1531; +v0000000000bdab50_1532 .array/port v0000000000bdab50, 1532; +E_00000000006a3090/383 .event edge, v0000000000bdab50_1529, v0000000000bdab50_1530, v0000000000bdab50_1531, v0000000000bdab50_1532; +v0000000000bdab50_1533 .array/port v0000000000bdab50, 1533; +v0000000000bdab50_1534 .array/port v0000000000bdab50, 1534; +v0000000000bdab50_1535 .array/port v0000000000bdab50, 1535; +v0000000000bdab50_1536 .array/port v0000000000bdab50, 1536; +E_00000000006a3090/384 .event edge, v0000000000bdab50_1533, v0000000000bdab50_1534, v0000000000bdab50_1535, v0000000000bdab50_1536; +v0000000000bdab50_1537 .array/port v0000000000bdab50, 1537; +v0000000000bdab50_1538 .array/port v0000000000bdab50, 1538; +v0000000000bdab50_1539 .array/port v0000000000bdab50, 1539; +v0000000000bdab50_1540 .array/port v0000000000bdab50, 1540; +E_00000000006a3090/385 .event edge, v0000000000bdab50_1537, v0000000000bdab50_1538, v0000000000bdab50_1539, v0000000000bdab50_1540; +v0000000000bdab50_1541 .array/port v0000000000bdab50, 1541; +v0000000000bdab50_1542 .array/port v0000000000bdab50, 1542; +v0000000000bdab50_1543 .array/port v0000000000bdab50, 1543; +v0000000000bdab50_1544 .array/port v0000000000bdab50, 1544; +E_00000000006a3090/386 .event edge, v0000000000bdab50_1541, v0000000000bdab50_1542, v0000000000bdab50_1543, v0000000000bdab50_1544; +v0000000000bdab50_1545 .array/port v0000000000bdab50, 1545; +v0000000000bdab50_1546 .array/port v0000000000bdab50, 1546; +v0000000000bdab50_1547 .array/port v0000000000bdab50, 1547; +v0000000000bdab50_1548 .array/port v0000000000bdab50, 1548; +E_00000000006a3090/387 .event edge, v0000000000bdab50_1545, v0000000000bdab50_1546, v0000000000bdab50_1547, v0000000000bdab50_1548; +v0000000000bdab50_1549 .array/port v0000000000bdab50, 1549; +v0000000000bdab50_1550 .array/port v0000000000bdab50, 1550; +v0000000000bdab50_1551 .array/port v0000000000bdab50, 1551; +v0000000000bdab50_1552 .array/port v0000000000bdab50, 1552; +E_00000000006a3090/388 .event edge, v0000000000bdab50_1549, v0000000000bdab50_1550, v0000000000bdab50_1551, v0000000000bdab50_1552; +v0000000000bdab50_1553 .array/port v0000000000bdab50, 1553; +v0000000000bdab50_1554 .array/port v0000000000bdab50, 1554; +v0000000000bdab50_1555 .array/port v0000000000bdab50, 1555; +v0000000000bdab50_1556 .array/port v0000000000bdab50, 1556; +E_00000000006a3090/389 .event edge, v0000000000bdab50_1553, v0000000000bdab50_1554, v0000000000bdab50_1555, v0000000000bdab50_1556; +v0000000000bdab50_1557 .array/port v0000000000bdab50, 1557; +v0000000000bdab50_1558 .array/port v0000000000bdab50, 1558; +v0000000000bdab50_1559 .array/port v0000000000bdab50, 1559; +v0000000000bdab50_1560 .array/port v0000000000bdab50, 1560; +E_00000000006a3090/390 .event edge, v0000000000bdab50_1557, v0000000000bdab50_1558, v0000000000bdab50_1559, v0000000000bdab50_1560; +v0000000000bdab50_1561 .array/port v0000000000bdab50, 1561; +v0000000000bdab50_1562 .array/port v0000000000bdab50, 1562; +v0000000000bdab50_1563 .array/port v0000000000bdab50, 1563; +v0000000000bdab50_1564 .array/port v0000000000bdab50, 1564; +E_00000000006a3090/391 .event edge, v0000000000bdab50_1561, v0000000000bdab50_1562, v0000000000bdab50_1563, v0000000000bdab50_1564; +v0000000000bdab50_1565 .array/port v0000000000bdab50, 1565; +v0000000000bdab50_1566 .array/port v0000000000bdab50, 1566; +v0000000000bdab50_1567 .array/port v0000000000bdab50, 1567; +v0000000000bdab50_1568 .array/port v0000000000bdab50, 1568; +E_00000000006a3090/392 .event edge, v0000000000bdab50_1565, v0000000000bdab50_1566, v0000000000bdab50_1567, v0000000000bdab50_1568; +v0000000000bdab50_1569 .array/port v0000000000bdab50, 1569; +v0000000000bdab50_1570 .array/port v0000000000bdab50, 1570; +v0000000000bdab50_1571 .array/port v0000000000bdab50, 1571; +v0000000000bdab50_1572 .array/port v0000000000bdab50, 1572; +E_00000000006a3090/393 .event edge, v0000000000bdab50_1569, v0000000000bdab50_1570, v0000000000bdab50_1571, v0000000000bdab50_1572; +v0000000000bdab50_1573 .array/port v0000000000bdab50, 1573; +v0000000000bdab50_1574 .array/port v0000000000bdab50, 1574; +v0000000000bdab50_1575 .array/port v0000000000bdab50, 1575; +v0000000000bdab50_1576 .array/port v0000000000bdab50, 1576; +E_00000000006a3090/394 .event edge, v0000000000bdab50_1573, v0000000000bdab50_1574, v0000000000bdab50_1575, v0000000000bdab50_1576; +v0000000000bdab50_1577 .array/port v0000000000bdab50, 1577; +v0000000000bdab50_1578 .array/port v0000000000bdab50, 1578; +v0000000000bdab50_1579 .array/port v0000000000bdab50, 1579; +v0000000000bdab50_1580 .array/port v0000000000bdab50, 1580; +E_00000000006a3090/395 .event edge, v0000000000bdab50_1577, v0000000000bdab50_1578, v0000000000bdab50_1579, v0000000000bdab50_1580; +v0000000000bdab50_1581 .array/port v0000000000bdab50, 1581; +v0000000000bdab50_1582 .array/port v0000000000bdab50, 1582; +v0000000000bdab50_1583 .array/port v0000000000bdab50, 1583; +v0000000000bdab50_1584 .array/port v0000000000bdab50, 1584; +E_00000000006a3090/396 .event edge, v0000000000bdab50_1581, v0000000000bdab50_1582, v0000000000bdab50_1583, v0000000000bdab50_1584; +v0000000000bdab50_1585 .array/port v0000000000bdab50, 1585; +v0000000000bdab50_1586 .array/port v0000000000bdab50, 1586; +v0000000000bdab50_1587 .array/port v0000000000bdab50, 1587; +v0000000000bdab50_1588 .array/port v0000000000bdab50, 1588; +E_00000000006a3090/397 .event edge, v0000000000bdab50_1585, v0000000000bdab50_1586, v0000000000bdab50_1587, v0000000000bdab50_1588; +v0000000000bdab50_1589 .array/port v0000000000bdab50, 1589; +v0000000000bdab50_1590 .array/port v0000000000bdab50, 1590; +v0000000000bdab50_1591 .array/port v0000000000bdab50, 1591; +v0000000000bdab50_1592 .array/port v0000000000bdab50, 1592; +E_00000000006a3090/398 .event edge, v0000000000bdab50_1589, v0000000000bdab50_1590, v0000000000bdab50_1591, v0000000000bdab50_1592; +v0000000000bdab50_1593 .array/port v0000000000bdab50, 1593; +v0000000000bdab50_1594 .array/port v0000000000bdab50, 1594; +v0000000000bdab50_1595 .array/port v0000000000bdab50, 1595; +v0000000000bdab50_1596 .array/port v0000000000bdab50, 1596; +E_00000000006a3090/399 .event edge, v0000000000bdab50_1593, v0000000000bdab50_1594, v0000000000bdab50_1595, v0000000000bdab50_1596; +v0000000000bdab50_1597 .array/port v0000000000bdab50, 1597; +v0000000000bdab50_1598 .array/port v0000000000bdab50, 1598; +v0000000000bdab50_1599 .array/port v0000000000bdab50, 1599; +v0000000000bdab50_1600 .array/port v0000000000bdab50, 1600; +E_00000000006a3090/400 .event edge, v0000000000bdab50_1597, v0000000000bdab50_1598, v0000000000bdab50_1599, v0000000000bdab50_1600; +v0000000000bdab50_1601 .array/port v0000000000bdab50, 1601; +v0000000000bdab50_1602 .array/port v0000000000bdab50, 1602; +v0000000000bdab50_1603 .array/port v0000000000bdab50, 1603; +v0000000000bdab50_1604 .array/port v0000000000bdab50, 1604; +E_00000000006a3090/401 .event edge, v0000000000bdab50_1601, v0000000000bdab50_1602, v0000000000bdab50_1603, v0000000000bdab50_1604; +v0000000000bdab50_1605 .array/port v0000000000bdab50, 1605; +v0000000000bdab50_1606 .array/port v0000000000bdab50, 1606; +v0000000000bdab50_1607 .array/port v0000000000bdab50, 1607; +v0000000000bdab50_1608 .array/port v0000000000bdab50, 1608; +E_00000000006a3090/402 .event edge, v0000000000bdab50_1605, v0000000000bdab50_1606, v0000000000bdab50_1607, v0000000000bdab50_1608; +v0000000000bdab50_1609 .array/port v0000000000bdab50, 1609; +v0000000000bdab50_1610 .array/port v0000000000bdab50, 1610; +v0000000000bdab50_1611 .array/port v0000000000bdab50, 1611; +v0000000000bdab50_1612 .array/port v0000000000bdab50, 1612; +E_00000000006a3090/403 .event edge, v0000000000bdab50_1609, v0000000000bdab50_1610, v0000000000bdab50_1611, v0000000000bdab50_1612; +v0000000000bdab50_1613 .array/port v0000000000bdab50, 1613; +v0000000000bdab50_1614 .array/port v0000000000bdab50, 1614; +v0000000000bdab50_1615 .array/port v0000000000bdab50, 1615; +v0000000000bdab50_1616 .array/port v0000000000bdab50, 1616; +E_00000000006a3090/404 .event edge, v0000000000bdab50_1613, v0000000000bdab50_1614, v0000000000bdab50_1615, v0000000000bdab50_1616; +v0000000000bdab50_1617 .array/port v0000000000bdab50, 1617; +v0000000000bdab50_1618 .array/port v0000000000bdab50, 1618; +v0000000000bdab50_1619 .array/port v0000000000bdab50, 1619; +v0000000000bdab50_1620 .array/port v0000000000bdab50, 1620; +E_00000000006a3090/405 .event edge, v0000000000bdab50_1617, v0000000000bdab50_1618, v0000000000bdab50_1619, v0000000000bdab50_1620; +v0000000000bdab50_1621 .array/port v0000000000bdab50, 1621; +v0000000000bdab50_1622 .array/port v0000000000bdab50, 1622; +v0000000000bdab50_1623 .array/port v0000000000bdab50, 1623; +v0000000000bdab50_1624 .array/port v0000000000bdab50, 1624; +E_00000000006a3090/406 .event edge, v0000000000bdab50_1621, v0000000000bdab50_1622, v0000000000bdab50_1623, v0000000000bdab50_1624; +v0000000000bdab50_1625 .array/port v0000000000bdab50, 1625; +v0000000000bdab50_1626 .array/port v0000000000bdab50, 1626; +v0000000000bdab50_1627 .array/port v0000000000bdab50, 1627; +v0000000000bdab50_1628 .array/port v0000000000bdab50, 1628; +E_00000000006a3090/407 .event edge, v0000000000bdab50_1625, v0000000000bdab50_1626, v0000000000bdab50_1627, v0000000000bdab50_1628; +v0000000000bdab50_1629 .array/port v0000000000bdab50, 1629; +v0000000000bdab50_1630 .array/port v0000000000bdab50, 1630; +v0000000000bdab50_1631 .array/port v0000000000bdab50, 1631; +v0000000000bdab50_1632 .array/port v0000000000bdab50, 1632; +E_00000000006a3090/408 .event edge, v0000000000bdab50_1629, v0000000000bdab50_1630, v0000000000bdab50_1631, v0000000000bdab50_1632; +v0000000000bdab50_1633 .array/port v0000000000bdab50, 1633; +v0000000000bdab50_1634 .array/port v0000000000bdab50, 1634; +v0000000000bdab50_1635 .array/port v0000000000bdab50, 1635; +v0000000000bdab50_1636 .array/port v0000000000bdab50, 1636; +E_00000000006a3090/409 .event edge, v0000000000bdab50_1633, v0000000000bdab50_1634, v0000000000bdab50_1635, v0000000000bdab50_1636; +v0000000000bdab50_1637 .array/port v0000000000bdab50, 1637; +v0000000000bdab50_1638 .array/port v0000000000bdab50, 1638; +v0000000000bdab50_1639 .array/port v0000000000bdab50, 1639; +v0000000000bdab50_1640 .array/port v0000000000bdab50, 1640; +E_00000000006a3090/410 .event edge, v0000000000bdab50_1637, v0000000000bdab50_1638, v0000000000bdab50_1639, v0000000000bdab50_1640; +v0000000000bdab50_1641 .array/port v0000000000bdab50, 1641; +v0000000000bdab50_1642 .array/port v0000000000bdab50, 1642; +v0000000000bdab50_1643 .array/port v0000000000bdab50, 1643; +v0000000000bdab50_1644 .array/port v0000000000bdab50, 1644; +E_00000000006a3090/411 .event edge, v0000000000bdab50_1641, v0000000000bdab50_1642, v0000000000bdab50_1643, v0000000000bdab50_1644; +v0000000000bdab50_1645 .array/port v0000000000bdab50, 1645; +v0000000000bdab50_1646 .array/port v0000000000bdab50, 1646; +v0000000000bdab50_1647 .array/port v0000000000bdab50, 1647; +v0000000000bdab50_1648 .array/port v0000000000bdab50, 1648; +E_00000000006a3090/412 .event edge, v0000000000bdab50_1645, v0000000000bdab50_1646, v0000000000bdab50_1647, v0000000000bdab50_1648; +v0000000000bdab50_1649 .array/port v0000000000bdab50, 1649; +v0000000000bdab50_1650 .array/port v0000000000bdab50, 1650; +v0000000000bdab50_1651 .array/port v0000000000bdab50, 1651; +v0000000000bdab50_1652 .array/port v0000000000bdab50, 1652; +E_00000000006a3090/413 .event edge, v0000000000bdab50_1649, v0000000000bdab50_1650, v0000000000bdab50_1651, v0000000000bdab50_1652; +v0000000000bdab50_1653 .array/port v0000000000bdab50, 1653; +v0000000000bdab50_1654 .array/port v0000000000bdab50, 1654; +v0000000000bdab50_1655 .array/port v0000000000bdab50, 1655; +v0000000000bdab50_1656 .array/port v0000000000bdab50, 1656; +E_00000000006a3090/414 .event edge, v0000000000bdab50_1653, v0000000000bdab50_1654, v0000000000bdab50_1655, v0000000000bdab50_1656; +v0000000000bdab50_1657 .array/port v0000000000bdab50, 1657; +v0000000000bdab50_1658 .array/port v0000000000bdab50, 1658; +v0000000000bdab50_1659 .array/port v0000000000bdab50, 1659; +v0000000000bdab50_1660 .array/port v0000000000bdab50, 1660; +E_00000000006a3090/415 .event edge, v0000000000bdab50_1657, v0000000000bdab50_1658, v0000000000bdab50_1659, v0000000000bdab50_1660; +v0000000000bdab50_1661 .array/port v0000000000bdab50, 1661; +v0000000000bdab50_1662 .array/port v0000000000bdab50, 1662; +v0000000000bdab50_1663 .array/port v0000000000bdab50, 1663; +v0000000000bdab50_1664 .array/port v0000000000bdab50, 1664; +E_00000000006a3090/416 .event edge, v0000000000bdab50_1661, v0000000000bdab50_1662, v0000000000bdab50_1663, v0000000000bdab50_1664; +v0000000000bdab50_1665 .array/port v0000000000bdab50, 1665; +v0000000000bdab50_1666 .array/port v0000000000bdab50, 1666; +v0000000000bdab50_1667 .array/port v0000000000bdab50, 1667; +v0000000000bdab50_1668 .array/port v0000000000bdab50, 1668; +E_00000000006a3090/417 .event edge, v0000000000bdab50_1665, v0000000000bdab50_1666, v0000000000bdab50_1667, v0000000000bdab50_1668; +v0000000000bdab50_1669 .array/port v0000000000bdab50, 1669; +v0000000000bdab50_1670 .array/port v0000000000bdab50, 1670; +v0000000000bdab50_1671 .array/port v0000000000bdab50, 1671; +v0000000000bdab50_1672 .array/port v0000000000bdab50, 1672; +E_00000000006a3090/418 .event edge, v0000000000bdab50_1669, v0000000000bdab50_1670, v0000000000bdab50_1671, v0000000000bdab50_1672; +v0000000000bdab50_1673 .array/port v0000000000bdab50, 1673; +v0000000000bdab50_1674 .array/port v0000000000bdab50, 1674; +v0000000000bdab50_1675 .array/port v0000000000bdab50, 1675; +v0000000000bdab50_1676 .array/port v0000000000bdab50, 1676; +E_00000000006a3090/419 .event edge, v0000000000bdab50_1673, v0000000000bdab50_1674, v0000000000bdab50_1675, v0000000000bdab50_1676; +v0000000000bdab50_1677 .array/port v0000000000bdab50, 1677; +v0000000000bdab50_1678 .array/port v0000000000bdab50, 1678; +v0000000000bdab50_1679 .array/port v0000000000bdab50, 1679; +v0000000000bdab50_1680 .array/port v0000000000bdab50, 1680; +E_00000000006a3090/420 .event edge, v0000000000bdab50_1677, v0000000000bdab50_1678, v0000000000bdab50_1679, v0000000000bdab50_1680; +v0000000000bdab50_1681 .array/port v0000000000bdab50, 1681; +v0000000000bdab50_1682 .array/port v0000000000bdab50, 1682; +v0000000000bdab50_1683 .array/port v0000000000bdab50, 1683; +v0000000000bdab50_1684 .array/port v0000000000bdab50, 1684; +E_00000000006a3090/421 .event edge, v0000000000bdab50_1681, v0000000000bdab50_1682, v0000000000bdab50_1683, v0000000000bdab50_1684; +v0000000000bdab50_1685 .array/port v0000000000bdab50, 1685; +v0000000000bdab50_1686 .array/port v0000000000bdab50, 1686; +v0000000000bdab50_1687 .array/port v0000000000bdab50, 1687; +v0000000000bdab50_1688 .array/port v0000000000bdab50, 1688; +E_00000000006a3090/422 .event edge, v0000000000bdab50_1685, v0000000000bdab50_1686, v0000000000bdab50_1687, v0000000000bdab50_1688; +v0000000000bdab50_1689 .array/port v0000000000bdab50, 1689; +v0000000000bdab50_1690 .array/port v0000000000bdab50, 1690; +v0000000000bdab50_1691 .array/port v0000000000bdab50, 1691; +v0000000000bdab50_1692 .array/port v0000000000bdab50, 1692; +E_00000000006a3090/423 .event edge, v0000000000bdab50_1689, v0000000000bdab50_1690, v0000000000bdab50_1691, v0000000000bdab50_1692; +v0000000000bdab50_1693 .array/port v0000000000bdab50, 1693; +v0000000000bdab50_1694 .array/port v0000000000bdab50, 1694; +v0000000000bdab50_1695 .array/port v0000000000bdab50, 1695; +v0000000000bdab50_1696 .array/port v0000000000bdab50, 1696; +E_00000000006a3090/424 .event edge, v0000000000bdab50_1693, v0000000000bdab50_1694, v0000000000bdab50_1695, v0000000000bdab50_1696; +v0000000000bdab50_1697 .array/port v0000000000bdab50, 1697; +v0000000000bdab50_1698 .array/port v0000000000bdab50, 1698; +v0000000000bdab50_1699 .array/port v0000000000bdab50, 1699; +v0000000000bdab50_1700 .array/port v0000000000bdab50, 1700; +E_00000000006a3090/425 .event edge, v0000000000bdab50_1697, v0000000000bdab50_1698, v0000000000bdab50_1699, v0000000000bdab50_1700; +v0000000000bdab50_1701 .array/port v0000000000bdab50, 1701; +v0000000000bdab50_1702 .array/port v0000000000bdab50, 1702; +v0000000000bdab50_1703 .array/port v0000000000bdab50, 1703; +v0000000000bdab50_1704 .array/port v0000000000bdab50, 1704; +E_00000000006a3090/426 .event edge, v0000000000bdab50_1701, v0000000000bdab50_1702, v0000000000bdab50_1703, v0000000000bdab50_1704; +v0000000000bdab50_1705 .array/port v0000000000bdab50, 1705; +v0000000000bdab50_1706 .array/port v0000000000bdab50, 1706; +v0000000000bdab50_1707 .array/port v0000000000bdab50, 1707; +v0000000000bdab50_1708 .array/port v0000000000bdab50, 1708; +E_00000000006a3090/427 .event edge, v0000000000bdab50_1705, v0000000000bdab50_1706, v0000000000bdab50_1707, v0000000000bdab50_1708; +v0000000000bdab50_1709 .array/port v0000000000bdab50, 1709; +v0000000000bdab50_1710 .array/port v0000000000bdab50, 1710; +v0000000000bdab50_1711 .array/port v0000000000bdab50, 1711; +v0000000000bdab50_1712 .array/port v0000000000bdab50, 1712; +E_00000000006a3090/428 .event edge, v0000000000bdab50_1709, v0000000000bdab50_1710, v0000000000bdab50_1711, v0000000000bdab50_1712; +v0000000000bdab50_1713 .array/port v0000000000bdab50, 1713; +v0000000000bdab50_1714 .array/port v0000000000bdab50, 1714; +v0000000000bdab50_1715 .array/port v0000000000bdab50, 1715; +v0000000000bdab50_1716 .array/port v0000000000bdab50, 1716; +E_00000000006a3090/429 .event edge, v0000000000bdab50_1713, v0000000000bdab50_1714, v0000000000bdab50_1715, v0000000000bdab50_1716; +v0000000000bdab50_1717 .array/port v0000000000bdab50, 1717; +v0000000000bdab50_1718 .array/port v0000000000bdab50, 1718; +v0000000000bdab50_1719 .array/port v0000000000bdab50, 1719; +v0000000000bdab50_1720 .array/port v0000000000bdab50, 1720; +E_00000000006a3090/430 .event edge, v0000000000bdab50_1717, v0000000000bdab50_1718, v0000000000bdab50_1719, v0000000000bdab50_1720; +v0000000000bdab50_1721 .array/port v0000000000bdab50, 1721; +v0000000000bdab50_1722 .array/port v0000000000bdab50, 1722; +v0000000000bdab50_1723 .array/port v0000000000bdab50, 1723; +v0000000000bdab50_1724 .array/port v0000000000bdab50, 1724; +E_00000000006a3090/431 .event edge, v0000000000bdab50_1721, v0000000000bdab50_1722, v0000000000bdab50_1723, v0000000000bdab50_1724; +v0000000000bdab50_1725 .array/port v0000000000bdab50, 1725; +v0000000000bdab50_1726 .array/port v0000000000bdab50, 1726; +v0000000000bdab50_1727 .array/port v0000000000bdab50, 1727; +v0000000000bdab50_1728 .array/port v0000000000bdab50, 1728; +E_00000000006a3090/432 .event edge, v0000000000bdab50_1725, v0000000000bdab50_1726, v0000000000bdab50_1727, v0000000000bdab50_1728; +v0000000000bdab50_1729 .array/port v0000000000bdab50, 1729; +v0000000000bdab50_1730 .array/port v0000000000bdab50, 1730; +v0000000000bdab50_1731 .array/port v0000000000bdab50, 1731; +v0000000000bdab50_1732 .array/port v0000000000bdab50, 1732; +E_00000000006a3090/433 .event edge, v0000000000bdab50_1729, v0000000000bdab50_1730, v0000000000bdab50_1731, v0000000000bdab50_1732; +v0000000000bdab50_1733 .array/port v0000000000bdab50, 1733; +v0000000000bdab50_1734 .array/port v0000000000bdab50, 1734; +v0000000000bdab50_1735 .array/port v0000000000bdab50, 1735; +v0000000000bdab50_1736 .array/port v0000000000bdab50, 1736; +E_00000000006a3090/434 .event edge, v0000000000bdab50_1733, v0000000000bdab50_1734, v0000000000bdab50_1735, v0000000000bdab50_1736; +v0000000000bdab50_1737 .array/port v0000000000bdab50, 1737; +v0000000000bdab50_1738 .array/port v0000000000bdab50, 1738; +v0000000000bdab50_1739 .array/port v0000000000bdab50, 1739; +v0000000000bdab50_1740 .array/port v0000000000bdab50, 1740; +E_00000000006a3090/435 .event edge, v0000000000bdab50_1737, v0000000000bdab50_1738, v0000000000bdab50_1739, v0000000000bdab50_1740; +v0000000000bdab50_1741 .array/port v0000000000bdab50, 1741; +v0000000000bdab50_1742 .array/port v0000000000bdab50, 1742; +v0000000000bdab50_1743 .array/port v0000000000bdab50, 1743; +v0000000000bdab50_1744 .array/port v0000000000bdab50, 1744; +E_00000000006a3090/436 .event edge, v0000000000bdab50_1741, v0000000000bdab50_1742, v0000000000bdab50_1743, v0000000000bdab50_1744; +v0000000000bdab50_1745 .array/port v0000000000bdab50, 1745; +v0000000000bdab50_1746 .array/port v0000000000bdab50, 1746; +v0000000000bdab50_1747 .array/port v0000000000bdab50, 1747; +v0000000000bdab50_1748 .array/port v0000000000bdab50, 1748; +E_00000000006a3090/437 .event edge, v0000000000bdab50_1745, v0000000000bdab50_1746, v0000000000bdab50_1747, v0000000000bdab50_1748; +v0000000000bdab50_1749 .array/port v0000000000bdab50, 1749; +v0000000000bdab50_1750 .array/port v0000000000bdab50, 1750; +v0000000000bdab50_1751 .array/port v0000000000bdab50, 1751; +v0000000000bdab50_1752 .array/port v0000000000bdab50, 1752; +E_00000000006a3090/438 .event edge, v0000000000bdab50_1749, v0000000000bdab50_1750, v0000000000bdab50_1751, v0000000000bdab50_1752; +v0000000000bdab50_1753 .array/port v0000000000bdab50, 1753; +v0000000000bdab50_1754 .array/port v0000000000bdab50, 1754; +v0000000000bdab50_1755 .array/port v0000000000bdab50, 1755; +v0000000000bdab50_1756 .array/port v0000000000bdab50, 1756; +E_00000000006a3090/439 .event edge, v0000000000bdab50_1753, v0000000000bdab50_1754, v0000000000bdab50_1755, v0000000000bdab50_1756; +v0000000000bdab50_1757 .array/port v0000000000bdab50, 1757; +v0000000000bdab50_1758 .array/port v0000000000bdab50, 1758; +v0000000000bdab50_1759 .array/port v0000000000bdab50, 1759; +v0000000000bdab50_1760 .array/port v0000000000bdab50, 1760; +E_00000000006a3090/440 .event edge, v0000000000bdab50_1757, v0000000000bdab50_1758, v0000000000bdab50_1759, v0000000000bdab50_1760; +v0000000000bdab50_1761 .array/port v0000000000bdab50, 1761; +v0000000000bdab50_1762 .array/port v0000000000bdab50, 1762; +v0000000000bdab50_1763 .array/port v0000000000bdab50, 1763; +v0000000000bdab50_1764 .array/port v0000000000bdab50, 1764; +E_00000000006a3090/441 .event edge, v0000000000bdab50_1761, v0000000000bdab50_1762, v0000000000bdab50_1763, v0000000000bdab50_1764; +v0000000000bdab50_1765 .array/port v0000000000bdab50, 1765; +v0000000000bdab50_1766 .array/port v0000000000bdab50, 1766; +v0000000000bdab50_1767 .array/port v0000000000bdab50, 1767; +v0000000000bdab50_1768 .array/port v0000000000bdab50, 1768; +E_00000000006a3090/442 .event edge, v0000000000bdab50_1765, v0000000000bdab50_1766, v0000000000bdab50_1767, v0000000000bdab50_1768; +v0000000000bdab50_1769 .array/port v0000000000bdab50, 1769; +v0000000000bdab50_1770 .array/port v0000000000bdab50, 1770; +v0000000000bdab50_1771 .array/port v0000000000bdab50, 1771; +v0000000000bdab50_1772 .array/port v0000000000bdab50, 1772; +E_00000000006a3090/443 .event edge, v0000000000bdab50_1769, v0000000000bdab50_1770, v0000000000bdab50_1771, v0000000000bdab50_1772; +v0000000000bdab50_1773 .array/port v0000000000bdab50, 1773; +v0000000000bdab50_1774 .array/port v0000000000bdab50, 1774; +v0000000000bdab50_1775 .array/port v0000000000bdab50, 1775; +v0000000000bdab50_1776 .array/port v0000000000bdab50, 1776; +E_00000000006a3090/444 .event edge, v0000000000bdab50_1773, v0000000000bdab50_1774, v0000000000bdab50_1775, v0000000000bdab50_1776; +v0000000000bdab50_1777 .array/port v0000000000bdab50, 1777; +v0000000000bdab50_1778 .array/port v0000000000bdab50, 1778; +v0000000000bdab50_1779 .array/port v0000000000bdab50, 1779; +v0000000000bdab50_1780 .array/port v0000000000bdab50, 1780; +E_00000000006a3090/445 .event edge, v0000000000bdab50_1777, v0000000000bdab50_1778, v0000000000bdab50_1779, v0000000000bdab50_1780; +v0000000000bdab50_1781 .array/port v0000000000bdab50, 1781; +v0000000000bdab50_1782 .array/port v0000000000bdab50, 1782; +v0000000000bdab50_1783 .array/port v0000000000bdab50, 1783; +v0000000000bdab50_1784 .array/port v0000000000bdab50, 1784; +E_00000000006a3090/446 .event edge, v0000000000bdab50_1781, v0000000000bdab50_1782, v0000000000bdab50_1783, v0000000000bdab50_1784; +v0000000000bdab50_1785 .array/port v0000000000bdab50, 1785; +v0000000000bdab50_1786 .array/port v0000000000bdab50, 1786; +v0000000000bdab50_1787 .array/port v0000000000bdab50, 1787; +v0000000000bdab50_1788 .array/port v0000000000bdab50, 1788; +E_00000000006a3090/447 .event edge, v0000000000bdab50_1785, v0000000000bdab50_1786, v0000000000bdab50_1787, v0000000000bdab50_1788; +v0000000000bdab50_1789 .array/port v0000000000bdab50, 1789; +v0000000000bdab50_1790 .array/port v0000000000bdab50, 1790; +v0000000000bdab50_1791 .array/port v0000000000bdab50, 1791; +v0000000000bdab50_1792 .array/port v0000000000bdab50, 1792; +E_00000000006a3090/448 .event edge, v0000000000bdab50_1789, v0000000000bdab50_1790, v0000000000bdab50_1791, v0000000000bdab50_1792; +v0000000000bdab50_1793 .array/port v0000000000bdab50, 1793; +v0000000000bdab50_1794 .array/port v0000000000bdab50, 1794; +v0000000000bdab50_1795 .array/port v0000000000bdab50, 1795; +v0000000000bdab50_1796 .array/port v0000000000bdab50, 1796; +E_00000000006a3090/449 .event edge, v0000000000bdab50_1793, v0000000000bdab50_1794, v0000000000bdab50_1795, v0000000000bdab50_1796; +v0000000000bdab50_1797 .array/port v0000000000bdab50, 1797; +v0000000000bdab50_1798 .array/port v0000000000bdab50, 1798; +v0000000000bdab50_1799 .array/port v0000000000bdab50, 1799; +v0000000000bdab50_1800 .array/port v0000000000bdab50, 1800; +E_00000000006a3090/450 .event edge, v0000000000bdab50_1797, v0000000000bdab50_1798, v0000000000bdab50_1799, v0000000000bdab50_1800; +v0000000000bdab50_1801 .array/port v0000000000bdab50, 1801; +v0000000000bdab50_1802 .array/port v0000000000bdab50, 1802; +v0000000000bdab50_1803 .array/port v0000000000bdab50, 1803; +v0000000000bdab50_1804 .array/port v0000000000bdab50, 1804; +E_00000000006a3090/451 .event edge, v0000000000bdab50_1801, v0000000000bdab50_1802, v0000000000bdab50_1803, v0000000000bdab50_1804; +v0000000000bdab50_1805 .array/port v0000000000bdab50, 1805; +v0000000000bdab50_1806 .array/port v0000000000bdab50, 1806; +v0000000000bdab50_1807 .array/port v0000000000bdab50, 1807; +v0000000000bdab50_1808 .array/port v0000000000bdab50, 1808; +E_00000000006a3090/452 .event edge, v0000000000bdab50_1805, v0000000000bdab50_1806, v0000000000bdab50_1807, v0000000000bdab50_1808; +v0000000000bdab50_1809 .array/port v0000000000bdab50, 1809; +v0000000000bdab50_1810 .array/port v0000000000bdab50, 1810; +v0000000000bdab50_1811 .array/port v0000000000bdab50, 1811; +v0000000000bdab50_1812 .array/port v0000000000bdab50, 1812; +E_00000000006a3090/453 .event edge, v0000000000bdab50_1809, v0000000000bdab50_1810, v0000000000bdab50_1811, v0000000000bdab50_1812; +v0000000000bdab50_1813 .array/port v0000000000bdab50, 1813; +v0000000000bdab50_1814 .array/port v0000000000bdab50, 1814; +v0000000000bdab50_1815 .array/port v0000000000bdab50, 1815; +v0000000000bdab50_1816 .array/port v0000000000bdab50, 1816; +E_00000000006a3090/454 .event edge, v0000000000bdab50_1813, v0000000000bdab50_1814, v0000000000bdab50_1815, v0000000000bdab50_1816; +v0000000000bdab50_1817 .array/port v0000000000bdab50, 1817; +v0000000000bdab50_1818 .array/port v0000000000bdab50, 1818; +v0000000000bdab50_1819 .array/port v0000000000bdab50, 1819; +v0000000000bdab50_1820 .array/port v0000000000bdab50, 1820; +E_00000000006a3090/455 .event edge, v0000000000bdab50_1817, v0000000000bdab50_1818, v0000000000bdab50_1819, v0000000000bdab50_1820; +v0000000000bdab50_1821 .array/port v0000000000bdab50, 1821; +v0000000000bdab50_1822 .array/port v0000000000bdab50, 1822; +v0000000000bdab50_1823 .array/port v0000000000bdab50, 1823; +v0000000000bdab50_1824 .array/port v0000000000bdab50, 1824; +E_00000000006a3090/456 .event edge, v0000000000bdab50_1821, v0000000000bdab50_1822, v0000000000bdab50_1823, v0000000000bdab50_1824; +v0000000000bdab50_1825 .array/port v0000000000bdab50, 1825; +v0000000000bdab50_1826 .array/port v0000000000bdab50, 1826; +v0000000000bdab50_1827 .array/port v0000000000bdab50, 1827; +v0000000000bdab50_1828 .array/port v0000000000bdab50, 1828; +E_00000000006a3090/457 .event edge, v0000000000bdab50_1825, v0000000000bdab50_1826, v0000000000bdab50_1827, v0000000000bdab50_1828; +v0000000000bdab50_1829 .array/port v0000000000bdab50, 1829; +v0000000000bdab50_1830 .array/port v0000000000bdab50, 1830; +v0000000000bdab50_1831 .array/port v0000000000bdab50, 1831; +v0000000000bdab50_1832 .array/port v0000000000bdab50, 1832; +E_00000000006a3090/458 .event edge, v0000000000bdab50_1829, v0000000000bdab50_1830, v0000000000bdab50_1831, v0000000000bdab50_1832; +v0000000000bdab50_1833 .array/port v0000000000bdab50, 1833; +v0000000000bdab50_1834 .array/port v0000000000bdab50, 1834; +v0000000000bdab50_1835 .array/port v0000000000bdab50, 1835; +v0000000000bdab50_1836 .array/port v0000000000bdab50, 1836; +E_00000000006a3090/459 .event edge, v0000000000bdab50_1833, v0000000000bdab50_1834, v0000000000bdab50_1835, v0000000000bdab50_1836; +v0000000000bdab50_1837 .array/port v0000000000bdab50, 1837; +v0000000000bdab50_1838 .array/port v0000000000bdab50, 1838; +v0000000000bdab50_1839 .array/port v0000000000bdab50, 1839; +v0000000000bdab50_1840 .array/port v0000000000bdab50, 1840; +E_00000000006a3090/460 .event edge, v0000000000bdab50_1837, v0000000000bdab50_1838, v0000000000bdab50_1839, v0000000000bdab50_1840; +v0000000000bdab50_1841 .array/port v0000000000bdab50, 1841; +v0000000000bdab50_1842 .array/port v0000000000bdab50, 1842; +v0000000000bdab50_1843 .array/port v0000000000bdab50, 1843; +v0000000000bdab50_1844 .array/port v0000000000bdab50, 1844; +E_00000000006a3090/461 .event edge, v0000000000bdab50_1841, v0000000000bdab50_1842, v0000000000bdab50_1843, v0000000000bdab50_1844; +v0000000000bdab50_1845 .array/port v0000000000bdab50, 1845; +v0000000000bdab50_1846 .array/port v0000000000bdab50, 1846; +v0000000000bdab50_1847 .array/port v0000000000bdab50, 1847; +v0000000000bdab50_1848 .array/port v0000000000bdab50, 1848; +E_00000000006a3090/462 .event edge, v0000000000bdab50_1845, v0000000000bdab50_1846, v0000000000bdab50_1847, v0000000000bdab50_1848; +v0000000000bdab50_1849 .array/port v0000000000bdab50, 1849; +v0000000000bdab50_1850 .array/port v0000000000bdab50, 1850; +v0000000000bdab50_1851 .array/port v0000000000bdab50, 1851; +v0000000000bdab50_1852 .array/port v0000000000bdab50, 1852; +E_00000000006a3090/463 .event edge, v0000000000bdab50_1849, v0000000000bdab50_1850, v0000000000bdab50_1851, v0000000000bdab50_1852; +v0000000000bdab50_1853 .array/port v0000000000bdab50, 1853; +v0000000000bdab50_1854 .array/port v0000000000bdab50, 1854; +v0000000000bdab50_1855 .array/port v0000000000bdab50, 1855; +v0000000000bdab50_1856 .array/port v0000000000bdab50, 1856; +E_00000000006a3090/464 .event edge, v0000000000bdab50_1853, v0000000000bdab50_1854, v0000000000bdab50_1855, v0000000000bdab50_1856; +v0000000000bdab50_1857 .array/port v0000000000bdab50, 1857; +v0000000000bdab50_1858 .array/port v0000000000bdab50, 1858; +v0000000000bdab50_1859 .array/port v0000000000bdab50, 1859; +v0000000000bdab50_1860 .array/port v0000000000bdab50, 1860; +E_00000000006a3090/465 .event edge, v0000000000bdab50_1857, v0000000000bdab50_1858, v0000000000bdab50_1859, v0000000000bdab50_1860; +v0000000000bdab50_1861 .array/port v0000000000bdab50, 1861; +v0000000000bdab50_1862 .array/port v0000000000bdab50, 1862; +v0000000000bdab50_1863 .array/port v0000000000bdab50, 1863; +v0000000000bdab50_1864 .array/port v0000000000bdab50, 1864; +E_00000000006a3090/466 .event edge, v0000000000bdab50_1861, v0000000000bdab50_1862, v0000000000bdab50_1863, v0000000000bdab50_1864; +v0000000000bdab50_1865 .array/port v0000000000bdab50, 1865; +v0000000000bdab50_1866 .array/port v0000000000bdab50, 1866; +v0000000000bdab50_1867 .array/port v0000000000bdab50, 1867; +v0000000000bdab50_1868 .array/port v0000000000bdab50, 1868; +E_00000000006a3090/467 .event edge, v0000000000bdab50_1865, v0000000000bdab50_1866, v0000000000bdab50_1867, v0000000000bdab50_1868; +v0000000000bdab50_1869 .array/port v0000000000bdab50, 1869; +v0000000000bdab50_1870 .array/port v0000000000bdab50, 1870; +v0000000000bdab50_1871 .array/port v0000000000bdab50, 1871; +v0000000000bdab50_1872 .array/port v0000000000bdab50, 1872; +E_00000000006a3090/468 .event edge, v0000000000bdab50_1869, v0000000000bdab50_1870, v0000000000bdab50_1871, v0000000000bdab50_1872; +v0000000000bdab50_1873 .array/port v0000000000bdab50, 1873; +v0000000000bdab50_1874 .array/port v0000000000bdab50, 1874; +v0000000000bdab50_1875 .array/port v0000000000bdab50, 1875; +v0000000000bdab50_1876 .array/port v0000000000bdab50, 1876; +E_00000000006a3090/469 .event edge, v0000000000bdab50_1873, v0000000000bdab50_1874, v0000000000bdab50_1875, v0000000000bdab50_1876; +v0000000000bdab50_1877 .array/port v0000000000bdab50, 1877; +v0000000000bdab50_1878 .array/port v0000000000bdab50, 1878; +v0000000000bdab50_1879 .array/port v0000000000bdab50, 1879; +v0000000000bdab50_1880 .array/port v0000000000bdab50, 1880; +E_00000000006a3090/470 .event edge, v0000000000bdab50_1877, v0000000000bdab50_1878, v0000000000bdab50_1879, v0000000000bdab50_1880; +v0000000000bdab50_1881 .array/port v0000000000bdab50, 1881; +v0000000000bdab50_1882 .array/port v0000000000bdab50, 1882; +v0000000000bdab50_1883 .array/port v0000000000bdab50, 1883; +v0000000000bdab50_1884 .array/port v0000000000bdab50, 1884; +E_00000000006a3090/471 .event edge, v0000000000bdab50_1881, v0000000000bdab50_1882, v0000000000bdab50_1883, v0000000000bdab50_1884; +v0000000000bdab50_1885 .array/port v0000000000bdab50, 1885; +v0000000000bdab50_1886 .array/port v0000000000bdab50, 1886; +v0000000000bdab50_1887 .array/port v0000000000bdab50, 1887; +v0000000000bdab50_1888 .array/port v0000000000bdab50, 1888; +E_00000000006a3090/472 .event edge, v0000000000bdab50_1885, v0000000000bdab50_1886, v0000000000bdab50_1887, v0000000000bdab50_1888; +v0000000000bdab50_1889 .array/port v0000000000bdab50, 1889; +v0000000000bdab50_1890 .array/port v0000000000bdab50, 1890; +v0000000000bdab50_1891 .array/port v0000000000bdab50, 1891; +v0000000000bdab50_1892 .array/port v0000000000bdab50, 1892; +E_00000000006a3090/473 .event edge, v0000000000bdab50_1889, v0000000000bdab50_1890, v0000000000bdab50_1891, v0000000000bdab50_1892; +v0000000000bdab50_1893 .array/port v0000000000bdab50, 1893; +v0000000000bdab50_1894 .array/port v0000000000bdab50, 1894; +v0000000000bdab50_1895 .array/port v0000000000bdab50, 1895; +v0000000000bdab50_1896 .array/port v0000000000bdab50, 1896; +E_00000000006a3090/474 .event edge, v0000000000bdab50_1893, v0000000000bdab50_1894, v0000000000bdab50_1895, v0000000000bdab50_1896; +v0000000000bdab50_1897 .array/port v0000000000bdab50, 1897; +v0000000000bdab50_1898 .array/port v0000000000bdab50, 1898; +v0000000000bdab50_1899 .array/port v0000000000bdab50, 1899; +v0000000000bdab50_1900 .array/port v0000000000bdab50, 1900; +E_00000000006a3090/475 .event edge, v0000000000bdab50_1897, v0000000000bdab50_1898, v0000000000bdab50_1899, v0000000000bdab50_1900; +v0000000000bdab50_1901 .array/port v0000000000bdab50, 1901; +v0000000000bdab50_1902 .array/port v0000000000bdab50, 1902; +v0000000000bdab50_1903 .array/port v0000000000bdab50, 1903; +v0000000000bdab50_1904 .array/port v0000000000bdab50, 1904; +E_00000000006a3090/476 .event edge, v0000000000bdab50_1901, v0000000000bdab50_1902, v0000000000bdab50_1903, v0000000000bdab50_1904; +v0000000000bdab50_1905 .array/port v0000000000bdab50, 1905; +v0000000000bdab50_1906 .array/port v0000000000bdab50, 1906; +v0000000000bdab50_1907 .array/port v0000000000bdab50, 1907; +v0000000000bdab50_1908 .array/port v0000000000bdab50, 1908; +E_00000000006a3090/477 .event edge, v0000000000bdab50_1905, v0000000000bdab50_1906, v0000000000bdab50_1907, v0000000000bdab50_1908; +v0000000000bdab50_1909 .array/port v0000000000bdab50, 1909; +v0000000000bdab50_1910 .array/port v0000000000bdab50, 1910; +v0000000000bdab50_1911 .array/port v0000000000bdab50, 1911; +v0000000000bdab50_1912 .array/port v0000000000bdab50, 1912; +E_00000000006a3090/478 .event edge, v0000000000bdab50_1909, v0000000000bdab50_1910, v0000000000bdab50_1911, v0000000000bdab50_1912; +v0000000000bdab50_1913 .array/port v0000000000bdab50, 1913; +v0000000000bdab50_1914 .array/port v0000000000bdab50, 1914; +v0000000000bdab50_1915 .array/port v0000000000bdab50, 1915; +v0000000000bdab50_1916 .array/port v0000000000bdab50, 1916; +E_00000000006a3090/479 .event edge, v0000000000bdab50_1913, v0000000000bdab50_1914, v0000000000bdab50_1915, v0000000000bdab50_1916; +v0000000000bdab50_1917 .array/port v0000000000bdab50, 1917; +v0000000000bdab50_1918 .array/port v0000000000bdab50, 1918; +v0000000000bdab50_1919 .array/port v0000000000bdab50, 1919; +v0000000000bdab50_1920 .array/port v0000000000bdab50, 1920; +E_00000000006a3090/480 .event edge, v0000000000bdab50_1917, v0000000000bdab50_1918, v0000000000bdab50_1919, v0000000000bdab50_1920; +v0000000000bdab50_1921 .array/port v0000000000bdab50, 1921; +v0000000000bdab50_1922 .array/port v0000000000bdab50, 1922; +v0000000000bdab50_1923 .array/port v0000000000bdab50, 1923; +v0000000000bdab50_1924 .array/port v0000000000bdab50, 1924; +E_00000000006a3090/481 .event edge, v0000000000bdab50_1921, v0000000000bdab50_1922, v0000000000bdab50_1923, v0000000000bdab50_1924; +v0000000000bdab50_1925 .array/port v0000000000bdab50, 1925; +v0000000000bdab50_1926 .array/port v0000000000bdab50, 1926; +v0000000000bdab50_1927 .array/port v0000000000bdab50, 1927; +v0000000000bdab50_1928 .array/port v0000000000bdab50, 1928; +E_00000000006a3090/482 .event edge, v0000000000bdab50_1925, v0000000000bdab50_1926, v0000000000bdab50_1927, v0000000000bdab50_1928; +v0000000000bdab50_1929 .array/port v0000000000bdab50, 1929; +v0000000000bdab50_1930 .array/port v0000000000bdab50, 1930; +v0000000000bdab50_1931 .array/port v0000000000bdab50, 1931; +v0000000000bdab50_1932 .array/port v0000000000bdab50, 1932; +E_00000000006a3090/483 .event edge, v0000000000bdab50_1929, v0000000000bdab50_1930, v0000000000bdab50_1931, v0000000000bdab50_1932; +v0000000000bdab50_1933 .array/port v0000000000bdab50, 1933; +v0000000000bdab50_1934 .array/port v0000000000bdab50, 1934; +v0000000000bdab50_1935 .array/port v0000000000bdab50, 1935; +v0000000000bdab50_1936 .array/port v0000000000bdab50, 1936; +E_00000000006a3090/484 .event edge, v0000000000bdab50_1933, v0000000000bdab50_1934, v0000000000bdab50_1935, v0000000000bdab50_1936; +v0000000000bdab50_1937 .array/port v0000000000bdab50, 1937; +v0000000000bdab50_1938 .array/port v0000000000bdab50, 1938; +v0000000000bdab50_1939 .array/port v0000000000bdab50, 1939; +v0000000000bdab50_1940 .array/port v0000000000bdab50, 1940; +E_00000000006a3090/485 .event edge, v0000000000bdab50_1937, v0000000000bdab50_1938, v0000000000bdab50_1939, v0000000000bdab50_1940; +v0000000000bdab50_1941 .array/port v0000000000bdab50, 1941; +v0000000000bdab50_1942 .array/port v0000000000bdab50, 1942; +v0000000000bdab50_1943 .array/port v0000000000bdab50, 1943; +v0000000000bdab50_1944 .array/port v0000000000bdab50, 1944; +E_00000000006a3090/486 .event edge, v0000000000bdab50_1941, v0000000000bdab50_1942, v0000000000bdab50_1943, v0000000000bdab50_1944; +v0000000000bdab50_1945 .array/port v0000000000bdab50, 1945; +v0000000000bdab50_1946 .array/port v0000000000bdab50, 1946; +v0000000000bdab50_1947 .array/port v0000000000bdab50, 1947; +v0000000000bdab50_1948 .array/port v0000000000bdab50, 1948; +E_00000000006a3090/487 .event edge, v0000000000bdab50_1945, v0000000000bdab50_1946, v0000000000bdab50_1947, v0000000000bdab50_1948; +v0000000000bdab50_1949 .array/port v0000000000bdab50, 1949; +v0000000000bdab50_1950 .array/port v0000000000bdab50, 1950; +v0000000000bdab50_1951 .array/port v0000000000bdab50, 1951; +v0000000000bdab50_1952 .array/port v0000000000bdab50, 1952; +E_00000000006a3090/488 .event edge, v0000000000bdab50_1949, v0000000000bdab50_1950, v0000000000bdab50_1951, v0000000000bdab50_1952; +v0000000000bdab50_1953 .array/port v0000000000bdab50, 1953; +v0000000000bdab50_1954 .array/port v0000000000bdab50, 1954; +v0000000000bdab50_1955 .array/port v0000000000bdab50, 1955; +v0000000000bdab50_1956 .array/port v0000000000bdab50, 1956; +E_00000000006a3090/489 .event edge, v0000000000bdab50_1953, v0000000000bdab50_1954, v0000000000bdab50_1955, v0000000000bdab50_1956; +v0000000000bdab50_1957 .array/port v0000000000bdab50, 1957; +v0000000000bdab50_1958 .array/port v0000000000bdab50, 1958; +v0000000000bdab50_1959 .array/port v0000000000bdab50, 1959; +v0000000000bdab50_1960 .array/port v0000000000bdab50, 1960; +E_00000000006a3090/490 .event edge, v0000000000bdab50_1957, v0000000000bdab50_1958, v0000000000bdab50_1959, v0000000000bdab50_1960; +v0000000000bdab50_1961 .array/port v0000000000bdab50, 1961; +v0000000000bdab50_1962 .array/port v0000000000bdab50, 1962; +v0000000000bdab50_1963 .array/port v0000000000bdab50, 1963; +v0000000000bdab50_1964 .array/port v0000000000bdab50, 1964; +E_00000000006a3090/491 .event edge, v0000000000bdab50_1961, v0000000000bdab50_1962, v0000000000bdab50_1963, v0000000000bdab50_1964; +v0000000000bdab50_1965 .array/port v0000000000bdab50, 1965; +v0000000000bdab50_1966 .array/port v0000000000bdab50, 1966; +v0000000000bdab50_1967 .array/port v0000000000bdab50, 1967; +v0000000000bdab50_1968 .array/port v0000000000bdab50, 1968; +E_00000000006a3090/492 .event edge, v0000000000bdab50_1965, v0000000000bdab50_1966, v0000000000bdab50_1967, v0000000000bdab50_1968; +v0000000000bdab50_1969 .array/port v0000000000bdab50, 1969; +v0000000000bdab50_1970 .array/port v0000000000bdab50, 1970; +v0000000000bdab50_1971 .array/port v0000000000bdab50, 1971; +v0000000000bdab50_1972 .array/port v0000000000bdab50, 1972; +E_00000000006a3090/493 .event edge, v0000000000bdab50_1969, v0000000000bdab50_1970, v0000000000bdab50_1971, v0000000000bdab50_1972; +v0000000000bdab50_1973 .array/port v0000000000bdab50, 1973; +v0000000000bdab50_1974 .array/port v0000000000bdab50, 1974; +v0000000000bdab50_1975 .array/port v0000000000bdab50, 1975; +v0000000000bdab50_1976 .array/port v0000000000bdab50, 1976; +E_00000000006a3090/494 .event edge, v0000000000bdab50_1973, v0000000000bdab50_1974, v0000000000bdab50_1975, v0000000000bdab50_1976; +v0000000000bdab50_1977 .array/port v0000000000bdab50, 1977; +v0000000000bdab50_1978 .array/port v0000000000bdab50, 1978; +v0000000000bdab50_1979 .array/port v0000000000bdab50, 1979; +v0000000000bdab50_1980 .array/port v0000000000bdab50, 1980; +E_00000000006a3090/495 .event edge, v0000000000bdab50_1977, v0000000000bdab50_1978, v0000000000bdab50_1979, v0000000000bdab50_1980; +v0000000000bdab50_1981 .array/port v0000000000bdab50, 1981; +v0000000000bdab50_1982 .array/port v0000000000bdab50, 1982; +v0000000000bdab50_1983 .array/port v0000000000bdab50, 1983; +v0000000000bdab50_1984 .array/port v0000000000bdab50, 1984; +E_00000000006a3090/496 .event edge, v0000000000bdab50_1981, v0000000000bdab50_1982, v0000000000bdab50_1983, v0000000000bdab50_1984; +v0000000000bdab50_1985 .array/port v0000000000bdab50, 1985; +v0000000000bdab50_1986 .array/port v0000000000bdab50, 1986; +v0000000000bdab50_1987 .array/port v0000000000bdab50, 1987; +v0000000000bdab50_1988 .array/port v0000000000bdab50, 1988; +E_00000000006a3090/497 .event edge, v0000000000bdab50_1985, v0000000000bdab50_1986, v0000000000bdab50_1987, v0000000000bdab50_1988; +v0000000000bdab50_1989 .array/port v0000000000bdab50, 1989; +v0000000000bdab50_1990 .array/port v0000000000bdab50, 1990; +v0000000000bdab50_1991 .array/port v0000000000bdab50, 1991; +v0000000000bdab50_1992 .array/port v0000000000bdab50, 1992; +E_00000000006a3090/498 .event edge, v0000000000bdab50_1989, v0000000000bdab50_1990, v0000000000bdab50_1991, v0000000000bdab50_1992; +v0000000000bdab50_1993 .array/port v0000000000bdab50, 1993; +v0000000000bdab50_1994 .array/port v0000000000bdab50, 1994; +v0000000000bdab50_1995 .array/port v0000000000bdab50, 1995; +v0000000000bdab50_1996 .array/port v0000000000bdab50, 1996; +E_00000000006a3090/499 .event edge, v0000000000bdab50_1993, v0000000000bdab50_1994, v0000000000bdab50_1995, v0000000000bdab50_1996; +v0000000000bdab50_1997 .array/port v0000000000bdab50, 1997; +v0000000000bdab50_1998 .array/port v0000000000bdab50, 1998; +v0000000000bdab50_1999 .array/port v0000000000bdab50, 1999; +v0000000000bdab50_2000 .array/port v0000000000bdab50, 2000; +E_00000000006a3090/500 .event edge, v0000000000bdab50_1997, v0000000000bdab50_1998, v0000000000bdab50_1999, v0000000000bdab50_2000; +v0000000000bdab50_2001 .array/port v0000000000bdab50, 2001; +v0000000000bdab50_2002 .array/port v0000000000bdab50, 2002; +v0000000000bdab50_2003 .array/port v0000000000bdab50, 2003; +v0000000000bdab50_2004 .array/port v0000000000bdab50, 2004; +E_00000000006a3090/501 .event edge, v0000000000bdab50_2001, v0000000000bdab50_2002, v0000000000bdab50_2003, v0000000000bdab50_2004; +v0000000000bdab50_2005 .array/port v0000000000bdab50, 2005; +v0000000000bdab50_2006 .array/port v0000000000bdab50, 2006; +v0000000000bdab50_2007 .array/port v0000000000bdab50, 2007; +v0000000000bdab50_2008 .array/port v0000000000bdab50, 2008; +E_00000000006a3090/502 .event edge, v0000000000bdab50_2005, v0000000000bdab50_2006, v0000000000bdab50_2007, v0000000000bdab50_2008; +v0000000000bdab50_2009 .array/port v0000000000bdab50, 2009; +v0000000000bdab50_2010 .array/port v0000000000bdab50, 2010; +v0000000000bdab50_2011 .array/port v0000000000bdab50, 2011; +v0000000000bdab50_2012 .array/port v0000000000bdab50, 2012; +E_00000000006a3090/503 .event edge, v0000000000bdab50_2009, v0000000000bdab50_2010, v0000000000bdab50_2011, v0000000000bdab50_2012; +v0000000000bdab50_2013 .array/port v0000000000bdab50, 2013; +v0000000000bdab50_2014 .array/port v0000000000bdab50, 2014; +v0000000000bdab50_2015 .array/port v0000000000bdab50, 2015; +v0000000000bdab50_2016 .array/port v0000000000bdab50, 2016; +E_00000000006a3090/504 .event edge, v0000000000bdab50_2013, v0000000000bdab50_2014, v0000000000bdab50_2015, v0000000000bdab50_2016; +v0000000000bdab50_2017 .array/port v0000000000bdab50, 2017; +v0000000000bdab50_2018 .array/port v0000000000bdab50, 2018; +v0000000000bdab50_2019 .array/port v0000000000bdab50, 2019; +v0000000000bdab50_2020 .array/port v0000000000bdab50, 2020; +E_00000000006a3090/505 .event edge, v0000000000bdab50_2017, v0000000000bdab50_2018, v0000000000bdab50_2019, v0000000000bdab50_2020; +v0000000000bdab50_2021 .array/port v0000000000bdab50, 2021; +v0000000000bdab50_2022 .array/port v0000000000bdab50, 2022; +v0000000000bdab50_2023 .array/port v0000000000bdab50, 2023; +v0000000000bdab50_2024 .array/port v0000000000bdab50, 2024; +E_00000000006a3090/506 .event edge, v0000000000bdab50_2021, v0000000000bdab50_2022, v0000000000bdab50_2023, v0000000000bdab50_2024; +v0000000000bdab50_2025 .array/port v0000000000bdab50, 2025; +v0000000000bdab50_2026 .array/port v0000000000bdab50, 2026; +v0000000000bdab50_2027 .array/port v0000000000bdab50, 2027; +v0000000000bdab50_2028 .array/port v0000000000bdab50, 2028; +E_00000000006a3090/507 .event edge, v0000000000bdab50_2025, v0000000000bdab50_2026, v0000000000bdab50_2027, v0000000000bdab50_2028; +v0000000000bdab50_2029 .array/port v0000000000bdab50, 2029; +v0000000000bdab50_2030 .array/port v0000000000bdab50, 2030; +v0000000000bdab50_2031 .array/port v0000000000bdab50, 2031; +v0000000000bdab50_2032 .array/port v0000000000bdab50, 2032; +E_00000000006a3090/508 .event edge, v0000000000bdab50_2029, v0000000000bdab50_2030, v0000000000bdab50_2031, v0000000000bdab50_2032; +v0000000000bdab50_2033 .array/port v0000000000bdab50, 2033; +v0000000000bdab50_2034 .array/port v0000000000bdab50, 2034; +v0000000000bdab50_2035 .array/port v0000000000bdab50, 2035; +v0000000000bdab50_2036 .array/port v0000000000bdab50, 2036; +E_00000000006a3090/509 .event edge, v0000000000bdab50_2033, v0000000000bdab50_2034, v0000000000bdab50_2035, v0000000000bdab50_2036; +v0000000000bdab50_2037 .array/port v0000000000bdab50, 2037; +v0000000000bdab50_2038 .array/port v0000000000bdab50, 2038; +v0000000000bdab50_2039 .array/port v0000000000bdab50, 2039; +v0000000000bdab50_2040 .array/port v0000000000bdab50, 2040; +E_00000000006a3090/510 .event edge, v0000000000bdab50_2037, v0000000000bdab50_2038, v0000000000bdab50_2039, v0000000000bdab50_2040; +v0000000000bdab50_2041 .array/port v0000000000bdab50, 2041; +v0000000000bdab50_2042 .array/port v0000000000bdab50, 2042; +v0000000000bdab50_2043 .array/port v0000000000bdab50, 2043; +v0000000000bdab50_2044 .array/port v0000000000bdab50, 2044; +E_00000000006a3090/511 .event edge, v0000000000bdab50_2041, v0000000000bdab50_2042, v0000000000bdab50_2043, v0000000000bdab50_2044; +v0000000000bdab50_2045 .array/port v0000000000bdab50, 2045; +v0000000000bdab50_2046 .array/port v0000000000bdab50, 2046; +v0000000000bdab50_2047 .array/port v0000000000bdab50, 2047; +E_00000000006a3090/512 .event edge, v0000000000bdab50_2045, v0000000000bdab50_2046, v0000000000bdab50_2047; +E_00000000006a3090 .event/or E_00000000006a3090/0, E_00000000006a3090/1, E_00000000006a3090/2, E_00000000006a3090/3, E_00000000006a3090/4, E_00000000006a3090/5, E_00000000006a3090/6, E_00000000006a3090/7, E_00000000006a3090/8, E_00000000006a3090/9, E_00000000006a3090/10, E_00000000006a3090/11, E_00000000006a3090/12, E_00000000006a3090/13, E_00000000006a3090/14, E_00000000006a3090/15, E_00000000006a3090/16, E_00000000006a3090/17, E_00000000006a3090/18, E_00000000006a3090/19, E_00000000006a3090/20, E_00000000006a3090/21, E_00000000006a3090/22, E_00000000006a3090/23, E_00000000006a3090/24, E_00000000006a3090/25, E_00000000006a3090/26, E_00000000006a3090/27, E_00000000006a3090/28, E_00000000006a3090/29, E_00000000006a3090/30, E_00000000006a3090/31, E_00000000006a3090/32, E_00000000006a3090/33, E_00000000006a3090/34, E_00000000006a3090/35, E_00000000006a3090/36, E_00000000006a3090/37, E_00000000006a3090/38, E_00000000006a3090/39, E_00000000006a3090/40, E_00000000006a3090/41, E_00000000006a3090/42, E_00000000006a3090/43, E_00000000006a3090/44, E_00000000006a3090/45, E_00000000006a3090/46, E_00000000006a3090/47, E_00000000006a3090/48, E_00000000006a3090/49, E_00000000006a3090/50, E_00000000006a3090/51, E_00000000006a3090/52, E_00000000006a3090/53, E_00000000006a3090/54, E_00000000006a3090/55, E_00000000006a3090/56, E_00000000006a3090/57, E_00000000006a3090/58, E_00000000006a3090/59, E_00000000006a3090/60, E_00000000006a3090/61, E_00000000006a3090/62, E_00000000006a3090/63, E_00000000006a3090/64, E_00000000006a3090/65, E_00000000006a3090/66, E_00000000006a3090/67, E_00000000006a3090/68, E_00000000006a3090/69, E_00000000006a3090/70, E_00000000006a3090/71, E_00000000006a3090/72, E_00000000006a3090/73, E_00000000006a3090/74, E_00000000006a3090/75, E_00000000006a3090/76, E_00000000006a3090/77, E_00000000006a3090/78, E_00000000006a3090/79, E_00000000006a3090/80, E_00000000006a3090/81, E_00000000006a3090/82, E_00000000006a3090/83, E_00000000006a3090/84, E_00000000006a3090/85, E_00000000006a3090/86, E_00000000006a3090/87, E_00000000006a3090/88, E_00000000006a3090/89, E_00000000006a3090/90, E_00000000006a3090/91, E_00000000006a3090/92, E_00000000006a3090/93, E_00000000006a3090/94, E_00000000006a3090/95, E_00000000006a3090/96, E_00000000006a3090/97, E_00000000006a3090/98, E_00000000006a3090/99, E_00000000006a3090/100, E_00000000006a3090/101, E_00000000006a3090/102, E_00000000006a3090/103, E_00000000006a3090/104, E_00000000006a3090/105, E_00000000006a3090/106, E_00000000006a3090/107, E_00000000006a3090/108, E_00000000006a3090/109, E_00000000006a3090/110, E_00000000006a3090/111, E_00000000006a3090/112, E_00000000006a3090/113, E_00000000006a3090/114, E_00000000006a3090/115, E_00000000006a3090/116, E_00000000006a3090/117, E_00000000006a3090/118, E_00000000006a3090/119, E_00000000006a3090/120, E_00000000006a3090/121, E_00000000006a3090/122, E_00000000006a3090/123, E_00000000006a3090/124, E_00000000006a3090/125, E_00000000006a3090/126, E_00000000006a3090/127, E_00000000006a3090/128, E_00000000006a3090/129, E_00000000006a3090/130, E_00000000006a3090/131, E_00000000006a3090/132, E_00000000006a3090/133, E_00000000006a3090/134, E_00000000006a3090/135, E_00000000006a3090/136, E_00000000006a3090/137, E_00000000006a3090/138, E_00000000006a3090/139, E_00000000006a3090/140, E_00000000006a3090/141, E_00000000006a3090/142, E_00000000006a3090/143, E_00000000006a3090/144, E_00000000006a3090/145, E_00000000006a3090/146, E_00000000006a3090/147, E_00000000006a3090/148, E_00000000006a3090/149, E_00000000006a3090/150, E_00000000006a3090/151, E_00000000006a3090/152, E_00000000006a3090/153, E_00000000006a3090/154, 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E_00000000006a3090/237, E_00000000006a3090/238, E_00000000006a3090/239, E_00000000006a3090/240, E_00000000006a3090/241, E_00000000006a3090/242, E_00000000006a3090/243, E_00000000006a3090/244, E_00000000006a3090/245, E_00000000006a3090/246, E_00000000006a3090/247, E_00000000006a3090/248, E_00000000006a3090/249, E_00000000006a3090/250, E_00000000006a3090/251, E_00000000006a3090/252, E_00000000006a3090/253, E_00000000006a3090/254, E_00000000006a3090/255, E_00000000006a3090/256, E_00000000006a3090/257, E_00000000006a3090/258, E_00000000006a3090/259, E_00000000006a3090/260, E_00000000006a3090/261, E_00000000006a3090/262, E_00000000006a3090/263, E_00000000006a3090/264, E_00000000006a3090/265, E_00000000006a3090/266, E_00000000006a3090/267, E_00000000006a3090/268, E_00000000006a3090/269, E_00000000006a3090/270, E_00000000006a3090/271, E_00000000006a3090/272, E_00000000006a3090/273, E_00000000006a3090/274, E_00000000006a3090/275, E_00000000006a3090/276, E_00000000006a3090/277, E_00000000006a3090/278, E_00000000006a3090/279, E_00000000006a3090/280, E_00000000006a3090/281, E_00000000006a3090/282, E_00000000006a3090/283, E_00000000006a3090/284, E_00000000006a3090/285, E_00000000006a3090/286, E_00000000006a3090/287, E_00000000006a3090/288, E_00000000006a3090/289, E_00000000006a3090/290, E_00000000006a3090/291, E_00000000006a3090/292, E_00000000006a3090/293, E_00000000006a3090/294, E_00000000006a3090/295, E_00000000006a3090/296, E_00000000006a3090/297, E_00000000006a3090/298, E_00000000006a3090/299, E_00000000006a3090/300, E_00000000006a3090/301, E_00000000006a3090/302, E_00000000006a3090/303, E_00000000006a3090/304, E_00000000006a3090/305, E_00000000006a3090/306, E_00000000006a3090/307, E_00000000006a3090/308, E_00000000006a3090/309, E_00000000006a3090/310, E_00000000006a3090/311, E_00000000006a3090/312, E_00000000006a3090/313, E_00000000006a3090/314, E_00000000006a3090/315, E_00000000006a3090/316, E_00000000006a3090/317, E_00000000006a3090/318, E_00000000006a3090/319, E_00000000006a3090/320, E_00000000006a3090/321, E_00000000006a3090/322, E_00000000006a3090/323, E_00000000006a3090/324, E_00000000006a3090/325, E_00000000006a3090/326, E_00000000006a3090/327, E_00000000006a3090/328, E_00000000006a3090/329, E_00000000006a3090/330, E_00000000006a3090/331, E_00000000006a3090/332, E_00000000006a3090/333, E_00000000006a3090/334, E_00000000006a3090/335, E_00000000006a3090/336, E_00000000006a3090/337, E_00000000006a3090/338, E_00000000006a3090/339, E_00000000006a3090/340, E_00000000006a3090/341, E_00000000006a3090/342, E_00000000006a3090/343, E_00000000006a3090/344, E_00000000006a3090/345, E_00000000006a3090/346, E_00000000006a3090/347, E_00000000006a3090/348, E_00000000006a3090/349, E_00000000006a3090/350, E_00000000006a3090/351, E_00000000006a3090/352, E_00000000006a3090/353, E_00000000006a3090/354, E_00000000006a3090/355, E_00000000006a3090/356, E_00000000006a3090/357, E_00000000006a3090/358, E_00000000006a3090/359, E_00000000006a3090/360, E_00000000006a3090/361, E_00000000006a3090/362, E_00000000006a3090/363, E_00000000006a3090/364, E_00000000006a3090/365, E_00000000006a3090/366, E_00000000006a3090/367, E_00000000006a3090/368, E_00000000006a3090/369, E_00000000006a3090/370, E_00000000006a3090/371, E_00000000006a3090/372, E_00000000006a3090/373, E_00000000006a3090/374, E_00000000006a3090/375, E_00000000006a3090/376, E_00000000006a3090/377, E_00000000006a3090/378, E_00000000006a3090/379, E_00000000006a3090/380, E_00000000006a3090/381, E_00000000006a3090/382, E_00000000006a3090/383, E_00000000006a3090/384, E_00000000006a3090/385, E_00000000006a3090/386, E_00000000006a3090/387, E_00000000006a3090/388, E_00000000006a3090/389, E_00000000006a3090/390, E_00000000006a3090/391, E_00000000006a3090/392, E_00000000006a3090/393, E_00000000006a3090/394, E_00000000006a3090/395, E_00000000006a3090/396, E_00000000006a3090/397, E_00000000006a3090/398, E_00000000006a3090/399, E_00000000006a3090/400, E_00000000006a3090/401, E_00000000006a3090/402, E_00000000006a3090/403, E_00000000006a3090/404, E_00000000006a3090/405, E_00000000006a3090/406, E_00000000006a3090/407, E_00000000006a3090/408, E_00000000006a3090/409, E_00000000006a3090/410, E_00000000006a3090/411, E_00000000006a3090/412, E_00000000006a3090/413, E_00000000006a3090/414, E_00000000006a3090/415, E_00000000006a3090/416, E_00000000006a3090/417, E_00000000006a3090/418, E_00000000006a3090/419, E_00000000006a3090/420, E_00000000006a3090/421, E_00000000006a3090/422, E_00000000006a3090/423, E_00000000006a3090/424, E_00000000006a3090/425, E_00000000006a3090/426, E_00000000006a3090/427, E_00000000006a3090/428, E_00000000006a3090/429, E_00000000006a3090/430, E_00000000006a3090/431, E_00000000006a3090/432, E_00000000006a3090/433, E_00000000006a3090/434, E_00000000006a3090/435, E_00000000006a3090/436, E_00000000006a3090/437, E_00000000006a3090/438, E_00000000006a3090/439, E_00000000006a3090/440, E_00000000006a3090/441, E_00000000006a3090/442, E_00000000006a3090/443, E_00000000006a3090/444, E_00000000006a3090/445, E_00000000006a3090/446, E_00000000006a3090/447, E_00000000006a3090/448, E_00000000006a3090/449, E_00000000006a3090/450, E_00000000006a3090/451, E_00000000006a3090/452, E_00000000006a3090/453, E_00000000006a3090/454, E_00000000006a3090/455, E_00000000006a3090/456, E_00000000006a3090/457, E_00000000006a3090/458, E_00000000006a3090/459, E_00000000006a3090/460, E_00000000006a3090/461, E_00000000006a3090/462, E_00000000006a3090/463, E_00000000006a3090/464, E_00000000006a3090/465, E_00000000006a3090/466, E_00000000006a3090/467, E_00000000006a3090/468, E_00000000006a3090/469, E_00000000006a3090/470, E_00000000006a3090/471, E_00000000006a3090/472, E_00000000006a3090/473, E_00000000006a3090/474, E_00000000006a3090/475, E_00000000006a3090/476, E_00000000006a3090/477, E_00000000006a3090/478, E_00000000006a3090/479, E_00000000006a3090/480, E_00000000006a3090/481, E_00000000006a3090/482, E_00000000006a3090/483, E_00000000006a3090/484, E_00000000006a3090/485, E_00000000006a3090/486, E_00000000006a3090/487, E_00000000006a3090/488, E_00000000006a3090/489, E_00000000006a3090/490, E_00000000006a3090/491, E_00000000006a3090/492, E_00000000006a3090/493, E_00000000006a3090/494, E_00000000006a3090/495, E_00000000006a3090/496, E_00000000006a3090/497, E_00000000006a3090/498, E_00000000006a3090/499, E_00000000006a3090/500, E_00000000006a3090/501, E_00000000006a3090/502, E_00000000006a3090/503, E_00000000006a3090/504, E_00000000006a3090/505, E_00000000006a3090/506, E_00000000006a3090/507, E_00000000006a3090/508, E_00000000006a3090/509, E_00000000006a3090/510, E_00000000006a3090/511, E_00000000006a3090/512; +E_00000000006a3010/0 .event edge, v0000000000b25020_0, v0000000000bd9750_0, v0000000000b25480_0, v0000000000bd9e30_0; +E_00000000006a3010/1 .event edge, v0000000000b25520_0, v0000000000bdab50_0, v0000000000bdab50_1, v0000000000bdab50_2; +E_00000000006a3010/2 .event edge, v0000000000bdab50_3, v0000000000bdab50_4, v0000000000bdab50_5, v0000000000bdab50_6; +E_00000000006a3010/3 .event edge, v0000000000bdab50_7, v0000000000bdab50_8, v0000000000bdab50_9, v0000000000bdab50_10; +E_00000000006a3010/4 .event edge, v0000000000bdab50_11, v0000000000bdab50_12, v0000000000bdab50_13, v0000000000bdab50_14; +E_00000000006a3010/5 .event edge, v0000000000bdab50_15, v0000000000bdab50_16, v0000000000bdab50_17, v0000000000bdab50_18; +E_00000000006a3010/6 .event edge, v0000000000bdab50_19, v0000000000bdab50_20, v0000000000bdab50_21, v0000000000bdab50_22; +E_00000000006a3010/7 .event edge, v0000000000bdab50_23, v0000000000bdab50_24, v0000000000bdab50_25, v0000000000bdab50_26; +E_00000000006a3010/8 .event edge, v0000000000bdab50_27, v0000000000bdab50_28, v0000000000bdab50_29, v0000000000bdab50_30; +E_00000000006a3010/9 .event edge, v0000000000bdab50_31, v0000000000bdab50_32, v0000000000bdab50_33, v0000000000bdab50_34; +E_00000000006a3010/10 .event edge, v0000000000bdab50_35, v0000000000bdab50_36, v0000000000bdab50_37, v0000000000bdab50_38; +E_00000000006a3010/11 .event edge, v0000000000bdab50_39, v0000000000bdab50_40, v0000000000bdab50_41, v0000000000bdab50_42; +E_00000000006a3010/12 .event edge, v0000000000bdab50_43, v0000000000bdab50_44, v0000000000bdab50_45, v0000000000bdab50_46; +E_00000000006a3010/13 .event edge, v0000000000bdab50_47, v0000000000bdab50_48, v0000000000bdab50_49, v0000000000bdab50_50; +E_00000000006a3010/14 .event edge, v0000000000bdab50_51, v0000000000bdab50_52, v0000000000bdab50_53, v0000000000bdab50_54; +E_00000000006a3010/15 .event edge, v0000000000bdab50_55, v0000000000bdab50_56, v0000000000bdab50_57, v0000000000bdab50_58; +E_00000000006a3010/16 .event edge, v0000000000bdab50_59, v0000000000bdab50_60, v0000000000bdab50_61, v0000000000bdab50_62; +E_00000000006a3010/17 .event edge, v0000000000bdab50_63, v0000000000bdab50_64, v0000000000bdab50_65, v0000000000bdab50_66; +E_00000000006a3010/18 .event edge, v0000000000bdab50_67, v0000000000bdab50_68, v0000000000bdab50_69, v0000000000bdab50_70; +E_00000000006a3010/19 .event edge, v0000000000bdab50_71, v0000000000bdab50_72, v0000000000bdab50_73, v0000000000bdab50_74; +E_00000000006a3010/20 .event edge, v0000000000bdab50_75, v0000000000bdab50_76, v0000000000bdab50_77, v0000000000bdab50_78; +E_00000000006a3010/21 .event edge, v0000000000bdab50_79, v0000000000bdab50_80, v0000000000bdab50_81, v0000000000bdab50_82; +E_00000000006a3010/22 .event edge, v0000000000bdab50_83, v0000000000bdab50_84, v0000000000bdab50_85, v0000000000bdab50_86; +E_00000000006a3010/23 .event edge, v0000000000bdab50_87, v0000000000bdab50_88, v0000000000bdab50_89, v0000000000bdab50_90; +E_00000000006a3010/24 .event edge, v0000000000bdab50_91, v0000000000bdab50_92, v0000000000bdab50_93, v0000000000bdab50_94; +E_00000000006a3010/25 .event edge, v0000000000bdab50_95, v0000000000bdab50_96, v0000000000bdab50_97, v0000000000bdab50_98; +E_00000000006a3010/26 .event edge, v0000000000bdab50_99, v0000000000bdab50_100, v0000000000bdab50_101, v0000000000bdab50_102; +E_00000000006a3010/27 .event edge, v0000000000bdab50_103, v0000000000bdab50_104, v0000000000bdab50_105, v0000000000bdab50_106; +E_00000000006a3010/28 .event edge, v0000000000bdab50_107, v0000000000bdab50_108, v0000000000bdab50_109, v0000000000bdab50_110; +E_00000000006a3010/29 .event edge, v0000000000bdab50_111, v0000000000bdab50_112, v0000000000bdab50_113, v0000000000bdab50_114; +E_00000000006a3010/30 .event edge, v0000000000bdab50_115, v0000000000bdab50_116, v0000000000bdab50_117, v0000000000bdab50_118; +E_00000000006a3010/31 .event edge, v0000000000bdab50_119, v0000000000bdab50_120, v0000000000bdab50_121, v0000000000bdab50_122; +E_00000000006a3010/32 .event edge, v0000000000bdab50_123, v0000000000bdab50_124, v0000000000bdab50_125, v0000000000bdab50_126; +E_00000000006a3010/33 .event edge, v0000000000bdab50_127, v0000000000bdab50_128, v0000000000bdab50_129, v0000000000bdab50_130; +E_00000000006a3010/34 .event edge, v0000000000bdab50_131, v0000000000bdab50_132, v0000000000bdab50_133, v0000000000bdab50_134; +E_00000000006a3010/35 .event edge, v0000000000bdab50_135, v0000000000bdab50_136, v0000000000bdab50_137, v0000000000bdab50_138; +E_00000000006a3010/36 .event edge, v0000000000bdab50_139, v0000000000bdab50_140, v0000000000bdab50_141, v0000000000bdab50_142; +E_00000000006a3010/37 .event edge, v0000000000bdab50_143, v0000000000bdab50_144, v0000000000bdab50_145, v0000000000bdab50_146; +E_00000000006a3010/38 .event edge, v0000000000bdab50_147, v0000000000bdab50_148, v0000000000bdab50_149, v0000000000bdab50_150; +E_00000000006a3010/39 .event edge, v0000000000bdab50_151, v0000000000bdab50_152, v0000000000bdab50_153, v0000000000bdab50_154; +E_00000000006a3010/40 .event edge, v0000000000bdab50_155, v0000000000bdab50_156, v0000000000bdab50_157, v0000000000bdab50_158; +E_00000000006a3010/41 .event edge, v0000000000bdab50_159, v0000000000bdab50_160, v0000000000bdab50_161, v0000000000bdab50_162; +E_00000000006a3010/42 .event edge, v0000000000bdab50_163, v0000000000bdab50_164, v0000000000bdab50_165, v0000000000bdab50_166; +E_00000000006a3010/43 .event edge, v0000000000bdab50_167, v0000000000bdab50_168, v0000000000bdab50_169, v0000000000bdab50_170; +E_00000000006a3010/44 .event edge, v0000000000bdab50_171, v0000000000bdab50_172, v0000000000bdab50_173, v0000000000bdab50_174; +E_00000000006a3010/45 .event edge, v0000000000bdab50_175, v0000000000bdab50_176, v0000000000bdab50_177, v0000000000bdab50_178; +E_00000000006a3010/46 .event edge, v0000000000bdab50_179, v0000000000bdab50_180, v0000000000bdab50_181, v0000000000bdab50_182; +E_00000000006a3010/47 .event edge, v0000000000bdab50_183, v0000000000bdab50_184, v0000000000bdab50_185, v0000000000bdab50_186; +E_00000000006a3010/48 .event edge, v0000000000bdab50_187, v0000000000bdab50_188, v0000000000bdab50_189, v0000000000bdab50_190; +E_00000000006a3010/49 .event edge, v0000000000bdab50_191, v0000000000bdab50_192, v0000000000bdab50_193, v0000000000bdab50_194; +E_00000000006a3010/50 .event edge, v0000000000bdab50_195, v0000000000bdab50_196, v0000000000bdab50_197, v0000000000bdab50_198; +E_00000000006a3010/51 .event edge, v0000000000bdab50_199, v0000000000bdab50_200, v0000000000bdab50_201, v0000000000bdab50_202; +E_00000000006a3010/52 .event edge, v0000000000bdab50_203, v0000000000bdab50_204, v0000000000bdab50_205, v0000000000bdab50_206; +E_00000000006a3010/53 .event edge, v0000000000bdab50_207, v0000000000bdab50_208, v0000000000bdab50_209, v0000000000bdab50_210; +E_00000000006a3010/54 .event edge, v0000000000bdab50_211, v0000000000bdab50_212, v0000000000bdab50_213, v0000000000bdab50_214; +E_00000000006a3010/55 .event edge, v0000000000bdab50_215, v0000000000bdab50_216, v0000000000bdab50_217, v0000000000bdab50_218; +E_00000000006a3010/56 .event edge, v0000000000bdab50_219, v0000000000bdab50_220, v0000000000bdab50_221, v0000000000bdab50_222; +E_00000000006a3010/57 .event edge, v0000000000bdab50_223, v0000000000bdab50_224, v0000000000bdab50_225, v0000000000bdab50_226; +E_00000000006a3010/58 .event edge, v0000000000bdab50_227, v0000000000bdab50_228, v0000000000bdab50_229, v0000000000bdab50_230; +E_00000000006a3010/59 .event edge, v0000000000bdab50_231, v0000000000bdab50_232, v0000000000bdab50_233, v0000000000bdab50_234; +E_00000000006a3010/60 .event edge, v0000000000bdab50_235, v0000000000bdab50_236, v0000000000bdab50_237, v0000000000bdab50_238; +E_00000000006a3010/61 .event edge, v0000000000bdab50_239, v0000000000bdab50_240, v0000000000bdab50_241, v0000000000bdab50_242; +E_00000000006a3010/62 .event edge, v0000000000bdab50_243, v0000000000bdab50_244, v0000000000bdab50_245, v0000000000bdab50_246; +E_00000000006a3010/63 .event edge, v0000000000bdab50_247, v0000000000bdab50_248, v0000000000bdab50_249, v0000000000bdab50_250; +E_00000000006a3010/64 .event edge, v0000000000bdab50_251, v0000000000bdab50_252, v0000000000bdab50_253, v0000000000bdab50_254; +E_00000000006a3010/65 .event edge, v0000000000bdab50_255, v0000000000bdab50_256, v0000000000bdab50_257, v0000000000bdab50_258; +E_00000000006a3010/66 .event edge, v0000000000bdab50_259, v0000000000bdab50_260, v0000000000bdab50_261, v0000000000bdab50_262; +E_00000000006a3010/67 .event edge, v0000000000bdab50_263, v0000000000bdab50_264, v0000000000bdab50_265, v0000000000bdab50_266; +E_00000000006a3010/68 .event edge, v0000000000bdab50_267, v0000000000bdab50_268, v0000000000bdab50_269, v0000000000bdab50_270; +E_00000000006a3010/69 .event edge, v0000000000bdab50_271, v0000000000bdab50_272, v0000000000bdab50_273, v0000000000bdab50_274; +E_00000000006a3010/70 .event edge, v0000000000bdab50_275, v0000000000bdab50_276, v0000000000bdab50_277, v0000000000bdab50_278; +E_00000000006a3010/71 .event edge, v0000000000bdab50_279, v0000000000bdab50_280, v0000000000bdab50_281, v0000000000bdab50_282; +E_00000000006a3010/72 .event edge, v0000000000bdab50_283, v0000000000bdab50_284, v0000000000bdab50_285, v0000000000bdab50_286; +E_00000000006a3010/73 .event edge, v0000000000bdab50_287, v0000000000bdab50_288, v0000000000bdab50_289, v0000000000bdab50_290; +E_00000000006a3010/74 .event edge, v0000000000bdab50_291, v0000000000bdab50_292, v0000000000bdab50_293, v0000000000bdab50_294; +E_00000000006a3010/75 .event edge, v0000000000bdab50_295, v0000000000bdab50_296, v0000000000bdab50_297, v0000000000bdab50_298; +E_00000000006a3010/76 .event edge, v0000000000bdab50_299, v0000000000bdab50_300, v0000000000bdab50_301, v0000000000bdab50_302; +E_00000000006a3010/77 .event edge, v0000000000bdab50_303, v0000000000bdab50_304, v0000000000bdab50_305, v0000000000bdab50_306; +E_00000000006a3010/78 .event edge, v0000000000bdab50_307, v0000000000bdab50_308, v0000000000bdab50_309, v0000000000bdab50_310; +E_00000000006a3010/79 .event edge, v0000000000bdab50_311, v0000000000bdab50_312, v0000000000bdab50_313, v0000000000bdab50_314; +E_00000000006a3010/80 .event edge, v0000000000bdab50_315, v0000000000bdab50_316, v0000000000bdab50_317, v0000000000bdab50_318; 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v0000000000bdab50_350; +E_00000000006a3010/89 .event edge, v0000000000bdab50_351, v0000000000bdab50_352, v0000000000bdab50_353, v0000000000bdab50_354; +E_00000000006a3010/90 .event edge, v0000000000bdab50_355, v0000000000bdab50_356, v0000000000bdab50_357, v0000000000bdab50_358; +E_00000000006a3010/91 .event edge, v0000000000bdab50_359, v0000000000bdab50_360, v0000000000bdab50_361, v0000000000bdab50_362; +E_00000000006a3010/92 .event edge, v0000000000bdab50_363, v0000000000bdab50_364, v0000000000bdab50_365, v0000000000bdab50_366; +E_00000000006a3010/93 .event edge, v0000000000bdab50_367, v0000000000bdab50_368, v0000000000bdab50_369, v0000000000bdab50_370; +E_00000000006a3010/94 .event edge, v0000000000bdab50_371, v0000000000bdab50_372, v0000000000bdab50_373, v0000000000bdab50_374; +E_00000000006a3010/95 .event edge, v0000000000bdab50_375, v0000000000bdab50_376, v0000000000bdab50_377, v0000000000bdab50_378; +E_00000000006a3010/96 .event edge, v0000000000bdab50_379, v0000000000bdab50_380, v0000000000bdab50_381, v0000000000bdab50_382; +E_00000000006a3010/97 .event edge, v0000000000bdab50_383, v0000000000bdab50_384, v0000000000bdab50_385, v0000000000bdab50_386; +E_00000000006a3010/98 .event edge, v0000000000bdab50_387, v0000000000bdab50_388, v0000000000bdab50_389, v0000000000bdab50_390; +E_00000000006a3010/99 .event edge, v0000000000bdab50_391, v0000000000bdab50_392, v0000000000bdab50_393, v0000000000bdab50_394; +E_00000000006a3010/100 .event edge, v0000000000bdab50_395, v0000000000bdab50_396, v0000000000bdab50_397, v0000000000bdab50_398; +E_00000000006a3010/101 .event edge, v0000000000bdab50_399, v0000000000bdab50_400, v0000000000bdab50_401, v0000000000bdab50_402; +E_00000000006a3010/102 .event edge, v0000000000bdab50_403, v0000000000bdab50_404, v0000000000bdab50_405, v0000000000bdab50_406; +E_00000000006a3010/103 .event edge, v0000000000bdab50_407, v0000000000bdab50_408, v0000000000bdab50_409, v0000000000bdab50_410; +E_00000000006a3010/104 .event edge, v0000000000bdab50_411, v0000000000bdab50_412, v0000000000bdab50_413, v0000000000bdab50_414; +E_00000000006a3010/105 .event edge, v0000000000bdab50_415, v0000000000bdab50_416, v0000000000bdab50_417, v0000000000bdab50_418; +E_00000000006a3010/106 .event edge, v0000000000bdab50_419, v0000000000bdab50_420, v0000000000bdab50_421, v0000000000bdab50_422; +E_00000000006a3010/107 .event edge, v0000000000bdab50_423, v0000000000bdab50_424, v0000000000bdab50_425, v0000000000bdab50_426; +E_00000000006a3010/108 .event edge, v0000000000bdab50_427, v0000000000bdab50_428, v0000000000bdab50_429, v0000000000bdab50_430; +E_00000000006a3010/109 .event edge, v0000000000bdab50_431, v0000000000bdab50_432, v0000000000bdab50_433, v0000000000bdab50_434; +E_00000000006a3010/110 .event edge, v0000000000bdab50_435, v0000000000bdab50_436, v0000000000bdab50_437, v0000000000bdab50_438; +E_00000000006a3010/111 .event edge, v0000000000bdab50_439, v0000000000bdab50_440, v0000000000bdab50_441, v0000000000bdab50_442; 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v0000000000bdab50_473, v0000000000bdab50_474; +E_00000000006a3010/120 .event edge, v0000000000bdab50_475, v0000000000bdab50_476, v0000000000bdab50_477, v0000000000bdab50_478; +E_00000000006a3010/121 .event edge, v0000000000bdab50_479, v0000000000bdab50_480, v0000000000bdab50_481, v0000000000bdab50_482; +E_00000000006a3010/122 .event edge, v0000000000bdab50_483, v0000000000bdab50_484, v0000000000bdab50_485, v0000000000bdab50_486; +E_00000000006a3010/123 .event edge, v0000000000bdab50_487, v0000000000bdab50_488, v0000000000bdab50_489, v0000000000bdab50_490; +E_00000000006a3010/124 .event edge, v0000000000bdab50_491, v0000000000bdab50_492, v0000000000bdab50_493, v0000000000bdab50_494; +E_00000000006a3010/125 .event edge, v0000000000bdab50_495, v0000000000bdab50_496, v0000000000bdab50_497, v0000000000bdab50_498; +E_00000000006a3010/126 .event edge, v0000000000bdab50_499, v0000000000bdab50_500, v0000000000bdab50_501, v0000000000bdab50_502; +E_00000000006a3010/127 .event edge, v0000000000bdab50_503, v0000000000bdab50_504, v0000000000bdab50_505, v0000000000bdab50_506; +E_00000000006a3010/128 .event edge, v0000000000bdab50_507, v0000000000bdab50_508, v0000000000bdab50_509, v0000000000bdab50_510; +E_00000000006a3010/129 .event edge, v0000000000bdab50_511, v0000000000bdab50_512, v0000000000bdab50_513, v0000000000bdab50_514; +E_00000000006a3010/130 .event edge, v0000000000bdab50_515, v0000000000bdab50_516, v0000000000bdab50_517, v0000000000bdab50_518; +E_00000000006a3010/131 .event edge, v0000000000bdab50_519, v0000000000bdab50_520, v0000000000bdab50_521, v0000000000bdab50_522; +E_00000000006a3010/132 .event edge, v0000000000bdab50_523, v0000000000bdab50_524, v0000000000bdab50_525, v0000000000bdab50_526; +E_00000000006a3010/133 .event edge, v0000000000bdab50_527, v0000000000bdab50_528, v0000000000bdab50_529, v0000000000bdab50_530; +E_00000000006a3010/134 .event edge, v0000000000bdab50_531, v0000000000bdab50_532, v0000000000bdab50_533, v0000000000bdab50_534; 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v0000000000bdab50_565, v0000000000bdab50_566; +E_00000000006a3010/143 .event edge, v0000000000bdab50_567, v0000000000bdab50_568, v0000000000bdab50_569, v0000000000bdab50_570; +E_00000000006a3010/144 .event edge, v0000000000bdab50_571, v0000000000bdab50_572, v0000000000bdab50_573, v0000000000bdab50_574; +E_00000000006a3010/145 .event edge, v0000000000bdab50_575, v0000000000bdab50_576, v0000000000bdab50_577, v0000000000bdab50_578; +E_00000000006a3010/146 .event edge, v0000000000bdab50_579, v0000000000bdab50_580, v0000000000bdab50_581, v0000000000bdab50_582; +E_00000000006a3010/147 .event edge, v0000000000bdab50_583, v0000000000bdab50_584, v0000000000bdab50_585, v0000000000bdab50_586; +E_00000000006a3010/148 .event edge, v0000000000bdab50_587, v0000000000bdab50_588, v0000000000bdab50_589, v0000000000bdab50_590; +E_00000000006a3010/149 .event edge, v0000000000bdab50_591, v0000000000bdab50_592, v0000000000bdab50_593, v0000000000bdab50_594; +E_00000000006a3010/150 .event edge, v0000000000bdab50_595, v0000000000bdab50_596, v0000000000bdab50_597, v0000000000bdab50_598; +E_00000000006a3010/151 .event edge, v0000000000bdab50_599, v0000000000bdab50_600, v0000000000bdab50_601, v0000000000bdab50_602; +E_00000000006a3010/152 .event edge, v0000000000bdab50_603, v0000000000bdab50_604, v0000000000bdab50_605, v0000000000bdab50_606; +E_00000000006a3010/153 .event edge, v0000000000bdab50_607, v0000000000bdab50_608, v0000000000bdab50_609, v0000000000bdab50_610; +E_00000000006a3010/154 .event edge, v0000000000bdab50_611, v0000000000bdab50_612, v0000000000bdab50_613, v0000000000bdab50_614; +E_00000000006a3010/155 .event edge, v0000000000bdab50_615, v0000000000bdab50_616, v0000000000bdab50_617, v0000000000bdab50_618; +E_00000000006a3010/156 .event edge, v0000000000bdab50_619, v0000000000bdab50_620, v0000000000bdab50_621, v0000000000bdab50_622; +E_00000000006a3010/157 .event edge, v0000000000bdab50_623, v0000000000bdab50_624, v0000000000bdab50_625, v0000000000bdab50_626; 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v0000000000bdab50_657, v0000000000bdab50_658; +E_00000000006a3010/166 .event edge, v0000000000bdab50_659, v0000000000bdab50_660, v0000000000bdab50_661, v0000000000bdab50_662; +E_00000000006a3010/167 .event edge, v0000000000bdab50_663, v0000000000bdab50_664, v0000000000bdab50_665, v0000000000bdab50_666; +E_00000000006a3010/168 .event edge, v0000000000bdab50_667, v0000000000bdab50_668, v0000000000bdab50_669, v0000000000bdab50_670; +E_00000000006a3010/169 .event edge, v0000000000bdab50_671, v0000000000bdab50_672, v0000000000bdab50_673, v0000000000bdab50_674; +E_00000000006a3010/170 .event edge, v0000000000bdab50_675, v0000000000bdab50_676, v0000000000bdab50_677, v0000000000bdab50_678; +E_00000000006a3010/171 .event edge, v0000000000bdab50_679, v0000000000bdab50_680, v0000000000bdab50_681, v0000000000bdab50_682; +E_00000000006a3010/172 .event edge, v0000000000bdab50_683, v0000000000bdab50_684, v0000000000bdab50_685, v0000000000bdab50_686; +E_00000000006a3010/173 .event edge, v0000000000bdab50_687, v0000000000bdab50_688, v0000000000bdab50_689, v0000000000bdab50_690; +E_00000000006a3010/174 .event edge, v0000000000bdab50_691, v0000000000bdab50_692, v0000000000bdab50_693, v0000000000bdab50_694; +E_00000000006a3010/175 .event edge, v0000000000bdab50_695, v0000000000bdab50_696, v0000000000bdab50_697, v0000000000bdab50_698; +E_00000000006a3010/176 .event edge, v0000000000bdab50_699, v0000000000bdab50_700, v0000000000bdab50_701, v0000000000bdab50_702; +E_00000000006a3010/177 .event edge, v0000000000bdab50_703, v0000000000bdab50_704, v0000000000bdab50_705, v0000000000bdab50_706; +E_00000000006a3010/178 .event edge, v0000000000bdab50_707, v0000000000bdab50_708, v0000000000bdab50_709, v0000000000bdab50_710; +E_00000000006a3010/179 .event edge, v0000000000bdab50_711, v0000000000bdab50_712, v0000000000bdab50_713, v0000000000bdab50_714; +E_00000000006a3010/180 .event edge, v0000000000bdab50_715, v0000000000bdab50_716, v0000000000bdab50_717, v0000000000bdab50_718; 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v0000000000bdab50_749, v0000000000bdab50_750; +E_00000000006a3010/189 .event edge, v0000000000bdab50_751, v0000000000bdab50_752, v0000000000bdab50_753, v0000000000bdab50_754; +E_00000000006a3010/190 .event edge, v0000000000bdab50_755, v0000000000bdab50_756, v0000000000bdab50_757, v0000000000bdab50_758; +E_00000000006a3010/191 .event edge, v0000000000bdab50_759, v0000000000bdab50_760, v0000000000bdab50_761, v0000000000bdab50_762; +E_00000000006a3010/192 .event edge, v0000000000bdab50_763, v0000000000bdab50_764, v0000000000bdab50_765, v0000000000bdab50_766; +E_00000000006a3010/193 .event edge, v0000000000bdab50_767, v0000000000bdab50_768, v0000000000bdab50_769, v0000000000bdab50_770; +E_00000000006a3010/194 .event edge, v0000000000bdab50_771, v0000000000bdab50_772, v0000000000bdab50_773, v0000000000bdab50_774; +E_00000000006a3010/195 .event edge, v0000000000bdab50_775, v0000000000bdab50_776, v0000000000bdab50_777, v0000000000bdab50_778; +E_00000000006a3010/196 .event edge, v0000000000bdab50_779, v0000000000bdab50_780, v0000000000bdab50_781, v0000000000bdab50_782; +E_00000000006a3010/197 .event edge, v0000000000bdab50_783, v0000000000bdab50_784, v0000000000bdab50_785, v0000000000bdab50_786; +E_00000000006a3010/198 .event edge, v0000000000bdab50_787, v0000000000bdab50_788, v0000000000bdab50_789, v0000000000bdab50_790; +E_00000000006a3010/199 .event edge, v0000000000bdab50_791, v0000000000bdab50_792, v0000000000bdab50_793, v0000000000bdab50_794; +E_00000000006a3010/200 .event edge, v0000000000bdab50_795, v0000000000bdab50_796, v0000000000bdab50_797, v0000000000bdab50_798; +E_00000000006a3010/201 .event edge, v0000000000bdab50_799, v0000000000bdab50_800, v0000000000bdab50_801, v0000000000bdab50_802; +E_00000000006a3010/202 .event edge, v0000000000bdab50_803, v0000000000bdab50_804, v0000000000bdab50_805, v0000000000bdab50_806; +E_00000000006a3010/203 .event edge, v0000000000bdab50_807, v0000000000bdab50_808, v0000000000bdab50_809, v0000000000bdab50_810; +E_00000000006a3010/204 .event edge, v0000000000bdab50_811, v0000000000bdab50_812, v0000000000bdab50_813, v0000000000bdab50_814; +E_00000000006a3010/205 .event edge, v0000000000bdab50_815, v0000000000bdab50_816, v0000000000bdab50_817, v0000000000bdab50_818; +E_00000000006a3010/206 .event edge, v0000000000bdab50_819, v0000000000bdab50_820, v0000000000bdab50_821, v0000000000bdab50_822; +E_00000000006a3010/207 .event edge, v0000000000bdab50_823, v0000000000bdab50_824, v0000000000bdab50_825, v0000000000bdab50_826; +E_00000000006a3010/208 .event edge, v0000000000bdab50_827, v0000000000bdab50_828, v0000000000bdab50_829, v0000000000bdab50_830; +E_00000000006a3010/209 .event edge, v0000000000bdab50_831, v0000000000bdab50_832, v0000000000bdab50_833, v0000000000bdab50_834; +E_00000000006a3010/210 .event edge, v0000000000bdab50_835, v0000000000bdab50_836, v0000000000bdab50_837, v0000000000bdab50_838; +E_00000000006a3010/211 .event edge, v0000000000bdab50_839, v0000000000bdab50_840, v0000000000bdab50_841, v0000000000bdab50_842; +E_00000000006a3010/212 .event edge, v0000000000bdab50_843, v0000000000bdab50_844, v0000000000bdab50_845, v0000000000bdab50_846; +E_00000000006a3010/213 .event edge, v0000000000bdab50_847, v0000000000bdab50_848, v0000000000bdab50_849, v0000000000bdab50_850; +E_00000000006a3010/214 .event edge, v0000000000bdab50_851, v0000000000bdab50_852, v0000000000bdab50_853, v0000000000bdab50_854; +E_00000000006a3010/215 .event edge, v0000000000bdab50_855, v0000000000bdab50_856, v0000000000bdab50_857, v0000000000bdab50_858; +E_00000000006a3010/216 .event edge, v0000000000bdab50_859, v0000000000bdab50_860, v0000000000bdab50_861, v0000000000bdab50_862; +E_00000000006a3010/217 .event edge, v0000000000bdab50_863, v0000000000bdab50_864, v0000000000bdab50_865, v0000000000bdab50_866; +E_00000000006a3010/218 .event edge, v0000000000bdab50_867, v0000000000bdab50_868, v0000000000bdab50_869, v0000000000bdab50_870; +E_00000000006a3010/219 .event edge, v0000000000bdab50_871, v0000000000bdab50_872, v0000000000bdab50_873, v0000000000bdab50_874; +E_00000000006a3010/220 .event edge, v0000000000bdab50_875, v0000000000bdab50_876, v0000000000bdab50_877, v0000000000bdab50_878; +E_00000000006a3010/221 .event edge, v0000000000bdab50_879, v0000000000bdab50_880, v0000000000bdab50_881, v0000000000bdab50_882; +E_00000000006a3010/222 .event edge, v0000000000bdab50_883, v0000000000bdab50_884, v0000000000bdab50_885, v0000000000bdab50_886; +E_00000000006a3010/223 .event edge, v0000000000bdab50_887, v0000000000bdab50_888, v0000000000bdab50_889, v0000000000bdab50_890; +E_00000000006a3010/224 .event edge, v0000000000bdab50_891, v0000000000bdab50_892, v0000000000bdab50_893, v0000000000bdab50_894; +E_00000000006a3010/225 .event edge, v0000000000bdab50_895, v0000000000bdab50_896, v0000000000bdab50_897, v0000000000bdab50_898; +E_00000000006a3010/226 .event edge, v0000000000bdab50_899, v0000000000bdab50_900, v0000000000bdab50_901, v0000000000bdab50_902; +E_00000000006a3010/227 .event edge, v0000000000bdab50_903, v0000000000bdab50_904, v0000000000bdab50_905, v0000000000bdab50_906; +E_00000000006a3010/228 .event edge, v0000000000bdab50_907, v0000000000bdab50_908, v0000000000bdab50_909, v0000000000bdab50_910; +E_00000000006a3010/229 .event edge, v0000000000bdab50_911, v0000000000bdab50_912, v0000000000bdab50_913, v0000000000bdab50_914; +E_00000000006a3010/230 .event edge, v0000000000bdab50_915, v0000000000bdab50_916, v0000000000bdab50_917, v0000000000bdab50_918; +E_00000000006a3010/231 .event edge, v0000000000bdab50_919, v0000000000bdab50_920, v0000000000bdab50_921, v0000000000bdab50_922; +E_00000000006a3010/232 .event edge, v0000000000bdab50_923, v0000000000bdab50_924, v0000000000bdab50_925, v0000000000bdab50_926; +E_00000000006a3010/233 .event edge, v0000000000bdab50_927, v0000000000bdab50_928, v0000000000bdab50_929, v0000000000bdab50_930; +E_00000000006a3010/234 .event edge, v0000000000bdab50_931, v0000000000bdab50_932, v0000000000bdab50_933, v0000000000bdab50_934; +E_00000000006a3010/235 .event edge, v0000000000bdab50_935, v0000000000bdab50_936, v0000000000bdab50_937, v0000000000bdab50_938; +E_00000000006a3010/236 .event edge, v0000000000bdab50_939, v0000000000bdab50_940, v0000000000bdab50_941, v0000000000bdab50_942; +E_00000000006a3010/237 .event edge, v0000000000bdab50_943, v0000000000bdab50_944, v0000000000bdab50_945, v0000000000bdab50_946; +E_00000000006a3010/238 .event edge, v0000000000bdab50_947, v0000000000bdab50_948, v0000000000bdab50_949, v0000000000bdab50_950; +E_00000000006a3010/239 .event edge, v0000000000bdab50_951, v0000000000bdab50_952, v0000000000bdab50_953, v0000000000bdab50_954; +E_00000000006a3010/240 .event edge, v0000000000bdab50_955, v0000000000bdab50_956, v0000000000bdab50_957, v0000000000bdab50_958; +E_00000000006a3010/241 .event edge, v0000000000bdab50_959, v0000000000bdab50_960, v0000000000bdab50_961, v0000000000bdab50_962; +E_00000000006a3010/242 .event edge, v0000000000bdab50_963, v0000000000bdab50_964, v0000000000bdab50_965, v0000000000bdab50_966; +E_00000000006a3010/243 .event edge, v0000000000bdab50_967, v0000000000bdab50_968, v0000000000bdab50_969, v0000000000bdab50_970; +E_00000000006a3010/244 .event edge, v0000000000bdab50_971, v0000000000bdab50_972, v0000000000bdab50_973, v0000000000bdab50_974; +E_00000000006a3010/245 .event edge, v0000000000bdab50_975, v0000000000bdab50_976, v0000000000bdab50_977, v0000000000bdab50_978; +E_00000000006a3010/246 .event edge, v0000000000bdab50_979, v0000000000bdab50_980, v0000000000bdab50_981, v0000000000bdab50_982; +E_00000000006a3010/247 .event edge, v0000000000bdab50_983, v0000000000bdab50_984, v0000000000bdab50_985, v0000000000bdab50_986; +E_00000000006a3010/248 .event edge, v0000000000bdab50_987, v0000000000bdab50_988, v0000000000bdab50_989, v0000000000bdab50_990; +E_00000000006a3010/249 .event edge, v0000000000bdab50_991, v0000000000bdab50_992, v0000000000bdab50_993, v0000000000bdab50_994; +E_00000000006a3010/250 .event edge, v0000000000bdab50_995, v0000000000bdab50_996, v0000000000bdab50_997, v0000000000bdab50_998; +E_00000000006a3010/251 .event edge, v0000000000bdab50_999, v0000000000bdab50_1000, v0000000000bdab50_1001, v0000000000bdab50_1002; +E_00000000006a3010/252 .event edge, v0000000000bdab50_1003, v0000000000bdab50_1004, v0000000000bdab50_1005, v0000000000bdab50_1006; +E_00000000006a3010/253 .event edge, v0000000000bdab50_1007, v0000000000bdab50_1008, v0000000000bdab50_1009, v0000000000bdab50_1010; +E_00000000006a3010/254 .event edge, v0000000000bdab50_1011, v0000000000bdab50_1012, v0000000000bdab50_1013, v0000000000bdab50_1014; +E_00000000006a3010/255 .event edge, v0000000000bdab50_1015, v0000000000bdab50_1016, v0000000000bdab50_1017, v0000000000bdab50_1018; +E_00000000006a3010/256 .event edge, v0000000000bdab50_1019, v0000000000bdab50_1020, v0000000000bdab50_1021, v0000000000bdab50_1022; +E_00000000006a3010/257 .event edge, v0000000000bdab50_1023, v0000000000bdab50_1024, v0000000000bdab50_1025, v0000000000bdab50_1026; +E_00000000006a3010/258 .event edge, v0000000000bdab50_1027, v0000000000bdab50_1028, v0000000000bdab50_1029, v0000000000bdab50_1030; +E_00000000006a3010/259 .event edge, v0000000000bdab50_1031, v0000000000bdab50_1032, v0000000000bdab50_1033, v0000000000bdab50_1034; +E_00000000006a3010/260 .event edge, v0000000000bdab50_1035, v0000000000bdab50_1036, v0000000000bdab50_1037, v0000000000bdab50_1038; +E_00000000006a3010/261 .event edge, v0000000000bdab50_1039, v0000000000bdab50_1040, v0000000000bdab50_1041, v0000000000bdab50_1042; +E_00000000006a3010/262 .event edge, v0000000000bdab50_1043, v0000000000bdab50_1044, v0000000000bdab50_1045, v0000000000bdab50_1046; +E_00000000006a3010/263 .event edge, v0000000000bdab50_1047, v0000000000bdab50_1048, v0000000000bdab50_1049, v0000000000bdab50_1050; +E_00000000006a3010/264 .event edge, v0000000000bdab50_1051, v0000000000bdab50_1052, v0000000000bdab50_1053, v0000000000bdab50_1054; +E_00000000006a3010/265 .event edge, v0000000000bdab50_1055, v0000000000bdab50_1056, v0000000000bdab50_1057, v0000000000bdab50_1058; +E_00000000006a3010/266 .event edge, v0000000000bdab50_1059, v0000000000bdab50_1060, v0000000000bdab50_1061, v0000000000bdab50_1062; +E_00000000006a3010/267 .event edge, v0000000000bdab50_1063, v0000000000bdab50_1064, v0000000000bdab50_1065, v0000000000bdab50_1066; +E_00000000006a3010/268 .event edge, v0000000000bdab50_1067, v0000000000bdab50_1068, v0000000000bdab50_1069, v0000000000bdab50_1070; +E_00000000006a3010/269 .event edge, v0000000000bdab50_1071, v0000000000bdab50_1072, v0000000000bdab50_1073, v0000000000bdab50_1074; +E_00000000006a3010/270 .event edge, v0000000000bdab50_1075, v0000000000bdab50_1076, v0000000000bdab50_1077, v0000000000bdab50_1078; +E_00000000006a3010/271 .event edge, v0000000000bdab50_1079, v0000000000bdab50_1080, v0000000000bdab50_1081, v0000000000bdab50_1082; +E_00000000006a3010/272 .event edge, v0000000000bdab50_1083, v0000000000bdab50_1084, v0000000000bdab50_1085, v0000000000bdab50_1086; +E_00000000006a3010/273 .event edge, v0000000000bdab50_1087, v0000000000bdab50_1088, v0000000000bdab50_1089, v0000000000bdab50_1090; +E_00000000006a3010/274 .event edge, v0000000000bdab50_1091, v0000000000bdab50_1092, v0000000000bdab50_1093, v0000000000bdab50_1094; +E_00000000006a3010/275 .event edge, v0000000000bdab50_1095, v0000000000bdab50_1096, v0000000000bdab50_1097, v0000000000bdab50_1098; +E_00000000006a3010/276 .event edge, v0000000000bdab50_1099, v0000000000bdab50_1100, v0000000000bdab50_1101, v0000000000bdab50_1102; +E_00000000006a3010/277 .event edge, v0000000000bdab50_1103, v0000000000bdab50_1104, v0000000000bdab50_1105, v0000000000bdab50_1106; +E_00000000006a3010/278 .event edge, v0000000000bdab50_1107, v0000000000bdab50_1108, v0000000000bdab50_1109, v0000000000bdab50_1110; +E_00000000006a3010/279 .event edge, v0000000000bdab50_1111, v0000000000bdab50_1112, v0000000000bdab50_1113, v0000000000bdab50_1114; +E_00000000006a3010/280 .event edge, v0000000000bdab50_1115, v0000000000bdab50_1116, v0000000000bdab50_1117, v0000000000bdab50_1118; +E_00000000006a3010/281 .event edge, v0000000000bdab50_1119, v0000000000bdab50_1120, v0000000000bdab50_1121, v0000000000bdab50_1122; +E_00000000006a3010/282 .event edge, v0000000000bdab50_1123, v0000000000bdab50_1124, v0000000000bdab50_1125, v0000000000bdab50_1126; +E_00000000006a3010/283 .event edge, v0000000000bdab50_1127, v0000000000bdab50_1128, v0000000000bdab50_1129, v0000000000bdab50_1130; +E_00000000006a3010/284 .event edge, v0000000000bdab50_1131, v0000000000bdab50_1132, v0000000000bdab50_1133, v0000000000bdab50_1134; +E_00000000006a3010/285 .event edge, v0000000000bdab50_1135, v0000000000bdab50_1136, v0000000000bdab50_1137, v0000000000bdab50_1138; +E_00000000006a3010/286 .event edge, v0000000000bdab50_1139, v0000000000bdab50_1140, v0000000000bdab50_1141, v0000000000bdab50_1142; +E_00000000006a3010/287 .event edge, v0000000000bdab50_1143, v0000000000bdab50_1144, v0000000000bdab50_1145, v0000000000bdab50_1146; +E_00000000006a3010/288 .event edge, v0000000000bdab50_1147, v0000000000bdab50_1148, v0000000000bdab50_1149, v0000000000bdab50_1150; +E_00000000006a3010/289 .event edge, v0000000000bdab50_1151, v0000000000bdab50_1152, v0000000000bdab50_1153, v0000000000bdab50_1154; +E_00000000006a3010/290 .event edge, v0000000000bdab50_1155, v0000000000bdab50_1156, v0000000000bdab50_1157, v0000000000bdab50_1158; +E_00000000006a3010/291 .event edge, v0000000000bdab50_1159, v0000000000bdab50_1160, v0000000000bdab50_1161, v0000000000bdab50_1162; +E_00000000006a3010/292 .event edge, v0000000000bdab50_1163, v0000000000bdab50_1164, v0000000000bdab50_1165, v0000000000bdab50_1166; +E_00000000006a3010/293 .event edge, v0000000000bdab50_1167, v0000000000bdab50_1168, v0000000000bdab50_1169, v0000000000bdab50_1170; +E_00000000006a3010/294 .event edge, v0000000000bdab50_1171, v0000000000bdab50_1172, v0000000000bdab50_1173, v0000000000bdab50_1174; +E_00000000006a3010/295 .event edge, v0000000000bdab50_1175, v0000000000bdab50_1176, v0000000000bdab50_1177, v0000000000bdab50_1178; +E_00000000006a3010/296 .event edge, v0000000000bdab50_1179, v0000000000bdab50_1180, v0000000000bdab50_1181, v0000000000bdab50_1182; +E_00000000006a3010/297 .event edge, v0000000000bdab50_1183, v0000000000bdab50_1184, v0000000000bdab50_1185, v0000000000bdab50_1186; +E_00000000006a3010/298 .event edge, v0000000000bdab50_1187, v0000000000bdab50_1188, v0000000000bdab50_1189, v0000000000bdab50_1190; +E_00000000006a3010/299 .event edge, v0000000000bdab50_1191, v0000000000bdab50_1192, v0000000000bdab50_1193, v0000000000bdab50_1194; +E_00000000006a3010/300 .event edge, v0000000000bdab50_1195, v0000000000bdab50_1196, v0000000000bdab50_1197, v0000000000bdab50_1198; +E_00000000006a3010/301 .event edge, v0000000000bdab50_1199, v0000000000bdab50_1200, v0000000000bdab50_1201, v0000000000bdab50_1202; +E_00000000006a3010/302 .event edge, v0000000000bdab50_1203, v0000000000bdab50_1204, v0000000000bdab50_1205, v0000000000bdab50_1206; +E_00000000006a3010/303 .event edge, v0000000000bdab50_1207, v0000000000bdab50_1208, v0000000000bdab50_1209, v0000000000bdab50_1210; +E_00000000006a3010/304 .event edge, v0000000000bdab50_1211, v0000000000bdab50_1212, v0000000000bdab50_1213, v0000000000bdab50_1214; +E_00000000006a3010/305 .event edge, v0000000000bdab50_1215, v0000000000bdab50_1216, v0000000000bdab50_1217, v0000000000bdab50_1218; +E_00000000006a3010/306 .event edge, v0000000000bdab50_1219, v0000000000bdab50_1220, v0000000000bdab50_1221, v0000000000bdab50_1222; +E_00000000006a3010/307 .event edge, v0000000000bdab50_1223, v0000000000bdab50_1224, v0000000000bdab50_1225, v0000000000bdab50_1226; +E_00000000006a3010/308 .event edge, v0000000000bdab50_1227, v0000000000bdab50_1228, v0000000000bdab50_1229, v0000000000bdab50_1230; +E_00000000006a3010/309 .event edge, v0000000000bdab50_1231, v0000000000bdab50_1232, v0000000000bdab50_1233, v0000000000bdab50_1234; +E_00000000006a3010/310 .event edge, v0000000000bdab50_1235, v0000000000bdab50_1236, v0000000000bdab50_1237, v0000000000bdab50_1238; +E_00000000006a3010/311 .event edge, v0000000000bdab50_1239, v0000000000bdab50_1240, v0000000000bdab50_1241, v0000000000bdab50_1242; +E_00000000006a3010/312 .event edge, v0000000000bdab50_1243, v0000000000bdab50_1244, v0000000000bdab50_1245, v0000000000bdab50_1246; +E_00000000006a3010/313 .event edge, v0000000000bdab50_1247, v0000000000bdab50_1248, v0000000000bdab50_1249, v0000000000bdab50_1250; +E_00000000006a3010/314 .event edge, v0000000000bdab50_1251, v0000000000bdab50_1252, v0000000000bdab50_1253, v0000000000bdab50_1254; +E_00000000006a3010/315 .event edge, v0000000000bdab50_1255, v0000000000bdab50_1256, v0000000000bdab50_1257, v0000000000bdab50_1258; +E_00000000006a3010/316 .event edge, v0000000000bdab50_1259, v0000000000bdab50_1260, v0000000000bdab50_1261, v0000000000bdab50_1262; +E_00000000006a3010/317 .event edge, v0000000000bdab50_1263, v0000000000bdab50_1264, v0000000000bdab50_1265, v0000000000bdab50_1266; +E_00000000006a3010/318 .event edge, v0000000000bdab50_1267, v0000000000bdab50_1268, v0000000000bdab50_1269, v0000000000bdab50_1270; +E_00000000006a3010/319 .event edge, v0000000000bdab50_1271, v0000000000bdab50_1272, v0000000000bdab50_1273, v0000000000bdab50_1274; +E_00000000006a3010/320 .event edge, v0000000000bdab50_1275, v0000000000bdab50_1276, v0000000000bdab50_1277, v0000000000bdab50_1278; +E_00000000006a3010/321 .event edge, v0000000000bdab50_1279, v0000000000bdab50_1280, v0000000000bdab50_1281, v0000000000bdab50_1282; +E_00000000006a3010/322 .event edge, v0000000000bdab50_1283, v0000000000bdab50_1284, v0000000000bdab50_1285, v0000000000bdab50_1286; +E_00000000006a3010/323 .event edge, v0000000000bdab50_1287, v0000000000bdab50_1288, v0000000000bdab50_1289, v0000000000bdab50_1290; +E_00000000006a3010/324 .event edge, v0000000000bdab50_1291, v0000000000bdab50_1292, v0000000000bdab50_1293, v0000000000bdab50_1294; +E_00000000006a3010/325 .event edge, v0000000000bdab50_1295, v0000000000bdab50_1296, v0000000000bdab50_1297, v0000000000bdab50_1298; +E_00000000006a3010/326 .event edge, v0000000000bdab50_1299, v0000000000bdab50_1300, v0000000000bdab50_1301, v0000000000bdab50_1302; +E_00000000006a3010/327 .event edge, v0000000000bdab50_1303, v0000000000bdab50_1304, v0000000000bdab50_1305, v0000000000bdab50_1306; +E_00000000006a3010/328 .event edge, v0000000000bdab50_1307, v0000000000bdab50_1308, v0000000000bdab50_1309, v0000000000bdab50_1310; +E_00000000006a3010/329 .event edge, v0000000000bdab50_1311, v0000000000bdab50_1312, v0000000000bdab50_1313, v0000000000bdab50_1314; +E_00000000006a3010/330 .event edge, v0000000000bdab50_1315, v0000000000bdab50_1316, v0000000000bdab50_1317, v0000000000bdab50_1318; +E_00000000006a3010/331 .event edge, v0000000000bdab50_1319, v0000000000bdab50_1320, v0000000000bdab50_1321, v0000000000bdab50_1322; +E_00000000006a3010/332 .event edge, v0000000000bdab50_1323, v0000000000bdab50_1324, v0000000000bdab50_1325, v0000000000bdab50_1326; +E_00000000006a3010/333 .event edge, v0000000000bdab50_1327, v0000000000bdab50_1328, v0000000000bdab50_1329, v0000000000bdab50_1330; +E_00000000006a3010/334 .event edge, v0000000000bdab50_1331, v0000000000bdab50_1332, v0000000000bdab50_1333, v0000000000bdab50_1334; +E_00000000006a3010/335 .event edge, v0000000000bdab50_1335, v0000000000bdab50_1336, v0000000000bdab50_1337, v0000000000bdab50_1338; +E_00000000006a3010/336 .event edge, v0000000000bdab50_1339, v0000000000bdab50_1340, v0000000000bdab50_1341, v0000000000bdab50_1342; +E_00000000006a3010/337 .event edge, v0000000000bdab50_1343, v0000000000bdab50_1344, v0000000000bdab50_1345, v0000000000bdab50_1346; +E_00000000006a3010/338 .event edge, v0000000000bdab50_1347, v0000000000bdab50_1348, v0000000000bdab50_1349, v0000000000bdab50_1350; +E_00000000006a3010/339 .event edge, v0000000000bdab50_1351, v0000000000bdab50_1352, v0000000000bdab50_1353, v0000000000bdab50_1354; +E_00000000006a3010/340 .event edge, v0000000000bdab50_1355, v0000000000bdab50_1356, v0000000000bdab50_1357, v0000000000bdab50_1358; +E_00000000006a3010/341 .event edge, v0000000000bdab50_1359, v0000000000bdab50_1360, v0000000000bdab50_1361, v0000000000bdab50_1362; +E_00000000006a3010/342 .event edge, v0000000000bdab50_1363, v0000000000bdab50_1364, v0000000000bdab50_1365, v0000000000bdab50_1366; +E_00000000006a3010/343 .event edge, v0000000000bdab50_1367, v0000000000bdab50_1368, v0000000000bdab50_1369, v0000000000bdab50_1370; +E_00000000006a3010/344 .event edge, v0000000000bdab50_1371, v0000000000bdab50_1372, v0000000000bdab50_1373, v0000000000bdab50_1374; +E_00000000006a3010/345 .event edge, v0000000000bdab50_1375, v0000000000bdab50_1376, v0000000000bdab50_1377, v0000000000bdab50_1378; +E_00000000006a3010/346 .event edge, v0000000000bdab50_1379, v0000000000bdab50_1380, v0000000000bdab50_1381, v0000000000bdab50_1382; +E_00000000006a3010/347 .event edge, v0000000000bdab50_1383, v0000000000bdab50_1384, v0000000000bdab50_1385, v0000000000bdab50_1386; +E_00000000006a3010/348 .event edge, v0000000000bdab50_1387, v0000000000bdab50_1388, v0000000000bdab50_1389, v0000000000bdab50_1390; +E_00000000006a3010/349 .event edge, v0000000000bdab50_1391, v0000000000bdab50_1392, v0000000000bdab50_1393, v0000000000bdab50_1394; +E_00000000006a3010/350 .event edge, v0000000000bdab50_1395, v0000000000bdab50_1396, v0000000000bdab50_1397, v0000000000bdab50_1398; +E_00000000006a3010/351 .event edge, v0000000000bdab50_1399, v0000000000bdab50_1400, v0000000000bdab50_1401, v0000000000bdab50_1402; +E_00000000006a3010/352 .event edge, v0000000000bdab50_1403, v0000000000bdab50_1404, v0000000000bdab50_1405, v0000000000bdab50_1406; +E_00000000006a3010/353 .event edge, v0000000000bdab50_1407, v0000000000bdab50_1408, v0000000000bdab50_1409, v0000000000bdab50_1410; +E_00000000006a3010/354 .event edge, v0000000000bdab50_1411, v0000000000bdab50_1412, v0000000000bdab50_1413, v0000000000bdab50_1414; +E_00000000006a3010/355 .event edge, v0000000000bdab50_1415, v0000000000bdab50_1416, v0000000000bdab50_1417, v0000000000bdab50_1418; +E_00000000006a3010/356 .event edge, v0000000000bdab50_1419, v0000000000bdab50_1420, v0000000000bdab50_1421, v0000000000bdab50_1422; +E_00000000006a3010/357 .event edge, v0000000000bdab50_1423, v0000000000bdab50_1424, v0000000000bdab50_1425, v0000000000bdab50_1426; +E_00000000006a3010/358 .event edge, v0000000000bdab50_1427, v0000000000bdab50_1428, v0000000000bdab50_1429, v0000000000bdab50_1430; +E_00000000006a3010/359 .event edge, v0000000000bdab50_1431, v0000000000bdab50_1432, v0000000000bdab50_1433, v0000000000bdab50_1434; +E_00000000006a3010/360 .event edge, v0000000000bdab50_1435, v0000000000bdab50_1436, v0000000000bdab50_1437, v0000000000bdab50_1438; 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v0000000000bdab50_1468, v0000000000bdab50_1469, v0000000000bdab50_1470; +E_00000000006a3010/369 .event edge, v0000000000bdab50_1471, v0000000000bdab50_1472, v0000000000bdab50_1473, v0000000000bdab50_1474; +E_00000000006a3010/370 .event edge, v0000000000bdab50_1475, v0000000000bdab50_1476, v0000000000bdab50_1477, v0000000000bdab50_1478; +E_00000000006a3010/371 .event edge, v0000000000bdab50_1479, v0000000000bdab50_1480, v0000000000bdab50_1481, v0000000000bdab50_1482; +E_00000000006a3010/372 .event edge, v0000000000bdab50_1483, v0000000000bdab50_1484, v0000000000bdab50_1485, v0000000000bdab50_1486; +E_00000000006a3010/373 .event edge, v0000000000bdab50_1487, v0000000000bdab50_1488, v0000000000bdab50_1489, v0000000000bdab50_1490; +E_00000000006a3010/374 .event edge, v0000000000bdab50_1491, v0000000000bdab50_1492, v0000000000bdab50_1493, v0000000000bdab50_1494; +E_00000000006a3010/375 .event edge, v0000000000bdab50_1495, v0000000000bdab50_1496, v0000000000bdab50_1497, v0000000000bdab50_1498; +E_00000000006a3010/376 .event edge, v0000000000bdab50_1499, v0000000000bdab50_1500, v0000000000bdab50_1501, v0000000000bdab50_1502; +E_00000000006a3010/377 .event edge, v0000000000bdab50_1503, v0000000000bdab50_1504, v0000000000bdab50_1505, v0000000000bdab50_1506; +E_00000000006a3010/378 .event edge, v0000000000bdab50_1507, v0000000000bdab50_1508, v0000000000bdab50_1509, v0000000000bdab50_1510; +E_00000000006a3010/379 .event edge, v0000000000bdab50_1511, v0000000000bdab50_1512, v0000000000bdab50_1513, v0000000000bdab50_1514; +E_00000000006a3010/380 .event edge, v0000000000bdab50_1515, v0000000000bdab50_1516, v0000000000bdab50_1517, v0000000000bdab50_1518; +E_00000000006a3010/381 .event edge, v0000000000bdab50_1519, v0000000000bdab50_1520, v0000000000bdab50_1521, v0000000000bdab50_1522; +E_00000000006a3010/382 .event edge, v0000000000bdab50_1523, v0000000000bdab50_1524, v0000000000bdab50_1525, v0000000000bdab50_1526; +E_00000000006a3010/383 .event edge, v0000000000bdab50_1527, v0000000000bdab50_1528, v0000000000bdab50_1529, v0000000000bdab50_1530; +E_00000000006a3010/384 .event edge, v0000000000bdab50_1531, v0000000000bdab50_1532, v0000000000bdab50_1533, v0000000000bdab50_1534; +E_00000000006a3010/385 .event edge, v0000000000bdab50_1535, v0000000000bdab50_1536, v0000000000bdab50_1537, v0000000000bdab50_1538; +E_00000000006a3010/386 .event edge, v0000000000bdab50_1539, v0000000000bdab50_1540, v0000000000bdab50_1541, v0000000000bdab50_1542; +E_00000000006a3010/387 .event edge, v0000000000bdab50_1543, v0000000000bdab50_1544, v0000000000bdab50_1545, v0000000000bdab50_1546; +E_00000000006a3010/388 .event edge, v0000000000bdab50_1547, v0000000000bdab50_1548, v0000000000bdab50_1549, v0000000000bdab50_1550; +E_00000000006a3010/389 .event edge, v0000000000bdab50_1551, v0000000000bdab50_1552, v0000000000bdab50_1553, v0000000000bdab50_1554; +E_00000000006a3010/390 .event edge, v0000000000bdab50_1555, v0000000000bdab50_1556, v0000000000bdab50_1557, v0000000000bdab50_1558; +E_00000000006a3010/391 .event edge, v0000000000bdab50_1559, v0000000000bdab50_1560, v0000000000bdab50_1561, v0000000000bdab50_1562; +E_00000000006a3010/392 .event edge, v0000000000bdab50_1563, v0000000000bdab50_1564, v0000000000bdab50_1565, v0000000000bdab50_1566; +E_00000000006a3010/393 .event edge, v0000000000bdab50_1567, v0000000000bdab50_1568, v0000000000bdab50_1569, v0000000000bdab50_1570; +E_00000000006a3010/394 .event edge, v0000000000bdab50_1571, v0000000000bdab50_1572, v0000000000bdab50_1573, v0000000000bdab50_1574; +E_00000000006a3010/395 .event edge, v0000000000bdab50_1575, v0000000000bdab50_1576, v0000000000bdab50_1577, v0000000000bdab50_1578; +E_00000000006a3010/396 .event edge, v0000000000bdab50_1579, v0000000000bdab50_1580, v0000000000bdab50_1581, v0000000000bdab50_1582; +E_00000000006a3010/397 .event edge, v0000000000bdab50_1583, v0000000000bdab50_1584, v0000000000bdab50_1585, v0000000000bdab50_1586; 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v0000000000bdab50_1616, v0000000000bdab50_1617, v0000000000bdab50_1618; +E_00000000006a3010/406 .event edge, v0000000000bdab50_1619, v0000000000bdab50_1620, v0000000000bdab50_1621, v0000000000bdab50_1622; +E_00000000006a3010/407 .event edge, v0000000000bdab50_1623, v0000000000bdab50_1624, v0000000000bdab50_1625, v0000000000bdab50_1626; +E_00000000006a3010/408 .event edge, v0000000000bdab50_1627, v0000000000bdab50_1628, v0000000000bdab50_1629, v0000000000bdab50_1630; +E_00000000006a3010/409 .event edge, v0000000000bdab50_1631, v0000000000bdab50_1632, v0000000000bdab50_1633, v0000000000bdab50_1634; +E_00000000006a3010/410 .event edge, v0000000000bdab50_1635, v0000000000bdab50_1636, v0000000000bdab50_1637, v0000000000bdab50_1638; +E_00000000006a3010/411 .event edge, v0000000000bdab50_1639, v0000000000bdab50_1640, v0000000000bdab50_1641, v0000000000bdab50_1642; +E_00000000006a3010/412 .event edge, v0000000000bdab50_1643, v0000000000bdab50_1644, v0000000000bdab50_1645, v0000000000bdab50_1646; +E_00000000006a3010/413 .event edge, v0000000000bdab50_1647, v0000000000bdab50_1648, v0000000000bdab50_1649, v0000000000bdab50_1650; +E_00000000006a3010/414 .event edge, v0000000000bdab50_1651, v0000000000bdab50_1652, v0000000000bdab50_1653, v0000000000bdab50_1654; +E_00000000006a3010/415 .event edge, v0000000000bdab50_1655, v0000000000bdab50_1656, v0000000000bdab50_1657, v0000000000bdab50_1658; +E_00000000006a3010/416 .event edge, v0000000000bdab50_1659, v0000000000bdab50_1660, v0000000000bdab50_1661, v0000000000bdab50_1662; +E_00000000006a3010/417 .event edge, v0000000000bdab50_1663, v0000000000bdab50_1664, v0000000000bdab50_1665, v0000000000bdab50_1666; +E_00000000006a3010/418 .event edge, v0000000000bdab50_1667, v0000000000bdab50_1668, v0000000000bdab50_1669, v0000000000bdab50_1670; +E_00000000006a3010/419 .event edge, v0000000000bdab50_1671, v0000000000bdab50_1672, v0000000000bdab50_1673, v0000000000bdab50_1674; +E_00000000006a3010/420 .event edge, v0000000000bdab50_1675, v0000000000bdab50_1676, v0000000000bdab50_1677, v0000000000bdab50_1678; +E_00000000006a3010/421 .event edge, v0000000000bdab50_1679, v0000000000bdab50_1680, v0000000000bdab50_1681, v0000000000bdab50_1682; +E_00000000006a3010/422 .event edge, v0000000000bdab50_1683, v0000000000bdab50_1684, v0000000000bdab50_1685, v0000000000bdab50_1686; +E_00000000006a3010/423 .event edge, v0000000000bdab50_1687, v0000000000bdab50_1688, v0000000000bdab50_1689, v0000000000bdab50_1690; +E_00000000006a3010/424 .event edge, v0000000000bdab50_1691, v0000000000bdab50_1692, v0000000000bdab50_1693, v0000000000bdab50_1694; +E_00000000006a3010/425 .event edge, v0000000000bdab50_1695, v0000000000bdab50_1696, v0000000000bdab50_1697, v0000000000bdab50_1698; +E_00000000006a3010/426 .event edge, v0000000000bdab50_1699, v0000000000bdab50_1700, v0000000000bdab50_1701, v0000000000bdab50_1702; +E_00000000006a3010/427 .event edge, v0000000000bdab50_1703, v0000000000bdab50_1704, v0000000000bdab50_1705, v0000000000bdab50_1706; +E_00000000006a3010/428 .event edge, v0000000000bdab50_1707, v0000000000bdab50_1708, v0000000000bdab50_1709, v0000000000bdab50_1710; +E_00000000006a3010/429 .event edge, v0000000000bdab50_1711, v0000000000bdab50_1712, v0000000000bdab50_1713, v0000000000bdab50_1714; +E_00000000006a3010/430 .event edge, v0000000000bdab50_1715, v0000000000bdab50_1716, v0000000000bdab50_1717, v0000000000bdab50_1718; +E_00000000006a3010/431 .event edge, v0000000000bdab50_1719, v0000000000bdab50_1720, v0000000000bdab50_1721, v0000000000bdab50_1722; +E_00000000006a3010/432 .event edge, v0000000000bdab50_1723, v0000000000bdab50_1724, v0000000000bdab50_1725, v0000000000bdab50_1726; +E_00000000006a3010/433 .event edge, v0000000000bdab50_1727, v0000000000bdab50_1728, v0000000000bdab50_1729, v0000000000bdab50_1730; +E_00000000006a3010/434 .event edge, v0000000000bdab50_1731, v0000000000bdab50_1732, v0000000000bdab50_1733, v0000000000bdab50_1734; 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v0000000000bdab50_1764, v0000000000bdab50_1765, v0000000000bdab50_1766; +E_00000000006a3010/443 .event edge, v0000000000bdab50_1767, v0000000000bdab50_1768, v0000000000bdab50_1769, v0000000000bdab50_1770; +E_00000000006a3010/444 .event edge, v0000000000bdab50_1771, v0000000000bdab50_1772, v0000000000bdab50_1773, v0000000000bdab50_1774; +E_00000000006a3010/445 .event edge, v0000000000bdab50_1775, v0000000000bdab50_1776, v0000000000bdab50_1777, v0000000000bdab50_1778; +E_00000000006a3010/446 .event edge, v0000000000bdab50_1779, v0000000000bdab50_1780, v0000000000bdab50_1781, v0000000000bdab50_1782; +E_00000000006a3010/447 .event edge, v0000000000bdab50_1783, v0000000000bdab50_1784, v0000000000bdab50_1785, v0000000000bdab50_1786; +E_00000000006a3010/448 .event edge, v0000000000bdab50_1787, v0000000000bdab50_1788, v0000000000bdab50_1789, v0000000000bdab50_1790; +E_00000000006a3010/449 .event edge, v0000000000bdab50_1791, v0000000000bdab50_1792, v0000000000bdab50_1793, v0000000000bdab50_1794; +E_00000000006a3010/450 .event edge, v0000000000bdab50_1795, v0000000000bdab50_1796, v0000000000bdab50_1797, v0000000000bdab50_1798; +E_00000000006a3010/451 .event edge, v0000000000bdab50_1799, v0000000000bdab50_1800, v0000000000bdab50_1801, v0000000000bdab50_1802; +E_00000000006a3010/452 .event edge, v0000000000bdab50_1803, v0000000000bdab50_1804, v0000000000bdab50_1805, v0000000000bdab50_1806; +E_00000000006a3010/453 .event edge, v0000000000bdab50_1807, v0000000000bdab50_1808, v0000000000bdab50_1809, v0000000000bdab50_1810; +E_00000000006a3010/454 .event edge, v0000000000bdab50_1811, v0000000000bdab50_1812, v0000000000bdab50_1813, v0000000000bdab50_1814; +E_00000000006a3010/455 .event edge, v0000000000bdab50_1815, v0000000000bdab50_1816, v0000000000bdab50_1817, v0000000000bdab50_1818; +E_00000000006a3010/456 .event edge, v0000000000bdab50_1819, v0000000000bdab50_1820, v0000000000bdab50_1821, v0000000000bdab50_1822; +E_00000000006a3010/457 .event edge, v0000000000bdab50_1823, v0000000000bdab50_1824, v0000000000bdab50_1825, v0000000000bdab50_1826; +E_00000000006a3010/458 .event edge, v0000000000bdab50_1827, v0000000000bdab50_1828, v0000000000bdab50_1829, v0000000000bdab50_1830; +E_00000000006a3010/459 .event edge, v0000000000bdab50_1831, v0000000000bdab50_1832, v0000000000bdab50_1833, v0000000000bdab50_1834; +E_00000000006a3010/460 .event edge, v0000000000bdab50_1835, v0000000000bdab50_1836, v0000000000bdab50_1837, v0000000000bdab50_1838; +E_00000000006a3010/461 .event edge, v0000000000bdab50_1839, v0000000000bdab50_1840, v0000000000bdab50_1841, v0000000000bdab50_1842; +E_00000000006a3010/462 .event edge, v0000000000bdab50_1843, v0000000000bdab50_1844, v0000000000bdab50_1845, v0000000000bdab50_1846; +E_00000000006a3010/463 .event edge, v0000000000bdab50_1847, v0000000000bdab50_1848, v0000000000bdab50_1849, v0000000000bdab50_1850; +E_00000000006a3010/464 .event edge, v0000000000bdab50_1851, v0000000000bdab50_1852, v0000000000bdab50_1853, v0000000000bdab50_1854; +E_00000000006a3010/465 .event edge, v0000000000bdab50_1855, v0000000000bdab50_1856, v0000000000bdab50_1857, v0000000000bdab50_1858; +E_00000000006a3010/466 .event edge, v0000000000bdab50_1859, v0000000000bdab50_1860, v0000000000bdab50_1861, v0000000000bdab50_1862; +E_00000000006a3010/467 .event edge, v0000000000bdab50_1863, v0000000000bdab50_1864, v0000000000bdab50_1865, v0000000000bdab50_1866; +E_00000000006a3010/468 .event edge, v0000000000bdab50_1867, v0000000000bdab50_1868, v0000000000bdab50_1869, v0000000000bdab50_1870; +E_00000000006a3010/469 .event edge, v0000000000bdab50_1871, v0000000000bdab50_1872, v0000000000bdab50_1873, v0000000000bdab50_1874; +E_00000000006a3010/470 .event edge, v0000000000bdab50_1875, v0000000000bdab50_1876, v0000000000bdab50_1877, v0000000000bdab50_1878; +E_00000000006a3010/471 .event edge, v0000000000bdab50_1879, v0000000000bdab50_1880, v0000000000bdab50_1881, v0000000000bdab50_1882; +E_00000000006a3010/472 .event edge, v0000000000bdab50_1883, v0000000000bdab50_1884, v0000000000bdab50_1885, v0000000000bdab50_1886; +E_00000000006a3010/473 .event edge, v0000000000bdab50_1887, v0000000000bdab50_1888, v0000000000bdab50_1889, v0000000000bdab50_1890; +E_00000000006a3010/474 .event edge, v0000000000bdab50_1891, v0000000000bdab50_1892, v0000000000bdab50_1893, v0000000000bdab50_1894; +E_00000000006a3010/475 .event edge, v0000000000bdab50_1895, v0000000000bdab50_1896, v0000000000bdab50_1897, v0000000000bdab50_1898; +E_00000000006a3010/476 .event edge, v0000000000bdab50_1899, v0000000000bdab50_1900, v0000000000bdab50_1901, v0000000000bdab50_1902; +E_00000000006a3010/477 .event edge, v0000000000bdab50_1903, v0000000000bdab50_1904, v0000000000bdab50_1905, v0000000000bdab50_1906; +E_00000000006a3010/478 .event edge, v0000000000bdab50_1907, v0000000000bdab50_1908, v0000000000bdab50_1909, v0000000000bdab50_1910; +E_00000000006a3010/479 .event edge, v0000000000bdab50_1911, v0000000000bdab50_1912, v0000000000bdab50_1913, v0000000000bdab50_1914; +E_00000000006a3010/480 .event edge, v0000000000bdab50_1915, v0000000000bdab50_1916, v0000000000bdab50_1917, v0000000000bdab50_1918; +E_00000000006a3010/481 .event edge, v0000000000bdab50_1919, v0000000000bdab50_1920, v0000000000bdab50_1921, v0000000000bdab50_1922; +E_00000000006a3010/482 .event edge, v0000000000bdab50_1923, v0000000000bdab50_1924, v0000000000bdab50_1925, v0000000000bdab50_1926; +E_00000000006a3010/483 .event edge, v0000000000bdab50_1927, v0000000000bdab50_1928, v0000000000bdab50_1929, v0000000000bdab50_1930; +E_00000000006a3010/484 .event edge, v0000000000bdab50_1931, v0000000000bdab50_1932, v0000000000bdab50_1933, v0000000000bdab50_1934; +E_00000000006a3010/485 .event edge, v0000000000bdab50_1935, v0000000000bdab50_1936, v0000000000bdab50_1937, v0000000000bdab50_1938; +E_00000000006a3010/486 .event edge, v0000000000bdab50_1939, v0000000000bdab50_1940, v0000000000bdab50_1941, v0000000000bdab50_1942; +E_00000000006a3010/487 .event edge, v0000000000bdab50_1943, v0000000000bdab50_1944, v0000000000bdab50_1945, v0000000000bdab50_1946; +E_00000000006a3010/488 .event edge, v0000000000bdab50_1947, v0000000000bdab50_1948, v0000000000bdab50_1949, v0000000000bdab50_1950; +E_00000000006a3010/489 .event edge, v0000000000bdab50_1951, v0000000000bdab50_1952, v0000000000bdab50_1953, v0000000000bdab50_1954; +E_00000000006a3010/490 .event edge, v0000000000bdab50_1955, v0000000000bdab50_1956, v0000000000bdab50_1957, v0000000000bdab50_1958; +E_00000000006a3010/491 .event edge, v0000000000bdab50_1959, v0000000000bdab50_1960, v0000000000bdab50_1961, v0000000000bdab50_1962; +E_00000000006a3010/492 .event edge, v0000000000bdab50_1963, v0000000000bdab50_1964, v0000000000bdab50_1965, v0000000000bdab50_1966; +E_00000000006a3010/493 .event edge, v0000000000bdab50_1967, v0000000000bdab50_1968, v0000000000bdab50_1969, v0000000000bdab50_1970; +E_00000000006a3010/494 .event edge, v0000000000bdab50_1971, v0000000000bdab50_1972, v0000000000bdab50_1973, v0000000000bdab50_1974; +E_00000000006a3010/495 .event edge, v0000000000bdab50_1975, v0000000000bdab50_1976, v0000000000bdab50_1977, v0000000000bdab50_1978; +E_00000000006a3010/496 .event edge, v0000000000bdab50_1979, v0000000000bdab50_1980, v0000000000bdab50_1981, v0000000000bdab50_1982; +E_00000000006a3010/497 .event edge, v0000000000bdab50_1983, v0000000000bdab50_1984, v0000000000bdab50_1985, v0000000000bdab50_1986; +E_00000000006a3010/498 .event edge, v0000000000bdab50_1987, v0000000000bdab50_1988, v0000000000bdab50_1989, v0000000000bdab50_1990; +E_00000000006a3010/499 .event edge, v0000000000bdab50_1991, v0000000000bdab50_1992, v0000000000bdab50_1993, v0000000000bdab50_1994; +E_00000000006a3010/500 .event edge, v0000000000bdab50_1995, v0000000000bdab50_1996, v0000000000bdab50_1997, v0000000000bdab50_1998; +E_00000000006a3010/501 .event edge, v0000000000bdab50_1999, v0000000000bdab50_2000, v0000000000bdab50_2001, v0000000000bdab50_2002; +E_00000000006a3010/502 .event edge, v0000000000bdab50_2003, v0000000000bdab50_2004, v0000000000bdab50_2005, v0000000000bdab50_2006; +E_00000000006a3010/503 .event edge, v0000000000bdab50_2007, v0000000000bdab50_2008, v0000000000bdab50_2009, v0000000000bdab50_2010; +E_00000000006a3010/504 .event edge, v0000000000bdab50_2011, v0000000000bdab50_2012, v0000000000bdab50_2013, v0000000000bdab50_2014; +E_00000000006a3010/505 .event edge, v0000000000bdab50_2015, v0000000000bdab50_2016, v0000000000bdab50_2017, v0000000000bdab50_2018; +E_00000000006a3010/506 .event edge, v0000000000bdab50_2019, v0000000000bdab50_2020, v0000000000bdab50_2021, v0000000000bdab50_2022; +E_00000000006a3010/507 .event edge, v0000000000bdab50_2023, v0000000000bdab50_2024, v0000000000bdab50_2025, v0000000000bdab50_2026; +E_00000000006a3010/508 .event edge, v0000000000bdab50_2027, v0000000000bdab50_2028, v0000000000bdab50_2029, v0000000000bdab50_2030; +E_00000000006a3010/509 .event edge, v0000000000bdab50_2031, v0000000000bdab50_2032, v0000000000bdab50_2033, v0000000000bdab50_2034; +E_00000000006a3010/510 .event edge, v0000000000bdab50_2035, v0000000000bdab50_2036, v0000000000bdab50_2037, v0000000000bdab50_2038; +E_00000000006a3010/511 .event edge, v0000000000bdab50_2039, v0000000000bdab50_2040, v0000000000bdab50_2041, v0000000000bdab50_2042; +E_00000000006a3010/512 .event edge, v0000000000bdab50_2043, v0000000000bdab50_2044, v0000000000bdab50_2045, v0000000000bdab50_2046; +E_00000000006a3010/513 .event edge, v0000000000bdab50_2047; +E_00000000006a3010 .event/or E_00000000006a3010/0, E_00000000006a3010/1, E_00000000006a3010/2, E_00000000006a3010/3, E_00000000006a3010/4, E_00000000006a3010/5, E_00000000006a3010/6, E_00000000006a3010/7, E_00000000006a3010/8, E_00000000006a3010/9, E_00000000006a3010/10, E_00000000006a3010/11, E_00000000006a3010/12, E_00000000006a3010/13, E_00000000006a3010/14, E_00000000006a3010/15, E_00000000006a3010/16, E_00000000006a3010/17, E_00000000006a3010/18, E_00000000006a3010/19, E_00000000006a3010/20, E_00000000006a3010/21, E_00000000006a3010/22, E_00000000006a3010/23, E_00000000006a3010/24, E_00000000006a3010/25, E_00000000006a3010/26, E_00000000006a3010/27, E_00000000006a3010/28, E_00000000006a3010/29, E_00000000006a3010/30, E_00000000006a3010/31, E_00000000006a3010/32, E_00000000006a3010/33, E_00000000006a3010/34, E_00000000006a3010/35, E_00000000006a3010/36, E_00000000006a3010/37, E_00000000006a3010/38, E_00000000006a3010/39, E_00000000006a3010/40, E_00000000006a3010/41, E_00000000006a3010/42, E_00000000006a3010/43, E_00000000006a3010/44, E_00000000006a3010/45, E_00000000006a3010/46, E_00000000006a3010/47, E_00000000006a3010/48, E_00000000006a3010/49, E_00000000006a3010/50, E_00000000006a3010/51, E_00000000006a3010/52, E_00000000006a3010/53, E_00000000006a3010/54, E_00000000006a3010/55, E_00000000006a3010/56, E_00000000006a3010/57, E_00000000006a3010/58, E_00000000006a3010/59, E_00000000006a3010/60, E_00000000006a3010/61, E_00000000006a3010/62, E_00000000006a3010/63, E_00000000006a3010/64, E_00000000006a3010/65, E_00000000006a3010/66, E_00000000006a3010/67, E_00000000006a3010/68, E_00000000006a3010/69, E_00000000006a3010/70, E_00000000006a3010/71, E_00000000006a3010/72, E_00000000006a3010/73, E_00000000006a3010/74, E_00000000006a3010/75, E_00000000006a3010/76, E_00000000006a3010/77, E_00000000006a3010/78, E_00000000006a3010/79, E_00000000006a3010/80, E_00000000006a3010/81, E_00000000006a3010/82, E_00000000006a3010/83, E_00000000006a3010/84, E_00000000006a3010/85, E_00000000006a3010/86, E_00000000006a3010/87, E_00000000006a3010/88, E_00000000006a3010/89, E_00000000006a3010/90, E_00000000006a3010/91, E_00000000006a3010/92, E_00000000006a3010/93, E_00000000006a3010/94, E_00000000006a3010/95, E_00000000006a3010/96, E_00000000006a3010/97, E_00000000006a3010/98, E_00000000006a3010/99, E_00000000006a3010/100, E_00000000006a3010/101, E_00000000006a3010/102, E_00000000006a3010/103, E_00000000006a3010/104, E_00000000006a3010/105, E_00000000006a3010/106, E_00000000006a3010/107, E_00000000006a3010/108, E_00000000006a3010/109, E_00000000006a3010/110, E_00000000006a3010/111, E_00000000006a3010/112, E_00000000006a3010/113, E_00000000006a3010/114, E_00000000006a3010/115, E_00000000006a3010/116, E_00000000006a3010/117, E_00000000006a3010/118, E_00000000006a3010/119, E_00000000006a3010/120, E_00000000006a3010/121, E_00000000006a3010/122, E_00000000006a3010/123, E_00000000006a3010/124, E_00000000006a3010/125, E_00000000006a3010/126, E_00000000006a3010/127, E_00000000006a3010/128, E_00000000006a3010/129, E_00000000006a3010/130, E_00000000006a3010/131, E_00000000006a3010/132, E_00000000006a3010/133, E_00000000006a3010/134, E_00000000006a3010/135, E_00000000006a3010/136, E_00000000006a3010/137, E_00000000006a3010/138, E_00000000006a3010/139, E_00000000006a3010/140, E_00000000006a3010/141, E_00000000006a3010/142, E_00000000006a3010/143, E_00000000006a3010/144, E_00000000006a3010/145, E_00000000006a3010/146, E_00000000006a3010/147, E_00000000006a3010/148, E_00000000006a3010/149, E_00000000006a3010/150, E_00000000006a3010/151, E_00000000006a3010/152, E_00000000006a3010/153, E_00000000006a3010/154, E_00000000006a3010/155, E_00000000006a3010/156, E_00000000006a3010/157, E_00000000006a3010/158, E_00000000006a3010/159, E_00000000006a3010/160, E_00000000006a3010/161, E_00000000006a3010/162, E_00000000006a3010/163, E_00000000006a3010/164, E_00000000006a3010/165, E_00000000006a3010/166, E_00000000006a3010/167, E_00000000006a3010/168, E_00000000006a3010/169, E_00000000006a3010/170, E_00000000006a3010/171, E_00000000006a3010/172, E_00000000006a3010/173, E_00000000006a3010/174, E_00000000006a3010/175, E_00000000006a3010/176, E_00000000006a3010/177, E_00000000006a3010/178, E_00000000006a3010/179, E_00000000006a3010/180, E_00000000006a3010/181, E_00000000006a3010/182, E_00000000006a3010/183, E_00000000006a3010/184, E_00000000006a3010/185, E_00000000006a3010/186, E_00000000006a3010/187, E_00000000006a3010/188, E_00000000006a3010/189, E_00000000006a3010/190, E_00000000006a3010/191, E_00000000006a3010/192, E_00000000006a3010/193, E_00000000006a3010/194, E_00000000006a3010/195, E_00000000006a3010/196, E_00000000006a3010/197, E_00000000006a3010/198, E_00000000006a3010/199, E_00000000006a3010/200, E_00000000006a3010/201, E_00000000006a3010/202, E_00000000006a3010/203, E_00000000006a3010/204, E_00000000006a3010/205, E_00000000006a3010/206, E_00000000006a3010/207, E_00000000006a3010/208, E_00000000006a3010/209, E_00000000006a3010/210, E_00000000006a3010/211, E_00000000006a3010/212, E_00000000006a3010/213, E_00000000006a3010/214, E_00000000006a3010/215, E_00000000006a3010/216, E_00000000006a3010/217, E_00000000006a3010/218, E_00000000006a3010/219, E_00000000006a3010/220, E_00000000006a3010/221, E_00000000006a3010/222, E_00000000006a3010/223, E_00000000006a3010/224, E_00000000006a3010/225, E_00000000006a3010/226, E_00000000006a3010/227, E_00000000006a3010/228, E_00000000006a3010/229, E_00000000006a3010/230, E_00000000006a3010/231, E_00000000006a3010/232, E_00000000006a3010/233, E_00000000006a3010/234, E_00000000006a3010/235, E_00000000006a3010/236, E_00000000006a3010/237, E_00000000006a3010/238, E_00000000006a3010/239, E_00000000006a3010/240, E_00000000006a3010/241, E_00000000006a3010/242, E_00000000006a3010/243, E_00000000006a3010/244, E_00000000006a3010/245, E_00000000006a3010/246, E_00000000006a3010/247, E_00000000006a3010/248, E_00000000006a3010/249, E_00000000006a3010/250, E_00000000006a3010/251, E_00000000006a3010/252, E_00000000006a3010/253, E_00000000006a3010/254, E_00000000006a3010/255, E_00000000006a3010/256, E_00000000006a3010/257, E_00000000006a3010/258, E_00000000006a3010/259, E_00000000006a3010/260, E_00000000006a3010/261, E_00000000006a3010/262, E_00000000006a3010/263, E_00000000006a3010/264, E_00000000006a3010/265, E_00000000006a3010/266, E_00000000006a3010/267, E_00000000006a3010/268, E_00000000006a3010/269, E_00000000006a3010/270, E_00000000006a3010/271, E_00000000006a3010/272, E_00000000006a3010/273, E_00000000006a3010/274, E_00000000006a3010/275, E_00000000006a3010/276, E_00000000006a3010/277, E_00000000006a3010/278, E_00000000006a3010/279, E_00000000006a3010/280, E_00000000006a3010/281, E_00000000006a3010/282, E_00000000006a3010/283, E_00000000006a3010/284, E_00000000006a3010/285, E_00000000006a3010/286, E_00000000006a3010/287, E_00000000006a3010/288, E_00000000006a3010/289, E_00000000006a3010/290, E_00000000006a3010/291, E_00000000006a3010/292, E_00000000006a3010/293, E_00000000006a3010/294, E_00000000006a3010/295, E_00000000006a3010/296, E_00000000006a3010/297, E_00000000006a3010/298, E_00000000006a3010/299, E_00000000006a3010/300, E_00000000006a3010/301, E_00000000006a3010/302, E_00000000006a3010/303, E_00000000006a3010/304, E_00000000006a3010/305, E_00000000006a3010/306, E_00000000006a3010/307, E_00000000006a3010/308, E_00000000006a3010/309, E_00000000006a3010/310, E_00000000006a3010/311, E_00000000006a3010/312, E_00000000006a3010/313, E_00000000006a3010/314, E_00000000006a3010/315, E_00000000006a3010/316, E_00000000006a3010/317, E_00000000006a3010/318, E_00000000006a3010/319, E_00000000006a3010/320, E_00000000006a3010/321, E_00000000006a3010/322, E_00000000006a3010/323, E_00000000006a3010/324, E_00000000006a3010/325, E_00000000006a3010/326, E_00000000006a3010/327, E_00000000006a3010/328, E_00000000006a3010/329, E_00000000006a3010/330, E_00000000006a3010/331, E_00000000006a3010/332, E_00000000006a3010/333, E_00000000006a3010/334, E_00000000006a3010/335, E_00000000006a3010/336, E_00000000006a3010/337, E_00000000006a3010/338, E_00000000006a3010/339, E_00000000006a3010/340, E_00000000006a3010/341, E_00000000006a3010/342, E_00000000006a3010/343, E_00000000006a3010/344, E_00000000006a3010/345, E_00000000006a3010/346, E_00000000006a3010/347, E_00000000006a3010/348, E_00000000006a3010/349, E_00000000006a3010/350, E_00000000006a3010/351, E_00000000006a3010/352, E_00000000006a3010/353, E_00000000006a3010/354, E_00000000006a3010/355, E_00000000006a3010/356, E_00000000006a3010/357, E_00000000006a3010/358, E_00000000006a3010/359, E_00000000006a3010/360, E_00000000006a3010/361, E_00000000006a3010/362, E_00000000006a3010/363, E_00000000006a3010/364, E_00000000006a3010/365, E_00000000006a3010/366, E_00000000006a3010/367, E_00000000006a3010/368, E_00000000006a3010/369, E_00000000006a3010/370, E_00000000006a3010/371, E_00000000006a3010/372, E_00000000006a3010/373, E_00000000006a3010/374, E_00000000006a3010/375, E_00000000006a3010/376, E_00000000006a3010/377, E_00000000006a3010/378, E_00000000006a3010/379, E_00000000006a3010/380, E_00000000006a3010/381, E_00000000006a3010/382, E_00000000006a3010/383, E_00000000006a3010/384, E_00000000006a3010/385, E_00000000006a3010/386, E_00000000006a3010/387, E_00000000006a3010/388, E_00000000006a3010/389, E_00000000006a3010/390, E_00000000006a3010/391, E_00000000006a3010/392, E_00000000006a3010/393, E_00000000006a3010/394, E_00000000006a3010/395, E_00000000006a3010/396, E_00000000006a3010/397, E_00000000006a3010/398, E_00000000006a3010/399, E_00000000006a3010/400, E_00000000006a3010/401, E_00000000006a3010/402, E_00000000006a3010/403, E_00000000006a3010/404, E_00000000006a3010/405, E_00000000006a3010/406, E_00000000006a3010/407, E_00000000006a3010/408, E_00000000006a3010/409, E_00000000006a3010/410, E_00000000006a3010/411, E_00000000006a3010/412, E_00000000006a3010/413, E_00000000006a3010/414, E_00000000006a3010/415, E_00000000006a3010/416, E_00000000006a3010/417, E_00000000006a3010/418, E_00000000006a3010/419, E_00000000006a3010/420, E_00000000006a3010/421, E_00000000006a3010/422, E_00000000006a3010/423, E_00000000006a3010/424, E_00000000006a3010/425, E_00000000006a3010/426, E_00000000006a3010/427, E_00000000006a3010/428, E_00000000006a3010/429, E_00000000006a3010/430, E_00000000006a3010/431, E_00000000006a3010/432, E_00000000006a3010/433, E_00000000006a3010/434, E_00000000006a3010/435, E_00000000006a3010/436, E_00000000006a3010/437, E_00000000006a3010/438, E_00000000006a3010/439, E_00000000006a3010/440, E_00000000006a3010/441, E_00000000006a3010/442, E_00000000006a3010/443, E_00000000006a3010/444, E_00000000006a3010/445, E_00000000006a3010/446, E_00000000006a3010/447, E_00000000006a3010/448, E_00000000006a3010/449, E_00000000006a3010/450, E_00000000006a3010/451, E_00000000006a3010/452, E_00000000006a3010/453, E_00000000006a3010/454, E_00000000006a3010/455, E_00000000006a3010/456, E_00000000006a3010/457, E_00000000006a3010/458, E_00000000006a3010/459, E_00000000006a3010/460, E_00000000006a3010/461, E_00000000006a3010/462, E_00000000006a3010/463, E_00000000006a3010/464, E_00000000006a3010/465, E_00000000006a3010/466, E_00000000006a3010/467, E_00000000006a3010/468, E_00000000006a3010/469, E_00000000006a3010/470, E_00000000006a3010/471, E_00000000006a3010/472, E_00000000006a3010/473, E_00000000006a3010/474, E_00000000006a3010/475, E_00000000006a3010/476, E_00000000006a3010/477, E_00000000006a3010/478, E_00000000006a3010/479, E_00000000006a3010/480, E_00000000006a3010/481, E_00000000006a3010/482, E_00000000006a3010/483, E_00000000006a3010/484, E_00000000006a3010/485, E_00000000006a3010/486, E_00000000006a3010/487, E_00000000006a3010/488, E_00000000006a3010/489, E_00000000006a3010/490, E_00000000006a3010/491, E_00000000006a3010/492, E_00000000006a3010/493, E_00000000006a3010/494, E_00000000006a3010/495, E_00000000006a3010/496, E_00000000006a3010/497, E_00000000006a3010/498, E_00000000006a3010/499, E_00000000006a3010/500, E_00000000006a3010/501, E_00000000006a3010/502, E_00000000006a3010/503, E_00000000006a3010/504, E_00000000006a3010/505, E_00000000006a3010/506, E_00000000006a3010/507, E_00000000006a3010/508, E_00000000006a3010/509, E_00000000006a3010/510, E_00000000006a3010/511, E_00000000006a3010/512, E_00000000006a3010/513; + .scope S_0000000000ac6910; +T_0 ; + %wait E_00000000006a1b90; + %load/vec4 v0000000000bdabf0_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_0.0, 4; + %load/vec4 v0000000000bdadd0_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_0.2, 4; + %load/vec4 v0000000000bdad30_0; + %load/vec4 v0000000000bdac90_0; + %parti/s 12, 2, 3; + %pad/u 13; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000000000bdab50, 0, 4; +T_0.2 ; +T_0.0 ; + %jmp T_0; + .thread T_0; + .scope S_0000000000ac6910; +T_1 ; + %wait E_00000000006a3010; + %load/vec4 v0000000000bdabf0_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_1.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bdaa10_0, 0; + %jmp T_1.1; +T_1.0 ; + %load/vec4 v0000000000bda970_0; + %load/vec4 v0000000000bdac90_0; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000bdaab0_0; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_1.2, 8; + %load/vec4 v0000000000bdad30_0; + %assign/vec4 v0000000000bdaa10_0, 0; + %jmp T_1.3; +T_1.2 ; + %load/vec4 v0000000000bdaab0_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_1.4, 4; + %load/vec4 v0000000000bda970_0; + %ix/load 5, 2, 0; + %flag_set/imm 4, 0; + %shiftr 5; + %ix/vec4 4; + %load/vec4a v0000000000bdab50, 4; + %assign/vec4 v0000000000bdaa10_0, 0; + %jmp T_1.5; +T_1.4 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bdaa10_0, 0; +T_1.5 ; +T_1.3 ; +T_1.1 ; + %jmp T_1; + .thread T_1, $push; + .scope S_0000000000ac6910; +T_2 ; + %wait E_00000000006a3090; + %load/vec4 v0000000000bdabf0_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_2.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bda830_0, 0; + %jmp T_2.1; +T_2.0 ; + %load/vec4 v0000000000bda8d0_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_2.2, 4; + %load/vec4 v0000000000bda790_0; + %parti/s 12, 2, 3; + %pad/u 13; + %ix/vec4 4; + %load/vec4a v0000000000bdab50, 4; + %assign/vec4 v0000000000bda830_0, 0; + %jmp T_2.3; +T_2.2 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bda830_0, 0; +T_2.3 ; +T_2.1 ; + %jmp T_2; + .thread T_2, $push; + .scope S_0000000000aad080; +T_3 ; + %wait E_00000000006a1b90; + %load/vec4 v0000000000bd9ed0_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_3.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bd9d90_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bd9cf0_0, 0; + %jmp T_3.1; +T_3.0 ; + %load/vec4 v0000000000bd9c50_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_3.2, 4; + %load/vec4 v0000000000bd9bb0_0; + %assign/vec4 v0000000000bd9d90_0, 0; + %load/vec4 v0000000000bd9bb0_0; + %addi 4, 0, 32; + %assign/vec4 v0000000000bd9cf0_0, 0; + %jmp T_3.3; +T_3.2 ; + %load/vec4 v0000000000bd9cf0_0; + %assign/vec4 v0000000000bd9d90_0, 0; + %load/vec4 v0000000000bd9cf0_0; + %addi 4, 0, 32; + %assign/vec4 v0000000000bd9cf0_0, 0; +T_3.3 ; +T_3.1 ; + %jmp T_3; + .thread T_3; + .scope S_0000000000aad080; +T_4 ; + %wait E_00000000006a1b90; + %load/vec4 v0000000000bd9ed0_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_4.0, 4; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9e30_0, 0; + %jmp T_4.1; +T_4.0 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9e30_0, 0; +T_4.1 ; + %jmp T_4; + .thread T_4; + .scope S_0000000000aad210; +T_5 ; + %wait E_00000000006a1b90; + %load/vec4 v0000000000bda470_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_5.0, 4; + %load/vec4 v0000000000bda650_0; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000bda510_0; + %pushi/vec4 0, 0, 5; + %cmp/ne; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_5.2, 8; + %load/vec4 v0000000000bda5b0_0; + %load/vec4 v0000000000bda510_0; + %pad/u 7; + %ix/vec4 3; + %ix/load 4, 0, 0; Constant delay + %assign/vec4/a/d v0000000000bda3d0, 0, 4; +T_5.2 ; +T_5.0 ; + %jmp T_5; + .thread T_5; + .scope S_0000000000aad210; +T_6 ; + %wait E_00000000006a3110; + %load/vec4 v0000000000bda470_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_6.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bda150_0, 0; + %jmp T_6.1; +T_6.0 ; + %load/vec4 v0000000000bda010_0; + %cmpi/e 0, 0, 5; + %jmp/0xz T_6.2, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bda150_0, 0; + %jmp T_6.3; +T_6.2 ; + %load/vec4 v0000000000bda290_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_6.4, 4; + %load/vec4 v0000000000bda010_0; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0000000000bda3d0, 4; + %assign/vec4 v0000000000bda150_0, 0; + %jmp T_6.5; +T_6.4 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bda150_0, 0; +T_6.5 ; +T_6.3 ; +T_6.1 ; + %jmp T_6; + .thread T_6, $push; + .scope S_0000000000aad210; +T_7 ; + %wait E_00000000006a1b50; + %load/vec4 v0000000000bda470_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_7.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bda1f0_0, 0; + %jmp T_7.1; +T_7.0 ; + %load/vec4 v0000000000bda0b0_0; + %cmpi/e 0, 0, 5; + %jmp/0xz T_7.2, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bda1f0_0, 0; + %jmp T_7.3; +T_7.2 ; + %load/vec4 v0000000000bda330_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_7.4, 4; + %load/vec4 v0000000000bda0b0_0; + %pad/u 7; + %ix/vec4 4; + %load/vec4a v0000000000bda3d0, 4; + %assign/vec4 v0000000000bda1f0_0, 0; + %jmp T_7.5; +T_7.4 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bda1f0_0, 0; +T_7.5 ; +T_7.3 ; +T_7.1 ; + %jmp T_7; + .thread T_7, $push; + .scope S_0000000000ab3dc0; +T_8 ; + %wait E_00000000006a1b90; + %load/vec4 v0000000000bd9a70_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_8.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bd9930_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bd97f0_0, 0; + %jmp T_8.1; +T_8.0 ; + %load/vec4 v0000000000bd99d0_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_8.2, 4; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000bd9930_0, 0; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000bd97f0_0, 0; + %jmp T_8.3; +T_8.2 ; + %load/vec4 v0000000000bd9890_0; + %assign/vec4 v0000000000bd9930_0, 0; + %load/vec4 v0000000000bd9750_0; + %assign/vec4 v0000000000bd97f0_0, 0; +T_8.3 ; +T_8.1 ; + %jmp T_8; + .thread T_8; + .scope S_0000000000ac0200; +T_9 ; + %wait E_00000000006a1b90; + %load/vec4 v0000000000bd94d0_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_9.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b258e0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9570_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %jmp T_9.1; +T_9.0 ; + %load/vec4 v0000000000b25a20_0; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b25840_0; + %pushi/vec4 1, 0, 32; + %cmp/ne; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_9.2, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b258e0_0, 0; + %jmp T_9.3; +T_9.2 ; + %load/vec4 v0000000000b25840_0; + %assign/vec4 v0000000000b258e0_0, 0; + %load/vec4 v0000000000b25700_0; + %assign/vec4 v0000000000b257a0_0, 0; + %load/vec4 v0000000000b25ac0_0; + %dup/vec4; + %pushi/vec4 19, 0, 7; + %cmp/u; + %jmp/1 T_9.4, 6; + %dup/vec4; + %pushi/vec4 51, 0, 7; + %cmp/u; + %jmp/1 T_9.5, 6; + %dup/vec4; + %pushi/vec4 3, 0, 7; + %cmp/u; + %jmp/1 T_9.6, 6; + %dup/vec4; + %pushi/vec4 35, 0, 7; + %cmp/u; + %jmp/1 T_9.7, 6; + %dup/vec4; + %pushi/vec4 99, 0, 7; + %cmp/u; + %jmp/1 T_9.8, 6; + %dup/vec4; + %pushi/vec4 111, 0, 7; + %cmp/u; + %jmp/1 T_9.9, 6; + %dup/vec4; + %pushi/vec4 103, 0, 7; + %cmp/u; + %jmp/1 T_9.10, 6; + %dup/vec4; + %pushi/vec4 55, 0, 7; + %cmp/u; + %jmp/1 T_9.11, 6; + %dup/vec4; + %pushi/vec4 23, 0, 7; + %cmp/u; + %jmp/1 T_9.12, 6; + %dup/vec4; + %pushi/vec4 1, 0, 7; + %cmp/u; + %jmp/1 T_9.13, 6; + %dup/vec4; + %pushi/vec4 15, 0, 7; + %cmp/u; + %jmp/1 T_9.14, 6; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.16; +T_9.4 ; + %load/vec4 v0000000000b25660_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_9.17, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_9.18, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_9.19, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_9.20, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_9.21, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_9.22, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_9.23, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_9.24, 6; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %jmp T_9.26; +T_9.17 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.26; +T_9.18 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.26; +T_9.19 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.26; +T_9.20 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.26; +T_9.21 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.26; +T_9.22 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.26; +T_9.23 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.26; +T_9.24 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.26; +T_9.26 ; + %pop/vec4 1; + %jmp T_9.16; +T_9.5 ; + %load/vec4 v0000000000b25660_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_9.27, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_9.28, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_9.29, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_9.30, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_9.31, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_9.32, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_9.33, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_9.34, 6; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %jmp T_9.36; +T_9.27 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.36; +T_9.28 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.36; +T_9.29 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.36; +T_9.30 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.36; +T_9.31 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.36; +T_9.32 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.36; +T_9.33 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.36; +T_9.34 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.36; +T_9.36 ; + %pop/vec4 1; + %jmp T_9.16; +T_9.6 ; + %load/vec4 v0000000000b25660_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_9.37, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_9.38, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_9.39, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_9.40, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_9.41, 6; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %jmp T_9.43; +T_9.37 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9570_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.43; +T_9.38 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9570_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.43; +T_9.39 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9570_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.43; +T_9.40 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9570_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.43; +T_9.41 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9570_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %jmp T_9.43; +T_9.43 ; + %pop/vec4 1; + %jmp T_9.16; +T_9.7 ; + %load/vec4 v0000000000b25660_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_9.44, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_9.45, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_9.46, 6; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %jmp T_9.48; +T_9.44 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9570_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.48; +T_9.45 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9570_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.48; +T_9.46 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.48; +T_9.48 ; + %pop/vec4 1; + %jmp T_9.16; +T_9.8 ; + %load/vec4 v0000000000b25660_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_9.49, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_9.50, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_9.51, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_9.52, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_9.53, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_9.54, 6; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %jmp T_9.56; +T_9.49 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.56; +T_9.50 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.56; +T_9.51 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.56; +T_9.52 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.56; +T_9.53 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.56; +T_9.54 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd91b0_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %load/vec4 v0000000000bd9430_0; + %assign/vec4 v0000000000bd9110_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.56; +T_9.56 ; + %pop/vec4 1; + %jmp T_9.16; +T_9.9 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %jmp T_9.16; +T_9.10 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd9070_0, 0; + %load/vec4 v0000000000bd9390_0; + %assign/vec4 v0000000000bd8fd0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %jmp T_9.16; +T_9.11 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %jmp T_9.16; +T_9.12 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %load/vec4 v0000000000bd8f30_0; + %assign/vec4 v0000000000bd9250_0, 0; + %jmp T_9.16; +T_9.13 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.16; +T_9.14 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b25980_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd9610_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000bd92f0_0, 0; + %jmp T_9.16; +T_9.16 ; + %pop/vec4 1; +T_9.3 ; +T_9.1 ; + %jmp T_9; + .thread T_9; + .scope S_0000000000b8cea0; +T_10 ; + %wait E_00000000006a1b90; + %load/vec4 v0000000000b25020_0; + %cmpi/e 0, 0, 1; + %jmp/0xz T_10.0, 4; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b252a0_0, 0; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0000000000b25200_0, 0; + %pushi/vec4 0, 0, 2; + %assign/vec4 v0000000000b253e0_0, 0; +T_10.0 ; + %jmp T_10; + .thread T_10; + .scope S_0000000000b8cea0; +T_11 ; + %wait E_00000000006a1c50; + %load/vec4 v0000000000b24bc0_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_11.0, 4; + %load/vec4 v0000000000b24da0_0; + %dup/vec4; + %pushi/vec4 19, 0, 7; + %cmp/u; + %jmp/1 T_11.2, 6; + %dup/vec4; + %pushi/vec4 51, 0, 7; + %cmp/u; + %jmp/1 T_11.3, 6; + %dup/vec4; + %pushi/vec4 3, 0, 7; + %cmp/u; + %jmp/1 T_11.4, 6; + %dup/vec4; + %pushi/vec4 35, 0, 7; + %cmp/u; + %jmp/1 T_11.5, 6; + %dup/vec4; + %pushi/vec4 99, 0, 7; + %cmp/u; + %jmp/1 T_11.6, 6; + %dup/vec4; + %pushi/vec4 111, 0, 7; + %cmp/u; + %jmp/1 T_11.7, 6; + %dup/vec4; + %pushi/vec4 103, 0, 7; + %cmp/u; + %jmp/1 T_11.8, 6; + %dup/vec4; + %pushi/vec4 55, 0, 7; + %cmp/u; + %jmp/1 T_11.9, 6; + %dup/vec4; + %pushi/vec4 23, 0, 7; + %cmp/u; + %jmp/1 T_11.10, 6; + %dup/vec4; + %pushi/vec4 1, 0, 7; + %cmp/u; + %jmp/1 T_11.11, 6; + %dup/vec4; + %pushi/vec4 15, 0, 7; + %cmp/u; + %jmp/1 T_11.12, 6; + %jmp T_11.14; +T_11.2 ; + %load/vec4 v0000000000b249e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_11.15, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_11.16, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_11.17, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_11.18, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_11.19, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_11.20, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_11.21, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_11.22, 6; + %jmp T_11.23; +T_11.15 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.23; +T_11.16 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b25160_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.24, 8; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b25160_0; + %cmp/u; + %jmp/0xz T_11.26, 5; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.27; +T_11.26 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.27 ; + %jmp T_11.25; +T_11.24 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b25160_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.28, 8; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.29; +T_11.28 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b25160_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.30, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.31; +T_11.30 ; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b25160_0; + %cmp/u; + %jmp/0xz T_11.32, 5; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.33; +T_11.32 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.33 ; +T_11.31 ; +T_11.29 ; +T_11.25 ; + %jmp T_11.23; +T_11.17 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b25160_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.34, 8; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b25160_0; + %cmp/u; + %jmp/0xz T_11.36, 5; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.37; +T_11.36 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.37 ; + %jmp T_11.35; +T_11.34 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b25160_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.38, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.39; +T_11.38 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b25160_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.40, 8; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.41; +T_11.40 ; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b25160_0; + %cmp/u; + %jmp/0xz T_11.42, 5; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.43; +T_11.42 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.43 ; +T_11.41 ; +T_11.39 ; +T_11.35 ; + %jmp T_11.23; +T_11.18 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %xor; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.23; +T_11.19 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %or; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.23; +T_11.20 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %and; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.23; +T_11.21 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %ix/getv 4, v0000000000b250c0_0; + %shiftl 4; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.23; +T_11.22 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 30, 6; + %cmpi/e 1, 0, 1; + %jmp/0xz T_11.44, 4; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %replicate 32; + %pushi/vec4 32, 0, 6; + %pushi/vec4 0, 0, 1; + %load/vec4 v0000000000b250c0_0; + %concat/vec4; draw_concat_vec4 + %sub; + %ix/vec4 4; + %shiftl 4; + %load/vec4 v0000000000b24e40_0; + %ix/getv 4, v0000000000b250c0_0; + %shiftr 4; + %or; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.45; +T_11.44 ; + %load/vec4 v0000000000b24e40_0; + %ix/getv 4, v0000000000b250c0_0; + %shiftr 4; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.45 ; + %jmp T_11.23; +T_11.23 ; + %pop/vec4 1; + %jmp T_11.14; +T_11.3 ; + %load/vec4 v0000000000b249e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_11.46, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_11.47, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_11.48, 6; + %dup/vec4; + %pushi/vec4 3, 0, 3; + %cmp/u; + %jmp/1 T_11.49, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_11.50, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_11.51, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_11.52, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_11.53, 6; + %jmp T_11.54; +T_11.46 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 30, 6; + %cmpi/e 0, 0, 1; + %jmp/0xz T_11.55, 4; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %add; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.56; +T_11.55 ; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %sub; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.56 ; + %jmp T_11.54; +T_11.47 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %parti/s 5, 0, 2; + %ix/vec4 4; + %shiftl 4; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.54; +T_11.48 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.57, 8; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/u; + %jmp/0xz T_11.59, 5; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.60; +T_11.59 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.60 ; + %jmp T_11.58; +T_11.57 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.61, 8; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.62; +T_11.61 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.63, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.64; +T_11.63 ; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/u; + %jmp/0xz T_11.65, 5; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.66; +T_11.65 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.66 ; +T_11.64 ; +T_11.62 ; +T_11.58 ; + %jmp T_11.54; +T_11.49 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.67, 8; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/u; + %jmp/0xz T_11.69, 5; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.70; +T_11.69 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.70 ; + %jmp T_11.68; +T_11.67 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.71, 8; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.72; +T_11.71 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.73, 8; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.74; +T_11.73 ; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/u; + %jmp/0xz T_11.75, 5; + %pushi/vec4 1, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.76; +T_11.75 ; + %pushi/vec4 0, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.76 ; +T_11.74 ; +T_11.72 ; +T_11.68 ; + %jmp T_11.54; +T_11.50 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %xor; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.54; +T_11.51 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 30, 6; + %cmpi/e 1, 0, 1; + %jmp/0xz T_11.77, 4; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %replicate 32; + %pushi/vec4 32, 0, 6; + %pushi/vec4 0, 0, 1; + %load/vec4 v0000000000b24ee0_0; + %parti/s 5, 0, 2; + %concat/vec4; draw_concat_vec4 + %sub; + %ix/vec4 4; + %shiftl 4; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %parti/s 5, 0, 2; + %ix/vec4 4; + %shiftr 4; + %or; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.78; +T_11.77 ; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %parti/s 5, 0, 2; + %ix/vec4 4; + %shiftr 4; + %assign/vec4 v0000000000b24f80_0, 0; +T_11.78 ; + %jmp T_11.54; +T_11.52 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %or; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.54; +T_11.53 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %and; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.54; +T_11.54 ; + %pop/vec4 1; + %jmp T_11.14; +T_11.4 ; + %load/vec4 v0000000000b249e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_11.79, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_11.80, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_11.81, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_11.82, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_11.83, 6; + %jmp T_11.84; +T_11.79 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b252a0_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %pushi/vec4 4294967292, 0, 32; + %and; + %sub; + %pushi/vec4 3, 0, 32; + %and; + %pad/u 2; + %assign/vec4 v0000000000b25200_0, 0; + %jmp T_11.84; +T_11.80 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b252a0_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %pushi/vec4 4294967292, 0, 32; + %and; + %sub; + %pushi/vec4 3, 0, 32; + %and; + %pad/u 2; + %assign/vec4 v0000000000b25200_0, 0; + %jmp T_11.84; +T_11.81 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b252a0_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %pushi/vec4 4294967292, 0, 32; + %and; + %sub; + %pushi/vec4 3, 0, 32; + %and; + %pad/u 2; + %assign/vec4 v0000000000b25200_0, 0; + %jmp T_11.84; +T_11.82 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b252a0_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %pushi/vec4 4294967292, 0, 32; + %and; + %sub; + %pushi/vec4 3, 0, 32; + %and; + %pad/u 2; + %assign/vec4 v0000000000b25200_0, 0; + %jmp T_11.84; +T_11.83 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b252a0_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %pushi/vec4 4294967292, 0, 32; + %and; + %sub; + %pushi/vec4 3, 0, 32; + %and; + %pad/u 2; + %assign/vec4 v0000000000b25200_0, 0; + %jmp T_11.84; +T_11.84 ; + %pop/vec4 1; + %jmp T_11.14; +T_11.5 ; + %load/vec4 v0000000000b249e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_11.85, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_11.86, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_11.87, 6; + %jmp T_11.88; +T_11.85 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 7, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 5, 7, 4; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b25480_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 7, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 5, 7, 4; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b252a0_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 7, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 5, 7, 4; + %concat/vec4; draw_concat_vec4 + %add; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 7, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 5, 7, 4; + %concat/vec4; draw_concat_vec4 + %add; + %pushi/vec4 4294967292, 0, 32; + %and; + %sub; + %pushi/vec4 3, 0, 32; + %and; + %pad/u 2; + %assign/vec4 v0000000000b253e0_0, 0; + %jmp T_11.88; +T_11.86 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 7, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 5, 7, 4; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b25480_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 7, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 5, 7, 4; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b252a0_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 7, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 5, 7, 4; + %concat/vec4; draw_concat_vec4 + %add; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 7, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 5, 7, 4; + %concat/vec4; draw_concat_vec4 + %add; + %pushi/vec4 4294967292, 0, 32; + %and; + %sub; + %pushi/vec4 3, 0, 32; + %and; + %pad/u 2; + %assign/vec4 v0000000000b253e0_0, 0; + %jmp T_11.88; +T_11.87 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 7, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 5, 7, 4; + %concat/vec4; draw_concat_vec4 + %add; + %assign/vec4 v0000000000b25480_0, 0; + %load/vec4 v0000000000b24ee0_0; + %assign/vec4 v0000000000b25520_0, 0; + %jmp T_11.88; +T_11.88 ; + %pop/vec4 1; + %jmp T_11.14; +T_11.6 ; + %load/vec4 v0000000000b249e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_11.89, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_11.90, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_11.91, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_11.92, 6; + %dup/vec4; + %pushi/vec4 6, 0, 3; + %cmp/u; + %jmp/1 T_11.93, 6; + %dup/vec4; + %pushi/vec4 7, 0, 3; + %cmp/u; + %jmp/1 T_11.94, 6; + %jmp T_11.95; +T_11.89 ; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/e; + %jmp/0xz T_11.96, 4; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; + %jmp T_11.97; +T_11.96 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; +T_11.97 ; + %jmp T_11.95; +T_11.90 ; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/ne; + %jmp/0xz T_11.98, 4; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; + %jmp T_11.99; +T_11.98 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; +T_11.99 ; + %jmp T_11.95; +T_11.91 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.100, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; + %jmp T_11.101; +T_11.100 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.102, 8; + %load/vec4 v0000000000b24ee0_0; + %load/vec4 v0000000000b24e40_0; + %cmp/u; + %flag_or 5, 4; + %jmp/0xz T_11.104, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.105; +T_11.104 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.105 ; + %jmp T_11.103; +T_11.102 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.106, 8; + %load/vec4 v0000000000b24ee0_0; + %load/vec4 v0000000000b24e40_0; + %cmp/u; + %flag_or 5, 4; + %jmp/0xz T_11.108, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.109; +T_11.108 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.109 ; + %jmp T_11.107; +T_11.106 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; +T_11.107 ; +T_11.103 ; +T_11.101 ; + %jmp T_11.95; +T_11.92 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.110, 8; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; + %jmp T_11.111; +T_11.110 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.112, 8; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/u; + %jmp/0xz T_11.114, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.115; +T_11.114 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.115 ; + %jmp T_11.113; +T_11.112 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.116, 8; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/u; + %jmp/0xz T_11.118, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.119; +T_11.118 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.119 ; + %jmp T_11.117; +T_11.116 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; +T_11.117 ; +T_11.113 ; +T_11.111 ; + %jmp T_11.95; +T_11.93 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.120, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.121; +T_11.120 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.122, 8; + %load/vec4 v0000000000b24ee0_0; + %load/vec4 v0000000000b24e40_0; + %cmp/u; + %flag_or 5, 4; + %jmp/0xz T_11.124, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.125; +T_11.124 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.125 ; + %jmp T_11.123; +T_11.122 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.126, 8; + %load/vec4 v0000000000b24ee0_0; + %load/vec4 v0000000000b24e40_0; + %cmp/u; + %flag_or 5, 4; + %jmp/0xz T_11.128, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.129; +T_11.128 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.129 ; + %jmp T_11.127; +T_11.126 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.127 ; +T_11.123 ; +T_11.121 ; + %jmp T_11.95; +T_11.94 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.130, 8; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.131; +T_11.130 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 1, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.132, 8; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/u; + %jmp/0xz T_11.134, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.135; +T_11.134 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.135 ; + %jmp T_11.133; +T_11.132 ; + %load/vec4 v0000000000b24e40_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %load/vec4 v0000000000b24ee0_0; + %parti/s 1, 31, 6; + %pushi/vec4 0, 0, 1; + %cmp/e; + %flag_get/vec4 4; + %and; + %flag_set/vec4 8; + %jmp/0xz T_11.136, 8; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24ee0_0; + %cmp/u; + %jmp/0xz T_11.138, 5; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.139; +T_11.138 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.139 ; + %jmp T_11.137; +T_11.136 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 7, 4; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 6, 25, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 4, 8, 5; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; +T_11.137 ; +T_11.133 ; +T_11.131 ; + %jmp T_11.95; +T_11.95 ; + %pop/vec4 1; + %jmp T_11.14; +T_11.7 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 12; + %load/vec4 v0000000000b24b20_0; + %parti/s 8, 12, 5; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 20, 6; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b24b20_0; + %parti/s 10, 21, 6; + %concat/vec4; draw_concat_vec4 + %concati/vec4 0, 0, 1; + %add; + %assign/vec4 v0000000000b24c60_0, 0; + %load/vec4 v0000000000b24a80_0; + %addi 4, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.14; +T_11.8 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24e40_0; + %load/vec4 v0000000000b24b20_0; + %parti/s 1, 31, 6; + %replicate 20; + %load/vec4 v0000000000b24b20_0; + %parti/s 12, 20, 6; + %concat/vec4; draw_concat_vec4 + %add; + %pushi/vec4 4294967294, 0, 32; + %and; + %assign/vec4 v0000000000b24c60_0, 0; + %load/vec4 v0000000000b24a80_0; + %addi 4, 0, 32; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.14; +T_11.9 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24b20_0; + %parti/s 20, 12, 5; + %concati/vec4 0, 0, 12; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.14; +T_11.10 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24b20_0; + %parti/s 20, 12, 5; + %concati/vec4 0, 0, 12; + %load/vec4 v0000000000b24a80_0; + %add; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_11.14; +T_11.11 ; + %pushi/vec4 0, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %jmp T_11.14; +T_11.12 ; + %pushi/vec4 1, 0, 1; + %assign/vec4 v0000000000b24d00_0, 0; + %load/vec4 v0000000000b24a80_0; + %addi 4, 0, 32; + %assign/vec4 v0000000000b24c60_0, 0; + %jmp T_11.14; +T_11.14 ; + %pop/vec4 1; +T_11.0 ; + %jmp T_11; + .thread T_11, $push; + .scope S_0000000000b8cea0; +T_12 ; + %wait E_00000000006a1d50; + %load/vec4 v0000000000b24bc0_0; + %cmpi/e 1, 0, 1; + %jmp/0xz T_12.0, 4; + %load/vec4 v0000000000b24da0_0; + %dup/vec4; + %pushi/vec4 3, 0, 7; + %cmp/u; + %jmp/1 T_12.2, 6; + %dup/vec4; + %pushi/vec4 35, 0, 7; + %cmp/u; + %jmp/1 T_12.3, 6; + %jmp T_12.4; +T_12.2 ; + %load/vec4 v0000000000b249e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_12.5, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_12.6, 6; + %dup/vec4; + %pushi/vec4 2, 0, 3; + %cmp/u; + %jmp/1 T_12.7, 6; + %dup/vec4; + %pushi/vec4 4, 0, 3; + %cmp/u; + %jmp/1 T_12.8, 6; + %dup/vec4; + %pushi/vec4 5, 0, 3; + %cmp/u; + %jmp/1 T_12.9, 6; + %jmp T_12.10; +T_12.5 ; + %load/vec4 v0000000000b25200_0; + %cmpi/e 0, 0, 2; + %jmp/0xz T_12.11, 4; + %load/vec4 v0000000000b25340_0; + %parti/s 1, 7, 4; + %replicate 24; + %load/vec4 v0000000000b25340_0; + %parti/s 8, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_12.12; +T_12.11 ; + %load/vec4 v0000000000b25200_0; + %cmpi/e 1, 0, 2; + %jmp/0xz T_12.13, 4; + %load/vec4 v0000000000b25340_0; + %parti/s 1, 15, 5; + %replicate 24; + %load/vec4 v0000000000b25340_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_12.14; +T_12.13 ; + %load/vec4 v0000000000b25200_0; + %cmpi/e 2, 0, 2; + %jmp/0xz T_12.15, 4; + %load/vec4 v0000000000b25340_0; + %parti/s 1, 23, 6; + %replicate 24; + %load/vec4 v0000000000b25340_0; + %parti/s 8, 16, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_12.16; +T_12.15 ; + %load/vec4 v0000000000b25340_0; + %parti/s 1, 31, 6; + %replicate 24; + %load/vec4 v0000000000b25340_0; + %parti/s 8, 24, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; +T_12.16 ; +T_12.14 ; +T_12.12 ; + %jmp T_12.10; +T_12.6 ; + %load/vec4 v0000000000b25200_0; + %cmpi/e 0, 0, 2; + %jmp/0xz T_12.17, 4; + %load/vec4 v0000000000b25340_0; + %parti/s 1, 15, 5; + %replicate 16; + %load/vec4 v0000000000b25340_0; + %parti/s 16, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_12.18; +T_12.17 ; + %load/vec4 v0000000000b25340_0; + %parti/s 1, 31, 6; + %replicate 16; + %load/vec4 v0000000000b25340_0; + %parti/s 16, 16, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; +T_12.18 ; + %jmp T_12.10; +T_12.7 ; + %load/vec4 v0000000000b25340_0; + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_12.10; +T_12.8 ; + %load/vec4 v0000000000b25200_0; + %cmpi/e 0, 0, 2; + %jmp/0xz T_12.19, 4; + %pushi/vec4 0, 0, 24; + %load/vec4 v0000000000b25340_0; + %parti/s 8, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_12.20; +T_12.19 ; + %load/vec4 v0000000000b25200_0; + %cmpi/e 1, 0, 2; + %jmp/0xz T_12.21, 4; + %pushi/vec4 0, 0, 24; + %load/vec4 v0000000000b25340_0; + %parti/s 8, 8, 5; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_12.22; +T_12.21 ; + %load/vec4 v0000000000b25200_0; + %cmpi/e 2, 0, 2; + %jmp/0xz T_12.23, 4; + %pushi/vec4 0, 0, 24; + %load/vec4 v0000000000b25340_0; + %parti/s 8, 16, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_12.24; +T_12.23 ; + %pushi/vec4 0, 0, 24; + %load/vec4 v0000000000b25340_0; + %parti/s 8, 24, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; +T_12.24 ; +T_12.22 ; +T_12.20 ; + %jmp T_12.10; +T_12.9 ; + %load/vec4 v0000000000b25200_0; + %cmpi/e 0, 0, 2; + %jmp/0xz T_12.25, 4; + %pushi/vec4 0, 0, 16; + %load/vec4 v0000000000b25340_0; + %parti/s 16, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; + %jmp T_12.26; +T_12.25 ; + %pushi/vec4 0, 0, 16; + %load/vec4 v0000000000b25340_0; + %parti/s 16, 16, 6; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b24f80_0, 0; +T_12.26 ; + %jmp T_12.10; +T_12.10 ; + %pop/vec4 1; + %jmp T_12.4; +T_12.3 ; + %load/vec4 v0000000000b249e0_0; + %dup/vec4; + %pushi/vec4 0, 0, 3; + %cmp/u; + %jmp/1 T_12.27, 6; + %dup/vec4; + %pushi/vec4 1, 0, 3; + %cmp/u; + %jmp/1 T_12.28, 6; + %jmp T_12.29; +T_12.27 ; + %load/vec4 v0000000000b253e0_0; + %cmpi/e 0, 0, 2; + %jmp/0xz T_12.30, 4; + %load/vec4 v0000000000b25340_0; + %parti/s 24, 8, 5; + %load/vec4 v0000000000b24ee0_0; + %parti/s 8, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b25520_0, 0; + %jmp T_12.31; +T_12.30 ; + %load/vec4 v0000000000b253e0_0; + %cmpi/e 1, 0, 2; + %jmp/0xz T_12.32, 4; + %load/vec4 v0000000000b25340_0; + %parti/s 16, 16, 6; + %load/vec4 v0000000000b24ee0_0; + %parti/s 8, 0, 2; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b25340_0; + %parti/s 8, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b25520_0, 0; + %jmp T_12.33; +T_12.32 ; + %load/vec4 v0000000000b253e0_0; + %cmpi/e 2, 0, 2; + %jmp/0xz T_12.34, 4; + %load/vec4 v0000000000b25340_0; + %parti/s 8, 24, 6; + %load/vec4 v0000000000b24ee0_0; + %parti/s 8, 0, 2; + %concat/vec4; draw_concat_vec4 + %load/vec4 v0000000000b25340_0; + %parti/s 16, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b25520_0, 0; + %jmp T_12.35; +T_12.34 ; + %load/vec4 v0000000000b24ee0_0; + %parti/s 8, 0, 2; + %load/vec4 v0000000000b25340_0; + %parti/s 24, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b25520_0, 0; +T_12.35 ; +T_12.33 ; +T_12.31 ; + %jmp T_12.29; +T_12.28 ; + %load/vec4 v0000000000b253e0_0; + %cmpi/e 0, 0, 2; + %jmp/0xz T_12.36, 4; + %load/vec4 v0000000000b25340_0; + %parti/s 16, 16, 6; + %load/vec4 v0000000000b24ee0_0; + %parti/s 16, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b25520_0, 0; + %jmp T_12.37; +T_12.36 ; + %load/vec4 v0000000000b24ee0_0; + %parti/s 16, 0, 2; + %load/vec4 v0000000000b25340_0; + %parti/s 16, 0, 2; + %concat/vec4; draw_concat_vec4 + %assign/vec4 v0000000000b25520_0, 0; +T_12.37 ; + %jmp T_12.29; +T_12.29 ; + %pop/vec4 1; + %jmp T_12.4; +T_12.4 ; + %pop/vec4 1; +T_12.0 ; + %jmp T_12; + .thread T_12, $push; + .scope S_00000000007cdc30; +T_13 ; + %delay 10000, 0; + %load/vec4 v0000000000bf4070_0; + %inv; + %store/vec4 v0000000000bf4070_0, 0, 1; + %jmp T_13; + .thread T_13; + .scope S_00000000007cdc30; +T_14 ; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000bf4070_0, 0, 1; + %pushi/vec4 0, 0, 1; + %store/vec4 v0000000000bf41b0_0, 0, 1; + %vpi_call 2 21 "$display", "test running..." {0 0 0}; + %delay 40000, 0; + %pushi/vec4 1, 0, 1; + %store/vec4 v0000000000bf41b0_0, 0, 1; + %delay 100000, 0; +T_14.0 ; + %load/vec4 v0000000000bf4250_0; + %pushi/vec4 1, 0, 32; + %cmp/e; + %flag_get/vec4 4; + %cmpi/ne 1, 0, 1; + %jmp/0xz T_14.1, 6; + %wait E_00000000006a1d90; + %jmp T_14.0; +T_14.1 ; + %delay 100000, 0; + %load/vec4 v0000000000bf42f0_0; + %cmpi/e 1, 0, 32; + %jmp/0xz T_14.2, 4; + %vpi_call 2 28 "$display", "~~~~~~~~~~~~~~~~~~~ TEST_PASS ~~~~~~~~~~~~~~~~~~~" {0 0 0}; + %vpi_call 2 29 "$display", "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~" {0 0 0}; + %vpi_call 2 30 "$display", "~~~~~~~~~ ##### ## #### #### ~~~~~~~~~" {0 0 0}; + %vpi_call 2 31 "$display", "~~~~~~~~~ # # # # # # ~~~~~~~~~" {0 0 0}; + %vpi_call 2 32 "$display", "~~~~~~~~~ # # # # #### #### ~~~~~~~~~" {0 0 0}; + %vpi_call 2 33 "$display", "~~~~~~~~~ ##### ###### # #~~~~~~~~~" {0 0 0}; + %vpi_call 2 34 "$display", "~~~~~~~~~ # # # # # # #~~~~~~~~~" {0 0 0}; + %vpi_call 2 35 "$display", "~~~~~~~~~ # # # #### #### ~~~~~~~~~" {0 0 0}; + %vpi_call 2 36 "$display", "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~" {0 0 0}; + %jmp T_14.3; +T_14.2 ; + %vpi_call 2 38 "$display", "~~~~~~~~~~~~~~~~~~~ TEST_FAIL ~~~~~~~~~~~~~~~~~~~~" {0 0 0}; + %vpi_call 2 39 "$display", "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~" {0 0 0}; + %vpi_call 2 40 "$display", "~~~~~~~~~~###### ## # # ~~~~~~~~~~" {0 0 0}; + %vpi_call 2 41 "$display", "~~~~~~~~~~# # # # # ~~~~~~~~~~" {0 0 0}; + %vpi_call 2 42 "$display", "~~~~~~~~~~##### # # # # ~~~~~~~~~~" {0 0 0}; + %vpi_call 2 43 "$display", "~~~~~~~~~~# ###### # # ~~~~~~~~~~" {0 0 0}; + %vpi_call 2 44 "$display", "~~~~~~~~~~# # # # # ~~~~~~~~~~" {0 0 0}; + %vpi_call 2 45 "$display", "~~~~~~~~~~# # # # ######~~~~~~~~~~" {0 0 0}; + %vpi_call 2 46 "$display", "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~" {0 0 0}; + %vpi_call 2 47 "$display", "fail testnum = %2d", v0000000000bf4390_0 {0 0 0}; + %pushi/vec4 0, 0, 32; + %store/vec4 v0000000000bf4110_0, 0, 32; +T_14.4 ; + %load/vec4 v0000000000bf4110_0; + %cmpi/s 32, 0, 32; + %jmp/0xz T_14.5, 5; + %vpi_call 2 49 "$display", "x%2d = 0x%x", v0000000000bf4110_0, &A {0 0 0}; + ; show_stmt_assign_vector: Get l-value for compressed += operand + %load/vec4 v0000000000bf4110_0; + %pushi/vec4 1, 0, 32; + %add; + %store/vec4 v0000000000bf4110_0, 0, 32; + %jmp T_14.4; +T_14.5 ; +T_14.3 ; + %vpi_call 2 51 "$finish" {0 0 0}; + %end; + .thread T_14; + .scope S_00000000007cdc30; +T_15 ; + %delay 100000000, 0; + %vpi_call 2 57 "$display", "Time Out." {0 0 0}; + %vpi_call 2 58 "$finish" {0 0 0}; + %end; + .thread T_15; + .scope S_00000000007cdc30; +T_16 ; + %vpi_call 2 63 "$readmemh", "inst.data", v0000000000bdab50 {0 0 0}; + %end; + .thread T_16; + .scope S_00000000007cdc30; +T_17 ; + %vpi_call 2 68 "$dumpfile", "openriscv_core_tb.vcd" {0 0 0}; + %vpi_call 2 69 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000000007cdc30 {0 0 0}; + %end; + .thread T_17; +# The file index is used to find the file name in the following table. +:file_names 10; + "N/A"; + ""; + "openriscv_core_tb.v"; + "..\rtl\openriscv_core.v"; + "..\rtl\ex.v"; + "..\rtl\id.v"; + "..\rtl\if_id.v"; + "..\rtl\pc_reg.v"; + "..\rtl\regs.v"; + "..\rtl\sim_ram.v"; diff --git a/sim/sim_default_nowave.bat b/sim/sim_default_nowave.bat new file mode 100644 index 0000000..85767d6 --- /dev/null +++ b/sim/sim_default_nowave.bat @@ -0,0 +1,2 @@ +iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v +vvp out.vvp diff --git a/sim/sim_new_nowave.bat b/sim/sim_new_nowave.bat new file mode 100644 index 0000000..0232fb0 --- /dev/null +++ b/sim/sim_new_nowave.bat @@ -0,0 +1,3 @@ +..\tools\BinToMem_CLI.exe %1 %2 +iverilog -s openriscv_core_tb -o out.vvp -I ..\rtl openriscv_core_tb.v ..\rtl\defines.v ..\rtl\ex.v ..\rtl\id.v ..\rtl\openriscv_core.v ..\rtl\pc_reg.v ..\rtl\regs.v ..\rtl\sim_ram.v ..\rtl\if_id.v +vvp out.vvp diff --git a/tests/example/Makefile b/tests/example/Makefile new file mode 100644 index 0000000..45a4cab --- /dev/null +++ b/tests/example/Makefile @@ -0,0 +1,25 @@ + +RISCV_ARCH := rv32i +RISCV_ABI := ilp32 + +RISCV_PATH := ../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/ + +CFLAGS += -march=$(RISCV_ARCH) +CFLAGS += -mabi=$(RISCV_ABI) +CFLAGS += -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles + +RISCV_GCC := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gcc) +RISCV_AS := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-as) +RISCV_GXX := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-g++) +RISCV_OBJDUMP := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objdump) +RISCV_GDB := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-gdb) +RISCV_AR := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-ar) +RISCV_OBJCOPY := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-objcopy) +RISCV_READELF := $(abspath $(RISCV_PATH)/bin/riscv-none-embed-readelf) + + +.PHONY: all +all: + $(RISCV_GCC) $(CFLAGS) reset.S main.c -Tlink.ld -o example + $(RISCV_OBJCOPY) -O binary example example.bin + $(RISCV_OBJDUMP) --disassemble-all example > example.dump diff --git a/tests/example/README.md b/tests/example/README.md new file mode 100644 index 0000000..b31f14a --- /dev/null +++ b/tests/example/README.md @@ -0,0 +1 @@ +a simple c program which can run on tinyriscv. \ No newline at end of file diff --git a/tests/example/example b/tests/example/example new file mode 100644 index 0000000..adc4448 Binary files /dev/null and b/tests/example/example differ diff --git a/tests/example/example.bin b/tests/example/example.bin new file mode 100644 index 0000000..bc8e632 Binary files /dev/null and b/tests/example/example.bin differ diff --git a/tests/example/example.dump b/tests/example/example.dump new file mode 100644 index 0000000..3345834 --- /dev/null +++ b/tests/example/example.dump @@ -0,0 +1,96 @@ + +example: file format elf32-littleriscv + + +Disassembly of section .text: + +00000000 <_reset>: + 0: 10000113 li sp,256 + 4: 00000d13 li s10,0 + 8: 00000d93 li s11,0 + c: 04c000ef jal ra,58
+ 10: 00100d13 li s10,1 + +00000014 : + 14: 0000006f j 14 + +00000018 : + 18: ff010113 addi sp,sp,-16 + 1c: 00812623 sw s0,12(sp) + 20: 01010413 addi s0,sp,16 + 24: 00100d93 li s11,1 + 28: 00000013 nop + 2c: 00c12403 lw s0,12(sp) + 30: 01010113 addi sp,sp,16 + 34: 00008067 ret + +00000038 : + 38: ff010113 addi sp,sp,-16 + 3c: 00812623 sw s0,12(sp) + 40: 01010413 addi s0,sp,16 + 44: 00000d93 li s11,0 + 48: 00000013 nop + 4c: 00c12403 lw s0,12(sp) + 50: 01010113 addi sp,sp,16 + 54: 00008067 ret + +00000058
: + 58: fe010113 addi sp,sp,-32 + 5c: 00112e23 sw ra,28(sp) + 60: 00812c23 sw s0,24(sp) + 64: 02010413 addi s0,sp,32 + 68: fe042423 sw zero,-24(s0) + 6c: fe042623 sw zero,-20(s0) + 70: 0200006f j 90 + 74: fe842703 lw a4,-24(s0) + 78: fec42783 lw a5,-20(s0) + 7c: 00f707b3 add a5,a4,a5 + 80: fef42423 sw a5,-24(s0) + 84: fec42783 lw a5,-20(s0) + 88: 00178793 addi a5,a5,1 + 8c: fef42623 sw a5,-20(s0) + 90: fec42703 lw a4,-20(s0) + 94: 06400793 li a5,100 + 98: fce7dee3 bge a5,a4,74 + 9c: fe842703 lw a4,-24(s0) + a0: 000017b7 lui a5,0x1 + a4: 3ba78793 addi a5,a5,954 # 13ba <_end+0x12ba> + a8: 00f71663 bne a4,a5,b4 + ac: f6dff0ef jal ra,18 + b0: 0080006f j b8 + b4: f85ff0ef jal ra,38 + b8: 00000793 li a5,0 + bc: 00078513 mv a0,a5 + c0: 01c12083 lw ra,28(sp) + c4: 01812403 lw s0,24(sp) + c8: 02010113 addi sp,sp,32 + cc: 00008067 ret + +Disassembly of section .comment: + +00000000 <.comment>: + 0: 3a434347 fmsub.d ft6,ft6,ft4,ft7,rmm + 4: 2820 fld fs0,80(s0) + 6: 20554e47 fmsub.s ft8,fa0,ft5,ft4,rmm + a: 434d li t1,19 + c: 2055 jal b0 + e: 6345 lui t1,0x11 + 10: 696c flw fa1,84(a0) + 12: 7370 flw fa2,100(a4) + 14: 2065 jal bc + 16: 4952 lw s2,20(sp) + 18: 562d4353 0x562d4353 + 1c: 4520 lw s0,72(a0) + 1e: 626d lui tp,0x1b + 20: 6465 lui s0,0x19 + 22: 6564 flw fs1,76(a0) + 24: 2064 fld fs1,192(s0) + 26: 2c434347 0x2c434347 + 2a: 3620 fld fs0,104(a2) + 2c: 2d34 fld fa3,88(a0) + 2e: 6962 flw fs2,24(sp) + 30: 2974 fld fa3,208(a0) + 32: 3820 fld fs0,112(s0) + 34: 322e fld ft4,232(sp) + 36: 302e fld ft0,232(sp) + ... diff --git a/tests/example/link.ld b/tests/example/link.ld new file mode 100644 index 0000000..f11a55d --- /dev/null +++ b/tests/example/link.ld @@ -0,0 +1,25 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_reset) + +SECTIONS +{ + __stack_size = 0x100; + + . = 0x00000000; + .text : { *(.text) } + + PROVIDE( _data_start = . ); + .data ALIGN(0x1000) : { *(.data) } + . = ALIGN(4); + PROVIDE( _data_end = . ); + + PROVIDE( _bss_start = . ); + .bss : { *(.bss) } + PROVIDE( _bss_end = . ); + + PROVIDE(_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(_stack_end = .); + _end = .; +} diff --git a/tests/example/main.c b/tests/example/main.c new file mode 100644 index 0000000..607c04b --- /dev/null +++ b/tests/example/main.c @@ -0,0 +1,29 @@ + +static void set_test_pass() +{ + asm("li x27, 0x01"); +} + +static void set_test_fail() +{ + asm("li x27, 0x00"); +} + +// add 1 to 100 +int main() +{ + int i; + int sum; + + sum = 0; + + for (i = 0; i <= 100; i++) + sum += i; + + if (sum == 5050) + set_test_pass(); + else + set_test_fail(); + + return 0; +} diff --git a/tests/example/reset.S b/tests/example/reset.S new file mode 100644 index 0000000..248f810 --- /dev/null +++ b/tests/example/reset.S @@ -0,0 +1,15 @@ + .section .text; + .align 2; + .globl _reset; + +_reset: + la sp, _sp + li x26, 0x00 + li x27, 0x00 + + call main + + li x26, 0x01 + +loop: + j loop diff --git a/tests/isa/Makefile b/tests/isa/Makefile new file mode 100644 index 0000000..cfbb503 --- /dev/null +++ b/tests/isa/Makefile @@ -0,0 +1,65 @@ +#======================================================================= +# Makefile for riscv-tests/isa +#----------------------------------------------------------------------- + +XLEN := 32 + +src_dir := . + +include $(src_dir)/rv32ui/Makefrag + +default: all + +#-------------------------------------------------------------------- +# Build rules +#-------------------------------------------------------------------- + +RISCV_PREFIX ?= ../../tools/gnu-mcu-eclipse-riscv-none-gcc-8.2.0-2.2-20190521-0004-win64/bin/riscv-none-embed- +RISCV_GCC ?= $(RISCV_PREFIX)gcc +RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles +RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassemble-all +RISCV_OBJCOPY ?= $(RISCV_PREFIX)objcopy + + +vpath %.S $(src_dir) + +#------------------------------------------------------------ +# Build assembly tests + +%.dump: % + $(RISCV_OBJDUMP) generated/$< > generated/$@ + $(RISCV_OBJCOPY) -O verilog generated/$< generated/$<.verilog + $(RISCV_OBJCOPY) -O binary generated/$< generated/$<.bin + + +define compile_template + +$$($(1)_p_tests): $(1)-p-%: $(1)/%.S + $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir) -T$(src_dir)/link.ld $$< -o generated/$$@ +$(1)_tests += $$($(1)_p_tests) + +$(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests)) + +$(1): $$($(1)_tests_dump) + +.PHONY: $(1) + +tests += $$($(1)_tests) + +endef + +$(eval $(call compile_template,rv32ui,-march=rv32i -mabi=ilp32)) + + +tests_verilog = $(addsuffix .verilog, $(tests)) +tests_dump = $(addsuffix .dump, $(tests)) + + +#------------------------------------------------------------ +# Default + +all: $(tests_dump) + +clean: + rm -rf generated/* + diff --git a/tests/isa/README.md b/tests/isa/README.md new file mode 100644 index 0000000..79e53b2 --- /dev/null +++ b/tests/isa/README.md @@ -0,0 +1,4 @@ +RV32I instruction source code which copy from riscv(github). +I have modified it so can run on tinyriscv. +compile: type make under the cmd windows +recompile: type make after make clean under the cmd windows diff --git a/tests/isa/generated/rv32ui-p-add b/tests/isa/generated/rv32ui-p-add new file mode 100644 index 0000000..3955017 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-add differ diff --git a/tests/isa/generated/rv32ui-p-add.bin b/tests/isa/generated/rv32ui-p-add.bin new file mode 100644 index 0000000..96010f5 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-add.bin differ diff --git a/tests/isa/generated/rv32ui-p-add.dump b/tests/isa/generated/rv32ui-p-add.dump new file mode 100644 index 0000000..c17c150 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-add.dump @@ -0,0 +1,419 @@ + +generated/rv32ui-p-add: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00000093 li ra,0 + c: 00000113 li sp,0 + 10: 00208f33 add t5,ra,sp + 14: 00000e93 li t4,0 + 18: 00200193 li gp,2 + 1c: 4ddf1663 bne t5,t4,4e8 + +00000020 : + 20: 00100093 li ra,1 + 24: 00100113 li sp,1 + 28: 00208f33 add t5,ra,sp + 2c: 00200e93 li t4,2 + 30: 00300193 li gp,3 + 34: 4bdf1a63 bne t5,t4,4e8 + +00000038 : + 38: 00300093 li ra,3 + 3c: 00700113 li sp,7 + 40: 00208f33 add t5,ra,sp + 44: 00a00e93 li t4,10 + 48: 00400193 li gp,4 + 4c: 49df1e63 bne t5,t4,4e8 + +00000050 : + 50: 00000093 li ra,0 + 54: ffff8137 lui sp,0xffff8 + 58: 00208f33 add t5,ra,sp + 5c: ffff8eb7 lui t4,0xffff8 + 60: 00500193 li gp,5 + 64: 49df1263 bne t5,t4,4e8 + +00000068 : + 68: 800000b7 lui ra,0x80000 + 6c: 00000113 li sp,0 + 70: 00208f33 add t5,ra,sp + 74: 80000eb7 lui t4,0x80000 + 78: 00600193 li gp,6 + 7c: 47df1663 bne t5,t4,4e8 + +00000080 : + 80: 800000b7 lui ra,0x80000 + 84: ffff8137 lui sp,0xffff8 + 88: 00208f33 add t5,ra,sp + 8c: 7fff8eb7 lui t4,0x7fff8 + 90: 00700193 li gp,7 + 94: 45df1a63 bne t5,t4,4e8 + +00000098 : + 98: 00000093 li ra,0 + 9c: 00008137 lui sp,0x8 + a0: fff10113 addi sp,sp,-1 # 7fff + a4: 00208f33 add t5,ra,sp + a8: 00008eb7 lui t4,0x8 + ac: fffe8e93 addi t4,t4,-1 # 7fff + b0: 00800193 li gp,8 + b4: 43df1a63 bne t5,t4,4e8 + +000000b8 : + b8: 800000b7 lui ra,0x80000 + bc: fff08093 addi ra,ra,-1 # 7fffffff + c0: 00000113 li sp,0 + c4: 00208f33 add t5,ra,sp + c8: 80000eb7 lui t4,0x80000 + cc: fffe8e93 addi t4,t4,-1 # 7fffffff + d0: 00900193 li gp,9 + d4: 41df1a63 bne t5,t4,4e8 + +000000d8 : + d8: 800000b7 lui ra,0x80000 + dc: fff08093 addi ra,ra,-1 # 7fffffff + e0: 00008137 lui sp,0x8 + e4: fff10113 addi sp,sp,-1 # 7fff + e8: 00208f33 add t5,ra,sp + ec: 80008eb7 lui t4,0x80008 + f0: ffee8e93 addi t4,t4,-2 # 80007ffe + f4: 00a00193 li gp,10 + f8: 3fdf1863 bne t5,t4,4e8 + +000000fc : + fc: 800000b7 lui ra,0x80000 + 100: 00008137 lui sp,0x8 + 104: fff10113 addi sp,sp,-1 # 7fff + 108: 00208f33 add t5,ra,sp + 10c: 80008eb7 lui t4,0x80008 + 110: fffe8e93 addi t4,t4,-1 # 80007fff + 114: 00b00193 li gp,11 + 118: 3ddf1863 bne t5,t4,4e8 + +0000011c : + 11c: 800000b7 lui ra,0x80000 + 120: fff08093 addi ra,ra,-1 # 7fffffff + 124: ffff8137 lui sp,0xffff8 + 128: 00208f33 add t5,ra,sp + 12c: 7fff8eb7 lui t4,0x7fff8 + 130: fffe8e93 addi t4,t4,-1 # 7fff7fff + 134: 00c00193 li gp,12 + 138: 3bdf1863 bne t5,t4,4e8 + +0000013c : + 13c: 00000093 li ra,0 + 140: fff00113 li sp,-1 + 144: 00208f33 add t5,ra,sp + 148: fff00e93 li t4,-1 + 14c: 00d00193 li gp,13 + 150: 39df1c63 bne t5,t4,4e8 + +00000154 : + 154: fff00093 li ra,-1 + 158: 00100113 li sp,1 + 15c: 00208f33 add t5,ra,sp + 160: 00000e93 li t4,0 + 164: 00e00193 li gp,14 + 168: 39df1063 bne t5,t4,4e8 + +0000016c : + 16c: fff00093 li ra,-1 + 170: fff00113 li sp,-1 + 174: 00208f33 add t5,ra,sp + 178: ffe00e93 li t4,-2 + 17c: 00f00193 li gp,15 + 180: 37df1463 bne t5,t4,4e8 + +00000184 : + 184: 00100093 li ra,1 + 188: 80000137 lui sp,0x80000 + 18c: fff10113 addi sp,sp,-1 # 7fffffff + 190: 00208f33 add t5,ra,sp + 194: 80000eb7 lui t4,0x80000 + 198: 01000193 li gp,16 + 19c: 35df1663 bne t5,t4,4e8 + +000001a0 : + 1a0: 00d00093 li ra,13 + 1a4: 00b00113 li sp,11 + 1a8: 002080b3 add ra,ra,sp + 1ac: 01800e93 li t4,24 + 1b0: 01100193 li gp,17 + 1b4: 33d09a63 bne ra,t4,4e8 + +000001b8 : + 1b8: 00e00093 li ra,14 + 1bc: 00b00113 li sp,11 + 1c0: 00208133 add sp,ra,sp + 1c4: 01900e93 li t4,25 + 1c8: 01200193 li gp,18 + 1cc: 31d11e63 bne sp,t4,4e8 + +000001d0 : + 1d0: 00d00093 li ra,13 + 1d4: 001080b3 add ra,ra,ra + 1d8: 01a00e93 li t4,26 + 1dc: 01300193 li gp,19 + 1e0: 31d09463 bne ra,t4,4e8 + +000001e4 : + 1e4: 00000213 li tp,0 + 1e8: 00d00093 li ra,13 + 1ec: 00b00113 li sp,11 + 1f0: 00208f33 add t5,ra,sp + 1f4: 000f0313 mv t1,t5 + 1f8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1fc: 00200293 li t0,2 + 200: fe5214e3 bne tp,t0,1e8 + 204: 01800e93 li t4,24 + 208: 01400193 li gp,20 + 20c: 2dd31e63 bne t1,t4,4e8 + +00000210 : + 210: 00000213 li tp,0 + 214: 00e00093 li ra,14 + 218: 00b00113 li sp,11 + 21c: 00208f33 add t5,ra,sp + 220: 00000013 nop + 224: 000f0313 mv t1,t5 + 228: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 22c: 00200293 li t0,2 + 230: fe5212e3 bne tp,t0,214 + 234: 01900e93 li t4,25 + 238: 01500193 li gp,21 + 23c: 2bd31663 bne t1,t4,4e8 + +00000240 : + 240: 00000213 li tp,0 + 244: 00f00093 li ra,15 + 248: 00b00113 li sp,11 + 24c: 00208f33 add t5,ra,sp + 250: 00000013 nop + 254: 00000013 nop + 258: 000f0313 mv t1,t5 + 25c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 260: 00200293 li t0,2 + 264: fe5210e3 bne tp,t0,244 + 268: 01a00e93 li t4,26 + 26c: 01600193 li gp,22 + 270: 27d31c63 bne t1,t4,4e8 + +00000274 : + 274: 00000213 li tp,0 + 278: 00d00093 li ra,13 + 27c: 00b00113 li sp,11 + 280: 00208f33 add t5,ra,sp + 284: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 288: 00200293 li t0,2 + 28c: fe5216e3 bne tp,t0,278 + 290: 01800e93 li t4,24 + 294: 01700193 li gp,23 + 298: 25df1863 bne t5,t4,4e8 + +0000029c : + 29c: 00000213 li tp,0 + 2a0: 00e00093 li ra,14 + 2a4: 00b00113 li sp,11 + 2a8: 00000013 nop + 2ac: 00208f33 add t5,ra,sp + 2b0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2b4: 00200293 li t0,2 + 2b8: fe5214e3 bne tp,t0,2a0 + 2bc: 01900e93 li t4,25 + 2c0: 01800193 li gp,24 + 2c4: 23df1263 bne t5,t4,4e8 + +000002c8 : + 2c8: 00000213 li tp,0 + 2cc: 00f00093 li ra,15 + 2d0: 00b00113 li sp,11 + 2d4: 00000013 nop + 2d8: 00000013 nop + 2dc: 00208f33 add t5,ra,sp + 2e0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2e4: 00200293 li t0,2 + 2e8: fe5212e3 bne tp,t0,2cc + 2ec: 01a00e93 li t4,26 + 2f0: 01900193 li gp,25 + 2f4: 1fdf1a63 bne t5,t4,4e8 + +000002f8 : + 2f8: 00000213 li tp,0 + 2fc: 00d00093 li ra,13 + 300: 00000013 nop + 304: 00b00113 li sp,11 + 308: 00208f33 add t5,ra,sp + 30c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 310: 00200293 li t0,2 + 314: fe5214e3 bne tp,t0,2fc + 318: 01800e93 li t4,24 + 31c: 01a00193 li gp,26 + 320: 1ddf1463 bne t5,t4,4e8 + +00000324 : + 324: 00000213 li tp,0 + 328: 00e00093 li ra,14 + 32c: 00000013 nop + 330: 00b00113 li sp,11 + 334: 00000013 nop + 338: 00208f33 add t5,ra,sp + 33c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 340: 00200293 li t0,2 + 344: fe5212e3 bne tp,t0,328 + 348: 01900e93 li t4,25 + 34c: 01b00193 li gp,27 + 350: 19df1c63 bne t5,t4,4e8 + +00000354 : + 354: 00000213 li tp,0 + 358: 00f00093 li ra,15 + 35c: 00000013 nop + 360: 00000013 nop + 364: 00b00113 li sp,11 + 368: 00208f33 add t5,ra,sp + 36c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 370: 00200293 li t0,2 + 374: fe5212e3 bne tp,t0,358 + 378: 01a00e93 li t4,26 + 37c: 01c00193 li gp,28 + 380: 17df1463 bne t5,t4,4e8 + +00000384 : + 384: 00000213 li tp,0 + 388: 00b00113 li sp,11 + 38c: 00d00093 li ra,13 + 390: 00208f33 add t5,ra,sp + 394: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 398: 00200293 li t0,2 + 39c: fe5216e3 bne tp,t0,388 + 3a0: 01800e93 li t4,24 + 3a4: 01d00193 li gp,29 + 3a8: 15df1063 bne t5,t4,4e8 + +000003ac : + 3ac: 00000213 li tp,0 + 3b0: 00b00113 li sp,11 + 3b4: 00e00093 li ra,14 + 3b8: 00000013 nop + 3bc: 00208f33 add t5,ra,sp + 3c0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3c4: 00200293 li t0,2 + 3c8: fe5214e3 bne tp,t0,3b0 + 3cc: 01900e93 li t4,25 + 3d0: 01e00193 li gp,30 + 3d4: 11df1a63 bne t5,t4,4e8 + +000003d8 : + 3d8: 00000213 li tp,0 + 3dc: 00b00113 li sp,11 + 3e0: 00f00093 li ra,15 + 3e4: 00000013 nop + 3e8: 00000013 nop + 3ec: 00208f33 add t5,ra,sp + 3f0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3f4: 00200293 li t0,2 + 3f8: fe5212e3 bne tp,t0,3dc + 3fc: 01a00e93 li t4,26 + 400: 01f00193 li gp,31 + 404: 0fdf1263 bne t5,t4,4e8 + +00000408 : + 408: 00000213 li tp,0 + 40c: 00b00113 li sp,11 + 410: 00000013 nop + 414: 00d00093 li ra,13 + 418: 00208f33 add t5,ra,sp + 41c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 420: 00200293 li t0,2 + 424: fe5214e3 bne tp,t0,40c + 428: 01800e93 li t4,24 + 42c: 02000193 li gp,32 + 430: 0bdf1c63 bne t5,t4,4e8 + +00000434 : + 434: 00000213 li tp,0 + 438: 00b00113 li sp,11 + 43c: 00000013 nop + 440: 00e00093 li ra,14 + 444: 00000013 nop + 448: 00208f33 add t5,ra,sp + 44c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 450: 00200293 li t0,2 + 454: fe5212e3 bne tp,t0,438 + 458: 01900e93 li t4,25 + 45c: 02100193 li gp,33 + 460: 09df1463 bne t5,t4,4e8 + +00000464 : + 464: 00000213 li tp,0 + 468: 00b00113 li sp,11 + 46c: 00000013 nop + 470: 00000013 nop + 474: 00f00093 li ra,15 + 478: 00208f33 add t5,ra,sp + 47c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 480: 00200293 li t0,2 + 484: fe5212e3 bne tp,t0,468 + 488: 01a00e93 li t4,26 + 48c: 02200193 li gp,34 + 490: 05df1c63 bne t5,t4,4e8 + +00000494 : + 494: 00f00093 li ra,15 + 498: 00100133 add sp,zero,ra + 49c: 00f00e93 li t4,15 + 4a0: 02300193 li gp,35 + 4a4: 05d11263 bne sp,t4,4e8 + +000004a8 : + 4a8: 02000093 li ra,32 + 4ac: 00008133 add sp,ra,zero + 4b0: 02000e93 li t4,32 + 4b4: 02400193 li gp,36 + 4b8: 03d11863 bne sp,t4,4e8 + +000004bc : + 4bc: 000000b3 add ra,zero,zero + 4c0: 00000e93 li t4,0 + 4c4: 02500193 li gp,37 + 4c8: 03d09063 bne ra,t4,4e8 + +000004cc : + 4cc: 01000093 li ra,16 + 4d0: 01e00113 li sp,30 + 4d4: 00208033 add zero,ra,sp + 4d8: 00000e93 li t4,0 + 4dc: 02600193 li gp,38 + 4e0: 01d01463 bne zero,t4,4e8 + 4e4: 00301863 bne zero,gp,4f4 + +000004e8 : + 4e8: 00100d13 li s10,1 + 4ec: 00000d93 li s11,0 + +000004f0 : + 4f0: 0000006f j 4f0 + +000004f4 : + 4f4: 00100d13 li s10,1 + 4f8: 00100d93 li s11,1 + +000004fc : + 4fc: 0000006f j 4fc + 500: 0000 unimp + ... + +Disassembly of section .tohost: + +00000540 : + ... + +00000580 : + ... diff --git a/tests/isa/generated/rv32ui-p-add.verilog b/tests/isa/generated/rv32ui-p-add.verilog new file mode 100644 index 0000000..03c0528 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-add.verilog @@ -0,0 +1,88 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 00 00 13 01 00 00 +33 8F 20 00 93 0E 00 00 93 01 20 00 63 16 DF 4D +93 00 10 00 13 01 10 00 33 8F 20 00 93 0E 20 00 +93 01 30 00 63 1A DF 4B 93 00 30 00 13 01 70 00 +33 8F 20 00 93 0E A0 00 93 01 40 00 63 1E DF 49 +93 00 00 00 37 81 FF FF 33 8F 20 00 B7 8E FF FF +93 01 50 00 63 12 DF 49 B7 00 00 80 13 01 00 00 +33 8F 20 00 B7 0E 00 80 93 01 60 00 63 16 DF 47 +B7 00 00 80 37 81 FF FF 33 8F 20 00 B7 8E FF 7F +93 01 70 00 63 1A DF 45 93 00 00 00 37 81 00 00 +13 01 F1 FF 33 8F 20 00 B7 8E 00 00 93 8E FE FF +93 01 80 00 63 1A DF 43 B7 00 00 80 93 80 F0 FF +13 01 00 00 33 8F 20 00 B7 0E 00 80 93 8E FE FF +93 01 90 00 63 1A DF 41 B7 00 00 80 93 80 F0 FF +37 81 00 00 13 01 F1 FF 33 8F 20 00 B7 8E 00 80 +93 8E EE FF 93 01 A0 00 63 18 DF 3F B7 00 00 80 +37 81 00 00 13 01 F1 FF 33 8F 20 00 B7 8E 00 80 +93 8E FE FF 93 01 B0 00 63 18 DF 3D B7 00 00 80 +93 80 F0 FF 37 81 FF FF 33 8F 20 00 B7 8E FF 7F +93 8E FE FF 93 01 C0 00 63 18 DF 3B 93 00 00 00 +13 01 F0 FF 33 8F 20 00 93 0E F0 FF 93 01 D0 00 +63 1C DF 39 93 00 F0 FF 13 01 10 00 33 8F 20 00 +93 0E 00 00 93 01 E0 00 63 10 DF 39 93 00 F0 FF +13 01 F0 FF 33 8F 20 00 93 0E E0 FF 93 01 F0 00 +63 14 DF 37 93 00 10 00 37 01 00 80 13 01 F1 FF +33 8F 20 00 B7 0E 00 80 93 01 00 01 63 16 DF 35 +93 00 D0 00 13 01 B0 00 B3 80 20 00 93 0E 80 01 +93 01 10 01 63 9A D0 33 93 00 E0 00 13 01 B0 00 +33 81 20 00 93 0E 90 01 93 01 20 01 63 1E D1 31 +93 00 D0 00 B3 80 10 00 93 0E A0 01 93 01 30 01 +63 94 D0 31 13 02 00 00 93 00 D0 00 13 01 B0 00 +33 8F 20 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 80 01 93 01 40 01 63 1E D3 2D +13 02 00 00 93 00 E0 00 13 01 B0 00 33 8F 20 00 +13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E 90 01 93 01 50 01 63 16 D3 2B +13 02 00 00 93 00 F0 00 13 01 B0 00 33 8F 20 00 +13 00 00 00 13 00 00 00 13 03 0F 00 13 02 12 00 +93 02 20 00 E3 10 52 FE 93 0E A0 01 93 01 60 01 +63 1C D3 27 13 02 00 00 93 00 D0 00 13 01 B0 00 +33 8F 20 00 13 02 12 00 93 02 20 00 E3 16 52 FE +93 0E 80 01 93 01 70 01 63 18 DF 25 13 02 00 00 +93 00 E0 00 13 01 B0 00 13 00 00 00 33 8F 20 00 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 90 01 +93 01 80 01 63 12 DF 23 13 02 00 00 93 00 F0 00 +13 01 B0 00 13 00 00 00 13 00 00 00 33 8F 20 00 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E A0 01 +93 01 90 01 63 1A DF 1F 13 02 00 00 93 00 D0 00 +13 00 00 00 13 01 B0 00 33 8F 20 00 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 0E 80 01 93 01 A0 01 +63 14 DF 1D 13 02 00 00 93 00 E0 00 13 00 00 00 +13 01 B0 00 13 00 00 00 33 8F 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E 90 01 93 01 B0 01 +63 1C DF 19 13 02 00 00 93 00 F0 00 13 00 00 00 +13 00 00 00 13 01 B0 00 33 8F 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E A0 01 93 01 C0 01 +63 14 DF 17 13 02 00 00 13 01 B0 00 93 00 D0 00 +33 8F 20 00 13 02 12 00 93 02 20 00 E3 16 52 FE +93 0E 80 01 93 01 D0 01 63 10 DF 15 13 02 00 00 +13 01 B0 00 93 00 E0 00 13 00 00 00 33 8F 20 00 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 90 01 +93 01 E0 01 63 1A DF 11 13 02 00 00 13 01 B0 00 +93 00 F0 00 13 00 00 00 13 00 00 00 33 8F 20 00 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E A0 01 +93 01 F0 01 63 12 DF 0F 13 02 00 00 13 01 B0 00 +13 00 00 00 93 00 D0 00 33 8F 20 00 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 0E 80 01 93 01 00 02 +63 1C DF 0B 13 02 00 00 13 01 B0 00 13 00 00 00 +93 00 E0 00 13 00 00 00 33 8F 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E 90 01 93 01 10 02 +63 14 DF 09 13 02 00 00 13 01 B0 00 13 00 00 00 +13 00 00 00 93 00 F0 00 33 8F 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E A0 01 93 01 20 02 +63 1C DF 05 93 00 F0 00 33 01 10 00 93 0E F0 00 +93 01 30 02 63 12 D1 05 93 00 00 02 33 81 00 00 +93 0E 00 02 93 01 40 02 63 18 D1 03 B3 00 00 00 +93 0E 00 00 93 01 50 02 63 90 D0 03 93 00 00 01 +13 01 E0 01 33 80 20 00 93 0E 00 00 93 01 60 02 +63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 +@00000540 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-addi b/tests/isa/generated/rv32ui-p-addi new file mode 100644 index 0000000..1a8bf61 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-addi differ diff --git a/tests/isa/generated/rv32ui-p-addi.bin b/tests/isa/generated/rv32ui-p-addi.bin new file mode 100644 index 0000000..83aa0d8 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-addi.bin differ diff --git a/tests/isa/generated/rv32ui-p-addi.dump b/tests/isa/generated/rv32ui-p-addi.dump new file mode 100644 index 0000000..6ad58c4 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-addi.dump @@ -0,0 +1,242 @@ + +generated/rv32ui-p-addi: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00000093 li ra,0 + c: 00008f13 mv t5,ra + 10: 00000e93 li t4,0 + 14: 00200193 li gp,2 + 18: 27df1c63 bne t5,t4,290 + +0000001c : + 1c: 00100093 li ra,1 + 20: 00108f13 addi t5,ra,1 + 24: 00200e93 li t4,2 + 28: 00300193 li gp,3 + 2c: 27df1263 bne t5,t4,290 + +00000030 : + 30: 00300093 li ra,3 + 34: 00708f13 addi t5,ra,7 + 38: 00a00e93 li t4,10 + 3c: 00400193 li gp,4 + 40: 25df1863 bne t5,t4,290 + +00000044 : + 44: 00000093 li ra,0 + 48: 80008f13 addi t5,ra,-2048 + 4c: 80000e93 li t4,-2048 + 50: 00500193 li gp,5 + 54: 23df1e63 bne t5,t4,290 + +00000058 : + 58: 800000b7 lui ra,0x80000 + 5c: 00008f13 mv t5,ra + 60: 80000eb7 lui t4,0x80000 + 64: 00600193 li gp,6 + 68: 23df1463 bne t5,t4,290 + +0000006c : + 6c: 800000b7 lui ra,0x80000 + 70: 80008f13 addi t5,ra,-2048 # 7ffff800 + 74: 80000eb7 lui t4,0x80000 + 78: 800e8e93 addi t4,t4,-2048 # 7ffff800 + 7c: 00700193 li gp,7 + 80: 21df1863 bne t5,t4,290 + +00000084 : + 84: 00000093 li ra,0 + 88: 7ff08f13 addi t5,ra,2047 + 8c: 7ff00e93 li t4,2047 + 90: 00800193 li gp,8 + 94: 1fdf1e63 bne t5,t4,290 + +00000098 : + 98: 800000b7 lui ra,0x80000 + 9c: fff08093 addi ra,ra,-1 # 7fffffff + a0: 00008f13 mv t5,ra + a4: 80000eb7 lui t4,0x80000 + a8: fffe8e93 addi t4,t4,-1 # 7fffffff + ac: 00900193 li gp,9 + b0: 1fdf1063 bne t5,t4,290 + +000000b4 : + b4: 800000b7 lui ra,0x80000 + b8: fff08093 addi ra,ra,-1 # 7fffffff + bc: 7ff08f13 addi t5,ra,2047 + c0: 80000eb7 lui t4,0x80000 + c4: 7fee8e93 addi t4,t4,2046 # 800007fe + c8: 00a00193 li gp,10 + cc: 1ddf1263 bne t5,t4,290 + +000000d0 : + d0: 800000b7 lui ra,0x80000 + d4: 7ff08f13 addi t5,ra,2047 # 800007ff + d8: 80000eb7 lui t4,0x80000 + dc: 7ffe8e93 addi t4,t4,2047 # 800007ff + e0: 00b00193 li gp,11 + e4: 1bdf1663 bne t5,t4,290 + +000000e8 : + e8: 800000b7 lui ra,0x80000 + ec: fff08093 addi ra,ra,-1 # 7fffffff + f0: 80008f13 addi t5,ra,-2048 + f4: 7ffffeb7 lui t4,0x7ffff + f8: 7ffe8e93 addi t4,t4,2047 # 7ffff7ff + fc: 00c00193 li gp,12 + 100: 19df1863 bne t5,t4,290 + +00000104 : + 104: 00000093 li ra,0 + 108: fff08f13 addi t5,ra,-1 + 10c: fff00e93 li t4,-1 + 110: 00d00193 li gp,13 + 114: 17df1e63 bne t5,t4,290 + +00000118 : + 118: fff00093 li ra,-1 + 11c: 00108f13 addi t5,ra,1 + 120: 00000e93 li t4,0 + 124: 00e00193 li gp,14 + 128: 17df1463 bne t5,t4,290 + +0000012c : + 12c: fff00093 li ra,-1 + 130: fff08f13 addi t5,ra,-1 + 134: ffe00e93 li t4,-2 + 138: 00f00193 li gp,15 + 13c: 15df1a63 bne t5,t4,290 + +00000140 : + 140: 800000b7 lui ra,0x80000 + 144: fff08093 addi ra,ra,-1 # 7fffffff + 148: 00108f13 addi t5,ra,1 + 14c: 80000eb7 lui t4,0x80000 + 150: 01000193 li gp,16 + 154: 13df1e63 bne t5,t4,290 + +00000158 : + 158: 00d00093 li ra,13 + 15c: 00b08093 addi ra,ra,11 + 160: 01800e93 li t4,24 + 164: 01100193 li gp,17 + 168: 13d09463 bne ra,t4,290 + +0000016c : + 16c: 00000213 li tp,0 + 170: 00d00093 li ra,13 + 174: 00b08f13 addi t5,ra,11 + 178: 000f0313 mv t1,t5 + 17c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 180: 00200293 li t0,2 + 184: fe5216e3 bne tp,t0,170 + 188: 01800e93 li t4,24 + 18c: 01200193 li gp,18 + 190: 11d31063 bne t1,t4,290 + +00000194 : + 194: 00000213 li tp,0 + 198: 00d00093 li ra,13 + 19c: 00a08f13 addi t5,ra,10 + 1a0: 00000013 nop + 1a4: 000f0313 mv t1,t5 + 1a8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1ac: 00200293 li t0,2 + 1b0: fe5214e3 bne tp,t0,198 + 1b4: 01700e93 li t4,23 + 1b8: 01300193 li gp,19 + 1bc: 0dd31a63 bne t1,t4,290 + +000001c0 : + 1c0: 00000213 li tp,0 + 1c4: 00d00093 li ra,13 + 1c8: 00908f13 addi t5,ra,9 + 1cc: 00000013 nop + 1d0: 00000013 nop + 1d4: 000f0313 mv t1,t5 + 1d8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1dc: 00200293 li t0,2 + 1e0: fe5212e3 bne tp,t0,1c4 + 1e4: 01600e93 li t4,22 + 1e8: 01400193 li gp,20 + 1ec: 0bd31263 bne t1,t4,290 + +000001f0 : + 1f0: 00000213 li tp,0 + 1f4: 00d00093 li ra,13 + 1f8: 00b08f13 addi t5,ra,11 + 1fc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 200: 00200293 li t0,2 + 204: fe5218e3 bne tp,t0,1f4 + 208: 01800e93 li t4,24 + 20c: 01500193 li gp,21 + 210: 09df1063 bne t5,t4,290 + +00000214 : + 214: 00000213 li tp,0 + 218: 00d00093 li ra,13 + 21c: 00000013 nop + 220: 00a08f13 addi t5,ra,10 + 224: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 228: 00200293 li t0,2 + 22c: fe5216e3 bne tp,t0,218 + 230: 01700e93 li t4,23 + 234: 01600193 li gp,22 + 238: 05df1c63 bne t5,t4,290 + +0000023c : + 23c: 00000213 li tp,0 + 240: 00d00093 li ra,13 + 244: 00000013 nop + 248: 00000013 nop + 24c: 00908f13 addi t5,ra,9 + 250: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 254: 00200293 li t0,2 + 258: fe5214e3 bne tp,t0,240 + 25c: 01600e93 li t4,22 + 260: 01700193 li gp,23 + 264: 03df1663 bne t5,t4,290 + +00000268 : + 268: 02000093 li ra,32 + 26c: 02000e93 li t4,32 + 270: 01800193 li gp,24 + 274: 01d09e63 bne ra,t4,290 + +00000278 : + 278: 02100093 li ra,33 + 27c: 03208013 addi zero,ra,50 + 280: 00000e93 li t4,0 + 284: 01900193 li gp,25 + 288: 01d01463 bne zero,t4,290 + 28c: 00301863 bne zero,gp,29c + +00000290 : + 290: 00100d13 li s10,1 + 294: 00000d93 li s11,0 + +00000298 : + 298: 0000006f j 298 + +0000029c : + 29c: 00100d13 li s10,1 + 2a0: 00100d93 li s11,1 + +000002a4 : + 2a4: 0000006f j 2a4 + ... + +Disassembly of section .tohost: + +00000300 : + ... + +00000340 : + ... diff --git a/tests/isa/generated/rv32ui-p-addi.verilog b/tests/isa/generated/rv32ui-p-addi.verilog new file mode 100644 index 0000000..7597bdf --- /dev/null +++ b/tests/isa/generated/rv32ui-p-addi.verilog @@ -0,0 +1,52 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 00 00 13 8F 00 00 +93 0E 00 00 93 01 20 00 63 1C DF 27 93 00 10 00 +13 8F 10 00 93 0E 20 00 93 01 30 00 63 12 DF 27 +93 00 30 00 13 8F 70 00 93 0E A0 00 93 01 40 00 +63 18 DF 25 93 00 00 00 13 8F 00 80 93 0E 00 80 +93 01 50 00 63 1E DF 23 B7 00 00 80 13 8F 00 00 +B7 0E 00 80 93 01 60 00 63 14 DF 23 B7 00 00 80 +13 8F 00 80 B7 0E 00 80 93 8E 0E 80 93 01 70 00 +63 18 DF 21 93 00 00 00 13 8F F0 7F 93 0E F0 7F +93 01 80 00 63 1E DF 1F B7 00 00 80 93 80 F0 FF +13 8F 00 00 B7 0E 00 80 93 8E FE FF 93 01 90 00 +63 10 DF 1F B7 00 00 80 93 80 F0 FF 13 8F F0 7F +B7 0E 00 80 93 8E EE 7F 93 01 A0 00 63 12 DF 1D +B7 00 00 80 13 8F F0 7F B7 0E 00 80 93 8E FE 7F +93 01 B0 00 63 16 DF 1B B7 00 00 80 93 80 F0 FF +13 8F 00 80 B7 FE FF 7F 93 8E FE 7F 93 01 C0 00 +63 18 DF 19 93 00 00 00 13 8F F0 FF 93 0E F0 FF +93 01 D0 00 63 1E DF 17 93 00 F0 FF 13 8F 10 00 +93 0E 00 00 93 01 E0 00 63 14 DF 17 93 00 F0 FF +13 8F F0 FF 93 0E E0 FF 93 01 F0 00 63 1A DF 15 +B7 00 00 80 93 80 F0 FF 13 8F 10 00 B7 0E 00 80 +93 01 00 01 63 1E DF 13 93 00 D0 00 93 80 B0 00 +93 0E 80 01 93 01 10 01 63 94 D0 13 13 02 00 00 +93 00 D0 00 13 8F B0 00 13 03 0F 00 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 0E 80 01 93 01 20 01 +63 10 D3 11 13 02 00 00 93 00 D0 00 13 8F A0 00 +13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 70 01 93 01 30 01 63 1A D3 0D +13 02 00 00 93 00 D0 00 13 8F 90 00 13 00 00 00 +13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E 60 01 93 01 40 01 63 12 D3 0B +13 02 00 00 93 00 D0 00 13 8F B0 00 13 02 12 00 +93 02 20 00 E3 18 52 FE 93 0E 80 01 93 01 50 01 +63 10 DF 09 13 02 00 00 93 00 D0 00 13 00 00 00 +13 8F A0 00 13 02 12 00 93 02 20 00 E3 16 52 FE +93 0E 70 01 93 01 60 01 63 1C DF 05 13 02 00 00 +93 00 D0 00 13 00 00 00 13 00 00 00 13 8F 90 00 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 60 01 +93 01 70 01 63 16 DF 03 93 00 00 02 93 0E 00 02 +93 01 80 01 63 9E D0 01 93 00 10 02 13 80 20 03 +93 0E 00 00 93 01 90 01 63 14 D0 01 63 18 30 00 +13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00 +93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000300 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-and b/tests/isa/generated/rv32ui-p-and new file mode 100644 index 0000000..d3c6e92 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-and differ diff --git a/tests/isa/generated/rv32ui-p-and.bin b/tests/isa/generated/rv32ui-p-and.bin new file mode 100644 index 0000000..b50f97c Binary files /dev/null and b/tests/isa/generated/rv32ui-p-and.bin differ diff --git a/tests/isa/generated/rv32ui-p-and.dump b/tests/isa/generated/rv32ui-p-and.dump new file mode 100644 index 0000000..514a1b1 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-and.dump @@ -0,0 +1,386 @@ + +generated/rv32ui-p-and: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: ff0100b7 lui ra,0xff010 + c: f0008093 addi ra,ra,-256 # ff00ff00 + 10: 0f0f1137 lui sp,0xf0f1 + 14: f0f10113 addi sp,sp,-241 # f0f0f0f + 18: 0020ff33 and t5,ra,sp + 1c: 0f001eb7 lui t4,0xf001 + 20: f00e8e93 addi t4,t4,-256 # f000f00 + 24: 00200193 li gp,2 + 28: 49df1c63 bne t5,t4,4c0 + +0000002c : + 2c: 0ff010b7 lui ra,0xff01 + 30: ff008093 addi ra,ra,-16 # ff00ff0 + 34: f0f0f137 lui sp,0xf0f0f + 38: 0f010113 addi sp,sp,240 # f0f0f0f0 + 3c: 0020ff33 and t5,ra,sp + 40: 00f00eb7 lui t4,0xf00 + 44: 0f0e8e93 addi t4,t4,240 # f000f0 + 48: 00300193 li gp,3 + 4c: 47df1a63 bne t5,t4,4c0 + +00000050 : + 50: 00ff00b7 lui ra,0xff0 + 54: 0ff08093 addi ra,ra,255 # ff00ff + 58: 0f0f1137 lui sp,0xf0f1 + 5c: f0f10113 addi sp,sp,-241 # f0f0f0f + 60: 0020ff33 and t5,ra,sp + 64: 000f0eb7 lui t4,0xf0 + 68: 00fe8e93 addi t4,t4,15 # f000f + 6c: 00400193 li gp,4 + 70: 45df1863 bne t5,t4,4c0 + +00000074 : + 74: f00ff0b7 lui ra,0xf00ff + 78: 00f08093 addi ra,ra,15 # f00ff00f + 7c: f0f0f137 lui sp,0xf0f0f + 80: 0f010113 addi sp,sp,240 # f0f0f0f0 + 84: 0020ff33 and t5,ra,sp + 88: f000feb7 lui t4,0xf000f + 8c: 00500193 li gp,5 + 90: 43df1863 bne t5,t4,4c0 + +00000094 : + 94: ff0100b7 lui ra,0xff010 + 98: f0008093 addi ra,ra,-256 # ff00ff00 + 9c: 0f0f1137 lui sp,0xf0f1 + a0: f0f10113 addi sp,sp,-241 # f0f0f0f + a4: 0020f0b3 and ra,ra,sp + a8: 0f001eb7 lui t4,0xf001 + ac: f00e8e93 addi t4,t4,-256 # f000f00 + b0: 00600193 li gp,6 + b4: 41d09663 bne ra,t4,4c0 + +000000b8 : + b8: 0ff010b7 lui ra,0xff01 + bc: ff008093 addi ra,ra,-16 # ff00ff0 + c0: f0f0f137 lui sp,0xf0f0f + c4: 0f010113 addi sp,sp,240 # f0f0f0f0 + c8: 0020f133 and sp,ra,sp + cc: 00f00eb7 lui t4,0xf00 + d0: 0f0e8e93 addi t4,t4,240 # f000f0 + d4: 00700193 li gp,7 + d8: 3fd11463 bne sp,t4,4c0 + +000000dc : + dc: ff0100b7 lui ra,0xff010 + e0: f0008093 addi ra,ra,-256 # ff00ff00 + e4: 0010f0b3 and ra,ra,ra + e8: ff010eb7 lui t4,0xff010 + ec: f00e8e93 addi t4,t4,-256 # ff00ff00 + f0: 00800193 li gp,8 + f4: 3dd09663 bne ra,t4,4c0 + +000000f8 : + f8: 00000213 li tp,0 + fc: ff0100b7 lui ra,0xff010 + 100: f0008093 addi ra,ra,-256 # ff00ff00 + 104: 0f0f1137 lui sp,0xf0f1 + 108: f0f10113 addi sp,sp,-241 # f0f0f0f + 10c: 0020ff33 and t5,ra,sp + 110: 000f0313 mv t1,t5 + 114: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 118: 00200293 li t0,2 + 11c: fe5210e3 bne tp,t0,fc + 120: 0f001eb7 lui t4,0xf001 + 124: f00e8e93 addi t4,t4,-256 # f000f00 + 128: 00900193 li gp,9 + 12c: 39d31a63 bne t1,t4,4c0 + +00000130 : + 130: 00000213 li tp,0 + 134: 0ff010b7 lui ra,0xff01 + 138: ff008093 addi ra,ra,-16 # ff00ff0 + 13c: f0f0f137 lui sp,0xf0f0f + 140: 0f010113 addi sp,sp,240 # f0f0f0f0 + 144: 0020ff33 and t5,ra,sp + 148: 00000013 nop + 14c: 000f0313 mv t1,t5 + 150: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 154: 00200293 li t0,2 + 158: fc521ee3 bne tp,t0,134 + 15c: 00f00eb7 lui t4,0xf00 + 160: 0f0e8e93 addi t4,t4,240 # f000f0 + 164: 00a00193 li gp,10 + 168: 35d31c63 bne t1,t4,4c0 + +0000016c : + 16c: 00000213 li tp,0 + 170: 00ff00b7 lui ra,0xff0 + 174: 0ff08093 addi ra,ra,255 # ff00ff + 178: 0f0f1137 lui sp,0xf0f1 + 17c: f0f10113 addi sp,sp,-241 # f0f0f0f + 180: 0020ff33 and t5,ra,sp + 184: 00000013 nop + 188: 00000013 nop + 18c: 000f0313 mv t1,t5 + 190: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 194: 00200293 li t0,2 + 198: fc521ce3 bne tp,t0,170 + 19c: 000f0eb7 lui t4,0xf0 + 1a0: 00fe8e93 addi t4,t4,15 # f000f + 1a4: 00b00193 li gp,11 + 1a8: 31d31c63 bne t1,t4,4c0 + +000001ac : + 1ac: 00000213 li tp,0 + 1b0: ff0100b7 lui ra,0xff010 + 1b4: f0008093 addi ra,ra,-256 # ff00ff00 + 1b8: 0f0f1137 lui sp,0xf0f1 + 1bc: f0f10113 addi sp,sp,-241 # f0f0f0f + 1c0: 0020ff33 and t5,ra,sp + 1c4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1c8: 00200293 li t0,2 + 1cc: fe5212e3 bne tp,t0,1b0 + 1d0: 0f001eb7 lui t4,0xf001 + 1d4: f00e8e93 addi t4,t4,-256 # f000f00 + 1d8: 00c00193 li gp,12 + 1dc: 2fdf1263 bne t5,t4,4c0 + +000001e0 : + 1e0: 00000213 li tp,0 + 1e4: 0ff010b7 lui ra,0xff01 + 1e8: ff008093 addi ra,ra,-16 # ff00ff0 + 1ec: f0f0f137 lui sp,0xf0f0f + 1f0: 0f010113 addi sp,sp,240 # f0f0f0f0 + 1f4: 00000013 nop + 1f8: 0020ff33 and t5,ra,sp + 1fc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 200: 00200293 li t0,2 + 204: fe5210e3 bne tp,t0,1e4 + 208: 00f00eb7 lui t4,0xf00 + 20c: 0f0e8e93 addi t4,t4,240 # f000f0 + 210: 00d00193 li gp,13 + 214: 2bdf1663 bne t5,t4,4c0 + +00000218 : + 218: 00000213 li tp,0 + 21c: 00ff00b7 lui ra,0xff0 + 220: 0ff08093 addi ra,ra,255 # ff00ff + 224: 0f0f1137 lui sp,0xf0f1 + 228: f0f10113 addi sp,sp,-241 # f0f0f0f + 22c: 00000013 nop + 230: 00000013 nop + 234: 0020ff33 and t5,ra,sp + 238: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 23c: 00200293 li t0,2 + 240: fc521ee3 bne tp,t0,21c + 244: 000f0eb7 lui t4,0xf0 + 248: 00fe8e93 addi t4,t4,15 # f000f + 24c: 00e00193 li gp,14 + 250: 27df1863 bne t5,t4,4c0 + +00000254 : + 254: 00000213 li tp,0 + 258: ff0100b7 lui ra,0xff010 + 25c: f0008093 addi ra,ra,-256 # ff00ff00 + 260: 00000013 nop + 264: 0f0f1137 lui sp,0xf0f1 + 268: f0f10113 addi sp,sp,-241 # f0f0f0f + 26c: 0020ff33 and t5,ra,sp + 270: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 274: 00200293 li t0,2 + 278: fe5210e3 bne tp,t0,258 + 27c: 0f001eb7 lui t4,0xf001 + 280: f00e8e93 addi t4,t4,-256 # f000f00 + 284: 00f00193 li gp,15 + 288: 23df1c63 bne t5,t4,4c0 + +0000028c : + 28c: 00000213 li tp,0 + 290: 0ff010b7 lui ra,0xff01 + 294: ff008093 addi ra,ra,-16 # ff00ff0 + 298: 00000013 nop + 29c: f0f0f137 lui sp,0xf0f0f + 2a0: 0f010113 addi sp,sp,240 # f0f0f0f0 + 2a4: 00000013 nop + 2a8: 0020ff33 and t5,ra,sp + 2ac: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2b0: 00200293 li t0,2 + 2b4: fc521ee3 bne tp,t0,290 + 2b8: 00f00eb7 lui t4,0xf00 + 2bc: 0f0e8e93 addi t4,t4,240 # f000f0 + 2c0: 01000193 li gp,16 + 2c4: 1fdf1e63 bne t5,t4,4c0 + +000002c8 : + 2c8: 00000213 li tp,0 + 2cc: 00ff00b7 lui ra,0xff0 + 2d0: 0ff08093 addi ra,ra,255 # ff00ff + 2d4: 00000013 nop + 2d8: 00000013 nop + 2dc: 0f0f1137 lui sp,0xf0f1 + 2e0: f0f10113 addi sp,sp,-241 # f0f0f0f + 2e4: 0020ff33 and t5,ra,sp + 2e8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2ec: 00200293 li t0,2 + 2f0: fc521ee3 bne tp,t0,2cc + 2f4: 000f0eb7 lui t4,0xf0 + 2f8: 00fe8e93 addi t4,t4,15 # f000f + 2fc: 01100193 li gp,17 + 300: 1ddf1063 bne t5,t4,4c0 + +00000304 : + 304: 00000213 li tp,0 + 308: 0f0f1137 lui sp,0xf0f1 + 30c: f0f10113 addi sp,sp,-241 # f0f0f0f + 310: ff0100b7 lui ra,0xff010 + 314: f0008093 addi ra,ra,-256 # ff00ff00 + 318: 0020ff33 and t5,ra,sp + 31c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 320: 00200293 li t0,2 + 324: fe5212e3 bne tp,t0,308 + 328: 0f001eb7 lui t4,0xf001 + 32c: f00e8e93 addi t4,t4,-256 # f000f00 + 330: 01200193 li gp,18 + 334: 19df1663 bne t5,t4,4c0 + +00000338 : + 338: 00000213 li tp,0 + 33c: f0f0f137 lui sp,0xf0f0f + 340: 0f010113 addi sp,sp,240 # f0f0f0f0 + 344: 0ff010b7 lui ra,0xff01 + 348: ff008093 addi ra,ra,-16 # ff00ff0 + 34c: 00000013 nop + 350: 0020ff33 and t5,ra,sp + 354: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 358: 00200293 li t0,2 + 35c: fe5210e3 bne tp,t0,33c + 360: 00f00eb7 lui t4,0xf00 + 364: 0f0e8e93 addi t4,t4,240 # f000f0 + 368: 01300193 li gp,19 + 36c: 15df1a63 bne t5,t4,4c0 + +00000370 : + 370: 00000213 li tp,0 + 374: 0f0f1137 lui sp,0xf0f1 + 378: f0f10113 addi sp,sp,-241 # f0f0f0f + 37c: 00ff00b7 lui ra,0xff0 + 380: 0ff08093 addi ra,ra,255 # ff00ff + 384: 00000013 nop + 388: 00000013 nop + 38c: 0020ff33 and t5,ra,sp + 390: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 394: 00200293 li t0,2 + 398: fc521ee3 bne tp,t0,374 + 39c: 000f0eb7 lui t4,0xf0 + 3a0: 00fe8e93 addi t4,t4,15 # f000f + 3a4: 01400193 li gp,20 + 3a8: 11df1c63 bne t5,t4,4c0 + +000003ac : + 3ac: 00000213 li tp,0 + 3b0: 0f0f1137 lui sp,0xf0f1 + 3b4: f0f10113 addi sp,sp,-241 # f0f0f0f + 3b8: 00000013 nop + 3bc: ff0100b7 lui ra,0xff010 + 3c0: f0008093 addi ra,ra,-256 # ff00ff00 + 3c4: 0020ff33 and t5,ra,sp + 3c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3cc: 00200293 li t0,2 + 3d0: fe5210e3 bne tp,t0,3b0 + 3d4: 0f001eb7 lui t4,0xf001 + 3d8: f00e8e93 addi t4,t4,-256 # f000f00 + 3dc: 01500193 li gp,21 + 3e0: 0fdf1063 bne t5,t4,4c0 + +000003e4 : + 3e4: 00000213 li tp,0 + 3e8: f0f0f137 lui sp,0xf0f0f + 3ec: 0f010113 addi sp,sp,240 # f0f0f0f0 + 3f0: 00000013 nop + 3f4: 0ff010b7 lui ra,0xff01 + 3f8: ff008093 addi ra,ra,-16 # ff00ff0 + 3fc: 00000013 nop + 400: 0020ff33 and t5,ra,sp + 404: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 408: 00200293 li t0,2 + 40c: fc521ee3 bne tp,t0,3e8 + 410: 00f00eb7 lui t4,0xf00 + 414: 0f0e8e93 addi t4,t4,240 # f000f0 + 418: 01600193 li gp,22 + 41c: 0bdf1263 bne t5,t4,4c0 + +00000420 : + 420: 00000213 li tp,0 + 424: 0f0f1137 lui sp,0xf0f1 + 428: f0f10113 addi sp,sp,-241 # f0f0f0f + 42c: 00000013 nop + 430: 00000013 nop + 434: 00ff00b7 lui ra,0xff0 + 438: 0ff08093 addi ra,ra,255 # ff00ff + 43c: 0020ff33 and t5,ra,sp + 440: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 444: 00200293 li t0,2 + 448: fc521ee3 bne tp,t0,424 + 44c: 000f0eb7 lui t4,0xf0 + 450: 00fe8e93 addi t4,t4,15 # f000f + 454: 01700193 li gp,23 + 458: 07df1463 bne t5,t4,4c0 + +0000045c : + 45c: ff0100b7 lui ra,0xff010 + 460: f0008093 addi ra,ra,-256 # ff00ff00 + 464: 00107133 and sp,zero,ra + 468: 00000e93 li t4,0 + 46c: 01800193 li gp,24 + 470: 05d11863 bne sp,t4,4c0 + +00000474 : + 474: 00ff00b7 lui ra,0xff0 + 478: 0ff08093 addi ra,ra,255 # ff00ff + 47c: 0000f133 and sp,ra,zero + 480: 00000e93 li t4,0 + 484: 01900193 li gp,25 + 488: 03d11c63 bne sp,t4,4c0 + +0000048c : + 48c: 000070b3 and ra,zero,zero + 490: 00000e93 li t4,0 + 494: 01a00193 li gp,26 + 498: 03d09463 bne ra,t4,4c0 + +0000049c : + 49c: 111110b7 lui ra,0x11111 + 4a0: 11108093 addi ra,ra,273 # 11111111 + 4a4: 22222137 lui sp,0x22222 + 4a8: 22210113 addi sp,sp,546 # 22222222 + 4ac: 0020f033 and zero,ra,sp + 4b0: 00000e93 li t4,0 + 4b4: 01b00193 li gp,27 + 4b8: 01d01463 bne zero,t4,4c0 + 4bc: 00301863 bne zero,gp,4cc + +000004c0 : + 4c0: 00100d13 li s10,1 + 4c4: 00000d93 li s11,0 + +000004c8 : + 4c8: 0000006f j 4c8 + +000004cc : + 4cc: 00100d13 li s10,1 + 4d0: 00100d93 li s11,1 + +000004d4 : + 4d4: 0000006f j 4d4 + ... + +Disassembly of section .tohost: + +00000540 : + ... + +00000580 : + ... diff --git a/tests/isa/generated/rv32ui-p-and.verilog b/tests/isa/generated/rv32ui-p-and.verilog new file mode 100644 index 0000000..ac432d4 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-and.verilog @@ -0,0 +1,88 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 00 01 FF 93 80 00 F0 +37 11 0F 0F 13 01 F1 F0 33 FF 20 00 B7 1E 00 0F +93 8E 0E F0 93 01 20 00 63 1C DF 49 B7 10 F0 0F +93 80 00 FF 37 F1 F0 F0 13 01 01 0F 33 FF 20 00 +B7 0E F0 00 93 8E 0E 0F 93 01 30 00 63 1A DF 47 +B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 +33 FF 20 00 B7 0E 0F 00 93 8E FE 00 93 01 40 00 +63 18 DF 45 B7 F0 0F F0 93 80 F0 00 37 F1 F0 F0 +13 01 01 0F 33 FF 20 00 B7 FE 00 F0 93 01 50 00 +63 18 DF 43 B7 00 01 FF 93 80 00 F0 37 11 0F 0F +13 01 F1 F0 B3 F0 20 00 B7 1E 00 0F 93 8E 0E F0 +93 01 60 00 63 96 D0 41 B7 10 F0 0F 93 80 00 FF +37 F1 F0 F0 13 01 01 0F 33 F1 20 00 B7 0E F0 00 +93 8E 0E 0F 93 01 70 00 63 14 D1 3F B7 00 01 FF +93 80 00 F0 B3 F0 10 00 B7 0E 01 FF 93 8E 0E F0 +93 01 80 00 63 96 D0 3D 13 02 00 00 B7 00 01 FF +93 80 00 F0 37 11 0F 0F 13 01 F1 F0 33 FF 20 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE +B7 1E 00 0F 93 8E 0E F0 93 01 90 00 63 1A D3 39 +13 02 00 00 B7 10 F0 0F 93 80 00 FF 37 F1 F0 F0 +13 01 01 0F 33 FF 20 00 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 1E 52 FC B7 0E F0 00 +93 8E 0E 0F 93 01 A0 00 63 1C D3 35 13 02 00 00 +B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 +33 FF 20 00 13 00 00 00 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 1C 52 FC B7 0E 0F 00 +93 8E FE 00 93 01 B0 00 63 1C D3 31 13 02 00 00 +B7 00 01 FF 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 +33 FF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +B7 1E 00 0F 93 8E 0E F0 93 01 C0 00 63 12 DF 2F +13 02 00 00 B7 10 F0 0F 93 80 00 FF 37 F1 F0 F0 +13 01 01 0F 13 00 00 00 33 FF 20 00 13 02 12 00 +93 02 20 00 E3 10 52 FE B7 0E F0 00 93 8E 0E 0F +93 01 D0 00 63 16 DF 2B 13 02 00 00 B7 00 FF 00 +93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 13 00 00 00 +13 00 00 00 33 FF 20 00 13 02 12 00 93 02 20 00 +E3 1E 52 FC B7 0E 0F 00 93 8E FE 00 93 01 E0 00 +63 18 DF 27 13 02 00 00 B7 00 01 FF 93 80 00 F0 +13 00 00 00 37 11 0F 0F 13 01 F1 F0 33 FF 20 00 +13 02 12 00 93 02 20 00 E3 10 52 FE B7 1E 00 0F +93 8E 0E F0 93 01 F0 00 63 1C DF 23 13 02 00 00 +B7 10 F0 0F 93 80 00 FF 13 00 00 00 37 F1 F0 F0 +13 01 01 0F 13 00 00 00 33 FF 20 00 13 02 12 00 +93 02 20 00 E3 1E 52 FC B7 0E F0 00 93 8E 0E 0F +93 01 00 01 63 1E DF 1F 13 02 00 00 B7 00 FF 00 +93 80 F0 0F 13 00 00 00 13 00 00 00 37 11 0F 0F +13 01 F1 F0 33 FF 20 00 13 02 12 00 93 02 20 00 +E3 1E 52 FC B7 0E 0F 00 93 8E FE 00 93 01 10 01 +63 10 DF 1D 13 02 00 00 37 11 0F 0F 13 01 F1 F0 +B7 00 01 FF 93 80 00 F0 33 FF 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE B7 1E 00 0F 93 8E 0E F0 +93 01 20 01 63 16 DF 19 13 02 00 00 37 F1 F0 F0 +13 01 01 0F B7 10 F0 0F 93 80 00 FF 13 00 00 00 +33 FF 20 00 13 02 12 00 93 02 20 00 E3 10 52 FE +B7 0E F0 00 93 8E 0E 0F 93 01 30 01 63 1A DF 15 +13 02 00 00 37 11 0F 0F 13 01 F1 F0 B7 00 FF 00 +93 80 F0 0F 13 00 00 00 13 00 00 00 33 FF 20 00 +13 02 12 00 93 02 20 00 E3 1E 52 FC B7 0E 0F 00 +93 8E FE 00 93 01 40 01 63 1C DF 11 13 02 00 00 +37 11 0F 0F 13 01 F1 F0 13 00 00 00 B7 00 01 FF +93 80 00 F0 33 FF 20 00 13 02 12 00 93 02 20 00 +E3 10 52 FE B7 1E 00 0F 93 8E 0E F0 93 01 50 01 +63 10 DF 0F 13 02 00 00 37 F1 F0 F0 13 01 01 0F +13 00 00 00 B7 10 F0 0F 93 80 00 FF 13 00 00 00 +33 FF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC +B7 0E F0 00 93 8E 0E 0F 93 01 60 01 63 12 DF 0B +13 02 00 00 37 11 0F 0F 13 01 F1 F0 13 00 00 00 +13 00 00 00 B7 00 FF 00 93 80 F0 0F 33 FF 20 00 +13 02 12 00 93 02 20 00 E3 1E 52 FC B7 0E 0F 00 +93 8E FE 00 93 01 70 01 63 14 DF 07 B7 00 01 FF +93 80 00 F0 33 71 10 00 93 0E 00 00 93 01 80 01 +63 18 D1 05 B7 00 FF 00 93 80 F0 0F 33 F1 00 00 +93 0E 00 00 93 01 90 01 63 1C D1 03 B3 70 00 00 +93 0E 00 00 93 01 A0 01 63 94 D0 03 B7 10 11 11 +93 80 10 11 37 21 22 22 13 01 21 22 33 F0 20 00 +93 0E 00 00 93 01 B0 01 63 14 D0 01 63 18 30 00 +13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00 +93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000540 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-andi b/tests/isa/generated/rv32ui-p-andi new file mode 100644 index 0000000..31c181d Binary files /dev/null and b/tests/isa/generated/rv32ui-p-andi differ diff --git a/tests/isa/generated/rv32ui-p-andi.bin b/tests/isa/generated/rv32ui-p-andi.bin new file mode 100644 index 0000000..615827f Binary files /dev/null and b/tests/isa/generated/rv32ui-p-andi.bin differ diff --git a/tests/isa/generated/rv32ui-p-andi.dump b/tests/isa/generated/rv32ui-p-andi.dump new file mode 100644 index 0000000..7d5de3a --- /dev/null +++ b/tests/isa/generated/rv32ui-p-andi.dump @@ -0,0 +1,170 @@ + +generated/rv32ui-p-andi: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: ff0100b7 lui ra,0xff010 + c: f0008093 addi ra,ra,-256 # ff00ff00 + 10: f0f0ff13 andi t5,ra,-241 + 14: ff010eb7 lui t4,0xff010 + 18: f00e8e93 addi t4,t4,-256 # ff00ff00 + 1c: 00200193 li gp,2 + 20: 1bdf1463 bne t5,t4,1c8 + +00000024 : + 24: 0ff010b7 lui ra,0xff01 + 28: ff008093 addi ra,ra,-16 # ff00ff0 + 2c: 0f00ff13 andi t5,ra,240 + 30: 0f000e93 li t4,240 + 34: 00300193 li gp,3 + 38: 19df1863 bne t5,t4,1c8 + +0000003c : + 3c: 00ff00b7 lui ra,0xff0 + 40: 0ff08093 addi ra,ra,255 # ff00ff + 44: 70f0ff13 andi t5,ra,1807 + 48: 00f00e93 li t4,15 + 4c: 00400193 li gp,4 + 50: 17df1c63 bne t5,t4,1c8 + +00000054 : + 54: f00ff0b7 lui ra,0xf00ff + 58: 00f08093 addi ra,ra,15 # f00ff00f + 5c: 0f00ff13 andi t5,ra,240 + 60: 00000e93 li t4,0 + 64: 00500193 li gp,5 + 68: 17df1063 bne t5,t4,1c8 + +0000006c : + 6c: ff0100b7 lui ra,0xff010 + 70: f0008093 addi ra,ra,-256 # ff00ff00 + 74: 0f00f093 andi ra,ra,240 + 78: 00000e93 li t4,0 + 7c: 00600193 li gp,6 + 80: 15d09463 bne ra,t4,1c8 + +00000084 : + 84: 00000213 li tp,0 + 88: 0ff010b7 lui ra,0xff01 + 8c: ff008093 addi ra,ra,-16 # ff00ff0 + 90: 70f0ff13 andi t5,ra,1807 + 94: 000f0313 mv t1,t5 + 98: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 9c: 00200293 li t0,2 + a0: fe5214e3 bne tp,t0,88 + a4: 70000e93 li t4,1792 + a8: 00700193 li gp,7 + ac: 11d31e63 bne t1,t4,1c8 + +000000b0 : + b0: 00000213 li tp,0 + b4: 00ff00b7 lui ra,0xff0 + b8: 0ff08093 addi ra,ra,255 # ff00ff + bc: 0f00ff13 andi t5,ra,240 + c0: 00000013 nop + c4: 000f0313 mv t1,t5 + c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + cc: 00200293 li t0,2 + d0: fe5212e3 bne tp,t0,b4 + d4: 0f000e93 li t4,240 + d8: 00800193 li gp,8 + dc: 0fd31663 bne t1,t4,1c8 + +000000e0 : + e0: 00000213 li tp,0 + e4: f00ff0b7 lui ra,0xf00ff + e8: 00f08093 addi ra,ra,15 # f00ff00f + ec: f0f0ff13 andi t5,ra,-241 + f0: 00000013 nop + f4: 00000013 nop + f8: 000f0313 mv t1,t5 + fc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 100: 00200293 li t0,2 + 104: fe5210e3 bne tp,t0,e4 + 108: f00ffeb7 lui t4,0xf00ff + 10c: 00fe8e93 addi t4,t4,15 # f00ff00f + 110: 00900193 li gp,9 + 114: 0bd31a63 bne t1,t4,1c8 + +00000118 : + 118: 00000213 li tp,0 + 11c: 0ff010b7 lui ra,0xff01 + 120: ff008093 addi ra,ra,-16 # ff00ff0 + 124: 70f0ff13 andi t5,ra,1807 + 128: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 12c: 00200293 li t0,2 + 130: fe5216e3 bne tp,t0,11c + 134: 70000e93 li t4,1792 + 138: 00a00193 li gp,10 + 13c: 09df1663 bne t5,t4,1c8 + +00000140 : + 140: 00000213 li tp,0 + 144: 00ff00b7 lui ra,0xff0 + 148: 0ff08093 addi ra,ra,255 # ff00ff + 14c: 00000013 nop + 150: 0f00ff13 andi t5,ra,240 + 154: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 158: 00200293 li t0,2 + 15c: fe5214e3 bne tp,t0,144 + 160: 0f000e93 li t4,240 + 164: 00b00193 li gp,11 + 168: 07df1063 bne t5,t4,1c8 + +0000016c : + 16c: 00000213 li tp,0 + 170: f00ff0b7 lui ra,0xf00ff + 174: 00f08093 addi ra,ra,15 # f00ff00f + 178: 00000013 nop + 17c: 00000013 nop + 180: 70f0ff13 andi t5,ra,1807 + 184: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 188: 00200293 li t0,2 + 18c: fe5212e3 bne tp,t0,170 + 190: 00f00e93 li t4,15 + 194: 00c00193 li gp,12 + 198: 03df1863 bne t5,t4,1c8 + +0000019c : + 19c: 0f007093 andi ra,zero,240 + 1a0: 00000e93 li t4,0 + 1a4: 00d00193 li gp,13 + 1a8: 03d09063 bne ra,t4,1c8 + +000001ac : + 1ac: 00ff00b7 lui ra,0xff0 + 1b0: 0ff08093 addi ra,ra,255 # ff00ff + 1b4: 70f0f013 andi zero,ra,1807 + 1b8: 00000e93 li t4,0 + 1bc: 00e00193 li gp,14 + 1c0: 01d01463 bne zero,t4,1c8 + 1c4: 00301863 bne zero,gp,1d4 + +000001c8 : + 1c8: 00100d13 li s10,1 + 1cc: 00000d93 li s11,0 + +000001d0 : + 1d0: 0000006f j 1d0 + +000001d4 : + 1d4: 00100d13 li s10,1 + 1d8: 00100d93 li s11,1 + +000001dc : + 1dc: 0000006f j 1dc + ... + +Disassembly of section .tohost: + +00000240 : + ... + +00000280 : + ... diff --git a/tests/isa/generated/rv32ui-p-andi.verilog b/tests/isa/generated/rv32ui-p-andi.verilog new file mode 100644 index 0000000..6da253e --- /dev/null +++ b/tests/isa/generated/rv32ui-p-andi.verilog @@ -0,0 +1,40 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 00 01 FF 93 80 00 F0 +13 FF F0 F0 B7 0E 01 FF 93 8E 0E F0 93 01 20 00 +63 14 DF 1B B7 10 F0 0F 93 80 00 FF 13 FF 00 0F +93 0E 00 0F 93 01 30 00 63 18 DF 19 B7 00 FF 00 +93 80 F0 0F 13 FF F0 70 93 0E F0 00 93 01 40 00 +63 1C DF 17 B7 F0 0F F0 93 80 F0 00 13 FF 00 0F +93 0E 00 00 93 01 50 00 63 10 DF 17 B7 00 01 FF +93 80 00 F0 93 F0 00 0F 93 0E 00 00 93 01 60 00 +63 94 D0 15 13 02 00 00 B7 10 F0 0F 93 80 00 FF +13 FF F0 70 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 00 70 93 01 70 00 63 1E D3 11 +13 02 00 00 B7 00 FF 00 93 80 F0 0F 13 FF 00 0F +13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E 00 0F 93 01 80 00 63 16 D3 0F +13 02 00 00 B7 F0 0F F0 93 80 F0 00 13 FF F0 F0 +13 00 00 00 13 00 00 00 13 03 0F 00 13 02 12 00 +93 02 20 00 E3 10 52 FE B7 FE 0F F0 93 8E FE 00 +93 01 90 00 63 1A D3 0B 13 02 00 00 B7 10 F0 0F +93 80 00 FF 13 FF F0 70 13 02 12 00 93 02 20 00 +E3 16 52 FE 93 0E 00 70 93 01 A0 00 63 16 DF 09 +13 02 00 00 B7 00 FF 00 93 80 F0 0F 13 00 00 00 +13 FF 00 0F 13 02 12 00 93 02 20 00 E3 14 52 FE +93 0E 00 0F 93 01 B0 00 63 10 DF 07 13 02 00 00 +B7 F0 0F F0 93 80 F0 00 13 00 00 00 13 00 00 00 +13 FF F0 70 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E F0 00 93 01 C0 00 63 18 DF 03 93 70 00 0F +93 0E 00 00 93 01 D0 00 63 90 D0 03 B7 00 FF 00 +93 80 F0 0F 13 F0 F0 70 93 0E 00 00 93 01 E0 00 +63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000240 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-auipc b/tests/isa/generated/rv32ui-p-auipc new file mode 100644 index 0000000..ecdc68f Binary files /dev/null and b/tests/isa/generated/rv32ui-p-auipc differ diff --git a/tests/isa/generated/rv32ui-p-auipc.bin b/tests/isa/generated/rv32ui-p-auipc.bin new file mode 100644 index 0000000..10fa629 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-auipc.bin differ diff --git a/tests/isa/generated/rv32ui-p-auipc.dump b/tests/isa/generated/rv32ui-p-auipc.dump new file mode 100644 index 0000000..3789517 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-auipc.dump @@ -0,0 +1,53 @@ + +generated/rv32ui-p-auipc: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00002517 auipc a0,0x2 + c: 71c50513 addi a0,a0,1820 # 2724 + 10: 004005ef jal a1,14 + 14: 40b50533 sub a0,a0,a1 + 18: 00002eb7 lui t4,0x2 + 1c: 710e8e93 addi t4,t4,1808 # 2710 + 20: 00200193 li gp,2 + 24: 03d51463 bne a0,t4,4c + +00000028 : + 28: ffffe517 auipc a0,0xffffe + 2c: 8fc50513 addi a0,a0,-1796 # ffffd924 + 30: 004005ef jal a1,34 + 34: 40b50533 sub a0,a0,a1 + 38: ffffeeb7 lui t4,0xffffe + 3c: 8f0e8e93 addi t4,t4,-1808 # ffffd8f0 + 40: 00300193 li gp,3 + 44: 01d51463 bne a0,t4,4c + 48: 00301863 bne zero,gp,58 + +0000004c : + 4c: 00100d13 li s10,1 + 50: 00000d93 li s11,0 + +00000054 : + 54: 0000006f j 54 + +00000058 : + 58: 00100d13 li s10,1 + 5c: 00100d93 li s11,1 + +00000060 : + 60: 0000006f j 60 + ... + +Disassembly of section .tohost: + +00000080 : + ... + +000000c0 : + ... diff --git a/tests/isa/generated/rv32ui-p-auipc.verilog b/tests/isa/generated/rv32ui-p-auipc.verilog new file mode 100644 index 0000000..240076c --- /dev/null +++ b/tests/isa/generated/rv32ui-p-auipc.verilog @@ -0,0 +1,15 @@ +@00000000 +13 0D 00 00 93 0D 00 00 17 25 00 00 13 05 C5 71 +EF 05 40 00 33 05 B5 40 B7 2E 00 00 93 8E 0E 71 +93 01 20 00 63 14 D5 03 17 E5 FF FF 13 05 C5 8F +EF 05 40 00 33 05 B5 40 B7 EE FF FF 93 8E 0E 8F +93 01 30 00 63 14 D5 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 +@00000080 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-beq b/tests/isa/generated/rv32ui-p-beq new file mode 100644 index 0000000..24d5466 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-beq differ diff --git a/tests/isa/generated/rv32ui-p-beq.bin b/tests/isa/generated/rv32ui-p-beq.bin new file mode 100644 index 0000000..68b5c51 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-beq.bin differ diff --git a/tests/isa/generated/rv32ui-p-beq.dump b/tests/isa/generated/rv32ui-p-beq.dump new file mode 100644 index 0000000..9a5b7cc --- /dev/null +++ b/tests/isa/generated/rv32ui-p-beq.dump @@ -0,0 +1,248 @@ + +generated/rv32ui-p-beq: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00200193 li gp,2 + c: 00000093 li ra,0 + 10: 00000113 li sp,0 + 14: 00208663 beq ra,sp,20 + 18: 2a301863 bne zero,gp,2c8 + 1c: 00301663 bne zero,gp,28 + 20: fe208ee3 beq ra,sp,1c + 24: 2a301263 bne zero,gp,2c8 + +00000028 : + 28: 00300193 li gp,3 + 2c: 00100093 li ra,1 + 30: 00100113 li sp,1 + 34: 00208663 beq ra,sp,40 + 38: 28301863 bne zero,gp,2c8 + 3c: 00301663 bne zero,gp,48 + 40: fe208ee3 beq ra,sp,3c + 44: 28301263 bne zero,gp,2c8 + +00000048 : + 48: 00400193 li gp,4 + 4c: fff00093 li ra,-1 + 50: fff00113 li sp,-1 + 54: 00208663 beq ra,sp,60 + 58: 26301863 bne zero,gp,2c8 + 5c: 00301663 bne zero,gp,68 + 60: fe208ee3 beq ra,sp,5c + 64: 26301263 bne zero,gp,2c8 + +00000068 : + 68: 00500193 li gp,5 + 6c: 00000093 li ra,0 + 70: 00100113 li sp,1 + 74: 00208463 beq ra,sp,7c + 78: 00301463 bne zero,gp,80 + 7c: 24301663 bne zero,gp,2c8 + 80: fe208ee3 beq ra,sp,7c + +00000084 : + 84: 00600193 li gp,6 + 88: 00100093 li ra,1 + 8c: 00000113 li sp,0 + 90: 00208463 beq ra,sp,98 + 94: 00301463 bne zero,gp,9c + 98: 22301863 bne zero,gp,2c8 + 9c: fe208ee3 beq ra,sp,98 + +000000a0 : + a0: 00700193 li gp,7 + a4: fff00093 li ra,-1 + a8: 00100113 li sp,1 + ac: 00208463 beq ra,sp,b4 + b0: 00301463 bne zero,gp,b8 + b4: 20301a63 bne zero,gp,2c8 + b8: fe208ee3 beq ra,sp,b4 + +000000bc : + bc: 00800193 li gp,8 + c0: 00100093 li ra,1 + c4: fff00113 li sp,-1 + c8: 00208463 beq ra,sp,d0 + cc: 00301463 bne zero,gp,d4 + d0: 1e301c63 bne zero,gp,2c8 + d4: fe208ee3 beq ra,sp,d0 + +000000d8 : + d8: 00900193 li gp,9 + dc: 00000213 li tp,0 + e0: 00000093 li ra,0 + e4: fff00113 li sp,-1 + e8: 1e208063 beq ra,sp,2c8 + ec: 00120213 addi tp,tp,1 # 1 <_start+0x1> + f0: 00200293 li t0,2 + f4: fe5216e3 bne tp,t0,e0 + +000000f8 : + f8: 00a00193 li gp,10 + fc: 00000213 li tp,0 + 100: 00000093 li ra,0 + 104: fff00113 li sp,-1 + 108: 00000013 nop + 10c: 1a208e63 beq ra,sp,2c8 + 110: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 114: 00200293 li t0,2 + 118: fe5214e3 bne tp,t0,100 + +0000011c : + 11c: 00b00193 li gp,11 + 120: 00000213 li tp,0 + 124: 00000093 li ra,0 + 128: fff00113 li sp,-1 + 12c: 00000013 nop + 130: 00000013 nop + 134: 18208a63 beq ra,sp,2c8 + 138: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 13c: 00200293 li t0,2 + 140: fe5212e3 bne tp,t0,124 + +00000144 : + 144: 00c00193 li gp,12 + 148: 00000213 li tp,0 + 14c: 00000093 li ra,0 + 150: 00000013 nop + 154: fff00113 li sp,-1 + 158: 16208863 beq ra,sp,2c8 + 15c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 160: 00200293 li t0,2 + 164: fe5214e3 bne tp,t0,14c + +00000168 : + 168: 00d00193 li gp,13 + 16c: 00000213 li tp,0 + 170: 00000093 li ra,0 + 174: 00000013 nop + 178: fff00113 li sp,-1 + 17c: 00000013 nop + 180: 14208463 beq ra,sp,2c8 + 184: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 188: 00200293 li t0,2 + 18c: fe5212e3 bne tp,t0,170 + +00000190 : + 190: 00e00193 li gp,14 + 194: 00000213 li tp,0 + 198: 00000093 li ra,0 + 19c: 00000013 nop + 1a0: 00000013 nop + 1a4: fff00113 li sp,-1 + 1a8: 12208063 beq ra,sp,2c8 + 1ac: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1b0: 00200293 li t0,2 + 1b4: fe5212e3 bne tp,t0,198 + +000001b8 : + 1b8: 00f00193 li gp,15 + 1bc: 00000213 li tp,0 + 1c0: 00000093 li ra,0 + 1c4: fff00113 li sp,-1 + 1c8: 10208063 beq ra,sp,2c8 + 1cc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1d0: 00200293 li t0,2 + 1d4: fe5216e3 bne tp,t0,1c0 + +000001d8 : + 1d8: 01000193 li gp,16 + 1dc: 00000213 li tp,0 + 1e0: 00000093 li ra,0 + 1e4: fff00113 li sp,-1 + 1e8: 00000013 nop + 1ec: 0c208e63 beq ra,sp,2c8 + 1f0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1f4: 00200293 li t0,2 + 1f8: fe5214e3 bne tp,t0,1e0 + +000001fc : + 1fc: 01100193 li gp,17 + 200: 00000213 li tp,0 + 204: 00000093 li ra,0 + 208: fff00113 li sp,-1 + 20c: 00000013 nop + 210: 00000013 nop + 214: 0a208a63 beq ra,sp,2c8 + 218: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 21c: 00200293 li t0,2 + 220: fe5212e3 bne tp,t0,204 + +00000224 : + 224: 01200193 li gp,18 + 228: 00000213 li tp,0 + 22c: 00000093 li ra,0 + 230: 00000013 nop + 234: fff00113 li sp,-1 + 238: 08208863 beq ra,sp,2c8 + 23c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 240: 00200293 li t0,2 + 244: fe5214e3 bne tp,t0,22c + +00000248 : + 248: 01300193 li gp,19 + 24c: 00000213 li tp,0 + 250: 00000093 li ra,0 + 254: 00000013 nop + 258: fff00113 li sp,-1 + 25c: 00000013 nop + 260: 06208463 beq ra,sp,2c8 + 264: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 268: 00200293 li t0,2 + 26c: fe5212e3 bne tp,t0,250 + +00000270 : + 270: 01400193 li gp,20 + 274: 00000213 li tp,0 + 278: 00000093 li ra,0 + 27c: 00000013 nop + 280: 00000013 nop + 284: fff00113 li sp,-1 + 288: 04208063 beq ra,sp,2c8 + 28c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 290: 00200293 li t0,2 + 294: fe5212e3 bne tp,t0,278 + +00000298 : + 298: 00100093 li ra,1 + 29c: 00000a63 beqz zero,2b0 + 2a0: 00108093 addi ra,ra,1 + 2a4: 00108093 addi ra,ra,1 + 2a8: 00108093 addi ra,ra,1 + 2ac: 00108093 addi ra,ra,1 + 2b0: 00108093 addi ra,ra,1 + 2b4: 00108093 addi ra,ra,1 + 2b8: 00300e93 li t4,3 + 2bc: 01500193 li gp,21 + 2c0: 01d09463 bne ra,t4,2c8 + 2c4: 00301863 bne zero,gp,2d4 + +000002c8 : + 2c8: 00100d13 li s10,1 + 2cc: 00000d93 li s11,0 + +000002d0 : + 2d0: 0000006f j 2d0 + +000002d4 : + 2d4: 00100d13 li s10,1 + 2d8: 00100d93 li s11,1 + +000002dc : + 2dc: 0000006f j 2dc + ... + +Disassembly of section .tohost: + +00000340 : + ... + +00000380 : + ... diff --git a/tests/isa/generated/rv32ui-p-beq.verilog b/tests/isa/generated/rv32ui-p-beq.verilog new file mode 100644 index 0000000..dd5de24 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-beq.verilog @@ -0,0 +1,56 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 +13 01 00 00 63 86 20 00 63 18 30 2A 63 16 30 00 +E3 8E 20 FE 63 12 30 2A 93 01 30 00 93 00 10 00 +13 01 10 00 63 86 20 00 63 18 30 28 63 16 30 00 +E3 8E 20 FE 63 12 30 28 93 01 40 00 93 00 F0 FF +13 01 F0 FF 63 86 20 00 63 18 30 26 63 16 30 00 +E3 8E 20 FE 63 12 30 26 93 01 50 00 93 00 00 00 +13 01 10 00 63 84 20 00 63 14 30 00 63 16 30 24 +E3 8E 20 FE 93 01 60 00 93 00 10 00 13 01 00 00 +63 84 20 00 63 14 30 00 63 18 30 22 E3 8E 20 FE +93 01 70 00 93 00 F0 FF 13 01 10 00 63 84 20 00 +63 14 30 00 63 1A 30 20 E3 8E 20 FE 93 01 80 00 +93 00 10 00 13 01 F0 FF 63 84 20 00 63 14 30 00 +63 1C 30 1E E3 8E 20 FE 93 01 90 00 13 02 00 00 +93 00 00 00 13 01 F0 FF 63 80 20 1E 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 01 A0 00 13 02 00 00 +93 00 00 00 13 01 F0 FF 13 00 00 00 63 8E 20 1A +13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 B0 00 +13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 +13 00 00 00 63 8A 20 18 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 C0 00 13 02 00 00 93 00 00 00 +13 00 00 00 13 01 F0 FF 63 88 20 16 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 01 D0 00 13 02 00 00 +93 00 00 00 13 00 00 00 13 01 F0 FF 13 00 00 00 +63 84 20 14 13 02 12 00 93 02 20 00 E3 12 52 FE +93 01 E0 00 13 02 00 00 93 00 00 00 13 00 00 00 +13 00 00 00 13 01 F0 FF 63 80 20 12 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 F0 00 13 02 00 00 +93 00 00 00 13 01 F0 FF 63 80 20 10 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 01 00 01 13 02 00 00 +93 00 00 00 13 01 F0 FF 13 00 00 00 63 8E 20 0C +13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 10 01 +13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 +13 00 00 00 63 8A 20 0A 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 20 01 13 02 00 00 93 00 00 00 +13 00 00 00 13 01 F0 FF 63 88 20 08 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 01 30 01 13 02 00 00 +93 00 00 00 13 00 00 00 13 01 F0 FF 13 00 00 00 +63 84 20 06 13 02 12 00 93 02 20 00 E3 12 52 FE +93 01 40 01 13 02 00 00 93 00 00 00 13 00 00 00 +13 00 00 00 13 01 F0 FF 63 80 20 04 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 00 10 00 63 0A 00 00 +93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 +93 80 10 00 93 80 10 00 93 0E 30 00 93 01 50 01 +63 94 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000340 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-bge b/tests/isa/generated/rv32ui-p-bge new file mode 100644 index 0000000..15b96e5 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-bge differ diff --git a/tests/isa/generated/rv32ui-p-bge.bin b/tests/isa/generated/rv32ui-p-bge.bin new file mode 100644 index 0000000..4a173e5 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-bge.bin differ diff --git a/tests/isa/generated/rv32ui-p-bge.dump b/tests/isa/generated/rv32ui-p-bge.dump new file mode 100644 index 0000000..d41cd2f --- /dev/null +++ b/tests/isa/generated/rv32ui-p-bge.dump @@ -0,0 +1,279 @@ + +generated/rv32ui-p-bge: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00200193 li gp,2 + c: 00000093 li ra,0 + 10: 00000113 li sp,0 + 14: 0020d663 bge ra,sp,20 + 18: 30301863 bne zero,gp,328 + 1c: 00301663 bne zero,gp,28 + 20: fe20dee3 bge ra,sp,1c + 24: 30301263 bne zero,gp,328 + +00000028 : + 28: 00300193 li gp,3 + 2c: 00100093 li ra,1 + 30: 00100113 li sp,1 + 34: 0020d663 bge ra,sp,40 + 38: 2e301863 bne zero,gp,328 + 3c: 00301663 bne zero,gp,48 + 40: fe20dee3 bge ra,sp,3c + 44: 2e301263 bne zero,gp,328 + +00000048 : + 48: 00400193 li gp,4 + 4c: fff00093 li ra,-1 + 50: fff00113 li sp,-1 + 54: 0020d663 bge ra,sp,60 + 58: 2c301863 bne zero,gp,328 + 5c: 00301663 bne zero,gp,68 + 60: fe20dee3 bge ra,sp,5c + 64: 2c301263 bne zero,gp,328 + +00000068 : + 68: 00500193 li gp,5 + 6c: 00100093 li ra,1 + 70: 00000113 li sp,0 + 74: 0020d663 bge ra,sp,80 + 78: 2a301863 bne zero,gp,328 + 7c: 00301663 bne zero,gp,88 + 80: fe20dee3 bge ra,sp,7c + 84: 2a301263 bne zero,gp,328 + +00000088 : + 88: 00600193 li gp,6 + 8c: 00100093 li ra,1 + 90: fff00113 li sp,-1 + 94: 0020d663 bge ra,sp,a0 + 98: 28301863 bne zero,gp,328 + 9c: 00301663 bne zero,gp,a8 + a0: fe20dee3 bge ra,sp,9c + a4: 28301263 bne zero,gp,328 + +000000a8 : + a8: 00700193 li gp,7 + ac: fff00093 li ra,-1 + b0: ffe00113 li sp,-2 + b4: 0020d663 bge ra,sp,c0 + b8: 26301863 bne zero,gp,328 + bc: 00301663 bne zero,gp,c8 + c0: fe20dee3 bge ra,sp,bc + c4: 26301263 bne zero,gp,328 + +000000c8 : + c8: 00800193 li gp,8 + cc: 00000093 li ra,0 + d0: 00100113 li sp,1 + d4: 0020d463 bge ra,sp,dc + d8: 00301463 bne zero,gp,e0 + dc: 24301663 bne zero,gp,328 + e0: fe20dee3 bge ra,sp,dc + +000000e4 : + e4: 00900193 li gp,9 + e8: fff00093 li ra,-1 + ec: 00100113 li sp,1 + f0: 0020d463 bge ra,sp,f8 + f4: 00301463 bne zero,gp,fc + f8: 22301863 bne zero,gp,328 + fc: fe20dee3 bge ra,sp,f8 + +00000100 : + 100: 00a00193 li gp,10 + 104: ffe00093 li ra,-2 + 108: fff00113 li sp,-1 + 10c: 0020d463 bge ra,sp,114 + 110: 00301463 bne zero,gp,118 + 114: 20301a63 bne zero,gp,328 + 118: fe20dee3 bge ra,sp,114 + +0000011c : + 11c: 00b00193 li gp,11 + 120: ffe00093 li ra,-2 + 124: 00100113 li sp,1 + 128: 0020d463 bge ra,sp,130 + 12c: 00301463 bne zero,gp,134 + 130: 1e301c63 bne zero,gp,328 + 134: fe20dee3 bge ra,sp,130 + +00000138 : + 138: 00c00193 li gp,12 + 13c: 00000213 li tp,0 + 140: fff00093 li ra,-1 + 144: 00000113 li sp,0 + 148: 1e20d063 bge ra,sp,328 + 14c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 150: 00200293 li t0,2 + 154: fe5216e3 bne tp,t0,140 + +00000158 : + 158: 00d00193 li gp,13 + 15c: 00000213 li tp,0 + 160: fff00093 li ra,-1 + 164: 00000113 li sp,0 + 168: 00000013 nop + 16c: 1a20de63 bge ra,sp,328 + 170: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 174: 00200293 li t0,2 + 178: fe5214e3 bne tp,t0,160 + +0000017c : + 17c: 00e00193 li gp,14 + 180: 00000213 li tp,0 + 184: fff00093 li ra,-1 + 188: 00000113 li sp,0 + 18c: 00000013 nop + 190: 00000013 nop + 194: 1820da63 bge ra,sp,328 + 198: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 19c: 00200293 li t0,2 + 1a0: fe5212e3 bne tp,t0,184 + +000001a4 : + 1a4: 00f00193 li gp,15 + 1a8: 00000213 li tp,0 + 1ac: fff00093 li ra,-1 + 1b0: 00000013 nop + 1b4: 00000113 li sp,0 + 1b8: 1620d863 bge ra,sp,328 + 1bc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1c0: 00200293 li t0,2 + 1c4: fe5214e3 bne tp,t0,1ac + +000001c8 : + 1c8: 01000193 li gp,16 + 1cc: 00000213 li tp,0 + 1d0: fff00093 li ra,-1 + 1d4: 00000013 nop + 1d8: 00000113 li sp,0 + 1dc: 00000013 nop + 1e0: 1420d463 bge ra,sp,328 + 1e4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1e8: 00200293 li t0,2 + 1ec: fe5212e3 bne tp,t0,1d0 + +000001f0 : + 1f0: 01100193 li gp,17 + 1f4: 00000213 li tp,0 + 1f8: fff00093 li ra,-1 + 1fc: 00000013 nop + 200: 00000013 nop + 204: 00000113 li sp,0 + 208: 1220d063 bge ra,sp,328 + 20c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 210: 00200293 li t0,2 + 214: fe5212e3 bne tp,t0,1f8 + +00000218 : + 218: 01200193 li gp,18 + 21c: 00000213 li tp,0 + 220: fff00093 li ra,-1 + 224: 00000113 li sp,0 + 228: 1020d063 bge ra,sp,328 + 22c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 230: 00200293 li t0,2 + 234: fe5216e3 bne tp,t0,220 + +00000238 : + 238: 01300193 li gp,19 + 23c: 00000213 li tp,0 + 240: fff00093 li ra,-1 + 244: 00000113 li sp,0 + 248: 00000013 nop + 24c: 0c20de63 bge ra,sp,328 + 250: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 254: 00200293 li t0,2 + 258: fe5214e3 bne tp,t0,240 + +0000025c : + 25c: 01400193 li gp,20 + 260: 00000213 li tp,0 + 264: fff00093 li ra,-1 + 268: 00000113 li sp,0 + 26c: 00000013 nop + 270: 00000013 nop + 274: 0a20da63 bge ra,sp,328 + 278: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 27c: 00200293 li t0,2 + 280: fe5212e3 bne tp,t0,264 + +00000284 : + 284: 01500193 li gp,21 + 288: 00000213 li tp,0 + 28c: fff00093 li ra,-1 + 290: 00000013 nop + 294: 00000113 li sp,0 + 298: 0820d863 bge ra,sp,328 + 29c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2a0: 00200293 li t0,2 + 2a4: fe5214e3 bne tp,t0,28c + +000002a8 : + 2a8: 01600193 li gp,22 + 2ac: 00000213 li tp,0 + 2b0: fff00093 li ra,-1 + 2b4: 00000013 nop + 2b8: 00000113 li sp,0 + 2bc: 00000013 nop + 2c0: 0620d463 bge ra,sp,328 + 2c4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2c8: 00200293 li t0,2 + 2cc: fe5212e3 bne tp,t0,2b0 + +000002d0 : + 2d0: 01700193 li gp,23 + 2d4: 00000213 li tp,0 + 2d8: fff00093 li ra,-1 + 2dc: 00000013 nop + 2e0: 00000013 nop + 2e4: 00000113 li sp,0 + 2e8: 0420d063 bge ra,sp,328 + 2ec: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2f0: 00200293 li t0,2 + 2f4: fe5212e3 bne tp,t0,2d8 + +000002f8 : + 2f8: 00100093 li ra,1 + 2fc: 0000da63 bgez ra,310 + 300: 00108093 addi ra,ra,1 + 304: 00108093 addi ra,ra,1 + 308: 00108093 addi ra,ra,1 + 30c: 00108093 addi ra,ra,1 + 310: 00108093 addi ra,ra,1 + 314: 00108093 addi ra,ra,1 + 318: 00300e93 li t4,3 + 31c: 01800193 li gp,24 + 320: 01d09463 bne ra,t4,328 + 324: 00301863 bne zero,gp,334 + +00000328 : + 328: 00100d13 li s10,1 + 32c: 00000d93 li s11,0 + +00000330 : + 330: 0000006f j 330 + +00000334 : + 334: 00100d13 li s10,1 + 338: 00100d93 li s11,1 + +0000033c : + 33c: 0000006f j 33c + 340: 0000 unimp + ... + +Disassembly of section .tohost: + +00000380 : + ... + +000003c0 : + ... diff --git a/tests/isa/generated/rv32ui-p-bge.verilog b/tests/isa/generated/rv32ui-p-bge.verilog new file mode 100644 index 0000000..2df6e9b --- /dev/null +++ b/tests/isa/generated/rv32ui-p-bge.verilog @@ -0,0 +1,60 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 +13 01 00 00 63 D6 20 00 63 18 30 30 63 16 30 00 +E3 DE 20 FE 63 12 30 30 93 01 30 00 93 00 10 00 +13 01 10 00 63 D6 20 00 63 18 30 2E 63 16 30 00 +E3 DE 20 FE 63 12 30 2E 93 01 40 00 93 00 F0 FF +13 01 F0 FF 63 D6 20 00 63 18 30 2C 63 16 30 00 +E3 DE 20 FE 63 12 30 2C 93 01 50 00 93 00 10 00 +13 01 00 00 63 D6 20 00 63 18 30 2A 63 16 30 00 +E3 DE 20 FE 63 12 30 2A 93 01 60 00 93 00 10 00 +13 01 F0 FF 63 D6 20 00 63 18 30 28 63 16 30 00 +E3 DE 20 FE 63 12 30 28 93 01 70 00 93 00 F0 FF +13 01 E0 FF 63 D6 20 00 63 18 30 26 63 16 30 00 +E3 DE 20 FE 63 12 30 26 93 01 80 00 93 00 00 00 +13 01 10 00 63 D4 20 00 63 14 30 00 63 16 30 24 +E3 DE 20 FE 93 01 90 00 93 00 F0 FF 13 01 10 00 +63 D4 20 00 63 14 30 00 63 18 30 22 E3 DE 20 FE +93 01 A0 00 93 00 E0 FF 13 01 F0 FF 63 D4 20 00 +63 14 30 00 63 1A 30 20 E3 DE 20 FE 93 01 B0 00 +93 00 E0 FF 13 01 10 00 63 D4 20 00 63 14 30 00 +63 1C 30 1E E3 DE 20 FE 93 01 C0 00 13 02 00 00 +93 00 F0 FF 13 01 00 00 63 D0 20 1E 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 01 D0 00 13 02 00 00 +93 00 F0 FF 13 01 00 00 13 00 00 00 63 DE 20 1A +13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 E0 00 +13 02 00 00 93 00 F0 FF 13 01 00 00 13 00 00 00 +13 00 00 00 63 DA 20 18 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 F0 00 13 02 00 00 93 00 F0 FF +13 00 00 00 13 01 00 00 63 D8 20 16 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 01 00 01 13 02 00 00 +93 00 F0 FF 13 00 00 00 13 01 00 00 13 00 00 00 +63 D4 20 14 13 02 12 00 93 02 20 00 E3 12 52 FE +93 01 10 01 13 02 00 00 93 00 F0 FF 13 00 00 00 +13 00 00 00 13 01 00 00 63 D0 20 12 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 20 01 13 02 00 00 +93 00 F0 FF 13 01 00 00 63 D0 20 10 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 01 30 01 13 02 00 00 +93 00 F0 FF 13 01 00 00 13 00 00 00 63 DE 20 0C +13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 40 01 +13 02 00 00 93 00 F0 FF 13 01 00 00 13 00 00 00 +13 00 00 00 63 DA 20 0A 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 50 01 13 02 00 00 93 00 F0 FF +13 00 00 00 13 01 00 00 63 D8 20 08 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 01 60 01 13 02 00 00 +93 00 F0 FF 13 00 00 00 13 01 00 00 13 00 00 00 +63 D4 20 06 13 02 12 00 93 02 20 00 E3 12 52 FE +93 01 70 01 13 02 00 00 93 00 F0 FF 13 00 00 00 +13 00 00 00 13 01 00 00 63 D0 20 04 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 00 10 00 63 DA 00 00 +93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 +93 80 10 00 93 80 10 00 93 0E 30 00 93 01 80 01 +63 94 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 +@00000380 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-bgeu b/tests/isa/generated/rv32ui-p-bgeu new file mode 100644 index 0000000..54c978d Binary files /dev/null and b/tests/isa/generated/rv32ui-p-bgeu differ diff --git a/tests/isa/generated/rv32ui-p-bgeu.bin b/tests/isa/generated/rv32ui-p-bgeu.bin new file mode 100644 index 0000000..de52b58 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-bgeu.bin differ diff --git a/tests/isa/generated/rv32ui-p-bgeu.dump b/tests/isa/generated/rv32ui-p-bgeu.dump new file mode 100644 index 0000000..8f15f29 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-bgeu.dump @@ -0,0 +1,291 @@ + +generated/rv32ui-p-bgeu: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00200193 li gp,2 + c: 00000093 li ra,0 + 10: 00000113 li sp,0 + 14: 0020f663 bgeu ra,sp,20 + 18: 34301263 bne zero,gp,35c + 1c: 00301663 bne zero,gp,28 + 20: fe20fee3 bgeu ra,sp,1c + 24: 32301c63 bne zero,gp,35c + +00000028 : + 28: 00300193 li gp,3 + 2c: 00100093 li ra,1 + 30: 00100113 li sp,1 + 34: 0020f663 bgeu ra,sp,40 + 38: 32301263 bne zero,gp,35c + 3c: 00301663 bne zero,gp,48 + 40: fe20fee3 bgeu ra,sp,3c + 44: 30301c63 bne zero,gp,35c + +00000048 : + 48: 00400193 li gp,4 + 4c: fff00093 li ra,-1 + 50: fff00113 li sp,-1 + 54: 0020f663 bgeu ra,sp,60 + 58: 30301263 bne zero,gp,35c + 5c: 00301663 bne zero,gp,68 + 60: fe20fee3 bgeu ra,sp,5c + 64: 2e301c63 bne zero,gp,35c + +00000068 : + 68: 00500193 li gp,5 + 6c: 00100093 li ra,1 + 70: 00000113 li sp,0 + 74: 0020f663 bgeu ra,sp,80 + 78: 2e301263 bne zero,gp,35c + 7c: 00301663 bne zero,gp,88 + 80: fe20fee3 bgeu ra,sp,7c + 84: 2c301c63 bne zero,gp,35c + +00000088 : + 88: 00600193 li gp,6 + 8c: fff00093 li ra,-1 + 90: ffe00113 li sp,-2 + 94: 0020f663 bgeu ra,sp,a0 + 98: 2c301263 bne zero,gp,35c + 9c: 00301663 bne zero,gp,a8 + a0: fe20fee3 bgeu ra,sp,9c + a4: 2a301c63 bne zero,gp,35c + +000000a8 : + a8: 00700193 li gp,7 + ac: fff00093 li ra,-1 + b0: 00000113 li sp,0 + b4: 0020f663 bgeu ra,sp,c0 + b8: 2a301263 bne zero,gp,35c + bc: 00301663 bne zero,gp,c8 + c0: fe20fee3 bgeu ra,sp,bc + c4: 28301c63 bne zero,gp,35c + +000000c8 : + c8: 00800193 li gp,8 + cc: 00000093 li ra,0 + d0: 00100113 li sp,1 + d4: 0020f463 bgeu ra,sp,dc + d8: 00301463 bne zero,gp,e0 + dc: 28301063 bne zero,gp,35c + e0: fe20fee3 bgeu ra,sp,dc + +000000e4 : + e4: 00900193 li gp,9 + e8: ffe00093 li ra,-2 + ec: fff00113 li sp,-1 + f0: 0020f463 bgeu ra,sp,f8 + f4: 00301463 bne zero,gp,fc + f8: 26301263 bne zero,gp,35c + fc: fe20fee3 bgeu ra,sp,f8 + +00000100 : + 100: 00a00193 li gp,10 + 104: 00000093 li ra,0 + 108: fff00113 li sp,-1 + 10c: 0020f463 bgeu ra,sp,114 + 110: 00301463 bne zero,gp,118 + 114: 24301463 bne zero,gp,35c + 118: fe20fee3 bgeu ra,sp,114 + +0000011c : + 11c: 00b00193 li gp,11 + 120: 800000b7 lui ra,0x80000 + 124: fff08093 addi ra,ra,-1 # 7fffffff + 128: 80000137 lui sp,0x80000 + 12c: 0020f463 bgeu ra,sp,134 + 130: 00301463 bne zero,gp,138 + 134: 22301463 bne zero,gp,35c + 138: fe20fee3 bgeu ra,sp,134 + +0000013c : + 13c: 00c00193 li gp,12 + 140: 00000213 li tp,0 + 144: f00000b7 lui ra,0xf0000 + 148: fff08093 addi ra,ra,-1 # efffffff + 14c: f0000137 lui sp,0xf0000 + 150: 2020f663 bgeu ra,sp,35c + 154: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 158: 00200293 li t0,2 + 15c: fe5214e3 bne tp,t0,144 + +00000160 : + 160: 00d00193 li gp,13 + 164: 00000213 li tp,0 + 168: f00000b7 lui ra,0xf0000 + 16c: fff08093 addi ra,ra,-1 # efffffff + 170: f0000137 lui sp,0xf0000 + 174: 00000013 nop + 178: 1e20f263 bgeu ra,sp,35c + 17c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 180: 00200293 li t0,2 + 184: fe5212e3 bne tp,t0,168 + +00000188 : + 188: 00e00193 li gp,14 + 18c: 00000213 li tp,0 + 190: f00000b7 lui ra,0xf0000 + 194: fff08093 addi ra,ra,-1 # efffffff + 198: f0000137 lui sp,0xf0000 + 19c: 00000013 nop + 1a0: 00000013 nop + 1a4: 1a20fc63 bgeu ra,sp,35c + 1a8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1ac: 00200293 li t0,2 + 1b0: fe5210e3 bne tp,t0,190 + +000001b4 : + 1b4: 00f00193 li gp,15 + 1b8: 00000213 li tp,0 + 1bc: f00000b7 lui ra,0xf0000 + 1c0: fff08093 addi ra,ra,-1 # efffffff + 1c4: 00000013 nop + 1c8: f0000137 lui sp,0xf0000 + 1cc: 1820f863 bgeu ra,sp,35c + 1d0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1d4: 00200293 li t0,2 + 1d8: fe5212e3 bne tp,t0,1bc + +000001dc : + 1dc: 01000193 li gp,16 + 1e0: 00000213 li tp,0 + 1e4: f00000b7 lui ra,0xf0000 + 1e8: fff08093 addi ra,ra,-1 # efffffff + 1ec: 00000013 nop + 1f0: f0000137 lui sp,0xf0000 + 1f4: 00000013 nop + 1f8: 1620f263 bgeu ra,sp,35c + 1fc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 200: 00200293 li t0,2 + 204: fe5210e3 bne tp,t0,1e4 + +00000208 : + 208: 01100193 li gp,17 + 20c: 00000213 li tp,0 + 210: f00000b7 lui ra,0xf0000 + 214: fff08093 addi ra,ra,-1 # efffffff + 218: 00000013 nop + 21c: 00000013 nop + 220: f0000137 lui sp,0xf0000 + 224: 1220fc63 bgeu ra,sp,35c + 228: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 22c: 00200293 li t0,2 + 230: fe5210e3 bne tp,t0,210 + +00000234 : + 234: 01200193 li gp,18 + 238: 00000213 li tp,0 + 23c: f00000b7 lui ra,0xf0000 + 240: fff08093 addi ra,ra,-1 # efffffff + 244: f0000137 lui sp,0xf0000 + 248: 1020fa63 bgeu ra,sp,35c + 24c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 250: 00200293 li t0,2 + 254: fe5214e3 bne tp,t0,23c + +00000258 : + 258: 01300193 li gp,19 + 25c: 00000213 li tp,0 + 260: f00000b7 lui ra,0xf0000 + 264: fff08093 addi ra,ra,-1 # efffffff + 268: f0000137 lui sp,0xf0000 + 26c: 00000013 nop + 270: 0e20f663 bgeu ra,sp,35c + 274: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 278: 00200293 li t0,2 + 27c: fe5212e3 bne tp,t0,260 + +00000280 : + 280: 01400193 li gp,20 + 284: 00000213 li tp,0 + 288: f00000b7 lui ra,0xf0000 + 28c: fff08093 addi ra,ra,-1 # efffffff + 290: f0000137 lui sp,0xf0000 + 294: 00000013 nop + 298: 00000013 nop + 29c: 0c20f063 bgeu ra,sp,35c + 2a0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2a4: 00200293 li t0,2 + 2a8: fe5210e3 bne tp,t0,288 + +000002ac : + 2ac: 01500193 li gp,21 + 2b0: 00000213 li tp,0 + 2b4: f00000b7 lui ra,0xf0000 + 2b8: fff08093 addi ra,ra,-1 # efffffff + 2bc: 00000013 nop + 2c0: f0000137 lui sp,0xf0000 + 2c4: 0820fc63 bgeu ra,sp,35c + 2c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2cc: 00200293 li t0,2 + 2d0: fe5212e3 bne tp,t0,2b4 + +000002d4 : + 2d4: 01600193 li gp,22 + 2d8: 00000213 li tp,0 + 2dc: f00000b7 lui ra,0xf0000 + 2e0: fff08093 addi ra,ra,-1 # efffffff + 2e4: 00000013 nop + 2e8: f0000137 lui sp,0xf0000 + 2ec: 00000013 nop + 2f0: 0620f663 bgeu ra,sp,35c + 2f4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2f8: 00200293 li t0,2 + 2fc: fe5210e3 bne tp,t0,2dc + +00000300 : + 300: 01700193 li gp,23 + 304: 00000213 li tp,0 + 308: f00000b7 lui ra,0xf0000 + 30c: fff08093 addi ra,ra,-1 # efffffff + 310: 00000013 nop + 314: 00000013 nop + 318: f0000137 lui sp,0xf0000 + 31c: 0420f063 bgeu ra,sp,35c + 320: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 324: 00200293 li t0,2 + 328: fe5210e3 bne tp,t0,308 + +0000032c : + 32c: 00100093 li ra,1 + 330: 0000fa63 bgeu ra,zero,344 + 334: 00108093 addi ra,ra,1 + 338: 00108093 addi ra,ra,1 + 33c: 00108093 addi ra,ra,1 + 340: 00108093 addi ra,ra,1 + 344: 00108093 addi ra,ra,1 + 348: 00108093 addi ra,ra,1 + 34c: 00300e93 li t4,3 + 350: 01800193 li gp,24 + 354: 01d09463 bne ra,t4,35c + 358: 00301863 bne zero,gp,368 + +0000035c : + 35c: 00100d13 li s10,1 + 360: 00000d93 li s11,0 + +00000364 : + 364: 0000006f j 364 + +00000368 : + 368: 00100d13 li s10,1 + 36c: 00100d93 li s11,1 + +00000370 : + 370: 0000006f j 370 + ... + +Disassembly of section .tohost: + +000003c0 : + ... + +00000400 : + ... diff --git a/tests/isa/generated/rv32ui-p-bgeu.verilog b/tests/isa/generated/rv32ui-p-bgeu.verilog new file mode 100644 index 0000000..1771970 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-bgeu.verilog @@ -0,0 +1,64 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 +13 01 00 00 63 F6 20 00 63 12 30 34 63 16 30 00 +E3 FE 20 FE 63 1C 30 32 93 01 30 00 93 00 10 00 +13 01 10 00 63 F6 20 00 63 12 30 32 63 16 30 00 +E3 FE 20 FE 63 1C 30 30 93 01 40 00 93 00 F0 FF +13 01 F0 FF 63 F6 20 00 63 12 30 30 63 16 30 00 +E3 FE 20 FE 63 1C 30 2E 93 01 50 00 93 00 10 00 +13 01 00 00 63 F6 20 00 63 12 30 2E 63 16 30 00 +E3 FE 20 FE 63 1C 30 2C 93 01 60 00 93 00 F0 FF +13 01 E0 FF 63 F6 20 00 63 12 30 2C 63 16 30 00 +E3 FE 20 FE 63 1C 30 2A 93 01 70 00 93 00 F0 FF +13 01 00 00 63 F6 20 00 63 12 30 2A 63 16 30 00 +E3 FE 20 FE 63 1C 30 28 93 01 80 00 93 00 00 00 +13 01 10 00 63 F4 20 00 63 14 30 00 63 10 30 28 +E3 FE 20 FE 93 01 90 00 93 00 E0 FF 13 01 F0 FF +63 F4 20 00 63 14 30 00 63 12 30 26 E3 FE 20 FE +93 01 A0 00 93 00 00 00 13 01 F0 FF 63 F4 20 00 +63 14 30 00 63 14 30 24 E3 FE 20 FE 93 01 B0 00 +B7 00 00 80 93 80 F0 FF 37 01 00 80 63 F4 20 00 +63 14 30 00 63 14 30 22 E3 FE 20 FE 93 01 C0 00 +13 02 00 00 B7 00 00 F0 93 80 F0 FF 37 01 00 F0 +63 F6 20 20 13 02 12 00 93 02 20 00 E3 14 52 FE +93 01 D0 00 13 02 00 00 B7 00 00 F0 93 80 F0 FF +37 01 00 F0 13 00 00 00 63 F2 20 1E 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 E0 00 13 02 00 00 +B7 00 00 F0 93 80 F0 FF 37 01 00 F0 13 00 00 00 +13 00 00 00 63 FC 20 1A 13 02 12 00 93 02 20 00 +E3 10 52 FE 93 01 F0 00 13 02 00 00 B7 00 00 F0 +93 80 F0 FF 13 00 00 00 37 01 00 F0 63 F8 20 18 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 00 01 +13 02 00 00 B7 00 00 F0 93 80 F0 FF 13 00 00 00 +37 01 00 F0 13 00 00 00 63 F2 20 16 13 02 12 00 +93 02 20 00 E3 10 52 FE 93 01 10 01 13 02 00 00 +B7 00 00 F0 93 80 F0 FF 13 00 00 00 13 00 00 00 +37 01 00 F0 63 FC 20 12 13 02 12 00 93 02 20 00 +E3 10 52 FE 93 01 20 01 13 02 00 00 B7 00 00 F0 +93 80 F0 FF 37 01 00 F0 63 FA 20 10 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 01 30 01 13 02 00 00 +B7 00 00 F0 93 80 F0 FF 37 01 00 F0 13 00 00 00 +63 F6 20 0E 13 02 12 00 93 02 20 00 E3 12 52 FE +93 01 40 01 13 02 00 00 B7 00 00 F0 93 80 F0 FF +37 01 00 F0 13 00 00 00 13 00 00 00 63 F0 20 0C +13 02 12 00 93 02 20 00 E3 10 52 FE 93 01 50 01 +13 02 00 00 B7 00 00 F0 93 80 F0 FF 13 00 00 00 +37 01 00 F0 63 FC 20 08 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 60 01 13 02 00 00 B7 00 00 F0 +93 80 F0 FF 13 00 00 00 37 01 00 F0 13 00 00 00 +63 F6 20 06 13 02 12 00 93 02 20 00 E3 10 52 FE +93 01 70 01 13 02 00 00 B7 00 00 F0 93 80 F0 FF +13 00 00 00 13 00 00 00 37 01 00 F0 63 F0 20 04 +13 02 12 00 93 02 20 00 E3 10 52 FE 93 00 10 00 +63 FA 00 00 93 80 10 00 93 80 10 00 93 80 10 00 +93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 +93 01 80 01 63 94 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@000003C0 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-blt b/tests/isa/generated/rv32ui-p-blt new file mode 100644 index 0000000..4194810 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-blt differ diff --git a/tests/isa/generated/rv32ui-p-blt.bin b/tests/isa/generated/rv32ui-p-blt.bin new file mode 100644 index 0000000..8d3346e Binary files /dev/null and b/tests/isa/generated/rv32ui-p-blt.bin differ diff --git a/tests/isa/generated/rv32ui-p-blt.dump b/tests/isa/generated/rv32ui-p-blt.dump new file mode 100644 index 0000000..4f6176f --- /dev/null +++ b/tests/isa/generated/rv32ui-p-blt.dump @@ -0,0 +1,248 @@ + +generated/rv32ui-p-blt: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00200193 li gp,2 + c: 00000093 li ra,0 + 10: 00100113 li sp,1 + 14: 0020c663 blt ra,sp,20 + 18: 2a301863 bne zero,gp,2c8 + 1c: 00301663 bne zero,gp,28 + 20: fe20cee3 blt ra,sp,1c + 24: 2a301263 bne zero,gp,2c8 + +00000028 : + 28: 00300193 li gp,3 + 2c: fff00093 li ra,-1 + 30: 00100113 li sp,1 + 34: 0020c663 blt ra,sp,40 + 38: 28301863 bne zero,gp,2c8 + 3c: 00301663 bne zero,gp,48 + 40: fe20cee3 blt ra,sp,3c + 44: 28301263 bne zero,gp,2c8 + +00000048 : + 48: 00400193 li gp,4 + 4c: ffe00093 li ra,-2 + 50: fff00113 li sp,-1 + 54: 0020c663 blt ra,sp,60 + 58: 26301863 bne zero,gp,2c8 + 5c: 00301663 bne zero,gp,68 + 60: fe20cee3 blt ra,sp,5c + 64: 26301263 bne zero,gp,2c8 + +00000068 : + 68: 00500193 li gp,5 + 6c: 00100093 li ra,1 + 70: 00000113 li sp,0 + 74: 0020c463 blt ra,sp,7c + 78: 00301463 bne zero,gp,80 + 7c: 24301663 bne zero,gp,2c8 + 80: fe20cee3 blt ra,sp,7c + +00000084 : + 84: 00600193 li gp,6 + 88: 00100093 li ra,1 + 8c: fff00113 li sp,-1 + 90: 0020c463 blt ra,sp,98 + 94: 00301463 bne zero,gp,9c + 98: 22301863 bne zero,gp,2c8 + 9c: fe20cee3 blt ra,sp,98 + +000000a0 : + a0: 00700193 li gp,7 + a4: fff00093 li ra,-1 + a8: ffe00113 li sp,-2 + ac: 0020c463 blt ra,sp,b4 + b0: 00301463 bne zero,gp,b8 + b4: 20301a63 bne zero,gp,2c8 + b8: fe20cee3 blt ra,sp,b4 + +000000bc : + bc: 00800193 li gp,8 + c0: 00100093 li ra,1 + c4: ffe00113 li sp,-2 + c8: 0020c463 blt ra,sp,d0 + cc: 00301463 bne zero,gp,d4 + d0: 1e301c63 bne zero,gp,2c8 + d4: fe20cee3 blt ra,sp,d0 + +000000d8 : + d8: 00900193 li gp,9 + dc: 00000213 li tp,0 + e0: 00000093 li ra,0 + e4: fff00113 li sp,-1 + e8: 1e20c063 blt ra,sp,2c8 + ec: 00120213 addi tp,tp,1 # 1 <_start+0x1> + f0: 00200293 li t0,2 + f4: fe5216e3 bne tp,t0,e0 + +000000f8 : + f8: 00a00193 li gp,10 + fc: 00000213 li tp,0 + 100: 00000093 li ra,0 + 104: fff00113 li sp,-1 + 108: 00000013 nop + 10c: 1a20ce63 blt ra,sp,2c8 + 110: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 114: 00200293 li t0,2 + 118: fe5214e3 bne tp,t0,100 + +0000011c : + 11c: 00b00193 li gp,11 + 120: 00000213 li tp,0 + 124: 00000093 li ra,0 + 128: fff00113 li sp,-1 + 12c: 00000013 nop + 130: 00000013 nop + 134: 1820ca63 blt ra,sp,2c8 + 138: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 13c: 00200293 li t0,2 + 140: fe5212e3 bne tp,t0,124 + +00000144 : + 144: 00c00193 li gp,12 + 148: 00000213 li tp,0 + 14c: 00000093 li ra,0 + 150: 00000013 nop + 154: fff00113 li sp,-1 + 158: 1620c863 blt ra,sp,2c8 + 15c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 160: 00200293 li t0,2 + 164: fe5214e3 bne tp,t0,14c + +00000168 : + 168: 00d00193 li gp,13 + 16c: 00000213 li tp,0 + 170: 00000093 li ra,0 + 174: 00000013 nop + 178: fff00113 li sp,-1 + 17c: 00000013 nop + 180: 1420c463 blt ra,sp,2c8 + 184: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 188: 00200293 li t0,2 + 18c: fe5212e3 bne tp,t0,170 + +00000190 : + 190: 00e00193 li gp,14 + 194: 00000213 li tp,0 + 198: 00000093 li ra,0 + 19c: 00000013 nop + 1a0: 00000013 nop + 1a4: fff00113 li sp,-1 + 1a8: 1220c063 blt ra,sp,2c8 + 1ac: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1b0: 00200293 li t0,2 + 1b4: fe5212e3 bne tp,t0,198 + +000001b8 : + 1b8: 00f00193 li gp,15 + 1bc: 00000213 li tp,0 + 1c0: 00000093 li ra,0 + 1c4: fff00113 li sp,-1 + 1c8: 1020c063 blt ra,sp,2c8 + 1cc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1d0: 00200293 li t0,2 + 1d4: fe5216e3 bne tp,t0,1c0 + +000001d8 : + 1d8: 01000193 li gp,16 + 1dc: 00000213 li tp,0 + 1e0: 00000093 li ra,0 + 1e4: fff00113 li sp,-1 + 1e8: 00000013 nop + 1ec: 0c20ce63 blt ra,sp,2c8 + 1f0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1f4: 00200293 li t0,2 + 1f8: fe5214e3 bne tp,t0,1e0 + +000001fc : + 1fc: 01100193 li gp,17 + 200: 00000213 li tp,0 + 204: 00000093 li ra,0 + 208: fff00113 li sp,-1 + 20c: 00000013 nop + 210: 00000013 nop + 214: 0a20ca63 blt ra,sp,2c8 + 218: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 21c: 00200293 li t0,2 + 220: fe5212e3 bne tp,t0,204 + +00000224 : + 224: 01200193 li gp,18 + 228: 00000213 li tp,0 + 22c: 00000093 li ra,0 + 230: 00000013 nop + 234: fff00113 li sp,-1 + 238: 0820c863 blt ra,sp,2c8 + 23c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 240: 00200293 li t0,2 + 244: fe5214e3 bne tp,t0,22c + +00000248 : + 248: 01300193 li gp,19 + 24c: 00000213 li tp,0 + 250: 00000093 li ra,0 + 254: 00000013 nop + 258: fff00113 li sp,-1 + 25c: 00000013 nop + 260: 0620c463 blt ra,sp,2c8 + 264: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 268: 00200293 li t0,2 + 26c: fe5212e3 bne tp,t0,250 + +00000270 : + 270: 01400193 li gp,20 + 274: 00000213 li tp,0 + 278: 00000093 li ra,0 + 27c: 00000013 nop + 280: 00000013 nop + 284: fff00113 li sp,-1 + 288: 0420c063 blt ra,sp,2c8 + 28c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 290: 00200293 li t0,2 + 294: fe5212e3 bne tp,t0,278 + +00000298 : + 298: 00100093 li ra,1 + 29c: 00104a63 bgtz ra,2b0 + 2a0: 00108093 addi ra,ra,1 + 2a4: 00108093 addi ra,ra,1 + 2a8: 00108093 addi ra,ra,1 + 2ac: 00108093 addi ra,ra,1 + 2b0: 00108093 addi ra,ra,1 + 2b4: 00108093 addi ra,ra,1 + 2b8: 00300e93 li t4,3 + 2bc: 01500193 li gp,21 + 2c0: 01d09463 bne ra,t4,2c8 + 2c4: 00301863 bne zero,gp,2d4 + +000002c8 : + 2c8: 00100d13 li s10,1 + 2cc: 00000d93 li s11,0 + +000002d0 : + 2d0: 0000006f j 2d0 + +000002d4 : + 2d4: 00100d13 li s10,1 + 2d8: 00100d93 li s11,1 + +000002dc : + 2dc: 0000006f j 2dc + ... + +Disassembly of section .tohost: + +00000340 : + ... + +00000380 : + ... diff --git a/tests/isa/generated/rv32ui-p-blt.verilog b/tests/isa/generated/rv32ui-p-blt.verilog new file mode 100644 index 0000000..b0f22b3 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-blt.verilog @@ -0,0 +1,56 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 +13 01 10 00 63 C6 20 00 63 18 30 2A 63 16 30 00 +E3 CE 20 FE 63 12 30 2A 93 01 30 00 93 00 F0 FF +13 01 10 00 63 C6 20 00 63 18 30 28 63 16 30 00 +E3 CE 20 FE 63 12 30 28 93 01 40 00 93 00 E0 FF +13 01 F0 FF 63 C6 20 00 63 18 30 26 63 16 30 00 +E3 CE 20 FE 63 12 30 26 93 01 50 00 93 00 10 00 +13 01 00 00 63 C4 20 00 63 14 30 00 63 16 30 24 +E3 CE 20 FE 93 01 60 00 93 00 10 00 13 01 F0 FF +63 C4 20 00 63 14 30 00 63 18 30 22 E3 CE 20 FE +93 01 70 00 93 00 F0 FF 13 01 E0 FF 63 C4 20 00 +63 14 30 00 63 1A 30 20 E3 CE 20 FE 93 01 80 00 +93 00 10 00 13 01 E0 FF 63 C4 20 00 63 14 30 00 +63 1C 30 1E E3 CE 20 FE 93 01 90 00 13 02 00 00 +93 00 00 00 13 01 F0 FF 63 C0 20 1E 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 01 A0 00 13 02 00 00 +93 00 00 00 13 01 F0 FF 13 00 00 00 63 CE 20 1A +13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 B0 00 +13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 +13 00 00 00 63 CA 20 18 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 C0 00 13 02 00 00 93 00 00 00 +13 00 00 00 13 01 F0 FF 63 C8 20 16 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 01 D0 00 13 02 00 00 +93 00 00 00 13 00 00 00 13 01 F0 FF 13 00 00 00 +63 C4 20 14 13 02 12 00 93 02 20 00 E3 12 52 FE +93 01 E0 00 13 02 00 00 93 00 00 00 13 00 00 00 +13 00 00 00 13 01 F0 FF 63 C0 20 12 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 F0 00 13 02 00 00 +93 00 00 00 13 01 F0 FF 63 C0 20 10 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 01 00 01 13 02 00 00 +93 00 00 00 13 01 F0 FF 13 00 00 00 63 CE 20 0C +13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 10 01 +13 02 00 00 93 00 00 00 13 01 F0 FF 13 00 00 00 +13 00 00 00 63 CA 20 0A 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 20 01 13 02 00 00 93 00 00 00 +13 00 00 00 13 01 F0 FF 63 C8 20 08 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 01 30 01 13 02 00 00 +93 00 00 00 13 00 00 00 13 01 F0 FF 13 00 00 00 +63 C4 20 06 13 02 12 00 93 02 20 00 E3 12 52 FE +93 01 40 01 13 02 00 00 93 00 00 00 13 00 00 00 +13 00 00 00 13 01 F0 FF 63 C0 20 04 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 00 10 00 63 4A 10 00 +93 80 10 00 93 80 10 00 93 80 10 00 93 80 10 00 +93 80 10 00 93 80 10 00 93 0E 30 00 93 01 50 01 +63 94 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000340 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-bltu b/tests/isa/generated/rv32ui-p-bltu new file mode 100644 index 0000000..d1c2cd5 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-bltu differ diff --git a/tests/isa/generated/rv32ui-p-bltu.bin b/tests/isa/generated/rv32ui-p-bltu.bin new file mode 100644 index 0000000..822cef3 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-bltu.bin differ diff --git a/tests/isa/generated/rv32ui-p-bltu.dump b/tests/isa/generated/rv32ui-p-bltu.dump new file mode 100644 index 0000000..f77ff22 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-bltu.dump @@ -0,0 +1,261 @@ + +generated/rv32ui-p-bltu: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00200193 li gp,2 + c: 00000093 li ra,0 + 10: 00100113 li sp,1 + 14: 0020e663 bltu ra,sp,20 + 18: 2e301263 bne zero,gp,2fc + 1c: 00301663 bne zero,gp,28 + 20: fe20eee3 bltu ra,sp,1c + 24: 2c301c63 bne zero,gp,2fc + +00000028 : + 28: 00300193 li gp,3 + 2c: ffe00093 li ra,-2 + 30: fff00113 li sp,-1 + 34: 0020e663 bltu ra,sp,40 + 38: 2c301263 bne zero,gp,2fc + 3c: 00301663 bne zero,gp,48 + 40: fe20eee3 bltu ra,sp,3c + 44: 2a301c63 bne zero,gp,2fc + +00000048 : + 48: 00400193 li gp,4 + 4c: 00000093 li ra,0 + 50: fff00113 li sp,-1 + 54: 0020e663 bltu ra,sp,60 + 58: 2a301263 bne zero,gp,2fc + 5c: 00301663 bne zero,gp,68 + 60: fe20eee3 bltu ra,sp,5c + 64: 28301c63 bne zero,gp,2fc + +00000068 : + 68: 00500193 li gp,5 + 6c: 00100093 li ra,1 + 70: 00000113 li sp,0 + 74: 0020e463 bltu ra,sp,7c + 78: 00301463 bne zero,gp,80 + 7c: 28301063 bne zero,gp,2fc + 80: fe20eee3 bltu ra,sp,7c + +00000084 : + 84: 00600193 li gp,6 + 88: fff00093 li ra,-1 + 8c: ffe00113 li sp,-2 + 90: 0020e463 bltu ra,sp,98 + 94: 00301463 bne zero,gp,9c + 98: 26301263 bne zero,gp,2fc + 9c: fe20eee3 bltu ra,sp,98 + +000000a0 : + a0: 00700193 li gp,7 + a4: fff00093 li ra,-1 + a8: 00000113 li sp,0 + ac: 0020e463 bltu ra,sp,b4 + b0: 00301463 bne zero,gp,b8 + b4: 24301463 bne zero,gp,2fc + b8: fe20eee3 bltu ra,sp,b4 + +000000bc : + bc: 00800193 li gp,8 + c0: 800000b7 lui ra,0x80000 + c4: 80000137 lui sp,0x80000 + c8: fff10113 addi sp,sp,-1 # 7fffffff + cc: 0020e463 bltu ra,sp,d4 + d0: 00301463 bne zero,gp,d8 + d4: 22301463 bne zero,gp,2fc + d8: fe20eee3 bltu ra,sp,d4 + +000000dc : + dc: 00900193 li gp,9 + e0: 00000213 li tp,0 + e4: f00000b7 lui ra,0xf0000 + e8: f0000137 lui sp,0xf0000 + ec: fff10113 addi sp,sp,-1 # efffffff + f0: 2020e663 bltu ra,sp,2fc + f4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + f8: 00200293 li t0,2 + fc: fe5214e3 bne tp,t0,e4 + +00000100 : + 100: 00a00193 li gp,10 + 104: 00000213 li tp,0 + 108: f00000b7 lui ra,0xf0000 + 10c: f0000137 lui sp,0xf0000 + 110: fff10113 addi sp,sp,-1 # efffffff + 114: 00000013 nop + 118: 1e20e263 bltu ra,sp,2fc + 11c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 120: 00200293 li t0,2 + 124: fe5212e3 bne tp,t0,108 + +00000128 : + 128: 00b00193 li gp,11 + 12c: 00000213 li tp,0 + 130: f00000b7 lui ra,0xf0000 + 134: f0000137 lui sp,0xf0000 + 138: fff10113 addi sp,sp,-1 # efffffff + 13c: 00000013 nop + 140: 00000013 nop + 144: 1a20ec63 bltu ra,sp,2fc + 148: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 14c: 00200293 li t0,2 + 150: fe5210e3 bne tp,t0,130 + +00000154 : + 154: 00c00193 li gp,12 + 158: 00000213 li tp,0 + 15c: f00000b7 lui ra,0xf0000 + 160: 00000013 nop + 164: f0000137 lui sp,0xf0000 + 168: fff10113 addi sp,sp,-1 # efffffff + 16c: 1820e863 bltu ra,sp,2fc + 170: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 174: 00200293 li t0,2 + 178: fe5212e3 bne tp,t0,15c + +0000017c : + 17c: 00d00193 li gp,13 + 180: 00000213 li tp,0 + 184: f00000b7 lui ra,0xf0000 + 188: 00000013 nop + 18c: f0000137 lui sp,0xf0000 + 190: fff10113 addi sp,sp,-1 # efffffff + 194: 00000013 nop + 198: 1620e263 bltu ra,sp,2fc + 19c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1a0: 00200293 li t0,2 + 1a4: fe5210e3 bne tp,t0,184 + +000001a8 : + 1a8: 00e00193 li gp,14 + 1ac: 00000213 li tp,0 + 1b0: f00000b7 lui ra,0xf0000 + 1b4: 00000013 nop + 1b8: 00000013 nop + 1bc: f0000137 lui sp,0xf0000 + 1c0: fff10113 addi sp,sp,-1 # efffffff + 1c4: 1220ec63 bltu ra,sp,2fc + 1c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1cc: 00200293 li t0,2 + 1d0: fe5210e3 bne tp,t0,1b0 + +000001d4 : + 1d4: 00f00193 li gp,15 + 1d8: 00000213 li tp,0 + 1dc: f00000b7 lui ra,0xf0000 + 1e0: f0000137 lui sp,0xf0000 + 1e4: fff10113 addi sp,sp,-1 # efffffff + 1e8: 1020ea63 bltu ra,sp,2fc + 1ec: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1f0: 00200293 li t0,2 + 1f4: fe5214e3 bne tp,t0,1dc + +000001f8 : + 1f8: 01000193 li gp,16 + 1fc: 00000213 li tp,0 + 200: f00000b7 lui ra,0xf0000 + 204: f0000137 lui sp,0xf0000 + 208: fff10113 addi sp,sp,-1 # efffffff + 20c: 00000013 nop + 210: 0e20e663 bltu ra,sp,2fc + 214: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 218: 00200293 li t0,2 + 21c: fe5212e3 bne tp,t0,200 + +00000220 : + 220: 01100193 li gp,17 + 224: 00000213 li tp,0 + 228: f00000b7 lui ra,0xf0000 + 22c: f0000137 lui sp,0xf0000 + 230: fff10113 addi sp,sp,-1 # efffffff + 234: 00000013 nop + 238: 00000013 nop + 23c: 0c20e063 bltu ra,sp,2fc + 240: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 244: 00200293 li t0,2 + 248: fe5210e3 bne tp,t0,228 + +0000024c : + 24c: 01200193 li gp,18 + 250: 00000213 li tp,0 + 254: f00000b7 lui ra,0xf0000 + 258: 00000013 nop + 25c: f0000137 lui sp,0xf0000 + 260: fff10113 addi sp,sp,-1 # efffffff + 264: 0820ec63 bltu ra,sp,2fc + 268: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 26c: 00200293 li t0,2 + 270: fe5212e3 bne tp,t0,254 + +00000274 : + 274: 01300193 li gp,19 + 278: 00000213 li tp,0 + 27c: f00000b7 lui ra,0xf0000 + 280: 00000013 nop + 284: f0000137 lui sp,0xf0000 + 288: fff10113 addi sp,sp,-1 # efffffff + 28c: 00000013 nop + 290: 0620e663 bltu ra,sp,2fc + 294: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 298: 00200293 li t0,2 + 29c: fe5210e3 bne tp,t0,27c + +000002a0 : + 2a0: 01400193 li gp,20 + 2a4: 00000213 li tp,0 + 2a8: f00000b7 lui ra,0xf0000 + 2ac: 00000013 nop + 2b0: 00000013 nop + 2b4: f0000137 lui sp,0xf0000 + 2b8: fff10113 addi sp,sp,-1 # efffffff + 2bc: 0420e063 bltu ra,sp,2fc + 2c0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2c4: 00200293 li t0,2 + 2c8: fe5210e3 bne tp,t0,2a8 + +000002cc : + 2cc: 00100093 li ra,1 + 2d0: 00106a63 bltu zero,ra,2e4 + 2d4: 00108093 addi ra,ra,1 # f0000001 + 2d8: 00108093 addi ra,ra,1 + 2dc: 00108093 addi ra,ra,1 + 2e0: 00108093 addi ra,ra,1 + 2e4: 00108093 addi ra,ra,1 + 2e8: 00108093 addi ra,ra,1 + 2ec: 00300e93 li t4,3 + 2f0: 01500193 li gp,21 + 2f4: 01d09463 bne ra,t4,2fc + 2f8: 00301863 bne zero,gp,308 + +000002fc : + 2fc: 00100d13 li s10,1 + 300: 00000d93 li s11,0 + +00000304 : + 304: 0000006f j 304 + +00000308 : + 308: 00100d13 li s10,1 + 30c: 00100d93 li s11,1 + +00000310 : + 310: 0000006f j 310 + ... + +Disassembly of section .tohost: + +00000380 : + ... + +000003c0 : + ... diff --git a/tests/isa/generated/rv32ui-p-bltu.verilog b/tests/isa/generated/rv32ui-p-bltu.verilog new file mode 100644 index 0000000..8bc8aef --- /dev/null +++ b/tests/isa/generated/rv32ui-p-bltu.verilog @@ -0,0 +1,60 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 +13 01 10 00 63 E6 20 00 63 12 30 2E 63 16 30 00 +E3 EE 20 FE 63 1C 30 2C 93 01 30 00 93 00 E0 FF +13 01 F0 FF 63 E6 20 00 63 12 30 2C 63 16 30 00 +E3 EE 20 FE 63 1C 30 2A 93 01 40 00 93 00 00 00 +13 01 F0 FF 63 E6 20 00 63 12 30 2A 63 16 30 00 +E3 EE 20 FE 63 1C 30 28 93 01 50 00 93 00 10 00 +13 01 00 00 63 E4 20 00 63 14 30 00 63 10 30 28 +E3 EE 20 FE 93 01 60 00 93 00 F0 FF 13 01 E0 FF +63 E4 20 00 63 14 30 00 63 12 30 26 E3 EE 20 FE +93 01 70 00 93 00 F0 FF 13 01 00 00 63 E4 20 00 +63 14 30 00 63 14 30 24 E3 EE 20 FE 93 01 80 00 +B7 00 00 80 37 01 00 80 13 01 F1 FF 63 E4 20 00 +63 14 30 00 63 14 30 22 E3 EE 20 FE 93 01 90 00 +13 02 00 00 B7 00 00 F0 37 01 00 F0 13 01 F1 FF +63 E6 20 20 13 02 12 00 93 02 20 00 E3 14 52 FE +93 01 A0 00 13 02 00 00 B7 00 00 F0 37 01 00 F0 +13 01 F1 FF 13 00 00 00 63 E2 20 1E 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 B0 00 13 02 00 00 +B7 00 00 F0 37 01 00 F0 13 01 F1 FF 13 00 00 00 +13 00 00 00 63 EC 20 1A 13 02 12 00 93 02 20 00 +E3 10 52 FE 93 01 C0 00 13 02 00 00 B7 00 00 F0 +13 00 00 00 37 01 00 F0 13 01 F1 FF 63 E8 20 18 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 D0 00 +13 02 00 00 B7 00 00 F0 13 00 00 00 37 01 00 F0 +13 01 F1 FF 13 00 00 00 63 E2 20 16 13 02 12 00 +93 02 20 00 E3 10 52 FE 93 01 E0 00 13 02 00 00 +B7 00 00 F0 13 00 00 00 13 00 00 00 37 01 00 F0 +13 01 F1 FF 63 EC 20 12 13 02 12 00 93 02 20 00 +E3 10 52 FE 93 01 F0 00 13 02 00 00 B7 00 00 F0 +37 01 00 F0 13 01 F1 FF 63 EA 20 10 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 01 00 01 13 02 00 00 +B7 00 00 F0 37 01 00 F0 13 01 F1 FF 13 00 00 00 +63 E6 20 0E 13 02 12 00 93 02 20 00 E3 12 52 FE +93 01 10 01 13 02 00 00 B7 00 00 F0 37 01 00 F0 +13 01 F1 FF 13 00 00 00 13 00 00 00 63 E0 20 0C +13 02 12 00 93 02 20 00 E3 10 52 FE 93 01 20 01 +13 02 00 00 B7 00 00 F0 13 00 00 00 37 01 00 F0 +13 01 F1 FF 63 EC 20 08 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 30 01 13 02 00 00 B7 00 00 F0 +13 00 00 00 37 01 00 F0 13 01 F1 FF 13 00 00 00 +63 E6 20 06 13 02 12 00 93 02 20 00 E3 10 52 FE +93 01 40 01 13 02 00 00 B7 00 00 F0 13 00 00 00 +13 00 00 00 37 01 00 F0 13 01 F1 FF 63 E0 20 04 +13 02 12 00 93 02 20 00 E3 10 52 FE 93 00 10 00 +63 6A 10 00 93 80 10 00 93 80 10 00 93 80 10 00 +93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 +93 01 50 01 63 94 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000380 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-bne b/tests/isa/generated/rv32ui-p-bne new file mode 100644 index 0000000..6778232 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-bne differ diff --git a/tests/isa/generated/rv32ui-p-bne.bin b/tests/isa/generated/rv32ui-p-bne.bin new file mode 100644 index 0000000..1e78a51 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-bne.bin differ diff --git a/tests/isa/generated/rv32ui-p-bne.dump b/tests/isa/generated/rv32ui-p-bne.dump new file mode 100644 index 0000000..6e97859 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-bne.dump @@ -0,0 +1,249 @@ + +generated/rv32ui-p-bne: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00200193 li gp,2 + c: 00000093 li ra,0 + 10: 00100113 li sp,1 + 14: 00209663 bne ra,sp,20 + 18: 2a301a63 bne zero,gp,2cc + 1c: 00301663 bne zero,gp,28 + 20: fe209ee3 bne ra,sp,1c + 24: 2a301463 bne zero,gp,2cc + +00000028 : + 28: 00300193 li gp,3 + 2c: 00100093 li ra,1 + 30: 00000113 li sp,0 + 34: 00209663 bne ra,sp,40 + 38: 28301a63 bne zero,gp,2cc + 3c: 00301663 bne zero,gp,48 + 40: fe209ee3 bne ra,sp,3c + 44: 28301463 bne zero,gp,2cc + +00000048 : + 48: 00400193 li gp,4 + 4c: fff00093 li ra,-1 + 50: 00100113 li sp,1 + 54: 00209663 bne ra,sp,60 + 58: 26301a63 bne zero,gp,2cc + 5c: 00301663 bne zero,gp,68 + 60: fe209ee3 bne ra,sp,5c + 64: 26301463 bne zero,gp,2cc + +00000068 : + 68: 00500193 li gp,5 + 6c: 00100093 li ra,1 + 70: fff00113 li sp,-1 + 74: 00209663 bne ra,sp,80 + 78: 24301a63 bne zero,gp,2cc + 7c: 00301663 bne zero,gp,88 + 80: fe209ee3 bne ra,sp,7c + 84: 24301463 bne zero,gp,2cc + +00000088 : + 88: 00600193 li gp,6 + 8c: 00000093 li ra,0 + 90: 00000113 li sp,0 + 94: 00209463 bne ra,sp,9c + 98: 00301463 bne zero,gp,a0 + 9c: 22301863 bne zero,gp,2cc + a0: fe209ee3 bne ra,sp,9c + +000000a4 : + a4: 00700193 li gp,7 + a8: 00100093 li ra,1 + ac: 00100113 li sp,1 + b0: 00209463 bne ra,sp,b8 + b4: 00301463 bne zero,gp,bc + b8: 20301a63 bne zero,gp,2cc + bc: fe209ee3 bne ra,sp,b8 + +000000c0 : + c0: 00800193 li gp,8 + c4: fff00093 li ra,-1 + c8: fff00113 li sp,-1 + cc: 00209463 bne ra,sp,d4 + d0: 00301463 bne zero,gp,d8 + d4: 1e301c63 bne zero,gp,2cc + d8: fe209ee3 bne ra,sp,d4 + +000000dc : + dc: 00900193 li gp,9 + e0: 00000213 li tp,0 + e4: 00000093 li ra,0 + e8: 00000113 li sp,0 + ec: 1e209063 bne ra,sp,2cc + f0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + f4: 00200293 li t0,2 + f8: fe5216e3 bne tp,t0,e4 + +000000fc : + fc: 00a00193 li gp,10 + 100: 00000213 li tp,0 + 104: 00000093 li ra,0 + 108: 00000113 li sp,0 + 10c: 00000013 nop + 110: 1a209e63 bne ra,sp,2cc + 114: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 118: 00200293 li t0,2 + 11c: fe5214e3 bne tp,t0,104 + +00000120 : + 120: 00b00193 li gp,11 + 124: 00000213 li tp,0 + 128: 00000093 li ra,0 + 12c: 00000113 li sp,0 + 130: 00000013 nop + 134: 00000013 nop + 138: 18209a63 bne ra,sp,2cc + 13c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 140: 00200293 li t0,2 + 144: fe5212e3 bne tp,t0,128 + +00000148 : + 148: 00c00193 li gp,12 + 14c: 00000213 li tp,0 + 150: 00000093 li ra,0 + 154: 00000013 nop + 158: 00000113 li sp,0 + 15c: 16209863 bne ra,sp,2cc + 160: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 164: 00200293 li t0,2 + 168: fe5214e3 bne tp,t0,150 + +0000016c : + 16c: 00d00193 li gp,13 + 170: 00000213 li tp,0 + 174: 00000093 li ra,0 + 178: 00000013 nop + 17c: 00000113 li sp,0 + 180: 00000013 nop + 184: 14209463 bne ra,sp,2cc + 188: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 18c: 00200293 li t0,2 + 190: fe5212e3 bne tp,t0,174 + +00000194 : + 194: 00e00193 li gp,14 + 198: 00000213 li tp,0 + 19c: 00000093 li ra,0 + 1a0: 00000013 nop + 1a4: 00000013 nop + 1a8: 00000113 li sp,0 + 1ac: 12209063 bne ra,sp,2cc + 1b0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1b4: 00200293 li t0,2 + 1b8: fe5212e3 bne tp,t0,19c + +000001bc : + 1bc: 00f00193 li gp,15 + 1c0: 00000213 li tp,0 + 1c4: 00000093 li ra,0 + 1c8: 00000113 li sp,0 + 1cc: 10209063 bne ra,sp,2cc + 1d0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1d4: 00200293 li t0,2 + 1d8: fe5216e3 bne tp,t0,1c4 + +000001dc : + 1dc: 01000193 li gp,16 + 1e0: 00000213 li tp,0 + 1e4: 00000093 li ra,0 + 1e8: 00000113 li sp,0 + 1ec: 00000013 nop + 1f0: 0c209e63 bne ra,sp,2cc + 1f4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1f8: 00200293 li t0,2 + 1fc: fe5214e3 bne tp,t0,1e4 + +00000200 : + 200: 01100193 li gp,17 + 204: 00000213 li tp,0 + 208: 00000093 li ra,0 + 20c: 00000113 li sp,0 + 210: 00000013 nop + 214: 00000013 nop + 218: 0a209a63 bne ra,sp,2cc + 21c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 220: 00200293 li t0,2 + 224: fe5212e3 bne tp,t0,208 + +00000228 : + 228: 01200193 li gp,18 + 22c: 00000213 li tp,0 + 230: 00000093 li ra,0 + 234: 00000013 nop + 238: 00000113 li sp,0 + 23c: 08209863 bne ra,sp,2cc + 240: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 244: 00200293 li t0,2 + 248: fe5214e3 bne tp,t0,230 + +0000024c : + 24c: 01300193 li gp,19 + 250: 00000213 li tp,0 + 254: 00000093 li ra,0 + 258: 00000013 nop + 25c: 00000113 li sp,0 + 260: 00000013 nop + 264: 06209463 bne ra,sp,2cc + 268: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 26c: 00200293 li t0,2 + 270: fe5212e3 bne tp,t0,254 + +00000274 : + 274: 01400193 li gp,20 + 278: 00000213 li tp,0 + 27c: 00000093 li ra,0 + 280: 00000013 nop + 284: 00000013 nop + 288: 00000113 li sp,0 + 28c: 04209063 bne ra,sp,2cc + 290: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 294: 00200293 li t0,2 + 298: fe5212e3 bne tp,t0,27c + +0000029c : + 29c: 00100093 li ra,1 + 2a0: 00009a63 bnez ra,2b4 + 2a4: 00108093 addi ra,ra,1 + 2a8: 00108093 addi ra,ra,1 + 2ac: 00108093 addi ra,ra,1 + 2b0: 00108093 addi ra,ra,1 + 2b4: 00108093 addi ra,ra,1 + 2b8: 00108093 addi ra,ra,1 + 2bc: 00300e93 li t4,3 + 2c0: 01500193 li gp,21 + 2c4: 01d09463 bne ra,t4,2cc + 2c8: 00301863 bne zero,gp,2d8 + +000002cc : + 2cc: 00100d13 li s10,1 + 2d0: 00000d93 li s11,0 + +000002d4 : + 2d4: 0000006f j 2d4 + +000002d8 : + 2d8: 00100d13 li s10,1 + 2dc: 00100d93 li s11,1 + +000002e0 : + 2e0: 0000006f j 2e0 + ... + +Disassembly of section .tohost: + +00000340 : + ... + +00000380 : + ... diff --git a/tests/isa/generated/rv32ui-p-bne.verilog b/tests/isa/generated/rv32ui-p-bne.verilog new file mode 100644 index 0000000..a70d927 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-bne.verilog @@ -0,0 +1,56 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 +13 01 10 00 63 96 20 00 63 1A 30 2A 63 16 30 00 +E3 9E 20 FE 63 14 30 2A 93 01 30 00 93 00 10 00 +13 01 00 00 63 96 20 00 63 1A 30 28 63 16 30 00 +E3 9E 20 FE 63 14 30 28 93 01 40 00 93 00 F0 FF +13 01 10 00 63 96 20 00 63 1A 30 26 63 16 30 00 +E3 9E 20 FE 63 14 30 26 93 01 50 00 93 00 10 00 +13 01 F0 FF 63 96 20 00 63 1A 30 24 63 16 30 00 +E3 9E 20 FE 63 14 30 24 93 01 60 00 93 00 00 00 +13 01 00 00 63 94 20 00 63 14 30 00 63 18 30 22 +E3 9E 20 FE 93 01 70 00 93 00 10 00 13 01 10 00 +63 94 20 00 63 14 30 00 63 1A 30 20 E3 9E 20 FE +93 01 80 00 93 00 F0 FF 13 01 F0 FF 63 94 20 00 +63 14 30 00 63 1C 30 1E E3 9E 20 FE 93 01 90 00 +13 02 00 00 93 00 00 00 13 01 00 00 63 90 20 1E +13 02 12 00 93 02 20 00 E3 16 52 FE 93 01 A0 00 +13 02 00 00 93 00 00 00 13 01 00 00 13 00 00 00 +63 9E 20 1A 13 02 12 00 93 02 20 00 E3 14 52 FE +93 01 B0 00 13 02 00 00 93 00 00 00 13 01 00 00 +13 00 00 00 13 00 00 00 63 9A 20 18 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 C0 00 13 02 00 00 +93 00 00 00 13 00 00 00 13 01 00 00 63 98 20 16 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 D0 00 +13 02 00 00 93 00 00 00 13 00 00 00 13 01 00 00 +13 00 00 00 63 94 20 14 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 E0 00 13 02 00 00 93 00 00 00 +13 00 00 00 13 00 00 00 13 01 00 00 63 90 20 12 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 01 F0 00 +13 02 00 00 93 00 00 00 13 01 00 00 63 90 20 10 +13 02 12 00 93 02 20 00 E3 16 52 FE 93 01 00 01 +13 02 00 00 93 00 00 00 13 01 00 00 13 00 00 00 +63 9E 20 0C 13 02 12 00 93 02 20 00 E3 14 52 FE +93 01 10 01 13 02 00 00 93 00 00 00 13 01 00 00 +13 00 00 00 13 00 00 00 63 9A 20 0A 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 20 01 13 02 00 00 +93 00 00 00 13 00 00 00 13 01 00 00 63 98 20 08 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 01 30 01 +13 02 00 00 93 00 00 00 13 00 00 00 13 01 00 00 +13 00 00 00 63 94 20 06 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 01 40 01 13 02 00 00 93 00 00 00 +13 00 00 00 13 00 00 00 13 01 00 00 63 90 20 04 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 00 10 00 +63 9A 00 00 93 80 10 00 93 80 10 00 93 80 10 00 +93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 +93 01 50 01 63 94 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000340 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-fence_i b/tests/isa/generated/rv32ui-p-fence_i new file mode 100644 index 0000000..4857f80 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-fence_i differ diff --git a/tests/isa/generated/rv32ui-p-fence_i.bin b/tests/isa/generated/rv32ui-p-fence_i.bin new file mode 100644 index 0000000..12cbbe9 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-fence_i.bin differ diff --git a/tests/isa/generated/rv32ui-p-fence_i.dump b/tests/isa/generated/rv32ui-p-fence_i.dump new file mode 100644 index 0000000..52c6dd7 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-fence_i.dump @@ -0,0 +1,94 @@ + +generated/rv32ui-p-fence_i: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + 8: 06f00693 li a3,111 + c: 00001517 auipc a0,0x1 + 10: ff451503 lh a0,-12(a0) # 1000 + 14: 00001597 auipc a1,0x1 + 18: fee59583 lh a1,-18(a1) # 1002 + 1c: 00000013 nop + 20: 00000013 nop + 24: 00000013 nop + 28: 00000013 nop + 2c: 00000013 nop + 30: 00000013 nop + 34: 00000013 nop + 38: 00000013 nop + 3c: 00000013 nop + 40: 00000297 auipc t0,0x0 + 44: 00a29a23 sh a0,20(t0) # 54 <_start+0x54> + 48: 00000297 auipc t0,0x0 + 4c: 00b29723 sh a1,14(t0) # 56 <_start+0x56> + 50: 0000100f fence.i + 54: 0de68693 addi a3,a3,222 + +00000058 : + 58: 00000013 nop + 5c: 1bc00e93 li t4,444 + 60: 00200193 li gp,2 + 64: 07d69a63 bne a3,t4,d8 + 68: 06400713 li a4,100 + 6c: fff70713 addi a4,a4,-1 + 70: fe071ee3 bnez a4,6c + 74: 00000297 auipc t0,0x0 + 78: 04a29623 sh a0,76(t0) # c0 + 7c: 00000297 auipc t0,0x0 + 80: 04b29323 sh a1,70(t0) # c2 + 84: 0000100f fence.i + 88: 00000013 nop + 8c: 00000013 nop + 90: 00000013 nop + 94: 00000013 nop + 98: 00000013 nop + 9c: 00000013 nop + a0: 00000013 nop + a4: 00000013 nop + a8: 00000013 nop + ac: 00000013 nop + b0: 00000013 nop + b4: 00000013 nop + b8: 00000013 nop + bc: 00000013 nop + c0: 22b68693 addi a3,a3,555 + +000000c4 : + c4: 00000013 nop + c8: 30900e93 li t4,777 + cc: 00300193 li gp,3 + d0: 01d69463 bne a3,t4,d8 + d4: 00301863 bne zero,gp,e4 + +000000d8 : + d8: 00100d13 li s10,1 + dc: 00000d93 li s11,0 + +000000e0 : + e0: 0000006f j e0 + +000000e4 : + e4: 00100d13 li s10,1 + e8: 00100d93 li s11,1 + +000000ec : + ec: 0000006f j ec + ... + +Disassembly of section .data: + +00001000 : + 1000: 14d68693 addi a3,a3,333 + ... + +Disassembly of section .tohost: + +00001040 : + ... + +00001080 : + ... diff --git a/tests/isa/generated/rv32ui-p-fence_i.verilog b/tests/isa/generated/rv32ui-p-fence_i.verilog new file mode 100644 index 0000000..0f09e58 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-fence_i.verilog @@ -0,0 +1,28 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 06 F0 06 17 15 00 00 +03 15 45 FF 97 15 00 00 83 95 E5 FE 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +97 02 00 00 23 9A A2 00 97 02 00 00 23 97 B2 00 +0F 10 00 00 93 86 E6 0D 13 00 00 00 93 0E C0 1B +93 01 20 00 63 9A D6 07 13 07 40 06 13 07 F7 FF +E3 1E 07 FE 97 02 00 00 23 96 A2 04 97 02 00 00 +23 93 B2 04 0F 10 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +93 86 B6 22 13 00 00 00 93 0E 90 30 93 01 30 00 +63 94 D6 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +@00001000 +93 86 D6 14 00 00 00 00 00 00 00 00 00 00 00 00 +@00001040 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-jal b/tests/isa/generated/rv32ui-p-jal new file mode 100644 index 0000000..af50f62 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-jal differ diff --git a/tests/isa/generated/rv32ui-p-jal.bin b/tests/isa/generated/rv32ui-p-jal.bin new file mode 100644 index 0000000..c9201af Binary files /dev/null and b/tests/isa/generated/rv32ui-p-jal.bin differ diff --git a/tests/isa/generated/rv32ui-p-jal.dump b/tests/isa/generated/rv32ui-p-jal.dump new file mode 100644 index 0000000..e2be4a2 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-jal.dump @@ -0,0 +1,61 @@ + +generated/rv32ui-p-jal: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00200193 li gp,2 + c: 00000093 li ra,0 + 10: 0100026f jal tp,20 + +00000014 : + 14: 00000013 nop + 18: 00000013 nop + 1c: 0400006f j 5c + +00000020 : + 20: 00000117 auipc sp,0x0 + 24: ff410113 addi sp,sp,-12 # 14 + 28: 02411a63 bne sp,tp,5c + +0000002c : + 2c: 00100093 li ra,1 + 30: 0140006f j 44 + 34: 00108093 addi ra,ra,1 + 38: 00108093 addi ra,ra,1 + 3c: 00108093 addi ra,ra,1 + 40: 00108093 addi ra,ra,1 + 44: 00108093 addi ra,ra,1 + 48: 00108093 addi ra,ra,1 + 4c: 00300e93 li t4,3 + 50: 00300193 li gp,3 + 54: 01d09463 bne ra,t4,5c + 58: 00301863 bne zero,gp,68 + +0000005c : + 5c: 00100d13 li s10,1 + 60: 00000d93 li s11,0 + +00000064 : + 64: 0000006f j 64 + +00000068 : + 68: 00100d13 li s10,1 + 6c: 00100d93 li s11,1 + +00000070 : + 70: 0000006f j 70 + ... + +Disassembly of section .tohost: + +000000c0 : + ... + +00000100 : + ... diff --git a/tests/isa/generated/rv32ui-p-jal.verilog b/tests/isa/generated/rv32ui-p-jal.verilog new file mode 100644 index 0000000..729fd9a --- /dev/null +++ b/tests/isa/generated/rv32ui-p-jal.verilog @@ -0,0 +1,16 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 01 20 00 93 00 00 00 +6F 02 00 01 13 00 00 00 13 00 00 00 6F 00 00 04 +17 01 00 00 13 01 41 FF 63 1A 41 02 93 00 10 00 +6F 00 40 01 93 80 10 00 93 80 10 00 93 80 10 00 +93 80 10 00 93 80 10 00 93 80 10 00 93 0E 30 00 +93 01 30 00 63 94 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@000000C0 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-jalr b/tests/isa/generated/rv32ui-p-jalr new file mode 100644 index 0000000..cc7f4ac Binary files /dev/null and b/tests/isa/generated/rv32ui-p-jalr differ diff --git a/tests/isa/generated/rv32ui-p-jalr.bin b/tests/isa/generated/rv32ui-p-jalr.bin new file mode 100644 index 0000000..9f97c67 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-jalr.bin differ diff --git a/tests/isa/generated/rv32ui-p-jalr.dump b/tests/isa/generated/rv32ui-p-jalr.dump new file mode 100644 index 0000000..4db7ea0 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-jalr.dump @@ -0,0 +1,99 @@ + +generated/rv32ui-p-jalr: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00200193 li gp,2 + c: 00000293 li t0,0 + 10: 00000317 auipc t1,0x0 + 14: 01030313 addi t1,t1,16 # 20 + 18: 000302e7 jalr t0,t1 + +0000001c : + 1c: 0c00006f j dc + +00000020 : + 20: 00000317 auipc t1,0x0 + 24: ffc30313 addi t1,t1,-4 # 1c + 28: 0a629a63 bne t0,t1,dc + +0000002c : + 2c: 00400193 li gp,4 + 30: 00000213 li tp,0 + 34: 00000317 auipc t1,0x0 + 38: 01030313 addi t1,t1,16 # 44 + 3c: 000309e7 jalr s3,t1 + 40: 08301e63 bne zero,gp,dc + 44: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 48: 00200293 li t0,2 + 4c: fe5214e3 bne tp,t0,34 + +00000050 : + 50: 00500193 li gp,5 + 54: 00000213 li tp,0 + 58: 00000317 auipc t1,0x0 + 5c: 01430313 addi t1,t1,20 # 6c + 60: 00000013 nop + 64: 000309e7 jalr s3,t1 + 68: 06301a63 bne zero,gp,dc + 6c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 70: 00200293 li t0,2 + 74: fe5212e3 bne tp,t0,58 + +00000078 : + 78: 00600193 li gp,6 + 7c: 00000213 li tp,0 + 80: 00000317 auipc t1,0x0 + 84: 01830313 addi t1,t1,24 # 98 + 88: 00000013 nop + 8c: 00000013 nop + 90: 000309e7 jalr s3,t1 + 94: 04301463 bne zero,gp,dc + 98: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 9c: 00200293 li t0,2 + a0: fe5210e3 bne tp,t0,80 + +000000a4 : + a4: 00100293 li t0,1 + a8: 00000317 auipc t1,0x0 + ac: 01c30313 addi t1,t1,28 # c4 + b0: ffc30067 jr -4(t1) + b4: 00128293 addi t0,t0,1 + b8: 00128293 addi t0,t0,1 + bc: 00128293 addi t0,t0,1 + c0: 00128293 addi t0,t0,1 + c4: 00128293 addi t0,t0,1 + c8: 00128293 addi t0,t0,1 + cc: 00400e93 li t4,4 + d0: 00700193 li gp,7 + d4: 01d29463 bne t0,t4,dc + d8: 00301863 bne zero,gp,e8 + +000000dc : + dc: 00100d13 li s10,1 + e0: 00000d93 li s11,0 + +000000e4 : + e4: 0000006f j e4 + +000000e8 : + e8: 00100d13 li s10,1 + ec: 00100d93 li s11,1 + +000000f0 : + f0: 0000006f j f0 + ... + +Disassembly of section .tohost: + +00000140 : + ... + +00000180 : + ... diff --git a/tests/isa/generated/rv32ui-p-jalr.verilog b/tests/isa/generated/rv32ui-p-jalr.verilog new file mode 100644 index 0000000..8819d6c --- /dev/null +++ b/tests/isa/generated/rv32ui-p-jalr.verilog @@ -0,0 +1,24 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 01 20 00 93 02 00 00 +17 03 00 00 13 03 03 01 E7 02 03 00 6F 00 00 0C +17 03 00 00 13 03 C3 FF 63 9A 62 0A 93 01 40 00 +13 02 00 00 17 03 00 00 13 03 03 01 E7 09 03 00 +63 1E 30 08 13 02 12 00 93 02 20 00 E3 14 52 FE +93 01 50 00 13 02 00 00 17 03 00 00 13 03 43 01 +13 00 00 00 E7 09 03 00 63 1A 30 06 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 60 00 13 02 00 00 +17 03 00 00 13 03 83 01 13 00 00 00 13 00 00 00 +E7 09 03 00 63 14 30 04 13 02 12 00 93 02 20 00 +E3 10 52 FE 93 02 10 00 17 03 00 00 13 03 C3 01 +67 00 C3 FF 93 82 12 00 93 82 12 00 93 82 12 00 +93 82 12 00 93 82 12 00 93 82 12 00 93 0E 40 00 +93 01 70 00 63 94 D2 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000140 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-lb b/tests/isa/generated/rv32ui-p-lb new file mode 100644 index 0000000..0c309ec Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lb differ diff --git a/tests/isa/generated/rv32ui-p-lb.bin b/tests/isa/generated/rv32ui-p-lb.bin new file mode 100644 index 0000000..cb19021 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lb.bin differ diff --git a/tests/isa/generated/rv32ui-p-lb.dump b/tests/isa/generated/rv32ui-p-lb.dump new file mode 100644 index 0000000..32bcefe --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lb.dump @@ -0,0 +1,230 @@ + +generated/rv32ui-p-lb: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00001097 auipc ra,0x1 + c: ff808093 addi ra,ra,-8 # 1000 + 10: 00008f03 lb t5,0(ra) + 14: fff00e93 li t4,-1 + 18: 00200193 li gp,2 + 1c: 23df1c63 bne t5,t4,254 + +00000020 : + 20: 00001097 auipc ra,0x1 + 24: fe008093 addi ra,ra,-32 # 1000 + 28: 00108f03 lb t5,1(ra) + 2c: 00000e93 li t4,0 + 30: 00300193 li gp,3 + 34: 23df1063 bne t5,t4,254 + +00000038 : + 38: 00001097 auipc ra,0x1 + 3c: fc808093 addi ra,ra,-56 # 1000 + 40: 00208f03 lb t5,2(ra) + 44: ff000e93 li t4,-16 + 48: 00400193 li gp,4 + 4c: 21df1463 bne t5,t4,254 + +00000050 : + 50: 00001097 auipc ra,0x1 + 54: fb008093 addi ra,ra,-80 # 1000 + 58: 00308f03 lb t5,3(ra) + 5c: 00f00e93 li t4,15 + 60: 00500193 li gp,5 + 64: 1fdf1863 bne t5,t4,254 + +00000068 : + 68: 00001097 auipc ra,0x1 + 6c: f9b08093 addi ra,ra,-101 # 1003 + 70: ffd08f03 lb t5,-3(ra) + 74: fff00e93 li t4,-1 + 78: 00600193 li gp,6 + 7c: 1ddf1c63 bne t5,t4,254 + +00000080 : + 80: 00001097 auipc ra,0x1 + 84: f8308093 addi ra,ra,-125 # 1003 + 88: ffe08f03 lb t5,-2(ra) + 8c: 00000e93 li t4,0 + 90: 00700193 li gp,7 + 94: 1ddf1063 bne t5,t4,254 + +00000098 : + 98: 00001097 auipc ra,0x1 + 9c: f6b08093 addi ra,ra,-149 # 1003 + a0: fff08f03 lb t5,-1(ra) + a4: ff000e93 li t4,-16 + a8: 00800193 li gp,8 + ac: 1bdf1463 bne t5,t4,254 + +000000b0 : + b0: 00001097 auipc ra,0x1 + b4: f5308093 addi ra,ra,-173 # 1003 + b8: 00008f03 lb t5,0(ra) + bc: 00f00e93 li t4,15 + c0: 00900193 li gp,9 + c4: 19df1863 bne t5,t4,254 + +000000c8 : + c8: 00001097 auipc ra,0x1 + cc: f3808093 addi ra,ra,-200 # 1000 + d0: fe008093 addi ra,ra,-32 + d4: 02008283 lb t0,32(ra) + d8: fff00e93 li t4,-1 + dc: 00a00193 li gp,10 + e0: 17d29a63 bne t0,t4,254 + +000000e4 : + e4: 00001097 auipc ra,0x1 + e8: f1c08093 addi ra,ra,-228 # 1000 + ec: ffa08093 addi ra,ra,-6 + f0: 00708283 lb t0,7(ra) + f4: 00000e93 li t4,0 + f8: 00b00193 li gp,11 + fc: 15d29c63 bne t0,t4,254 + +00000100 : + 100: 00c00193 li gp,12 + 104: 00000213 li tp,0 + 108: 00001097 auipc ra,0x1 + 10c: ef908093 addi ra,ra,-263 # 1001 + 110: 00108f03 lb t5,1(ra) + 114: 000f0313 mv t1,t5 + 118: ff000e93 li t4,-16 + 11c: 13d31c63 bne t1,t4,254 + 120: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 124: 00200293 li t0,2 + 128: fe5210e3 bne tp,t0,108 + +0000012c : + 12c: 00d00193 li gp,13 + 130: 00000213 li tp,0 + 134: 00001097 auipc ra,0x1 + 138: ece08093 addi ra,ra,-306 # 1002 + 13c: 00108f03 lb t5,1(ra) + 140: 00000013 nop + 144: 000f0313 mv t1,t5 + 148: 00f00e93 li t4,15 + 14c: 11d31463 bne t1,t4,254 + 150: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 154: 00200293 li t0,2 + 158: fc521ee3 bne tp,t0,134 + +0000015c : + 15c: 00e00193 li gp,14 + 160: 00000213 li tp,0 + 164: 00001097 auipc ra,0x1 + 168: e9c08093 addi ra,ra,-356 # 1000 + 16c: 00108f03 lb t5,1(ra) + 170: 00000013 nop + 174: 00000013 nop + 178: 000f0313 mv t1,t5 + 17c: 00000e93 li t4,0 + 180: 0dd31a63 bne t1,t4,254 + 184: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 188: 00200293 li t0,2 + 18c: fc521ce3 bne tp,t0,164 + +00000190 : + 190: 00f00193 li gp,15 + 194: 00000213 li tp,0 + 198: 00001097 auipc ra,0x1 + 19c: e6908093 addi ra,ra,-407 # 1001 + 1a0: 00108f03 lb t5,1(ra) + 1a4: ff000e93 li t4,-16 + 1a8: 0bdf1663 bne t5,t4,254 + 1ac: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1b0: 00200293 li t0,2 + 1b4: fe5212e3 bne tp,t0,198 + +000001b8 : + 1b8: 01000193 li gp,16 + 1bc: 00000213 li tp,0 + 1c0: 00001097 auipc ra,0x1 + 1c4: e4208093 addi ra,ra,-446 # 1002 + 1c8: 00000013 nop + 1cc: 00108f03 lb t5,1(ra) + 1d0: 00f00e93 li t4,15 + 1d4: 09df1063 bne t5,t4,254 + 1d8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1dc: 00200293 li t0,2 + 1e0: fe5210e3 bne tp,t0,1c0 + +000001e4 : + 1e4: 01100193 li gp,17 + 1e8: 00000213 li tp,0 + 1ec: 00001097 auipc ra,0x1 + 1f0: e1408093 addi ra,ra,-492 # 1000 + 1f4: 00000013 nop + 1f8: 00000013 nop + 1fc: 00108f03 lb t5,1(ra) + 200: 00000e93 li t4,0 + 204: 05df1863 bne t5,t4,254 + 208: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 20c: 00200293 li t0,2 + 210: fc521ee3 bne tp,t0,1ec + +00000214 : + 214: 00001297 auipc t0,0x1 + 218: dec28293 addi t0,t0,-532 # 1000 + 21c: 00028103 lb sp,0(t0) + 220: 00200113 li sp,2 + 224: 00200e93 li t4,2 + 228: 01200193 li gp,18 + 22c: 03d11463 bne sp,t4,254 + +00000230 : + 230: 00001297 auipc t0,0x1 + 234: dd028293 addi t0,t0,-560 # 1000 + 238: 00028103 lb sp,0(t0) + 23c: 00000013 nop + 240: 00200113 li sp,2 + 244: 00200e93 li t4,2 + 248: 01300193 li gp,19 + 24c: 01d11463 bne sp,t4,254 + 250: 00301863 bne zero,gp,260 + +00000254 : + 254: 00100d13 li s10,1 + 258: 00000d93 li s11,0 + +0000025c : + 25c: 0000006f j 25c + +00000260 : + 260: 00100d13 li s10,1 + 264: 00100d93 li s11,1 + +00000268 : + 268: 0000006f j 268 + ... + +Disassembly of section .data: + +00001000 : + 1000: 0xff + +00001001 : + ... + +00001002 : + 1002: addi a2,sp,988 + +00001003 : + 1003: 0000000f fence unknown,unknown + ... + +Disassembly of section .tohost: + +00001040 : + ... + +00001080 : + ... diff --git a/tests/isa/generated/rv32ui-p-lb.verilog b/tests/isa/generated/rv32ui-p-lb.verilog new file mode 100644 index 0000000..b899467 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lb.verilog @@ -0,0 +1,50 @@ +@00000000 +13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF +03 8F 00 00 93 0E F0 FF 93 01 20 00 63 1C DF 23 +97 10 00 00 93 80 00 FE 03 8F 10 00 93 0E 00 00 +93 01 30 00 63 10 DF 23 97 10 00 00 93 80 80 FC +03 8F 20 00 93 0E 00 FF 93 01 40 00 63 14 DF 21 +97 10 00 00 93 80 00 FB 03 8F 30 00 93 0E F0 00 +93 01 50 00 63 18 DF 1F 97 10 00 00 93 80 B0 F9 +03 8F D0 FF 93 0E F0 FF 93 01 60 00 63 1C DF 1D +97 10 00 00 93 80 30 F8 03 8F E0 FF 93 0E 00 00 +93 01 70 00 63 10 DF 1D 97 10 00 00 93 80 B0 F6 +03 8F F0 FF 93 0E 00 FF 93 01 80 00 63 14 DF 1B +97 10 00 00 93 80 30 F5 03 8F 00 00 93 0E F0 00 +93 01 90 00 63 18 DF 19 97 10 00 00 93 80 80 F3 +93 80 00 FE 83 82 00 02 93 0E F0 FF 93 01 A0 00 +63 9A D2 17 97 10 00 00 93 80 C0 F1 93 80 A0 FF +83 82 70 00 93 0E 00 00 93 01 B0 00 63 9C D2 15 +93 01 C0 00 13 02 00 00 97 10 00 00 93 80 90 EF +03 8F 10 00 13 03 0F 00 93 0E 00 FF 63 1C D3 13 +13 02 12 00 93 02 20 00 E3 10 52 FE 93 01 D0 00 +13 02 00 00 97 10 00 00 93 80 E0 EC 03 8F 10 00 +13 00 00 00 13 03 0F 00 93 0E F0 00 63 14 D3 11 +13 02 12 00 93 02 20 00 E3 1E 52 FC 93 01 E0 00 +13 02 00 00 97 10 00 00 93 80 C0 E9 03 8F 10 00 +13 00 00 00 13 00 00 00 13 03 0F 00 93 0E 00 00 +63 1A D3 0D 13 02 12 00 93 02 20 00 E3 1C 52 FC +93 01 F0 00 13 02 00 00 97 10 00 00 93 80 90 E6 +03 8F 10 00 93 0E 00 FF 63 16 DF 0B 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 00 01 13 02 00 00 +97 10 00 00 93 80 20 E4 13 00 00 00 03 8F 10 00 +93 0E F0 00 63 10 DF 09 13 02 12 00 93 02 20 00 +E3 10 52 FE 93 01 10 01 13 02 00 00 97 10 00 00 +93 80 40 E1 13 00 00 00 13 00 00 00 03 8F 10 00 +93 0E 00 00 63 18 DF 05 13 02 12 00 93 02 20 00 +E3 1E 52 FC 97 12 00 00 93 82 C2 DE 03 81 02 00 +13 01 20 00 93 0E 20 00 93 01 20 01 63 14 D1 03 +97 12 00 00 93 82 02 DD 03 81 02 00 13 00 00 00 +13 01 20 00 93 0E 20 00 93 01 30 01 63 14 D1 01 +63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 +13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00001000 +FF 00 F0 0F 00 00 00 00 00 00 00 00 00 00 00 00 +@00001040 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-lbu b/tests/isa/generated/rv32ui-p-lbu new file mode 100644 index 0000000..a0e07c8 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lbu differ diff --git a/tests/isa/generated/rv32ui-p-lbu.bin b/tests/isa/generated/rv32ui-p-lbu.bin new file mode 100644 index 0000000..0b9410a Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lbu.bin differ diff --git a/tests/isa/generated/rv32ui-p-lbu.dump b/tests/isa/generated/rv32ui-p-lbu.dump new file mode 100644 index 0000000..20d607b --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lbu.dump @@ -0,0 +1,230 @@ + +generated/rv32ui-p-lbu: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00001097 auipc ra,0x1 + c: ff808093 addi ra,ra,-8 # 1000 + 10: 0000cf03 lbu t5,0(ra) + 14: 0ff00e93 li t4,255 + 18: 00200193 li gp,2 + 1c: 23df1c63 bne t5,t4,254 + +00000020 : + 20: 00001097 auipc ra,0x1 + 24: fe008093 addi ra,ra,-32 # 1000 + 28: 0010cf03 lbu t5,1(ra) + 2c: 00000e93 li t4,0 + 30: 00300193 li gp,3 + 34: 23df1063 bne t5,t4,254 + +00000038 : + 38: 00001097 auipc ra,0x1 + 3c: fc808093 addi ra,ra,-56 # 1000 + 40: 0020cf03 lbu t5,2(ra) + 44: 0f000e93 li t4,240 + 48: 00400193 li gp,4 + 4c: 21df1463 bne t5,t4,254 + +00000050 : + 50: 00001097 auipc ra,0x1 + 54: fb008093 addi ra,ra,-80 # 1000 + 58: 0030cf03 lbu t5,3(ra) + 5c: 00f00e93 li t4,15 + 60: 00500193 li gp,5 + 64: 1fdf1863 bne t5,t4,254 + +00000068 : + 68: 00001097 auipc ra,0x1 + 6c: f9b08093 addi ra,ra,-101 # 1003 + 70: ffd0cf03 lbu t5,-3(ra) + 74: 0ff00e93 li t4,255 + 78: 00600193 li gp,6 + 7c: 1ddf1c63 bne t5,t4,254 + +00000080 : + 80: 00001097 auipc ra,0x1 + 84: f8308093 addi ra,ra,-125 # 1003 + 88: ffe0cf03 lbu t5,-2(ra) + 8c: 00000e93 li t4,0 + 90: 00700193 li gp,7 + 94: 1ddf1063 bne t5,t4,254 + +00000098 : + 98: 00001097 auipc ra,0x1 + 9c: f6b08093 addi ra,ra,-149 # 1003 + a0: fff0cf03 lbu t5,-1(ra) + a4: 0f000e93 li t4,240 + a8: 00800193 li gp,8 + ac: 1bdf1463 bne t5,t4,254 + +000000b0 : + b0: 00001097 auipc ra,0x1 + b4: f5308093 addi ra,ra,-173 # 1003 + b8: 0000cf03 lbu t5,0(ra) + bc: 00f00e93 li t4,15 + c0: 00900193 li gp,9 + c4: 19df1863 bne t5,t4,254 + +000000c8 : + c8: 00001097 auipc ra,0x1 + cc: f3808093 addi ra,ra,-200 # 1000 + d0: fe008093 addi ra,ra,-32 + d4: 0200c283 lbu t0,32(ra) + d8: 0ff00e93 li t4,255 + dc: 00a00193 li gp,10 + e0: 17d29a63 bne t0,t4,254 + +000000e4 : + e4: 00001097 auipc ra,0x1 + e8: f1c08093 addi ra,ra,-228 # 1000 + ec: ffa08093 addi ra,ra,-6 + f0: 0070c283 lbu t0,7(ra) + f4: 00000e93 li t4,0 + f8: 00b00193 li gp,11 + fc: 15d29c63 bne t0,t4,254 + +00000100 : + 100: 00c00193 li gp,12 + 104: 00000213 li tp,0 + 108: 00001097 auipc ra,0x1 + 10c: ef908093 addi ra,ra,-263 # 1001 + 110: 0010cf03 lbu t5,1(ra) + 114: 000f0313 mv t1,t5 + 118: 0f000e93 li t4,240 + 11c: 13d31c63 bne t1,t4,254 + 120: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 124: 00200293 li t0,2 + 128: fe5210e3 bne tp,t0,108 + +0000012c : + 12c: 00d00193 li gp,13 + 130: 00000213 li tp,0 + 134: 00001097 auipc ra,0x1 + 138: ece08093 addi ra,ra,-306 # 1002 + 13c: 0010cf03 lbu t5,1(ra) + 140: 00000013 nop + 144: 000f0313 mv t1,t5 + 148: 00f00e93 li t4,15 + 14c: 11d31463 bne t1,t4,254 + 150: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 154: 00200293 li t0,2 + 158: fc521ee3 bne tp,t0,134 + +0000015c : + 15c: 00e00193 li gp,14 + 160: 00000213 li tp,0 + 164: 00001097 auipc ra,0x1 + 168: e9c08093 addi ra,ra,-356 # 1000 + 16c: 0010cf03 lbu t5,1(ra) + 170: 00000013 nop + 174: 00000013 nop + 178: 000f0313 mv t1,t5 + 17c: 00000e93 li t4,0 + 180: 0dd31a63 bne t1,t4,254 + 184: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 188: 00200293 li t0,2 + 18c: fc521ce3 bne tp,t0,164 + +00000190 : + 190: 00f00193 li gp,15 + 194: 00000213 li tp,0 + 198: 00001097 auipc ra,0x1 + 19c: e6908093 addi ra,ra,-407 # 1001 + 1a0: 0010cf03 lbu t5,1(ra) + 1a4: 0f000e93 li t4,240 + 1a8: 0bdf1663 bne t5,t4,254 + 1ac: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1b0: 00200293 li t0,2 + 1b4: fe5212e3 bne tp,t0,198 + +000001b8 : + 1b8: 01000193 li gp,16 + 1bc: 00000213 li tp,0 + 1c0: 00001097 auipc ra,0x1 + 1c4: e4208093 addi ra,ra,-446 # 1002 + 1c8: 00000013 nop + 1cc: 0010cf03 lbu t5,1(ra) + 1d0: 00f00e93 li t4,15 + 1d4: 09df1063 bne t5,t4,254 + 1d8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1dc: 00200293 li t0,2 + 1e0: fe5210e3 bne tp,t0,1c0 + +000001e4 : + 1e4: 01100193 li gp,17 + 1e8: 00000213 li tp,0 + 1ec: 00001097 auipc ra,0x1 + 1f0: e1408093 addi ra,ra,-492 # 1000 + 1f4: 00000013 nop + 1f8: 00000013 nop + 1fc: 0010cf03 lbu t5,1(ra) + 200: 00000e93 li t4,0 + 204: 05df1863 bne t5,t4,254 + 208: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 20c: 00200293 li t0,2 + 210: fc521ee3 bne tp,t0,1ec + +00000214 : + 214: 00001297 auipc t0,0x1 + 218: dec28293 addi t0,t0,-532 # 1000 + 21c: 0002c103 lbu sp,0(t0) + 220: 00200113 li sp,2 + 224: 00200e93 li t4,2 + 228: 01200193 li gp,18 + 22c: 03d11463 bne sp,t4,254 + +00000230 : + 230: 00001297 auipc t0,0x1 + 234: dd028293 addi t0,t0,-560 # 1000 + 238: 0002c103 lbu sp,0(t0) + 23c: 00000013 nop + 240: 00200113 li sp,2 + 244: 00200e93 li t4,2 + 248: 01300193 li gp,19 + 24c: 01d11463 bne sp,t4,254 + 250: 00301863 bne zero,gp,260 + +00000254 : + 254: 00100d13 li s10,1 + 258: 00000d93 li s11,0 + +0000025c : + 25c: 0000006f j 25c + +00000260 : + 260: 00100d13 li s10,1 + 264: 00100d93 li s11,1 + +00000268 : + 268: 0000006f j 268 + ... + +Disassembly of section .data: + +00001000 : + 1000: 0xff + +00001001 : + ... + +00001002 : + 1002: addi a2,sp,988 + +00001003 : + 1003: 0000000f fence unknown,unknown + ... + +Disassembly of section .tohost: + +00001040 : + ... + +00001080 : + ... diff --git a/tests/isa/generated/rv32ui-p-lbu.verilog b/tests/isa/generated/rv32ui-p-lbu.verilog new file mode 100644 index 0000000..23d1169 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lbu.verilog @@ -0,0 +1,50 @@ +@00000000 +13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF +03 CF 00 00 93 0E F0 0F 93 01 20 00 63 1C DF 23 +97 10 00 00 93 80 00 FE 03 CF 10 00 93 0E 00 00 +93 01 30 00 63 10 DF 23 97 10 00 00 93 80 80 FC +03 CF 20 00 93 0E 00 0F 93 01 40 00 63 14 DF 21 +97 10 00 00 93 80 00 FB 03 CF 30 00 93 0E F0 00 +93 01 50 00 63 18 DF 1F 97 10 00 00 93 80 B0 F9 +03 CF D0 FF 93 0E F0 0F 93 01 60 00 63 1C DF 1D +97 10 00 00 93 80 30 F8 03 CF E0 FF 93 0E 00 00 +93 01 70 00 63 10 DF 1D 97 10 00 00 93 80 B0 F6 +03 CF F0 FF 93 0E 00 0F 93 01 80 00 63 14 DF 1B +97 10 00 00 93 80 30 F5 03 CF 00 00 93 0E F0 00 +93 01 90 00 63 18 DF 19 97 10 00 00 93 80 80 F3 +93 80 00 FE 83 C2 00 02 93 0E F0 0F 93 01 A0 00 +63 9A D2 17 97 10 00 00 93 80 C0 F1 93 80 A0 FF +83 C2 70 00 93 0E 00 00 93 01 B0 00 63 9C D2 15 +93 01 C0 00 13 02 00 00 97 10 00 00 93 80 90 EF +03 CF 10 00 13 03 0F 00 93 0E 00 0F 63 1C D3 13 +13 02 12 00 93 02 20 00 E3 10 52 FE 93 01 D0 00 +13 02 00 00 97 10 00 00 93 80 E0 EC 03 CF 10 00 +13 00 00 00 13 03 0F 00 93 0E F0 00 63 14 D3 11 +13 02 12 00 93 02 20 00 E3 1E 52 FC 93 01 E0 00 +13 02 00 00 97 10 00 00 93 80 C0 E9 03 CF 10 00 +13 00 00 00 13 00 00 00 13 03 0F 00 93 0E 00 00 +63 1A D3 0D 13 02 12 00 93 02 20 00 E3 1C 52 FC +93 01 F0 00 13 02 00 00 97 10 00 00 93 80 90 E6 +03 CF 10 00 93 0E 00 0F 63 16 DF 0B 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 01 00 01 13 02 00 00 +97 10 00 00 93 80 20 E4 13 00 00 00 03 CF 10 00 +93 0E F0 00 63 10 DF 09 13 02 12 00 93 02 20 00 +E3 10 52 FE 93 01 10 01 13 02 00 00 97 10 00 00 +93 80 40 E1 13 00 00 00 13 00 00 00 03 CF 10 00 +93 0E 00 00 63 18 DF 05 13 02 12 00 93 02 20 00 +E3 1E 52 FC 97 12 00 00 93 82 C2 DE 03 C1 02 00 +13 01 20 00 93 0E 20 00 93 01 20 01 63 14 D1 03 +97 12 00 00 93 82 02 DD 03 C1 02 00 13 00 00 00 +13 01 20 00 93 0E 20 00 93 01 30 01 63 14 D1 01 +63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 +13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00001000 +FF 00 F0 0F 00 00 00 00 00 00 00 00 00 00 00 00 +@00001040 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-lh b/tests/isa/generated/rv32ui-p-lh new file mode 100644 index 0000000..674ea1b Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lh differ diff --git a/tests/isa/generated/rv32ui-p-lh.bin b/tests/isa/generated/rv32ui-p-lh.bin new file mode 100644 index 0000000..9d856be Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lh.bin differ diff --git a/tests/isa/generated/rv32ui-p-lh.dump b/tests/isa/generated/rv32ui-p-lh.dump new file mode 100644 index 0000000..c72f573 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lh.dump @@ -0,0 +1,240 @@ + +generated/rv32ui-p-lh: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00001097 auipc ra,0x1 + c: ff808093 addi ra,ra,-8 # 1000 + 10: 00009f03 lh t5,0(ra) + 14: 0ff00e93 li t4,255 + 18: 00200193 li gp,2 + 1c: 25df1c63 bne t5,t4,274 + +00000020 : + 20: 00001097 auipc ra,0x1 + 24: fe008093 addi ra,ra,-32 # 1000 + 28: 00209f03 lh t5,2(ra) + 2c: f0000e93 li t4,-256 + 30: 00300193 li gp,3 + 34: 25df1063 bne t5,t4,274 + +00000038 : + 38: 00001097 auipc ra,0x1 + 3c: fc808093 addi ra,ra,-56 # 1000 + 40: 00409f03 lh t5,4(ra) + 44: 00001eb7 lui t4,0x1 + 48: ff0e8e93 addi t4,t4,-16 # ff0 + 4c: 00400193 li gp,4 + 50: 23df1263 bne t5,t4,274 + +00000054 : + 54: 00001097 auipc ra,0x1 + 58: fac08093 addi ra,ra,-84 # 1000 + 5c: 00609f03 lh t5,6(ra) + 60: fffffeb7 lui t4,0xfffff + 64: 00fe8e93 addi t4,t4,15 # fffff00f <_end+0xffffdf87> + 68: 00500193 li gp,5 + 6c: 21df1463 bne t5,t4,274 + +00000070 : + 70: 00001097 auipc ra,0x1 + 74: f9608093 addi ra,ra,-106 # 1006 + 78: ffa09f03 lh t5,-6(ra) + 7c: 0ff00e93 li t4,255 + 80: 00600193 li gp,6 + 84: 1fdf1863 bne t5,t4,274 + +00000088 : + 88: 00001097 auipc ra,0x1 + 8c: f7e08093 addi ra,ra,-130 # 1006 + 90: ffc09f03 lh t5,-4(ra) + 94: f0000e93 li t4,-256 + 98: 00700193 li gp,7 + 9c: 1ddf1c63 bne t5,t4,274 + +000000a0 : + a0: 00001097 auipc ra,0x1 + a4: f6608093 addi ra,ra,-154 # 1006 + a8: ffe09f03 lh t5,-2(ra) + ac: 00001eb7 lui t4,0x1 + b0: ff0e8e93 addi t4,t4,-16 # ff0 + b4: 00800193 li gp,8 + b8: 1bdf1e63 bne t5,t4,274 + +000000bc : + bc: 00001097 auipc ra,0x1 + c0: f4a08093 addi ra,ra,-182 # 1006 + c4: 00009f03 lh t5,0(ra) + c8: fffffeb7 lui t4,0xfffff + cc: 00fe8e93 addi t4,t4,15 # fffff00f <_end+0xffffdf87> + d0: 00900193 li gp,9 + d4: 1bdf1063 bne t5,t4,274 + +000000d8 : + d8: 00001097 auipc ra,0x1 + dc: f2808093 addi ra,ra,-216 # 1000 + e0: fe008093 addi ra,ra,-32 + e4: 02009283 lh t0,32(ra) + e8: 0ff00e93 li t4,255 + ec: 00a00193 li gp,10 + f0: 19d29263 bne t0,t4,274 + +000000f4 : + f4: 00001097 auipc ra,0x1 + f8: f0c08093 addi ra,ra,-244 # 1000 + fc: ffb08093 addi ra,ra,-5 + 100: 00709283 lh t0,7(ra) + 104: f0000e93 li t4,-256 + 108: 00b00193 li gp,11 + 10c: 17d29463 bne t0,t4,274 + +00000110 : + 110: 00c00193 li gp,12 + 114: 00000213 li tp,0 + 118: 00001097 auipc ra,0x1 + 11c: eea08093 addi ra,ra,-278 # 1002 + 120: 00209f03 lh t5,2(ra) + 124: 000f0313 mv t1,t5 + 128: 00001eb7 lui t4,0x1 + 12c: ff0e8e93 addi t4,t4,-16 # ff0 + 130: 15d31263 bne t1,t4,274 + 134: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 138: 00200293 li t0,2 + 13c: fc521ee3 bne tp,t0,118 + +00000140 : + 140: 00d00193 li gp,13 + 144: 00000213 li tp,0 + 148: 00001097 auipc ra,0x1 + 14c: ebc08093 addi ra,ra,-324 # 1004 + 150: 00209f03 lh t5,2(ra) + 154: 00000013 nop + 158: 000f0313 mv t1,t5 + 15c: fffffeb7 lui t4,0xfffff + 160: 00fe8e93 addi t4,t4,15 # fffff00f <_end+0xffffdf87> + 164: 11d31863 bne t1,t4,274 + 168: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 16c: 00200293 li t0,2 + 170: fc521ce3 bne tp,t0,148 + +00000174 : + 174: 00e00193 li gp,14 + 178: 00000213 li tp,0 + 17c: 00001097 auipc ra,0x1 + 180: e8408093 addi ra,ra,-380 # 1000 + 184: 00209f03 lh t5,2(ra) + 188: 00000013 nop + 18c: 00000013 nop + 190: 000f0313 mv t1,t5 + 194: f0000e93 li t4,-256 + 198: 0dd31e63 bne t1,t4,274 + 19c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1a0: 00200293 li t0,2 + 1a4: fc521ce3 bne tp,t0,17c + +000001a8 : + 1a8: 00f00193 li gp,15 + 1ac: 00000213 li tp,0 + 1b0: 00001097 auipc ra,0x1 + 1b4: e5208093 addi ra,ra,-430 # 1002 + 1b8: 00209f03 lh t5,2(ra) + 1bc: 00001eb7 lui t4,0x1 + 1c0: ff0e8e93 addi t4,t4,-16 # ff0 + 1c4: 0bdf1863 bne t5,t4,274 + 1c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1cc: 00200293 li t0,2 + 1d0: fe5210e3 bne tp,t0,1b0 + +000001d4 : + 1d4: 01000193 li gp,16 + 1d8: 00000213 li tp,0 + 1dc: 00001097 auipc ra,0x1 + 1e0: e2808093 addi ra,ra,-472 # 1004 + 1e4: 00000013 nop + 1e8: 00209f03 lh t5,2(ra) + 1ec: fffffeb7 lui t4,0xfffff + 1f0: 00fe8e93 addi t4,t4,15 # fffff00f <_end+0xffffdf87> + 1f4: 09df1063 bne t5,t4,274 + 1f8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1fc: 00200293 li t0,2 + 200: fc521ee3 bne tp,t0,1dc + +00000204 : + 204: 01100193 li gp,17 + 208: 00000213 li tp,0 + 20c: 00001097 auipc ra,0x1 + 210: df408093 addi ra,ra,-524 # 1000 + 214: 00000013 nop + 218: 00000013 nop + 21c: 00209f03 lh t5,2(ra) + 220: f0000e93 li t4,-256 + 224: 05df1863 bne t5,t4,274 + 228: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 22c: 00200293 li t0,2 + 230: fc521ee3 bne tp,t0,20c + +00000234 : + 234: 00001297 auipc t0,0x1 + 238: dcc28293 addi t0,t0,-564 # 1000 + 23c: 00029103 lh sp,0(t0) + 240: 00200113 li sp,2 + 244: 00200e93 li t4,2 + 248: 01200193 li gp,18 + 24c: 03d11463 bne sp,t4,274 + +00000250 : + 250: 00001297 auipc t0,0x1 + 254: db028293 addi t0,t0,-592 # 1000 + 258: 00029103 lh sp,0(t0) + 25c: 00000013 nop + 260: 00200113 li sp,2 + 264: 00200e93 li t4,2 + 268: 01300193 li gp,19 + 26c: 01d11463 bne sp,t4,274 + 270: 00301863 bne zero,gp,280 + +00000274 : + 274: 00100d13 li s10,1 + 278: 00000d93 li s11,0 + +0000027c : + 27c: 0000006f j 27c + +00000280 : + 280: 00100d13 li s10,1 + 284: 00100d93 li s11,1 + +00000288 : + 288: 0000006f j 288 + ... + +Disassembly of section .data: + +00001000 : + 1000: 00ff 0xff + +00001002 : + 1002: ff00 fsw fs0,56(a4) + +00001004 : + 1004: 0ff0 addi a2,sp,988 + +00001006 : + 1006: 0000f00f 0xf00f + 100a: 0000 unimp + 100c: 0000 unimp + ... + +Disassembly of section .tohost: + +00001040 : + ... + +00001080 : + ... diff --git a/tests/isa/generated/rv32ui-p-lh.verilog b/tests/isa/generated/rv32ui-p-lh.verilog new file mode 100644 index 0000000..eeadcd4 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lh.verilog @@ -0,0 +1,54 @@ +@00000000 +13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF +03 9F 00 00 93 0E F0 0F 93 01 20 00 63 1C DF 25 +97 10 00 00 93 80 00 FE 03 9F 20 00 93 0E 00 F0 +93 01 30 00 63 10 DF 25 97 10 00 00 93 80 80 FC +03 9F 40 00 B7 1E 00 00 93 8E 0E FF 93 01 40 00 +63 12 DF 23 97 10 00 00 93 80 C0 FA 03 9F 60 00 +B7 FE FF FF 93 8E FE 00 93 01 50 00 63 14 DF 21 +97 10 00 00 93 80 60 F9 03 9F A0 FF 93 0E F0 0F +93 01 60 00 63 18 DF 1F 97 10 00 00 93 80 E0 F7 +03 9F C0 FF 93 0E 00 F0 93 01 70 00 63 1C DF 1D +97 10 00 00 93 80 60 F6 03 9F E0 FF B7 1E 00 00 +93 8E 0E FF 93 01 80 00 63 1E DF 1B 97 10 00 00 +93 80 A0 F4 03 9F 00 00 B7 FE FF FF 93 8E FE 00 +93 01 90 00 63 10 DF 1B 97 10 00 00 93 80 80 F2 +93 80 00 FE 83 92 00 02 93 0E F0 0F 93 01 A0 00 +63 92 D2 19 97 10 00 00 93 80 C0 F0 93 80 B0 FF +83 92 70 00 93 0E 00 F0 93 01 B0 00 63 94 D2 17 +93 01 C0 00 13 02 00 00 97 10 00 00 93 80 A0 EE +03 9F 20 00 13 03 0F 00 B7 1E 00 00 93 8E 0E FF +63 12 D3 15 13 02 12 00 93 02 20 00 E3 1E 52 FC +93 01 D0 00 13 02 00 00 97 10 00 00 93 80 C0 EB +03 9F 20 00 13 00 00 00 13 03 0F 00 B7 FE FF FF +93 8E FE 00 63 18 D3 11 13 02 12 00 93 02 20 00 +E3 1C 52 FC 93 01 E0 00 13 02 00 00 97 10 00 00 +93 80 40 E8 03 9F 20 00 13 00 00 00 13 00 00 00 +13 03 0F 00 93 0E 00 F0 63 1E D3 0D 13 02 12 00 +93 02 20 00 E3 1C 52 FC 93 01 F0 00 13 02 00 00 +97 10 00 00 93 80 20 E5 03 9F 20 00 B7 1E 00 00 +93 8E 0E FF 63 18 DF 0B 13 02 12 00 93 02 20 00 +E3 10 52 FE 93 01 00 01 13 02 00 00 97 10 00 00 +93 80 80 E2 13 00 00 00 03 9F 20 00 B7 FE FF FF +93 8E FE 00 63 10 DF 09 13 02 12 00 93 02 20 00 +E3 1E 52 FC 93 01 10 01 13 02 00 00 97 10 00 00 +93 80 40 DF 13 00 00 00 13 00 00 00 03 9F 20 00 +93 0E 00 F0 63 18 DF 05 13 02 12 00 93 02 20 00 +E3 1E 52 FC 97 12 00 00 93 82 C2 DC 03 91 02 00 +13 01 20 00 93 0E 20 00 93 01 20 01 63 14 D1 03 +97 12 00 00 93 82 02 DB 03 91 02 00 13 00 00 00 +13 01 20 00 93 0E 20 00 93 01 30 01 63 14 D1 01 +63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 +13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00001000 +FF 00 00 FF F0 0F 0F F0 00 00 00 00 00 00 00 00 +@00001040 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-lhu b/tests/isa/generated/rv32ui-p-lhu new file mode 100644 index 0000000..96487ff Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lhu differ diff --git a/tests/isa/generated/rv32ui-p-lhu.bin b/tests/isa/generated/rv32ui-p-lhu.bin new file mode 100644 index 0000000..653b25b Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lhu.bin differ diff --git a/tests/isa/generated/rv32ui-p-lhu.dump b/tests/isa/generated/rv32ui-p-lhu.dump new file mode 100644 index 0000000..0bfa1f3 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lhu.dump @@ -0,0 +1,245 @@ + +generated/rv32ui-p-lhu: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00001097 auipc ra,0x1 + c: ff808093 addi ra,ra,-8 # 1000 + 10: 0000df03 lhu t5,0(ra) + 14: 0ff00e93 li t4,255 + 18: 00200193 li gp,2 + 1c: 27df1663 bne t5,t4,288 + +00000020 : + 20: 00001097 auipc ra,0x1 + 24: fe008093 addi ra,ra,-32 # 1000 + 28: 0020df03 lhu t5,2(ra) + 2c: 00010eb7 lui t4,0x10 + 30: f00e8e93 addi t4,t4,-256 # ff00 <_end+0xee78> + 34: 00300193 li gp,3 + 38: 25df1863 bne t5,t4,288 + +0000003c : + 3c: 00001097 auipc ra,0x1 + 40: fc408093 addi ra,ra,-60 # 1000 + 44: 0040df03 lhu t5,4(ra) + 48: 00001eb7 lui t4,0x1 + 4c: ff0e8e93 addi t4,t4,-16 # ff0 + 50: 00400193 li gp,4 + 54: 23df1a63 bne t5,t4,288 + +00000058 : + 58: 00001097 auipc ra,0x1 + 5c: fa808093 addi ra,ra,-88 # 1000 + 60: 0060df03 lhu t5,6(ra) + 64: 0000feb7 lui t4,0xf + 68: 00fe8e93 addi t4,t4,15 # f00f <_end+0xdf87> + 6c: 00500193 li gp,5 + 70: 21df1c63 bne t5,t4,288 + +00000074 : + 74: 00001097 auipc ra,0x1 + 78: f9208093 addi ra,ra,-110 # 1006 + 7c: ffa0df03 lhu t5,-6(ra) + 80: 0ff00e93 li t4,255 + 84: 00600193 li gp,6 + 88: 21df1063 bne t5,t4,288 + +0000008c : + 8c: 00001097 auipc ra,0x1 + 90: f7a08093 addi ra,ra,-134 # 1006 + 94: ffc0df03 lhu t5,-4(ra) + 98: 00010eb7 lui t4,0x10 + 9c: f00e8e93 addi t4,t4,-256 # ff00 <_end+0xee78> + a0: 00700193 li gp,7 + a4: 1fdf1263 bne t5,t4,288 + +000000a8 : + a8: 00001097 auipc ra,0x1 + ac: f5e08093 addi ra,ra,-162 # 1006 + b0: ffe0df03 lhu t5,-2(ra) + b4: 00001eb7 lui t4,0x1 + b8: ff0e8e93 addi t4,t4,-16 # ff0 + bc: 00800193 li gp,8 + c0: 1ddf1463 bne t5,t4,288 + +000000c4 : + c4: 00001097 auipc ra,0x1 + c8: f4208093 addi ra,ra,-190 # 1006 + cc: 0000df03 lhu t5,0(ra) + d0: 0000feb7 lui t4,0xf + d4: 00fe8e93 addi t4,t4,15 # f00f <_end+0xdf87> + d8: 00900193 li gp,9 + dc: 1bdf1663 bne t5,t4,288 + +000000e0 : + e0: 00001097 auipc ra,0x1 + e4: f2008093 addi ra,ra,-224 # 1000 + e8: fe008093 addi ra,ra,-32 + ec: 0200d283 lhu t0,32(ra) + f0: 0ff00e93 li t4,255 + f4: 00a00193 li gp,10 + f8: 19d29863 bne t0,t4,288 + +000000fc : + fc: 00001097 auipc ra,0x1 + 100: f0408093 addi ra,ra,-252 # 1000 + 104: ffb08093 addi ra,ra,-5 + 108: 0070d283 lhu t0,7(ra) + 10c: 00010eb7 lui t4,0x10 + 110: f00e8e93 addi t4,t4,-256 # ff00 <_end+0xee78> + 114: 00b00193 li gp,11 + 118: 17d29863 bne t0,t4,288 + +0000011c : + 11c: 00c00193 li gp,12 + 120: 00000213 li tp,0 + 124: 00001097 auipc ra,0x1 + 128: ede08093 addi ra,ra,-290 # 1002 + 12c: 0020df03 lhu t5,2(ra) + 130: 000f0313 mv t1,t5 + 134: 00001eb7 lui t4,0x1 + 138: ff0e8e93 addi t4,t4,-16 # ff0 + 13c: 15d31663 bne t1,t4,288 + 140: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 144: 00200293 li t0,2 + 148: fc521ee3 bne tp,t0,124 + +0000014c : + 14c: 00d00193 li gp,13 + 150: 00000213 li tp,0 + 154: 00001097 auipc ra,0x1 + 158: eb008093 addi ra,ra,-336 # 1004 + 15c: 0020df03 lhu t5,2(ra) + 160: 00000013 nop + 164: 000f0313 mv t1,t5 + 168: 0000feb7 lui t4,0xf + 16c: 00fe8e93 addi t4,t4,15 # f00f <_end+0xdf87> + 170: 11d31c63 bne t1,t4,288 + 174: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 178: 00200293 li t0,2 + 17c: fc521ce3 bne tp,t0,154 + +00000180 : + 180: 00e00193 li gp,14 + 184: 00000213 li tp,0 + 188: 00001097 auipc ra,0x1 + 18c: e7808093 addi ra,ra,-392 # 1000 + 190: 0020df03 lhu t5,2(ra) + 194: 00000013 nop + 198: 00000013 nop + 19c: 000f0313 mv t1,t5 + 1a0: 00010eb7 lui t4,0x10 + 1a4: f00e8e93 addi t4,t4,-256 # ff00 <_end+0xee78> + 1a8: 0fd31063 bne t1,t4,288 + 1ac: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1b0: 00200293 li t0,2 + 1b4: fc521ae3 bne tp,t0,188 + +000001b8 : + 1b8: 00f00193 li gp,15 + 1bc: 00000213 li tp,0 + 1c0: 00001097 auipc ra,0x1 + 1c4: e4208093 addi ra,ra,-446 # 1002 + 1c8: 0020df03 lhu t5,2(ra) + 1cc: 00001eb7 lui t4,0x1 + 1d0: ff0e8e93 addi t4,t4,-16 # ff0 + 1d4: 0bdf1a63 bne t5,t4,288 + 1d8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1dc: 00200293 li t0,2 + 1e0: fe5210e3 bne tp,t0,1c0 + +000001e4 : + 1e4: 01000193 li gp,16 + 1e8: 00000213 li tp,0 + 1ec: 00001097 auipc ra,0x1 + 1f0: e1808093 addi ra,ra,-488 # 1004 + 1f4: 00000013 nop + 1f8: 0020df03 lhu t5,2(ra) + 1fc: 0000feb7 lui t4,0xf + 200: 00fe8e93 addi t4,t4,15 # f00f <_end+0xdf87> + 204: 09df1263 bne t5,t4,288 + 208: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 20c: 00200293 li t0,2 + 210: fc521ee3 bne tp,t0,1ec + +00000214 : + 214: 01100193 li gp,17 + 218: 00000213 li tp,0 + 21c: 00001097 auipc ra,0x1 + 220: de408093 addi ra,ra,-540 # 1000 + 224: 00000013 nop + 228: 00000013 nop + 22c: 0020df03 lhu t5,2(ra) + 230: 00010eb7 lui t4,0x10 + 234: f00e8e93 addi t4,t4,-256 # ff00 <_end+0xee78> + 238: 05df1863 bne t5,t4,288 + 23c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 240: 00200293 li t0,2 + 244: fc521ce3 bne tp,t0,21c + +00000248 : + 248: 00001297 auipc t0,0x1 + 24c: db828293 addi t0,t0,-584 # 1000 + 250: 0002d103 lhu sp,0(t0) + 254: 00200113 li sp,2 + 258: 00200e93 li t4,2 + 25c: 01200193 li gp,18 + 260: 03d11463 bne sp,t4,288 + +00000264 : + 264: 00001297 auipc t0,0x1 + 268: d9c28293 addi t0,t0,-612 # 1000 + 26c: 0002d103 lhu sp,0(t0) + 270: 00000013 nop + 274: 00200113 li sp,2 + 278: 00200e93 li t4,2 + 27c: 01300193 li gp,19 + 280: 01d11463 bne sp,t4,288 + 284: 00301863 bne zero,gp,294 + +00000288 : + 288: 00100d13 li s10,1 + 28c: 00000d93 li s11,0 + +00000290 : + 290: 0000006f j 290 + +00000294 : + 294: 00100d13 li s10,1 + 298: 00100d93 li s11,1 + +0000029c : + 29c: 0000006f j 29c + ... + +Disassembly of section .data: + +00001000 : + 1000: 00ff 0xff + +00001002 : + 1002: ff00 fsw fs0,56(a4) + +00001004 : + 1004: 0ff0 addi a2,sp,988 + +00001006 : + 1006: 0000f00f 0xf00f + 100a: 0000 unimp + 100c: 0000 unimp + ... + +Disassembly of section .tohost: + +00001040 : + ... + +00001080 : + ... diff --git a/tests/isa/generated/rv32ui-p-lhu.verilog b/tests/isa/generated/rv32ui-p-lhu.verilog new file mode 100644 index 0000000..18961d7 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lhu.verilog @@ -0,0 +1,54 @@ +@00000000 +13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF +03 DF 00 00 93 0E F0 0F 93 01 20 00 63 16 DF 27 +97 10 00 00 93 80 00 FE 03 DF 20 00 B7 0E 01 00 +93 8E 0E F0 93 01 30 00 63 18 DF 25 97 10 00 00 +93 80 40 FC 03 DF 40 00 B7 1E 00 00 93 8E 0E FF +93 01 40 00 63 1A DF 23 97 10 00 00 93 80 80 FA +03 DF 60 00 B7 FE 00 00 93 8E FE 00 93 01 50 00 +63 1C DF 21 97 10 00 00 93 80 20 F9 03 DF A0 FF +93 0E F0 0F 93 01 60 00 63 10 DF 21 97 10 00 00 +93 80 A0 F7 03 DF C0 FF B7 0E 01 00 93 8E 0E F0 +93 01 70 00 63 12 DF 1F 97 10 00 00 93 80 E0 F5 +03 DF E0 FF B7 1E 00 00 93 8E 0E FF 93 01 80 00 +63 14 DF 1D 97 10 00 00 93 80 20 F4 03 DF 00 00 +B7 FE 00 00 93 8E FE 00 93 01 90 00 63 16 DF 1B +97 10 00 00 93 80 00 F2 93 80 00 FE 83 D2 00 02 +93 0E F0 0F 93 01 A0 00 63 98 D2 19 97 10 00 00 +93 80 40 F0 93 80 B0 FF 83 D2 70 00 B7 0E 01 00 +93 8E 0E F0 93 01 B0 00 63 98 D2 17 93 01 C0 00 +13 02 00 00 97 10 00 00 93 80 E0 ED 03 DF 20 00 +13 03 0F 00 B7 1E 00 00 93 8E 0E FF 63 16 D3 15 +13 02 12 00 93 02 20 00 E3 1E 52 FC 93 01 D0 00 +13 02 00 00 97 10 00 00 93 80 00 EB 03 DF 20 00 +13 00 00 00 13 03 0F 00 B7 FE 00 00 93 8E FE 00 +63 1C D3 11 13 02 12 00 93 02 20 00 E3 1C 52 FC +93 01 E0 00 13 02 00 00 97 10 00 00 93 80 80 E7 +03 DF 20 00 13 00 00 00 13 00 00 00 13 03 0F 00 +B7 0E 01 00 93 8E 0E F0 63 10 D3 0F 13 02 12 00 +93 02 20 00 E3 1A 52 FC 93 01 F0 00 13 02 00 00 +97 10 00 00 93 80 20 E4 03 DF 20 00 B7 1E 00 00 +93 8E 0E FF 63 1A DF 0B 13 02 12 00 93 02 20 00 +E3 10 52 FE 93 01 00 01 13 02 00 00 97 10 00 00 +93 80 80 E1 13 00 00 00 03 DF 20 00 B7 FE 00 00 +93 8E FE 00 63 12 DF 09 13 02 12 00 93 02 20 00 +E3 1E 52 FC 93 01 10 01 13 02 00 00 97 10 00 00 +93 80 40 DE 13 00 00 00 13 00 00 00 03 DF 20 00 +B7 0E 01 00 93 8E 0E F0 63 18 DF 05 13 02 12 00 +93 02 20 00 E3 1C 52 FC 97 12 00 00 93 82 82 DB +03 D1 02 00 13 01 20 00 93 0E 20 00 93 01 20 01 +63 14 D1 03 97 12 00 00 93 82 C2 D9 03 D1 02 00 +13 00 00 00 13 01 20 00 93 0E 20 00 93 01 30 01 +63 14 D1 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00001000 +FF 00 00 FF F0 0F 0F F0 00 00 00 00 00 00 00 00 +@00001040 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-lui b/tests/isa/generated/rv32ui-p-lui new file mode 100644 index 0000000..01d9e81 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lui differ diff --git a/tests/isa/generated/rv32ui-p-lui.bin b/tests/isa/generated/rv32ui-p-lui.bin new file mode 100644 index 0000000..7c7eb79 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lui.bin differ diff --git a/tests/isa/generated/rv32ui-p-lui.dump b/tests/isa/generated/rv32ui-p-lui.dump new file mode 100644 index 0000000..7bfdb46 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lui.dump @@ -0,0 +1,67 @@ + +generated/rv32ui-p-lui: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 000000b7 lui ra,0x0 + c: 00000e93 li t4,0 + 10: 00200193 li gp,2 + 14: 05d09a63 bne ra,t4,68 + +00000018 : + 18: fffff0b7 lui ra,0xfffff + 1c: 4010d093 srai ra,ra,0x1 + 20: 80000e93 li t4,-2048 + 24: 00300193 li gp,3 + 28: 05d09063 bne ra,t4,68 + +0000002c : + 2c: 7ffff0b7 lui ra,0x7ffff + 30: 4140d093 srai ra,ra,0x14 + 34: 7ff00e93 li t4,2047 + 38: 00400193 li gp,4 + 3c: 03d09663 bne ra,t4,68 + +00000040 : + 40: 800000b7 lui ra,0x80000 + 44: 4140d093 srai ra,ra,0x14 + 48: 80000e93 li t4,-2048 + 4c: 00500193 li gp,5 + 50: 01d09c63 bne ra,t4,68 + +00000054 : + 54: 80000037 lui zero,0x80000 + 58: 00000e93 li t4,0 + 5c: 00600193 li gp,6 + 60: 01d01463 bne zero,t4,68 + 64: 00301863 bne zero,gp,74 + +00000068 : + 68: 00100d13 li s10,1 + 6c: 00000d93 li s11,0 + +00000070 : + 70: 0000006f j 70 + +00000074 : + 74: 00100d13 li s10,1 + 78: 00100d93 li s11,1 + +0000007c : + 7c: 0000006f j 7c + 80: 0000 unimp + ... + +Disassembly of section .tohost: + +000000c0 : + ... + +00000100 : + ... diff --git a/tests/isa/generated/rv32ui-p-lui.verilog b/tests/isa/generated/rv32ui-p-lui.verilog new file mode 100644 index 0000000..d6392c3 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lui.verilog @@ -0,0 +1,16 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 00 00 00 93 0E 00 00 +93 01 20 00 63 9A D0 05 B7 F0 FF FF 93 D0 10 40 +93 0E 00 80 93 01 30 00 63 90 D0 05 B7 F0 FF 7F +93 D0 40 41 93 0E F0 7F 93 01 40 00 63 96 D0 03 +B7 00 00 80 93 D0 40 41 93 0E 00 80 93 01 50 00 +63 9C D0 01 37 00 00 80 93 0E 00 00 93 01 60 00 +63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 +@000000C0 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-lw b/tests/isa/generated/rv32ui-p-lw new file mode 100644 index 0000000..b38cda0 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lw differ diff --git a/tests/isa/generated/rv32ui-p-lw.bin b/tests/isa/generated/rv32ui-p-lw.bin new file mode 100644 index 0000000..68a83b3 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-lw.bin differ diff --git a/tests/isa/generated/rv32ui-p-lw.dump b/tests/isa/generated/rv32ui-p-lw.dump new file mode 100644 index 0000000..b5c5072 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lw.dump @@ -0,0 +1,248 @@ + +generated/rv32ui-p-lw: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00001097 auipc ra,0x1 + c: ff808093 addi ra,ra,-8 # 1000 + 10: 0000af03 lw t5,0(ra) + 14: 00ff0eb7 lui t4,0xff0 + 18: 0ffe8e93 addi t4,t4,255 # ff00ff <_end+0xfef077> + 1c: 00200193 li gp,2 + 20: 27df1a63 bne t5,t4,294 + +00000024 : + 24: 00001097 auipc ra,0x1 + 28: fdc08093 addi ra,ra,-36 # 1000 + 2c: 0040af03 lw t5,4(ra) + 30: ff010eb7 lui t4,0xff010 + 34: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0xff00ee78> + 38: 00300193 li gp,3 + 3c: 25df1c63 bne t5,t4,294 + +00000040 : + 40: 00001097 auipc ra,0x1 + 44: fc008093 addi ra,ra,-64 # 1000 + 48: 0080af03 lw t5,8(ra) + 4c: 0ff01eb7 lui t4,0xff01 + 50: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_end+0xfefff68> + 54: 00400193 li gp,4 + 58: 23df1e63 bne t5,t4,294 + +0000005c : + 5c: 00001097 auipc ra,0x1 + 60: fa408093 addi ra,ra,-92 # 1000 + 64: 00c0af03 lw t5,12(ra) + 68: f00ffeb7 lui t4,0xf00ff + 6c: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0xf00fdf87> + 70: 00500193 li gp,5 + 74: 23df1063 bne t5,t4,294 + +00000078 : + 78: 00001097 auipc ra,0x1 + 7c: f9408093 addi ra,ra,-108 # 100c + 80: ff40af03 lw t5,-12(ra) + 84: 00ff0eb7 lui t4,0xff0 + 88: 0ffe8e93 addi t4,t4,255 # ff00ff <_end+0xfef077> + 8c: 00600193 li gp,6 + 90: 21df1263 bne t5,t4,294 + +00000094 : + 94: 00001097 auipc ra,0x1 + 98: f7808093 addi ra,ra,-136 # 100c + 9c: ff80af03 lw t5,-8(ra) + a0: ff010eb7 lui t4,0xff010 + a4: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0xff00ee78> + a8: 00700193 li gp,7 + ac: 1fdf1463 bne t5,t4,294 + +000000b0 : + b0: 00001097 auipc ra,0x1 + b4: f5c08093 addi ra,ra,-164 # 100c + b8: ffc0af03 lw t5,-4(ra) + bc: 0ff01eb7 lui t4,0xff01 + c0: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_end+0xfefff68> + c4: 00800193 li gp,8 + c8: 1ddf1663 bne t5,t4,294 + +000000cc : + cc: 00001097 auipc ra,0x1 + d0: f4008093 addi ra,ra,-192 # 100c + d4: 0000af03 lw t5,0(ra) + d8: f00ffeb7 lui t4,0xf00ff + dc: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0xf00fdf87> + e0: 00900193 li gp,9 + e4: 1bdf1863 bne t5,t4,294 + +000000e8 : + e8: 00001097 auipc ra,0x1 + ec: f1808093 addi ra,ra,-232 # 1000 + f0: fe008093 addi ra,ra,-32 + f4: 0200a283 lw t0,32(ra) + f8: 00ff0eb7 lui t4,0xff0 + fc: 0ffe8e93 addi t4,t4,255 # ff00ff <_end+0xfef077> + 100: 00a00193 li gp,10 + 104: 19d29863 bne t0,t4,294 + +00000108 : + 108: 00001097 auipc ra,0x1 + 10c: ef808093 addi ra,ra,-264 # 1000 + 110: ffd08093 addi ra,ra,-3 + 114: 0070a283 lw t0,7(ra) + 118: ff010eb7 lui t4,0xff010 + 11c: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0xff00ee78> + 120: 00b00193 li gp,11 + 124: 17d29863 bne t0,t4,294 + +00000128 : + 128: 00c00193 li gp,12 + 12c: 00000213 li tp,0 + 130: 00001097 auipc ra,0x1 + 134: ed408093 addi ra,ra,-300 # 1004 + 138: 0040af03 lw t5,4(ra) + 13c: 000f0313 mv t1,t5 + 140: 0ff01eb7 lui t4,0xff01 + 144: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_end+0xfefff68> + 148: 15d31663 bne t1,t4,294 + 14c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 150: 00200293 li t0,2 + 154: fc521ee3 bne tp,t0,130 + +00000158 : + 158: 00d00193 li gp,13 + 15c: 00000213 li tp,0 + 160: 00001097 auipc ra,0x1 + 164: ea808093 addi ra,ra,-344 # 1008 + 168: 0040af03 lw t5,4(ra) + 16c: 00000013 nop + 170: 000f0313 mv t1,t5 + 174: f00ffeb7 lui t4,0xf00ff + 178: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0xf00fdf87> + 17c: 11d31c63 bne t1,t4,294 + 180: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 184: 00200293 li t0,2 + 188: fc521ce3 bne tp,t0,160 + +0000018c : + 18c: 00e00193 li gp,14 + 190: 00000213 li tp,0 + 194: 00001097 auipc ra,0x1 + 198: e6c08093 addi ra,ra,-404 # 1000 + 19c: 0040af03 lw t5,4(ra) + 1a0: 00000013 nop + 1a4: 00000013 nop + 1a8: 000f0313 mv t1,t5 + 1ac: ff010eb7 lui t4,0xff010 + 1b0: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0xff00ee78> + 1b4: 0fd31063 bne t1,t4,294 + 1b8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1bc: 00200293 li t0,2 + 1c0: fc521ae3 bne tp,t0,194 + +000001c4 : + 1c4: 00f00193 li gp,15 + 1c8: 00000213 li tp,0 + 1cc: 00001097 auipc ra,0x1 + 1d0: e3808093 addi ra,ra,-456 # 1004 + 1d4: 0040af03 lw t5,4(ra) + 1d8: 0ff01eb7 lui t4,0xff01 + 1dc: ff0e8e93 addi t4,t4,-16 # ff00ff0 <_end+0xfefff68> + 1e0: 0bdf1a63 bne t5,t4,294 + 1e4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1e8: 00200293 li t0,2 + 1ec: fe5210e3 bne tp,t0,1cc + +000001f0 : + 1f0: 01000193 li gp,16 + 1f4: 00000213 li tp,0 + 1f8: 00001097 auipc ra,0x1 + 1fc: e1008093 addi ra,ra,-496 # 1008 + 200: 00000013 nop + 204: 0040af03 lw t5,4(ra) + 208: f00ffeb7 lui t4,0xf00ff + 20c: 00fe8e93 addi t4,t4,15 # f00ff00f <_end+0xf00fdf87> + 210: 09df1263 bne t5,t4,294 + 214: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 218: 00200293 li t0,2 + 21c: fc521ee3 bne tp,t0,1f8 + +00000220 : + 220: 01100193 li gp,17 + 224: 00000213 li tp,0 + 228: 00001097 auipc ra,0x1 + 22c: dd808093 addi ra,ra,-552 # 1000 + 230: 00000013 nop + 234: 00000013 nop + 238: 0040af03 lw t5,4(ra) + 23c: ff010eb7 lui t4,0xff010 + 240: f00e8e93 addi t4,t4,-256 # ff00ff00 <_end+0xff00ee78> + 244: 05df1863 bne t5,t4,294 + 248: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 24c: 00200293 li t0,2 + 250: fc521ce3 bne tp,t0,228 + +00000254 : + 254: 00001297 auipc t0,0x1 + 258: dac28293 addi t0,t0,-596 # 1000 + 25c: 0002a103 lw sp,0(t0) + 260: 00200113 li sp,2 + 264: 00200e93 li t4,2 + 268: 01200193 li gp,18 + 26c: 03d11463 bne sp,t4,294 + +00000270 : + 270: 00001297 auipc t0,0x1 + 274: d9028293 addi t0,t0,-624 # 1000 + 278: 0002a103 lw sp,0(t0) + 27c: 00000013 nop + 280: 00200113 li sp,2 + 284: 00200e93 li t4,2 + 288: 01300193 li gp,19 + 28c: 01d11463 bne sp,t4,294 + 290: 00301863 bne zero,gp,2a0 + +00000294 : + 294: 00100d13 li s10,1 + 298: 00000d93 li s11,0 + +0000029c : + 29c: 0000006f j 29c + +000002a0 : + 2a0: 00100d13 li s10,1 + 2a4: 00100d93 li s11,1 + +000002a8 : + 2a8: 0000006f j 2a8 + ... + +Disassembly of section .data: + +00001000 : + 1000: 00ff 0xff + 1002: 00ff 0xff + +00001004 : + 1004: ff00 fsw fs0,56(a4) + 1006: ff00 fsw fs0,56(a4) + +00001008 : + 1008: 0ff0 addi a2,sp,988 + 100a: 0ff0 addi a2,sp,988 + +0000100c : + 100c: f00ff00f 0xf00ff00f + +Disassembly of section .tohost: + +00001040 : + ... + +00001080 : + ... diff --git a/tests/isa/generated/rv32ui-p-lw.verilog b/tests/isa/generated/rv32ui-p-lw.verilog new file mode 100644 index 0000000..339220a --- /dev/null +++ b/tests/isa/generated/rv32ui-p-lw.verilog @@ -0,0 +1,54 @@ +@00000000 +13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF +03 AF 00 00 B7 0E FF 00 93 8E FE 0F 93 01 20 00 +63 1A DF 27 97 10 00 00 93 80 C0 FD 03 AF 40 00 +B7 0E 01 FF 93 8E 0E F0 93 01 30 00 63 1C DF 25 +97 10 00 00 93 80 00 FC 03 AF 80 00 B7 1E F0 0F +93 8E 0E FF 93 01 40 00 63 1E DF 23 97 10 00 00 +93 80 40 FA 03 AF C0 00 B7 FE 0F F0 93 8E FE 00 +93 01 50 00 63 10 DF 23 97 10 00 00 93 80 40 F9 +03 AF 40 FF B7 0E FF 00 93 8E FE 0F 93 01 60 00 +63 12 DF 21 97 10 00 00 93 80 80 F7 03 AF 80 FF +B7 0E 01 FF 93 8E 0E F0 93 01 70 00 63 14 DF 1F +97 10 00 00 93 80 C0 F5 03 AF C0 FF B7 1E F0 0F +93 8E 0E FF 93 01 80 00 63 16 DF 1D 97 10 00 00 +93 80 00 F4 03 AF 00 00 B7 FE 0F F0 93 8E FE 00 +93 01 90 00 63 18 DF 1B 97 10 00 00 93 80 80 F1 +93 80 00 FE 83 A2 00 02 B7 0E FF 00 93 8E FE 0F +93 01 A0 00 63 98 D2 19 97 10 00 00 93 80 80 EF +93 80 D0 FF 83 A2 70 00 B7 0E 01 FF 93 8E 0E F0 +93 01 B0 00 63 98 D2 17 93 01 C0 00 13 02 00 00 +97 10 00 00 93 80 40 ED 03 AF 40 00 13 03 0F 00 +B7 1E F0 0F 93 8E 0E FF 63 16 D3 15 13 02 12 00 +93 02 20 00 E3 1E 52 FC 93 01 D0 00 13 02 00 00 +97 10 00 00 93 80 80 EA 03 AF 40 00 13 00 00 00 +13 03 0F 00 B7 FE 0F F0 93 8E FE 00 63 1C D3 11 +13 02 12 00 93 02 20 00 E3 1C 52 FC 93 01 E0 00 +13 02 00 00 97 10 00 00 93 80 C0 E6 03 AF 40 00 +13 00 00 00 13 00 00 00 13 03 0F 00 B7 0E 01 FF +93 8E 0E F0 63 10 D3 0F 13 02 12 00 93 02 20 00 +E3 1A 52 FC 93 01 F0 00 13 02 00 00 97 10 00 00 +93 80 80 E3 03 AF 40 00 B7 1E F0 0F 93 8E 0E FF +63 1A DF 0B 13 02 12 00 93 02 20 00 E3 10 52 FE +93 01 00 01 13 02 00 00 97 10 00 00 93 80 00 E1 +13 00 00 00 03 AF 40 00 B7 FE 0F F0 93 8E FE 00 +63 12 DF 09 13 02 12 00 93 02 20 00 E3 1E 52 FC +93 01 10 01 13 02 00 00 97 10 00 00 93 80 80 DD +13 00 00 00 13 00 00 00 03 AF 40 00 B7 0E 01 FF +93 8E 0E F0 63 18 DF 05 13 02 12 00 93 02 20 00 +E3 1C 52 FC 97 12 00 00 93 82 C2 DA 03 A1 02 00 +13 01 20 00 93 0E 20 00 93 01 20 01 63 14 D1 03 +97 12 00 00 93 82 02 D9 03 A1 02 00 13 00 00 00 +13 01 20 00 93 0E 20 00 93 01 30 01 63 14 D1 01 +63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 +13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00001000 +FF 00 FF 00 00 FF 00 FF F0 0F F0 0F 0F F0 0F F0 +@00001040 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-or b/tests/isa/generated/rv32ui-p-or new file mode 100644 index 0000000..e55ed55 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-or differ diff --git a/tests/isa/generated/rv32ui-p-or.bin b/tests/isa/generated/rv32ui-p-or.bin new file mode 100644 index 0000000..f365d1b Binary files /dev/null and b/tests/isa/generated/rv32ui-p-or.bin differ diff --git a/tests/isa/generated/rv32ui-p-or.dump b/tests/isa/generated/rv32ui-p-or.dump new file mode 100644 index 0000000..22bf579 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-or.dump @@ -0,0 +1,389 @@ + +generated/rv32ui-p-or: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: ff0100b7 lui ra,0xff010 + c: f0008093 addi ra,ra,-256 # ff00ff00 + 10: 0f0f1137 lui sp,0xf0f1 + 14: f0f10113 addi sp,sp,-241 # f0f0f0f + 18: 0020ef33 or t5,ra,sp + 1c: ff100eb7 lui t4,0xff100 + 20: f0fe8e93 addi t4,t4,-241 # ff0fff0f + 24: 00200193 li gp,2 + 28: 4bdf1263 bne t5,t4,4cc + +0000002c : + 2c: 0ff010b7 lui ra,0xff01 + 30: ff008093 addi ra,ra,-16 # ff00ff0 + 34: f0f0f137 lui sp,0xf0f0f + 38: 0f010113 addi sp,sp,240 # f0f0f0f0 + 3c: 0020ef33 or t5,ra,sp + 40: fff10eb7 lui t4,0xfff10 + 44: ff0e8e93 addi t4,t4,-16 # fff0fff0 + 48: 00300193 li gp,3 + 4c: 49df1063 bne t5,t4,4cc + +00000050 : + 50: 00ff00b7 lui ra,0xff0 + 54: 0ff08093 addi ra,ra,255 # ff00ff + 58: 0f0f1137 lui sp,0xf0f1 + 5c: f0f10113 addi sp,sp,-241 # f0f0f0f + 60: 0020ef33 or t5,ra,sp + 64: 0fff1eb7 lui t4,0xfff1 + 68: fffe8e93 addi t4,t4,-1 # fff0fff + 6c: 00400193 li gp,4 + 70: 45df1e63 bne t5,t4,4cc + +00000074 : + 74: f00ff0b7 lui ra,0xf00ff + 78: 00f08093 addi ra,ra,15 # f00ff00f + 7c: f0f0f137 lui sp,0xf0f0f + 80: 0f010113 addi sp,sp,240 # f0f0f0f0 + 84: 0020ef33 or t5,ra,sp + 88: f0fffeb7 lui t4,0xf0fff + 8c: 0ffe8e93 addi t4,t4,255 # f0fff0ff + 90: 00500193 li gp,5 + 94: 43df1c63 bne t5,t4,4cc + +00000098 : + 98: ff0100b7 lui ra,0xff010 + 9c: f0008093 addi ra,ra,-256 # ff00ff00 + a0: 0f0f1137 lui sp,0xf0f1 + a4: f0f10113 addi sp,sp,-241 # f0f0f0f + a8: 0020e0b3 or ra,ra,sp + ac: ff100eb7 lui t4,0xff100 + b0: f0fe8e93 addi t4,t4,-241 # ff0fff0f + b4: 00600193 li gp,6 + b8: 41d09a63 bne ra,t4,4cc + +000000bc : + bc: ff0100b7 lui ra,0xff010 + c0: f0008093 addi ra,ra,-256 # ff00ff00 + c4: 0f0f1137 lui sp,0xf0f1 + c8: f0f10113 addi sp,sp,-241 # f0f0f0f + cc: 0020e133 or sp,ra,sp + d0: ff100eb7 lui t4,0xff100 + d4: f0fe8e93 addi t4,t4,-241 # ff0fff0f + d8: 00700193 li gp,7 + dc: 3fd11863 bne sp,t4,4cc + +000000e0 : + e0: ff0100b7 lui ra,0xff010 + e4: f0008093 addi ra,ra,-256 # ff00ff00 + e8: 0010e0b3 or ra,ra,ra + ec: ff010eb7 lui t4,0xff010 + f0: f00e8e93 addi t4,t4,-256 # ff00ff00 + f4: 00800193 li gp,8 + f8: 3dd09a63 bne ra,t4,4cc + +000000fc : + fc: 00000213 li tp,0 + 100: ff0100b7 lui ra,0xff010 + 104: f0008093 addi ra,ra,-256 # ff00ff00 + 108: 0f0f1137 lui sp,0xf0f1 + 10c: f0f10113 addi sp,sp,-241 # f0f0f0f + 110: 0020ef33 or t5,ra,sp + 114: 000f0313 mv t1,t5 + 118: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 11c: 00200293 li t0,2 + 120: fe5210e3 bne tp,t0,100 + 124: ff100eb7 lui t4,0xff100 + 128: f0fe8e93 addi t4,t4,-241 # ff0fff0f + 12c: 00900193 li gp,9 + 130: 39d31e63 bne t1,t4,4cc + +00000134 : + 134: 00000213 li tp,0 + 138: 0ff010b7 lui ra,0xff01 + 13c: ff008093 addi ra,ra,-16 # ff00ff0 + 140: f0f0f137 lui sp,0xf0f0f + 144: 0f010113 addi sp,sp,240 # f0f0f0f0 + 148: 0020ef33 or t5,ra,sp + 14c: 00000013 nop + 150: 000f0313 mv t1,t5 + 154: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 158: 00200293 li t0,2 + 15c: fc521ee3 bne tp,t0,138 + 160: fff10eb7 lui t4,0xfff10 + 164: ff0e8e93 addi t4,t4,-16 # fff0fff0 + 168: 00a00193 li gp,10 + 16c: 37d31063 bne t1,t4,4cc + +00000170 : + 170: 00000213 li tp,0 + 174: 00ff00b7 lui ra,0xff0 + 178: 0ff08093 addi ra,ra,255 # ff00ff + 17c: 0f0f1137 lui sp,0xf0f1 + 180: f0f10113 addi sp,sp,-241 # f0f0f0f + 184: 0020ef33 or t5,ra,sp + 188: 00000013 nop + 18c: 00000013 nop + 190: 000f0313 mv t1,t5 + 194: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 198: 00200293 li t0,2 + 19c: fc521ce3 bne tp,t0,174 + 1a0: 0fff1eb7 lui t4,0xfff1 + 1a4: fffe8e93 addi t4,t4,-1 # fff0fff + 1a8: 00b00193 li gp,11 + 1ac: 33d31063 bne t1,t4,4cc + +000001b0 : + 1b0: 00000213 li tp,0 + 1b4: ff0100b7 lui ra,0xff010 + 1b8: f0008093 addi ra,ra,-256 # ff00ff00 + 1bc: 0f0f1137 lui sp,0xf0f1 + 1c0: f0f10113 addi sp,sp,-241 # f0f0f0f + 1c4: 0020ef33 or t5,ra,sp + 1c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1cc: 00200293 li t0,2 + 1d0: fe5212e3 bne tp,t0,1b4 + 1d4: ff100eb7 lui t4,0xff100 + 1d8: f0fe8e93 addi t4,t4,-241 # ff0fff0f + 1dc: 00c00193 li gp,12 + 1e0: 2fdf1663 bne t5,t4,4cc + +000001e4 : + 1e4: 00000213 li tp,0 + 1e8: 0ff010b7 lui ra,0xff01 + 1ec: ff008093 addi ra,ra,-16 # ff00ff0 + 1f0: f0f0f137 lui sp,0xf0f0f + 1f4: 0f010113 addi sp,sp,240 # f0f0f0f0 + 1f8: 00000013 nop + 1fc: 0020ef33 or t5,ra,sp + 200: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 204: 00200293 li t0,2 + 208: fe5210e3 bne tp,t0,1e8 + 20c: fff10eb7 lui t4,0xfff10 + 210: ff0e8e93 addi t4,t4,-16 # fff0fff0 + 214: 00d00193 li gp,13 + 218: 2bdf1a63 bne t5,t4,4cc + +0000021c : + 21c: 00000213 li tp,0 + 220: 00ff00b7 lui ra,0xff0 + 224: 0ff08093 addi ra,ra,255 # ff00ff + 228: 0f0f1137 lui sp,0xf0f1 + 22c: f0f10113 addi sp,sp,-241 # f0f0f0f + 230: 00000013 nop + 234: 00000013 nop + 238: 0020ef33 or t5,ra,sp + 23c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 240: 00200293 li t0,2 + 244: fc521ee3 bne tp,t0,220 + 248: 0fff1eb7 lui t4,0xfff1 + 24c: fffe8e93 addi t4,t4,-1 # fff0fff + 250: 00e00193 li gp,14 + 254: 27df1c63 bne t5,t4,4cc + +00000258 : + 258: 00000213 li tp,0 + 25c: ff0100b7 lui ra,0xff010 + 260: f0008093 addi ra,ra,-256 # ff00ff00 + 264: 00000013 nop + 268: 0f0f1137 lui sp,0xf0f1 + 26c: f0f10113 addi sp,sp,-241 # f0f0f0f + 270: 0020ef33 or t5,ra,sp + 274: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 278: 00200293 li t0,2 + 27c: fe5210e3 bne tp,t0,25c + 280: ff100eb7 lui t4,0xff100 + 284: f0fe8e93 addi t4,t4,-241 # ff0fff0f + 288: 00f00193 li gp,15 + 28c: 25df1063 bne t5,t4,4cc + +00000290 : + 290: 00000213 li tp,0 + 294: 0ff010b7 lui ra,0xff01 + 298: ff008093 addi ra,ra,-16 # ff00ff0 + 29c: 00000013 nop + 2a0: f0f0f137 lui sp,0xf0f0f + 2a4: 0f010113 addi sp,sp,240 # f0f0f0f0 + 2a8: 00000013 nop + 2ac: 0020ef33 or t5,ra,sp + 2b0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2b4: 00200293 li t0,2 + 2b8: fc521ee3 bne tp,t0,294 + 2bc: fff10eb7 lui t4,0xfff10 + 2c0: ff0e8e93 addi t4,t4,-16 # fff0fff0 + 2c4: 01000193 li gp,16 + 2c8: 21df1263 bne t5,t4,4cc + +000002cc : + 2cc: 00000213 li tp,0 + 2d0: 00ff00b7 lui ra,0xff0 + 2d4: 0ff08093 addi ra,ra,255 # ff00ff + 2d8: 00000013 nop + 2dc: 00000013 nop + 2e0: 0f0f1137 lui sp,0xf0f1 + 2e4: f0f10113 addi sp,sp,-241 # f0f0f0f + 2e8: 0020ef33 or t5,ra,sp + 2ec: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2f0: 00200293 li t0,2 + 2f4: fc521ee3 bne tp,t0,2d0 + 2f8: 0fff1eb7 lui t4,0xfff1 + 2fc: fffe8e93 addi t4,t4,-1 # fff0fff + 300: 01100193 li gp,17 + 304: 1ddf1463 bne t5,t4,4cc + +00000308 : + 308: 00000213 li tp,0 + 30c: 0f0f1137 lui sp,0xf0f1 + 310: f0f10113 addi sp,sp,-241 # f0f0f0f + 314: ff0100b7 lui ra,0xff010 + 318: f0008093 addi ra,ra,-256 # ff00ff00 + 31c: 0020ef33 or t5,ra,sp + 320: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 324: 00200293 li t0,2 + 328: fe5212e3 bne tp,t0,30c + 32c: ff100eb7 lui t4,0xff100 + 330: f0fe8e93 addi t4,t4,-241 # ff0fff0f + 334: 01200193 li gp,18 + 338: 19df1a63 bne t5,t4,4cc + +0000033c : + 33c: 00000213 li tp,0 + 340: f0f0f137 lui sp,0xf0f0f + 344: 0f010113 addi sp,sp,240 # f0f0f0f0 + 348: 0ff010b7 lui ra,0xff01 + 34c: ff008093 addi ra,ra,-16 # ff00ff0 + 350: 00000013 nop + 354: 0020ef33 or t5,ra,sp + 358: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 35c: 00200293 li t0,2 + 360: fe5210e3 bne tp,t0,340 + 364: fff10eb7 lui t4,0xfff10 + 368: ff0e8e93 addi t4,t4,-16 # fff0fff0 + 36c: 01300193 li gp,19 + 370: 15df1e63 bne t5,t4,4cc + +00000374 : + 374: 00000213 li tp,0 + 378: 0f0f1137 lui sp,0xf0f1 + 37c: f0f10113 addi sp,sp,-241 # f0f0f0f + 380: 00ff00b7 lui ra,0xff0 + 384: 0ff08093 addi ra,ra,255 # ff00ff + 388: 00000013 nop + 38c: 00000013 nop + 390: 0020ef33 or t5,ra,sp + 394: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 398: 00200293 li t0,2 + 39c: fc521ee3 bne tp,t0,378 + 3a0: 0fff1eb7 lui t4,0xfff1 + 3a4: fffe8e93 addi t4,t4,-1 # fff0fff + 3a8: 01400193 li gp,20 + 3ac: 13df1063 bne t5,t4,4cc + +000003b0 : + 3b0: 00000213 li tp,0 + 3b4: 0f0f1137 lui sp,0xf0f1 + 3b8: f0f10113 addi sp,sp,-241 # f0f0f0f + 3bc: 00000013 nop + 3c0: ff0100b7 lui ra,0xff010 + 3c4: f0008093 addi ra,ra,-256 # ff00ff00 + 3c8: 0020ef33 or t5,ra,sp + 3cc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3d0: 00200293 li t0,2 + 3d4: fe5210e3 bne tp,t0,3b4 + 3d8: ff100eb7 lui t4,0xff100 + 3dc: f0fe8e93 addi t4,t4,-241 # ff0fff0f + 3e0: 01500193 li gp,21 + 3e4: 0fdf1463 bne t5,t4,4cc + +000003e8 : + 3e8: 00000213 li tp,0 + 3ec: f0f0f137 lui sp,0xf0f0f + 3f0: 0f010113 addi sp,sp,240 # f0f0f0f0 + 3f4: 00000013 nop + 3f8: 0ff010b7 lui ra,0xff01 + 3fc: ff008093 addi ra,ra,-16 # ff00ff0 + 400: 00000013 nop + 404: 0020ef33 or t5,ra,sp + 408: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 40c: 00200293 li t0,2 + 410: fc521ee3 bne tp,t0,3ec + 414: fff10eb7 lui t4,0xfff10 + 418: ff0e8e93 addi t4,t4,-16 # fff0fff0 + 41c: 01600193 li gp,22 + 420: 0bdf1663 bne t5,t4,4cc + +00000424 : + 424: 00000213 li tp,0 + 428: 0f0f1137 lui sp,0xf0f1 + 42c: f0f10113 addi sp,sp,-241 # f0f0f0f + 430: 00000013 nop + 434: 00000013 nop + 438: 00ff00b7 lui ra,0xff0 + 43c: 0ff08093 addi ra,ra,255 # ff00ff + 440: 0020ef33 or t5,ra,sp + 444: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 448: 00200293 li t0,2 + 44c: fc521ee3 bne tp,t0,428 + 450: 0fff1eb7 lui t4,0xfff1 + 454: fffe8e93 addi t4,t4,-1 # fff0fff + 458: 01700193 li gp,23 + 45c: 07df1863 bne t5,t4,4cc + +00000460 : + 460: ff0100b7 lui ra,0xff010 + 464: f0008093 addi ra,ra,-256 # ff00ff00 + 468: 00106133 or sp,zero,ra + 46c: ff010eb7 lui t4,0xff010 + 470: f00e8e93 addi t4,t4,-256 # ff00ff00 + 474: 01800193 li gp,24 + 478: 05d11a63 bne sp,t4,4cc + +0000047c : + 47c: 00ff00b7 lui ra,0xff0 + 480: 0ff08093 addi ra,ra,255 # ff00ff + 484: 0000e133 or sp,ra,zero + 488: 00ff0eb7 lui t4,0xff0 + 48c: 0ffe8e93 addi t4,t4,255 # ff00ff + 490: 01900193 li gp,25 + 494: 03d11c63 bne sp,t4,4cc + +00000498 : + 498: 000060b3 or ra,zero,zero + 49c: 00000e93 li t4,0 + 4a0: 01a00193 li gp,26 + 4a4: 03d09463 bne ra,t4,4cc + +000004a8 : + 4a8: 111110b7 lui ra,0x11111 + 4ac: 11108093 addi ra,ra,273 # 11111111 + 4b0: 22222137 lui sp,0x22222 + 4b4: 22210113 addi sp,sp,546 # 22222222 + 4b8: 0020e033 or zero,ra,sp + 4bc: 00000e93 li t4,0 + 4c0: 01b00193 li gp,27 + 4c4: 01d01463 bne zero,t4,4cc + 4c8: 00301863 bne zero,gp,4d8 + +000004cc : + 4cc: 00100d13 li s10,1 + 4d0: 00000d93 li s11,0 + +000004d4 : + 4d4: 0000006f j 4d4 + +000004d8 : + 4d8: 00100d13 li s10,1 + 4dc: 00100d93 li s11,1 + +000004e0 : + 4e0: 0000006f j 4e0 + ... + +Disassembly of section .tohost: + +00000540 : + ... + +00000580 : + ... diff --git a/tests/isa/generated/rv32ui-p-or.verilog b/tests/isa/generated/rv32ui-p-or.verilog new file mode 100644 index 0000000..e6bc7a6 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-or.verilog @@ -0,0 +1,88 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 00 01 FF 93 80 00 F0 +37 11 0F 0F 13 01 F1 F0 33 EF 20 00 B7 0E 10 FF +93 8E FE F0 93 01 20 00 63 12 DF 4B B7 10 F0 0F +93 80 00 FF 37 F1 F0 F0 13 01 01 0F 33 EF 20 00 +B7 0E F1 FF 93 8E 0E FF 93 01 30 00 63 10 DF 49 +B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 +33 EF 20 00 B7 1E FF 0F 93 8E FE FF 93 01 40 00 +63 1E DF 45 B7 F0 0F F0 93 80 F0 00 37 F1 F0 F0 +13 01 01 0F 33 EF 20 00 B7 FE FF F0 93 8E FE 0F +93 01 50 00 63 1C DF 43 B7 00 01 FF 93 80 00 F0 +37 11 0F 0F 13 01 F1 F0 B3 E0 20 00 B7 0E 10 FF +93 8E FE F0 93 01 60 00 63 9A D0 41 B7 00 01 FF +93 80 00 F0 37 11 0F 0F 13 01 F1 F0 33 E1 20 00 +B7 0E 10 FF 93 8E FE F0 93 01 70 00 63 18 D1 3F +B7 00 01 FF 93 80 00 F0 B3 E0 10 00 B7 0E 01 FF +93 8E 0E F0 93 01 80 00 63 9A D0 3D 13 02 00 00 +B7 00 01 FF 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 +33 EF 20 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 10 52 FE B7 0E 10 FF 93 8E FE F0 93 01 90 00 +63 1E D3 39 13 02 00 00 B7 10 F0 0F 93 80 00 FF +37 F1 F0 F0 13 01 01 0F 33 EF 20 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 1E 52 FC +B7 0E F1 FF 93 8E 0E FF 93 01 A0 00 63 10 D3 37 +13 02 00 00 B7 00 FF 00 93 80 F0 0F 37 11 0F 0F +13 01 F1 F0 33 EF 20 00 13 00 00 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 1C 52 FC +B7 1E FF 0F 93 8E FE FF 93 01 B0 00 63 10 D3 33 +13 02 00 00 B7 00 01 FF 93 80 00 F0 37 11 0F 0F +13 01 F1 F0 33 EF 20 00 13 02 12 00 93 02 20 00 +E3 12 52 FE B7 0E 10 FF 93 8E FE F0 93 01 C0 00 +63 16 DF 2F 13 02 00 00 B7 10 F0 0F 93 80 00 FF +37 F1 F0 F0 13 01 01 0F 13 00 00 00 33 EF 20 00 +13 02 12 00 93 02 20 00 E3 10 52 FE B7 0E F1 FF +93 8E 0E FF 93 01 D0 00 63 1A DF 2B 13 02 00 00 +B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 +13 00 00 00 13 00 00 00 33 EF 20 00 13 02 12 00 +93 02 20 00 E3 1E 52 FC B7 1E FF 0F 93 8E FE FF +93 01 E0 00 63 1C DF 27 13 02 00 00 B7 00 01 FF +93 80 00 F0 13 00 00 00 37 11 0F 0F 13 01 F1 F0 +33 EF 20 00 13 02 12 00 93 02 20 00 E3 10 52 FE +B7 0E 10 FF 93 8E FE F0 93 01 F0 00 63 10 DF 25 +13 02 00 00 B7 10 F0 0F 93 80 00 FF 13 00 00 00 +37 F1 F0 F0 13 01 01 0F 13 00 00 00 33 EF 20 00 +13 02 12 00 93 02 20 00 E3 1E 52 FC B7 0E F1 FF +93 8E 0E FF 93 01 00 01 63 12 DF 21 13 02 00 00 +B7 00 FF 00 93 80 F0 0F 13 00 00 00 13 00 00 00 +37 11 0F 0F 13 01 F1 F0 33 EF 20 00 13 02 12 00 +93 02 20 00 E3 1E 52 FC B7 1E FF 0F 93 8E FE FF +93 01 10 01 63 14 DF 1D 13 02 00 00 37 11 0F 0F +13 01 F1 F0 B7 00 01 FF 93 80 00 F0 33 EF 20 00 +13 02 12 00 93 02 20 00 E3 12 52 FE B7 0E 10 FF +93 8E FE F0 93 01 20 01 63 1A DF 19 13 02 00 00 +37 F1 F0 F0 13 01 01 0F B7 10 F0 0F 93 80 00 FF +13 00 00 00 33 EF 20 00 13 02 12 00 93 02 20 00 +E3 10 52 FE B7 0E F1 FF 93 8E 0E FF 93 01 30 01 +63 1E DF 15 13 02 00 00 37 11 0F 0F 13 01 F1 F0 +B7 00 FF 00 93 80 F0 0F 13 00 00 00 13 00 00 00 +33 EF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC +B7 1E FF 0F 93 8E FE FF 93 01 40 01 63 10 DF 13 +13 02 00 00 37 11 0F 0F 13 01 F1 F0 13 00 00 00 +B7 00 01 FF 93 80 00 F0 33 EF 20 00 13 02 12 00 +93 02 20 00 E3 10 52 FE B7 0E 10 FF 93 8E FE F0 +93 01 50 01 63 14 DF 0F 13 02 00 00 37 F1 F0 F0 +13 01 01 0F 13 00 00 00 B7 10 F0 0F 93 80 00 FF +13 00 00 00 33 EF 20 00 13 02 12 00 93 02 20 00 +E3 1E 52 FC B7 0E F1 FF 93 8E 0E FF 93 01 60 01 +63 16 DF 0B 13 02 00 00 37 11 0F 0F 13 01 F1 F0 +13 00 00 00 13 00 00 00 B7 00 FF 00 93 80 F0 0F +33 EF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC +B7 1E FF 0F 93 8E FE FF 93 01 70 01 63 18 DF 07 +B7 00 01 FF 93 80 00 F0 33 61 10 00 B7 0E 01 FF +93 8E 0E F0 93 01 80 01 63 1A D1 05 B7 00 FF 00 +93 80 F0 0F 33 E1 00 00 B7 0E FF 00 93 8E FE 0F +93 01 90 01 63 1C D1 03 B3 60 00 00 93 0E 00 00 +93 01 A0 01 63 94 D0 03 B7 10 11 11 93 80 10 11 +37 21 22 22 13 01 21 22 33 E0 20 00 93 0E 00 00 +93 01 B0 01 63 14 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000540 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-ori b/tests/isa/generated/rv32ui-p-ori new file mode 100644 index 0000000..8d24d35 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-ori differ diff --git a/tests/isa/generated/rv32ui-p-ori.bin b/tests/isa/generated/rv32ui-p-ori.bin new file mode 100644 index 0000000..e939a15 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-ori.bin differ diff --git a/tests/isa/generated/rv32ui-p-ori.dump b/tests/isa/generated/rv32ui-p-ori.dump new file mode 100644 index 0000000..0ffdfdd --- /dev/null +++ b/tests/isa/generated/rv32ui-p-ori.dump @@ -0,0 +1,177 @@ + +generated/rv32ui-p-ori: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: ff0100b7 lui ra,0xff010 + c: f0008093 addi ra,ra,-256 # ff00ff00 + 10: f0f0ef13 ori t5,ra,-241 + 14: f0f00e93 li t4,-241 + 18: 00200193 li gp,2 + 1c: 1ddf1463 bne t5,t4,1e4 + +00000020 : + 20: 0ff010b7 lui ra,0xff01 + 24: ff008093 addi ra,ra,-16 # ff00ff0 + 28: 0f00ef13 ori t5,ra,240 + 2c: 0ff01eb7 lui t4,0xff01 + 30: ff0e8e93 addi t4,t4,-16 # ff00ff0 + 34: 00300193 li gp,3 + 38: 1bdf1663 bne t5,t4,1e4 + +0000003c : + 3c: 00ff00b7 lui ra,0xff0 + 40: 0ff08093 addi ra,ra,255 # ff00ff + 44: 70f0ef13 ori t5,ra,1807 + 48: 00ff0eb7 lui t4,0xff0 + 4c: 7ffe8e93 addi t4,t4,2047 # ff07ff + 50: 00400193 li gp,4 + 54: 19df1863 bne t5,t4,1e4 + +00000058 : + 58: f00ff0b7 lui ra,0xf00ff + 5c: 00f08093 addi ra,ra,15 # f00ff00f + 60: 0f00ef13 ori t5,ra,240 + 64: f00ffeb7 lui t4,0xf00ff + 68: 0ffe8e93 addi t4,t4,255 # f00ff0ff + 6c: 00500193 li gp,5 + 70: 17df1a63 bne t5,t4,1e4 + +00000074 : + 74: ff0100b7 lui ra,0xff010 + 78: f0008093 addi ra,ra,-256 # ff00ff00 + 7c: 0f00e093 ori ra,ra,240 + 80: ff010eb7 lui t4,0xff010 + 84: ff0e8e93 addi t4,t4,-16 # ff00fff0 + 88: 00600193 li gp,6 + 8c: 15d09c63 bne ra,t4,1e4 + +00000090 : + 90: 00000213 li tp,0 + 94: 0ff010b7 lui ra,0xff01 + 98: ff008093 addi ra,ra,-16 # ff00ff0 + 9c: 0f00ef13 ori t5,ra,240 + a0: 000f0313 mv t1,t5 + a4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + a8: 00200293 li t0,2 + ac: fe5214e3 bne tp,t0,94 + b0: 0ff01eb7 lui t4,0xff01 + b4: ff0e8e93 addi t4,t4,-16 # ff00ff0 + b8: 00700193 li gp,7 + bc: 13d31463 bne t1,t4,1e4 + +000000c0 : + c0: 00000213 li tp,0 + c4: 00ff00b7 lui ra,0xff0 + c8: 0ff08093 addi ra,ra,255 # ff00ff + cc: 70f0ef13 ori t5,ra,1807 + d0: 00000013 nop + d4: 000f0313 mv t1,t5 + d8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + dc: 00200293 li t0,2 + e0: fe5212e3 bne tp,t0,c4 + e4: 00ff0eb7 lui t4,0xff0 + e8: 7ffe8e93 addi t4,t4,2047 # ff07ff + ec: 00800193 li gp,8 + f0: 0fd31a63 bne t1,t4,1e4 + +000000f4 : + f4: 00000213 li tp,0 + f8: f00ff0b7 lui ra,0xf00ff + fc: 00f08093 addi ra,ra,15 # f00ff00f + 100: 0f00ef13 ori t5,ra,240 + 104: 00000013 nop + 108: 00000013 nop + 10c: 000f0313 mv t1,t5 + 110: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 114: 00200293 li t0,2 + 118: fe5210e3 bne tp,t0,f8 + 11c: f00ffeb7 lui t4,0xf00ff + 120: 0ffe8e93 addi t4,t4,255 # f00ff0ff + 124: 00900193 li gp,9 + 128: 0bd31e63 bne t1,t4,1e4 + +0000012c : + 12c: 00000213 li tp,0 + 130: 0ff010b7 lui ra,0xff01 + 134: ff008093 addi ra,ra,-16 # ff00ff0 + 138: 0f00ef13 ori t5,ra,240 + 13c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 140: 00200293 li t0,2 + 144: fe5216e3 bne tp,t0,130 + 148: 0ff01eb7 lui t4,0xff01 + 14c: ff0e8e93 addi t4,t4,-16 # ff00ff0 + 150: 00a00193 li gp,10 + 154: 09df1863 bne t5,t4,1e4 + +00000158 : + 158: 00000213 li tp,0 + 15c: 00ff00b7 lui ra,0xff0 + 160: 0ff08093 addi ra,ra,255 # ff00ff + 164: 00000013 nop + 168: f0f0ef13 ori t5,ra,-241 + 16c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 170: 00200293 li t0,2 + 174: fe5214e3 bne tp,t0,15c + 178: fff00e93 li t4,-1 + 17c: 00b00193 li gp,11 + 180: 07df1263 bne t5,t4,1e4 + +00000184 : + 184: 00000213 li tp,0 + 188: f00ff0b7 lui ra,0xf00ff + 18c: 00f08093 addi ra,ra,15 # f00ff00f + 190: 00000013 nop + 194: 00000013 nop + 198: 0f00ef13 ori t5,ra,240 + 19c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1a0: 00200293 li t0,2 + 1a4: fe5212e3 bne tp,t0,188 + 1a8: f00ffeb7 lui t4,0xf00ff + 1ac: 0ffe8e93 addi t4,t4,255 # f00ff0ff + 1b0: 00c00193 li gp,12 + 1b4: 03df1863 bne t5,t4,1e4 + +000001b8 : + 1b8: 0f006093 ori ra,zero,240 + 1bc: 0f000e93 li t4,240 + 1c0: 00d00193 li gp,13 + 1c4: 03d09063 bne ra,t4,1e4 + +000001c8 : + 1c8: 00ff00b7 lui ra,0xff0 + 1cc: 0ff08093 addi ra,ra,255 # ff00ff + 1d0: 70f0e013 ori zero,ra,1807 + 1d4: 00000e93 li t4,0 + 1d8: 00e00193 li gp,14 + 1dc: 01d01463 bne zero,t4,1e4 + 1e0: 00301863 bne zero,gp,1f0 + +000001e4 : + 1e4: 00100d13 li s10,1 + 1e8: 00000d93 li s11,0 + +000001ec : + 1ec: 0000006f j 1ec + +000001f0 : + 1f0: 00100d13 li s10,1 + 1f4: 00100d93 li s11,1 + +000001f8 : + 1f8: 0000006f j 1f8 + ... + +Disassembly of section .tohost: + +00000240 : + ... + +00000280 : + ... diff --git a/tests/isa/generated/rv32ui-p-ori.verilog b/tests/isa/generated/rv32ui-p-ori.verilog new file mode 100644 index 0000000..901516b --- /dev/null +++ b/tests/isa/generated/rv32ui-p-ori.verilog @@ -0,0 +1,40 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 00 01 FF 93 80 00 F0 +13 EF F0 F0 93 0E F0 F0 93 01 20 00 63 14 DF 1D +B7 10 F0 0F 93 80 00 FF 13 EF 00 0F B7 1E F0 0F +93 8E 0E FF 93 01 30 00 63 16 DF 1B B7 00 FF 00 +93 80 F0 0F 13 EF F0 70 B7 0E FF 00 93 8E FE 7F +93 01 40 00 63 18 DF 19 B7 F0 0F F0 93 80 F0 00 +13 EF 00 0F B7 FE 0F F0 93 8E FE 0F 93 01 50 00 +63 1A DF 17 B7 00 01 FF 93 80 00 F0 93 E0 00 0F +B7 0E 01 FF 93 8E 0E FF 93 01 60 00 63 9C D0 15 +13 02 00 00 B7 10 F0 0F 93 80 00 FF 13 EF 00 0F +13 03 0F 00 13 02 12 00 93 02 20 00 E3 14 52 FE +B7 1E F0 0F 93 8E 0E FF 93 01 70 00 63 14 D3 13 +13 02 00 00 B7 00 FF 00 93 80 F0 0F 13 EF F0 70 +13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 12 52 FE B7 0E FF 00 93 8E FE 7F 93 01 80 00 +63 1A D3 0F 13 02 00 00 B7 F0 0F F0 93 80 F0 00 +13 EF 00 0F 13 00 00 00 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 10 52 FE B7 FE 0F F0 +93 8E FE 0F 93 01 90 00 63 1E D3 0B 13 02 00 00 +B7 10 F0 0F 93 80 00 FF 13 EF 00 0F 13 02 12 00 +93 02 20 00 E3 16 52 FE B7 1E F0 0F 93 8E 0E FF +93 01 A0 00 63 18 DF 09 13 02 00 00 B7 00 FF 00 +93 80 F0 0F 13 00 00 00 13 EF F0 F0 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 0E F0 FF 93 01 B0 00 +63 12 DF 07 13 02 00 00 B7 F0 0F F0 93 80 F0 00 +13 00 00 00 13 00 00 00 13 EF 00 0F 13 02 12 00 +93 02 20 00 E3 12 52 FE B7 FE 0F F0 93 8E FE 0F +93 01 C0 00 63 18 DF 03 93 60 00 0F 93 0E 00 0F +93 01 D0 00 63 90 D0 03 B7 00 FF 00 93 80 F0 0F +13 E0 F0 70 93 0E 00 00 93 01 E0 00 63 14 D0 01 +63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 +13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 +00 00 00 00 +@00000240 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-sb b/tests/isa/generated/rv32ui-p-sb new file mode 100644 index 0000000..a4c3b7c Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sb differ diff --git a/tests/isa/generated/rv32ui-p-sb.bin b/tests/isa/generated/rv32ui-p-sb.bin new file mode 100644 index 0000000..d21bc1d Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sb.bin differ diff --git a/tests/isa/generated/rv32ui-p-sb.dump b/tests/isa/generated/rv32ui-p-sb.dump new file mode 100644 index 0000000..791562e --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sb.dump @@ -0,0 +1,363 @@ + +generated/rv32ui-p-sb: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00001097 auipc ra,0x1 + c: ff808093 addi ra,ra,-8 # 1000 + 10: faa00113 li sp,-86 + 14: 00208023 sb sp,0(ra) + 18: 00008f03 lb t5,0(ra) + 1c: faa00e93 li t4,-86 + 20: 00200193 li gp,2 + 24: 3ddf1c63 bne t5,t4,3fc + +00000028 : + 28: 00001097 auipc ra,0x1 + 2c: fd808093 addi ra,ra,-40 # 1000 + 30: 00000113 li sp,0 + 34: 002080a3 sb sp,1(ra) + 38: 00108f03 lb t5,1(ra) + 3c: 00000e93 li t4,0 + 40: 00300193 li gp,3 + 44: 3bdf1c63 bne t5,t4,3fc + +00000048 : + 48: 00001097 auipc ra,0x1 + 4c: fb808093 addi ra,ra,-72 # 1000 + 50: fffff137 lui sp,0xfffff + 54: fa010113 addi sp,sp,-96 # ffffefa0 <_end+0xffffdf18> + 58: 00208123 sb sp,2(ra) + 5c: 00209f03 lh t5,2(ra) + 60: fffffeb7 lui t4,0xfffff + 64: fa0e8e93 addi t4,t4,-96 # ffffefa0 <_end+0xffffdf18> + 68: 00400193 li gp,4 + 6c: 39df1863 bne t5,t4,3fc + +00000070 : + 70: 00001097 auipc ra,0x1 + 74: f9008093 addi ra,ra,-112 # 1000 + 78: 00a00113 li sp,10 + 7c: 002081a3 sb sp,3(ra) + 80: 00308f03 lb t5,3(ra) + 84: 00a00e93 li t4,10 + 88: 00500193 li gp,5 + 8c: 37df1863 bne t5,t4,3fc + +00000090 : + 90: 00001097 auipc ra,0x1 + 94: f7708093 addi ra,ra,-137 # 1007 + 98: faa00113 li sp,-86 + 9c: fe208ea3 sb sp,-3(ra) + a0: ffd08f03 lb t5,-3(ra) + a4: faa00e93 li t4,-86 + a8: 00600193 li gp,6 + ac: 35df1863 bne t5,t4,3fc + +000000b0 : + b0: 00001097 auipc ra,0x1 + b4: f5708093 addi ra,ra,-169 # 1007 + b8: 00000113 li sp,0 + bc: fe208f23 sb sp,-2(ra) + c0: ffe08f03 lb t5,-2(ra) + c4: 00000e93 li t4,0 + c8: 00700193 li gp,7 + cc: 33df1863 bne t5,t4,3fc + +000000d0 : + d0: 00001097 auipc ra,0x1 + d4: f3708093 addi ra,ra,-201 # 1007 + d8: fa000113 li sp,-96 + dc: fe208fa3 sb sp,-1(ra) + e0: fff08f03 lb t5,-1(ra) + e4: fa000e93 li t4,-96 + e8: 00800193 li gp,8 + ec: 31df1863 bne t5,t4,3fc + +000000f0 : + f0: 00001097 auipc ra,0x1 + f4: f1708093 addi ra,ra,-233 # 1007 + f8: 00a00113 li sp,10 + fc: 00208023 sb sp,0(ra) + 100: 00008f03 lb t5,0(ra) + 104: 00a00e93 li t4,10 + 108: 00900193 li gp,9 + 10c: 2fdf1863 bne t5,t4,3fc + +00000110 : + 110: 00001097 auipc ra,0x1 + 114: ef808093 addi ra,ra,-264 # 1008 + 118: 12345137 lui sp,0x12345 + 11c: 67810113 addi sp,sp,1656 # 12345678 <_end+0x123445f0> + 120: fe008213 addi tp,ra,-32 + 124: 02220023 sb sp,32(tp) # 20 + 128: 00008283 lb t0,0(ra) + 12c: 07800e93 li t4,120 + 130: 00a00193 li gp,10 + 134: 2dd29463 bne t0,t4,3fc + +00000138 : + 138: 00001097 auipc ra,0x1 + 13c: ed008093 addi ra,ra,-304 # 1008 + 140: 00003137 lui sp,0x3 + 144: 09810113 addi sp,sp,152 # 3098 <_end+0x2010> + 148: ffa08093 addi ra,ra,-6 + 14c: 002083a3 sb sp,7(ra) + 150: 00001217 auipc tp,0x1 + 154: eb920213 addi tp,tp,-327 # 1009 + 158: 00020283 lb t0,0(tp) # 0 <_start> + 15c: f9800e93 li t4,-104 + 160: 00b00193 li gp,11 + 164: 29d29c63 bne t0,t4,3fc + +00000168 : + 168: 00c00193 li gp,12 + 16c: 00000213 li tp,0 + 170: fdd00093 li ra,-35 + 174: 00001117 auipc sp,0x1 + 178: e8c10113 addi sp,sp,-372 # 1000 + 17c: 00110023 sb ra,0(sp) + 180: 00010f03 lb t5,0(sp) + 184: fdd00e93 li t4,-35 + 188: 27df1a63 bne t5,t4,3fc + 18c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 190: 00200293 li t0,2 + 194: fc521ee3 bne tp,t0,170 + +00000198 : + 198: 00d00193 li gp,13 + 19c: 00000213 li tp,0 + 1a0: fcd00093 li ra,-51 + 1a4: 00001117 auipc sp,0x1 + 1a8: e5c10113 addi sp,sp,-420 # 1000 + 1ac: 00000013 nop + 1b0: 001100a3 sb ra,1(sp) + 1b4: 00110f03 lb t5,1(sp) + 1b8: fcd00e93 li t4,-51 + 1bc: 25df1063 bne t5,t4,3fc + 1c0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1c4: 00200293 li t0,2 + 1c8: fc521ce3 bne tp,t0,1a0 + +000001cc : + 1cc: 00e00193 li gp,14 + 1d0: 00000213 li tp,0 + 1d4: fcc00093 li ra,-52 + 1d8: 00001117 auipc sp,0x1 + 1dc: e2810113 addi sp,sp,-472 # 1000 + 1e0: 00000013 nop + 1e4: 00000013 nop + 1e8: 00110123 sb ra,2(sp) + 1ec: 00210f03 lb t5,2(sp) + 1f0: fcc00e93 li t4,-52 + 1f4: 21df1463 bne t5,t4,3fc + 1f8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1fc: 00200293 li t0,2 + 200: fc521ae3 bne tp,t0,1d4 + +00000204 : + 204: 00f00193 li gp,15 + 208: 00000213 li tp,0 + 20c: fbc00093 li ra,-68 + 210: 00000013 nop + 214: 00001117 auipc sp,0x1 + 218: dec10113 addi sp,sp,-532 # 1000 + 21c: 001101a3 sb ra,3(sp) + 220: 00310f03 lb t5,3(sp) + 224: fbc00e93 li t4,-68 + 228: 1ddf1a63 bne t5,t4,3fc + 22c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 230: 00200293 li t0,2 + 234: fc521ce3 bne tp,t0,20c + +00000238 : + 238: 01000193 li gp,16 + 23c: 00000213 li tp,0 + 240: fbb00093 li ra,-69 + 244: 00000013 nop + 248: 00001117 auipc sp,0x1 + 24c: db810113 addi sp,sp,-584 # 1000 + 250: 00000013 nop + 254: 00110223 sb ra,4(sp) + 258: 00410f03 lb t5,4(sp) + 25c: fbb00e93 li t4,-69 + 260: 19df1e63 bne t5,t4,3fc + 264: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 268: 00200293 li t0,2 + 26c: fc521ae3 bne tp,t0,240 + +00000270 : + 270: 01100193 li gp,17 + 274: 00000213 li tp,0 + 278: fab00093 li ra,-85 + 27c: 00000013 nop + 280: 00000013 nop + 284: 00001117 auipc sp,0x1 + 288: d7c10113 addi sp,sp,-644 # 1000 + 28c: 001102a3 sb ra,5(sp) + 290: 00510f03 lb t5,5(sp) + 294: fab00e93 li t4,-85 + 298: 17df1263 bne t5,t4,3fc + 29c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2a0: 00200293 li t0,2 + 2a4: fc521ae3 bne tp,t0,278 + +000002a8 : + 2a8: 01200193 li gp,18 + 2ac: 00000213 li tp,0 + 2b0: 00001117 auipc sp,0x1 + 2b4: d5010113 addi sp,sp,-688 # 1000 + 2b8: 03300093 li ra,51 + 2bc: 00110023 sb ra,0(sp) + 2c0: 00010f03 lb t5,0(sp) + 2c4: 03300e93 li t4,51 + 2c8: 13df1a63 bne t5,t4,3fc + 2cc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2d0: 00200293 li t0,2 + 2d4: fc521ee3 bne tp,t0,2b0 + +000002d8 : + 2d8: 01300193 li gp,19 + 2dc: 00000213 li tp,0 + 2e0: 00001117 auipc sp,0x1 + 2e4: d2010113 addi sp,sp,-736 # 1000 + 2e8: 02300093 li ra,35 + 2ec: 00000013 nop + 2f0: 001100a3 sb ra,1(sp) + 2f4: 00110f03 lb t5,1(sp) + 2f8: 02300e93 li t4,35 + 2fc: 11df1063 bne t5,t4,3fc + 300: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 304: 00200293 li t0,2 + 308: fc521ce3 bne tp,t0,2e0 + +0000030c : + 30c: 01400193 li gp,20 + 310: 00000213 li tp,0 + 314: 00001117 auipc sp,0x1 + 318: cec10113 addi sp,sp,-788 # 1000 + 31c: 02200093 li ra,34 + 320: 00000013 nop + 324: 00000013 nop + 328: 00110123 sb ra,2(sp) + 32c: 00210f03 lb t5,2(sp) + 330: 02200e93 li t4,34 + 334: 0ddf1463 bne t5,t4,3fc + 338: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 33c: 00200293 li t0,2 + 340: fc521ae3 bne tp,t0,314 + +00000344 : + 344: 01500193 li gp,21 + 348: 00000213 li tp,0 + 34c: 00001117 auipc sp,0x1 + 350: cb410113 addi sp,sp,-844 # 1000 + 354: 00000013 nop + 358: 01200093 li ra,18 + 35c: 001101a3 sb ra,3(sp) + 360: 00310f03 lb t5,3(sp) + 364: 01200e93 li t4,18 + 368: 09df1a63 bne t5,t4,3fc + 36c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 370: 00200293 li t0,2 + 374: fc521ce3 bne tp,t0,34c + +00000378 : + 378: 01600193 li gp,22 + 37c: 00000213 li tp,0 + 380: 00001117 auipc sp,0x1 + 384: c8010113 addi sp,sp,-896 # 1000 + 388: 00000013 nop + 38c: 01100093 li ra,17 + 390: 00000013 nop + 394: 00110223 sb ra,4(sp) + 398: 00410f03 lb t5,4(sp) + 39c: 01100e93 li t4,17 + 3a0: 05df1e63 bne t5,t4,3fc + 3a4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3a8: 00200293 li t0,2 + 3ac: fc521ae3 bne tp,t0,380 + +000003b0 : + 3b0: 01700193 li gp,23 + 3b4: 00000213 li tp,0 + 3b8: 00001117 auipc sp,0x1 + 3bc: c4810113 addi sp,sp,-952 # 1000 + 3c0: 00000013 nop + 3c4: 00000013 nop + 3c8: 00100093 li ra,1 + 3cc: 001102a3 sb ra,5(sp) + 3d0: 00510f03 lb t5,5(sp) + 3d4: 00100e93 li t4,1 + 3d8: 03df1263 bne t5,t4,3fc + 3dc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3e0: 00200293 li t0,2 + 3e4: fc521ae3 bne tp,t0,3b8 + 3e8: 0ef00513 li a0,239 + 3ec: 00001597 auipc a1,0x1 + 3f0: c1458593 addi a1,a1,-1004 # 1000 + 3f4: 00a581a3 sb a0,3(a1) + 3f8: 00301863 bne zero,gp,408 + +000003fc : + 3fc: 00100d13 li s10,1 + 400: 00000d93 li s11,0 + +00000404 : + 404: 0000006f j 404 + +00000408 : + 408: 00100d13 li s10,1 + 40c: 00100d93 li s11,1 + +00000410 : + 410: 0000006f j 410 + ... + +Disassembly of section .data: + +00001000 : + 1000: jal t6,fffff6fe <_end+0xffffe676> + +00001001 : + 1001: jal t6,fffff6ff <_end+0xffffe677> + +00001002 : + 1002: jal t6,fffff700 <_end+0xffffe678> + +00001003 : + 1003: jal t6,fffff701 <_end+0xffffe679> + +00001004 : + 1004: jal t6,fffff702 <_end+0xffffe67a> + +00001005 : + 1005: jal t6,fffff703 <_end+0xffffe67b> + +00001006 : + 1006: jal t6,fffff704 <_end+0xffffe67c> + +00001007 : + 1007: jal t6,ff015 <_end+0xfdf8d> + +00001008 : + 1008: jal t6,f008 <_end+0xdf80> + +00001009 : + 1009: 000000ef jal ra,1009 + 100d: 0000 unimp + ... + +Disassembly of section .tohost: + +00001040 : + ... + +00001080 : + ... diff --git a/tests/isa/generated/rv32ui-p-sb.verilog b/tests/isa/generated/rv32ui-p-sb.verilog new file mode 100644 index 0000000..8e18bce --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sb.verilog @@ -0,0 +1,78 @@ +@00000000 +13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF +13 01 A0 FA 23 80 20 00 03 8F 00 00 93 0E A0 FA +93 01 20 00 63 1C DF 3D 97 10 00 00 93 80 80 FD +13 01 00 00 A3 80 20 00 03 8F 10 00 93 0E 00 00 +93 01 30 00 63 1C DF 3B 97 10 00 00 93 80 80 FB +37 F1 FF FF 13 01 01 FA 23 81 20 00 03 9F 20 00 +B7 FE FF FF 93 8E 0E FA 93 01 40 00 63 18 DF 39 +97 10 00 00 93 80 00 F9 13 01 A0 00 A3 81 20 00 +03 8F 30 00 93 0E A0 00 93 01 50 00 63 18 DF 37 +97 10 00 00 93 80 70 F7 13 01 A0 FA A3 8E 20 FE +03 8F D0 FF 93 0E A0 FA 93 01 60 00 63 18 DF 35 +97 10 00 00 93 80 70 F5 13 01 00 00 23 8F 20 FE +03 8F E0 FF 93 0E 00 00 93 01 70 00 63 18 DF 33 +97 10 00 00 93 80 70 F3 13 01 00 FA A3 8F 20 FE +03 8F F0 FF 93 0E 00 FA 93 01 80 00 63 18 DF 31 +97 10 00 00 93 80 70 F1 13 01 A0 00 23 80 20 00 +03 8F 00 00 93 0E A0 00 93 01 90 00 63 18 DF 2F +97 10 00 00 93 80 80 EF 37 51 34 12 13 01 81 67 +13 82 00 FE 23 00 22 02 83 82 00 00 93 0E 80 07 +93 01 A0 00 63 94 D2 2D 97 10 00 00 93 80 00 ED +37 31 00 00 13 01 81 09 93 80 A0 FF A3 83 20 00 +17 12 00 00 13 02 92 EB 83 02 02 00 93 0E 80 F9 +93 01 B0 00 63 9C D2 29 93 01 C0 00 13 02 00 00 +93 00 D0 FD 17 11 00 00 13 01 C1 E8 23 00 11 00 +03 0F 01 00 93 0E D0 FD 63 1A DF 27 13 02 12 00 +93 02 20 00 E3 1E 52 FC 93 01 D0 00 13 02 00 00 +93 00 D0 FC 17 11 00 00 13 01 C1 E5 13 00 00 00 +A3 00 11 00 03 0F 11 00 93 0E D0 FC 63 10 DF 25 +13 02 12 00 93 02 20 00 E3 1C 52 FC 93 01 E0 00 +13 02 00 00 93 00 C0 FC 17 11 00 00 13 01 81 E2 +13 00 00 00 13 00 00 00 23 01 11 00 03 0F 21 00 +93 0E C0 FC 63 14 DF 21 13 02 12 00 93 02 20 00 +E3 1A 52 FC 93 01 F0 00 13 02 00 00 93 00 C0 FB +13 00 00 00 17 11 00 00 13 01 C1 DE A3 01 11 00 +03 0F 31 00 93 0E C0 FB 63 1A DF 1D 13 02 12 00 +93 02 20 00 E3 1C 52 FC 93 01 00 01 13 02 00 00 +93 00 B0 FB 13 00 00 00 17 11 00 00 13 01 81 DB +13 00 00 00 23 02 11 00 03 0F 41 00 93 0E B0 FB +63 1E DF 19 13 02 12 00 93 02 20 00 E3 1A 52 FC +93 01 10 01 13 02 00 00 93 00 B0 FA 13 00 00 00 +13 00 00 00 17 11 00 00 13 01 C1 D7 A3 02 11 00 +03 0F 51 00 93 0E B0 FA 63 12 DF 17 13 02 12 00 +93 02 20 00 E3 1A 52 FC 93 01 20 01 13 02 00 00 +17 11 00 00 13 01 01 D5 93 00 30 03 23 00 11 00 +03 0F 01 00 93 0E 30 03 63 1A DF 13 13 02 12 00 +93 02 20 00 E3 1E 52 FC 93 01 30 01 13 02 00 00 +17 11 00 00 13 01 01 D2 93 00 30 02 13 00 00 00 +A3 00 11 00 03 0F 11 00 93 0E 30 02 63 10 DF 11 +13 02 12 00 93 02 20 00 E3 1C 52 FC 93 01 40 01 +13 02 00 00 17 11 00 00 13 01 C1 CE 93 00 20 02 +13 00 00 00 13 00 00 00 23 01 11 00 03 0F 21 00 +93 0E 20 02 63 14 DF 0D 13 02 12 00 93 02 20 00 +E3 1A 52 FC 93 01 50 01 13 02 00 00 17 11 00 00 +13 01 41 CB 13 00 00 00 93 00 20 01 A3 01 11 00 +03 0F 31 00 93 0E 20 01 63 1A DF 09 13 02 12 00 +93 02 20 00 E3 1C 52 FC 93 01 60 01 13 02 00 00 +17 11 00 00 13 01 01 C8 13 00 00 00 93 00 10 01 +13 00 00 00 23 02 11 00 03 0F 41 00 93 0E 10 01 +63 1E DF 05 13 02 12 00 93 02 20 00 E3 1A 52 FC +93 01 70 01 13 02 00 00 17 11 00 00 13 01 81 C4 +13 00 00 00 13 00 00 00 93 00 10 00 A3 02 11 00 +03 0F 51 00 93 0E 10 00 63 12 DF 03 13 02 12 00 +93 02 20 00 E3 1A 52 FC 13 05 F0 0E 97 15 00 00 +93 85 45 C1 A3 81 A5 00 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00001000 +EF EF EF EF EF EF EF EF EF EF 00 00 00 00 00 00 +@00001040 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-sh b/tests/isa/generated/rv32ui-p-sh new file mode 100644 index 0000000..20c2baf Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sh differ diff --git a/tests/isa/generated/rv32ui-p-sh.bin b/tests/isa/generated/rv32ui-p-sh.bin new file mode 100644 index 0000000..d5dfeb6 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sh.bin differ diff --git a/tests/isa/generated/rv32ui-p-sh.dump b/tests/isa/generated/rv32ui-p-sh.dump new file mode 100644 index 0000000..c2a8576 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sh.dump @@ -0,0 +1,395 @@ + +generated/rv32ui-p-sh: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00001097 auipc ra,0x1 + c: ff808093 addi ra,ra,-8 # 1000 + 10: 0aa00113 li sp,170 + 14: 00209023 sh sp,0(ra) + 18: 00009f03 lh t5,0(ra) + 1c: 0aa00e93 li t4,170 + 20: 00200193 li gp,2 + 24: 45df1e63 bne t5,t4,480 + +00000028 : + 28: 00001097 auipc ra,0x1 + 2c: fd808093 addi ra,ra,-40 # 1000 + 30: ffffb137 lui sp,0xffffb + 34: a0010113 addi sp,sp,-1536 # ffffaa00 <_end+0xffff9978> + 38: 00209123 sh sp,2(ra) + 3c: 00209f03 lh t5,2(ra) + 40: ffffbeb7 lui t4,0xffffb + 44: a00e8e93 addi t4,t4,-1536 # ffffaa00 <_end+0xffff9978> + 48: 00300193 li gp,3 + 4c: 43df1a63 bne t5,t4,480 + +00000050 : + 50: 00001097 auipc ra,0x1 + 54: fb008093 addi ra,ra,-80 # 1000 + 58: beef1137 lui sp,0xbeef1 + 5c: aa010113 addi sp,sp,-1376 # beef0aa0 <_end+0xbeeefa18> + 60: 00209223 sh sp,4(ra) + 64: 0040af03 lw t5,4(ra) + 68: beef1eb7 lui t4,0xbeef1 + 6c: aa0e8e93 addi t4,t4,-1376 # beef0aa0 <_end+0xbeeefa18> + 70: 00400193 li gp,4 + 74: 41df1663 bne t5,t4,480 + +00000078 : + 78: 00001097 auipc ra,0x1 + 7c: f8808093 addi ra,ra,-120 # 1000 + 80: ffffa137 lui sp,0xffffa + 84: 00a10113 addi sp,sp,10 # ffffa00a <_end+0xffff8f82> + 88: 00209323 sh sp,6(ra) + 8c: 00609f03 lh t5,6(ra) + 90: ffffaeb7 lui t4,0xffffa + 94: 00ae8e93 addi t4,t4,10 # ffffa00a <_end+0xffff8f82> + 98: 00500193 li gp,5 + 9c: 3fdf1263 bne t5,t4,480 + +000000a0 : + a0: 00001097 auipc ra,0x1 + a4: f6e08093 addi ra,ra,-146 # 100e + a8: 0aa00113 li sp,170 + ac: fe209d23 sh sp,-6(ra) + b0: ffa09f03 lh t5,-6(ra) + b4: 0aa00e93 li t4,170 + b8: 00600193 li gp,6 + bc: 3ddf1263 bne t5,t4,480 + +000000c0 : + c0: 00001097 auipc ra,0x1 + c4: f4e08093 addi ra,ra,-178 # 100e + c8: ffffb137 lui sp,0xffffb + cc: a0010113 addi sp,sp,-1536 # ffffaa00 <_end+0xffff9978> + d0: fe209e23 sh sp,-4(ra) + d4: ffc09f03 lh t5,-4(ra) + d8: ffffbeb7 lui t4,0xffffb + dc: a00e8e93 addi t4,t4,-1536 # ffffaa00 <_end+0xffff9978> + e0: 00700193 li gp,7 + e4: 39df1e63 bne t5,t4,480 + +000000e8 : + e8: 00001097 auipc ra,0x1 + ec: f2608093 addi ra,ra,-218 # 100e + f0: 00001137 lui sp,0x1 + f4: aa010113 addi sp,sp,-1376 # aa0 + f8: fe209f23 sh sp,-2(ra) + fc: ffe09f03 lh t5,-2(ra) + 100: 00001eb7 lui t4,0x1 + 104: aa0e8e93 addi t4,t4,-1376 # aa0 + 108: 00800193 li gp,8 + 10c: 37df1a63 bne t5,t4,480 + +00000110 : + 110: 00001097 auipc ra,0x1 + 114: efe08093 addi ra,ra,-258 # 100e + 118: ffffa137 lui sp,0xffffa + 11c: 00a10113 addi sp,sp,10 # ffffa00a <_end+0xffff8f82> + 120: 00209023 sh sp,0(ra) + 124: 00009f03 lh t5,0(ra) + 128: ffffaeb7 lui t4,0xffffa + 12c: 00ae8e93 addi t4,t4,10 # ffffa00a <_end+0xffff8f82> + 130: 00900193 li gp,9 + 134: 35df1663 bne t5,t4,480 + +00000138 : + 138: 00001097 auipc ra,0x1 + 13c: ed808093 addi ra,ra,-296 # 1010 + 140: 12345137 lui sp,0x12345 + 144: 67810113 addi sp,sp,1656 # 12345678 <_end+0x123445f0> + 148: fe008213 addi tp,ra,-32 + 14c: 02221023 sh sp,32(tp) # 20 + 150: 00009283 lh t0,0(ra) + 154: 00005eb7 lui t4,0x5 + 158: 678e8e93 addi t4,t4,1656 # 5678 <_end+0x45f0> + 15c: 00a00193 li gp,10 + 160: 33d29063 bne t0,t4,480 + +00000164 : + 164: 00001097 auipc ra,0x1 + 168: eac08093 addi ra,ra,-340 # 1010 + 16c: 00003137 lui sp,0x3 + 170: 09810113 addi sp,sp,152 # 3098 <_end+0x2010> + 174: ffb08093 addi ra,ra,-5 + 178: 002093a3 sh sp,7(ra) + 17c: 00001217 auipc tp,0x1 + 180: e9620213 addi tp,tp,-362 # 1012 + 184: 00021283 lh t0,0(tp) # 0 <_start> + 188: 00003eb7 lui t4,0x3 + 18c: 098e8e93 addi t4,t4,152 # 3098 <_end+0x2010> + 190: 00b00193 li gp,11 + 194: 2fd29663 bne t0,t4,480 + +00000198 : + 198: 00c00193 li gp,12 + 19c: 00000213 li tp,0 + 1a0: ffffd0b7 lui ra,0xffffd + 1a4: cdd08093 addi ra,ra,-803 # ffffccdd <_end+0xffffbc55> + 1a8: 00001117 auipc sp,0x1 + 1ac: e5810113 addi sp,sp,-424 # 1000 + 1b0: 00111023 sh ra,0(sp) + 1b4: 00011f03 lh t5,0(sp) + 1b8: ffffdeb7 lui t4,0xffffd + 1bc: cdde8e93 addi t4,t4,-803 # ffffccdd <_end+0xffffbc55> + 1c0: 2ddf1063 bne t5,t4,480 + 1c4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1c8: 00200293 li t0,2 + 1cc: fc521ae3 bne tp,t0,1a0 + +000001d0 : + 1d0: 00d00193 li gp,13 + 1d4: 00000213 li tp,0 + 1d8: ffffc0b7 lui ra,0xffffc + 1dc: ccd08093 addi ra,ra,-819 # ffffbccd <_end+0xffffac45> + 1e0: 00001117 auipc sp,0x1 + 1e4: e2010113 addi sp,sp,-480 # 1000 + 1e8: 00000013 nop + 1ec: 00111123 sh ra,2(sp) + 1f0: 00211f03 lh t5,2(sp) + 1f4: ffffceb7 lui t4,0xffffc + 1f8: ccde8e93 addi t4,t4,-819 # ffffbccd <_end+0xffffac45> + 1fc: 29df1263 bne t5,t4,480 + 200: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 204: 00200293 li t0,2 + 208: fc5218e3 bne tp,t0,1d8 + +0000020c : + 20c: 00e00193 li gp,14 + 210: 00000213 li tp,0 + 214: ffffc0b7 lui ra,0xffffc + 218: bcc08093 addi ra,ra,-1076 # ffffbbcc <_end+0xffffab44> + 21c: 00001117 auipc sp,0x1 + 220: de410113 addi sp,sp,-540 # 1000 + 224: 00000013 nop + 228: 00000013 nop + 22c: 00111223 sh ra,4(sp) + 230: 00411f03 lh t5,4(sp) + 234: ffffceb7 lui t4,0xffffc + 238: bcce8e93 addi t4,t4,-1076 # ffffbbcc <_end+0xffffab44> + 23c: 25df1263 bne t5,t4,480 + 240: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 244: 00200293 li t0,2 + 248: fc5216e3 bne tp,t0,214 + +0000024c : + 24c: 00f00193 li gp,15 + 250: 00000213 li tp,0 + 254: ffffb0b7 lui ra,0xffffb + 258: bbc08093 addi ra,ra,-1092 # ffffabbc <_end+0xffff9b34> + 25c: 00000013 nop + 260: 00001117 auipc sp,0x1 + 264: da010113 addi sp,sp,-608 # 1000 + 268: 00111323 sh ra,6(sp) + 26c: 00611f03 lh t5,6(sp) + 270: ffffbeb7 lui t4,0xffffb + 274: bbce8e93 addi t4,t4,-1092 # ffffabbc <_end+0xffff9b34> + 278: 21df1463 bne t5,t4,480 + 27c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 280: 00200293 li t0,2 + 284: fc5218e3 bne tp,t0,254 + +00000288 : + 288: 01000193 li gp,16 + 28c: 00000213 li tp,0 + 290: ffffb0b7 lui ra,0xffffb + 294: abb08093 addi ra,ra,-1349 # ffffaabb <_end+0xffff9a33> + 298: 00000013 nop + 29c: 00001117 auipc sp,0x1 + 2a0: d6410113 addi sp,sp,-668 # 1000 + 2a4: 00000013 nop + 2a8: 00111423 sh ra,8(sp) + 2ac: 00811f03 lh t5,8(sp) + 2b0: ffffbeb7 lui t4,0xffffb + 2b4: abbe8e93 addi t4,t4,-1349 # ffffaabb <_end+0xffff9a33> + 2b8: 1ddf1463 bne t5,t4,480 + 2bc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2c0: 00200293 li t0,2 + 2c4: fc5216e3 bne tp,t0,290 + +000002c8 : + 2c8: 01100193 li gp,17 + 2cc: 00000213 li tp,0 + 2d0: ffffe0b7 lui ra,0xffffe + 2d4: aab08093 addi ra,ra,-1365 # ffffdaab <_end+0xffffca23> + 2d8: 00000013 nop + 2dc: 00000013 nop + 2e0: 00001117 auipc sp,0x1 + 2e4: d2010113 addi sp,sp,-736 # 1000 + 2e8: 00111523 sh ra,10(sp) + 2ec: 00a11f03 lh t5,10(sp) + 2f0: ffffeeb7 lui t4,0xffffe + 2f4: aabe8e93 addi t4,t4,-1365 # ffffdaab <_end+0xffffca23> + 2f8: 19df1463 bne t5,t4,480 + 2fc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 300: 00200293 li t0,2 + 304: fc5216e3 bne tp,t0,2d0 + +00000308 : + 308: 01200193 li gp,18 + 30c: 00000213 li tp,0 + 310: 00001117 auipc sp,0x1 + 314: cf010113 addi sp,sp,-784 # 1000 + 318: 000020b7 lui ra,0x2 + 31c: 23308093 addi ra,ra,563 # 2233 <_end+0x11ab> + 320: 00111023 sh ra,0(sp) + 324: 00011f03 lh t5,0(sp) + 328: 00002eb7 lui t4,0x2 + 32c: 233e8e93 addi t4,t4,563 # 2233 <_end+0x11ab> + 330: 15df1863 bne t5,t4,480 + 334: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 338: 00200293 li t0,2 + 33c: fc521ae3 bne tp,t0,310 + +00000340 : + 340: 01300193 li gp,19 + 344: 00000213 li tp,0 + 348: 00001117 auipc sp,0x1 + 34c: cb810113 addi sp,sp,-840 # 1000 + 350: 000010b7 lui ra,0x1 + 354: 22308093 addi ra,ra,547 # 1223 <_end+0x19b> + 358: 00000013 nop + 35c: 00111123 sh ra,2(sp) + 360: 00211f03 lh t5,2(sp) + 364: 00001eb7 lui t4,0x1 + 368: 223e8e93 addi t4,t4,547 # 1223 <_end+0x19b> + 36c: 11df1a63 bne t5,t4,480 + 370: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 374: 00200293 li t0,2 + 378: fc5218e3 bne tp,t0,348 + +0000037c : + 37c: 01400193 li gp,20 + 380: 00000213 li tp,0 + 384: 00001117 auipc sp,0x1 + 388: c7c10113 addi sp,sp,-900 # 1000 + 38c: 000010b7 lui ra,0x1 + 390: 12208093 addi ra,ra,290 # 1122 <_end+0x9a> + 394: 00000013 nop + 398: 00000013 nop + 39c: 00111223 sh ra,4(sp) + 3a0: 00411f03 lh t5,4(sp) + 3a4: 00001eb7 lui t4,0x1 + 3a8: 122e8e93 addi t4,t4,290 # 1122 <_end+0x9a> + 3ac: 0ddf1a63 bne t5,t4,480 + 3b0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3b4: 00200293 li t0,2 + 3b8: fc5216e3 bne tp,t0,384 + +000003bc : + 3bc: 01500193 li gp,21 + 3c0: 00000213 li tp,0 + 3c4: 00001117 auipc sp,0x1 + 3c8: c3c10113 addi sp,sp,-964 # 1000 + 3cc: 00000013 nop + 3d0: 11200093 li ra,274 + 3d4: 00111323 sh ra,6(sp) + 3d8: 00611f03 lh t5,6(sp) + 3dc: 11200e93 li t4,274 + 3e0: 0bdf1063 bne t5,t4,480 + 3e4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3e8: 00200293 li t0,2 + 3ec: fc521ce3 bne tp,t0,3c4 + +000003f0 : + 3f0: 01600193 li gp,22 + 3f4: 00000213 li tp,0 + 3f8: 00001117 auipc sp,0x1 + 3fc: c0810113 addi sp,sp,-1016 # 1000 + 400: 00000013 nop + 404: 01100093 li ra,17 + 408: 00000013 nop + 40c: 00111423 sh ra,8(sp) + 410: 00811f03 lh t5,8(sp) + 414: 01100e93 li t4,17 + 418: 07df1463 bne t5,t4,480 + 41c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 420: 00200293 li t0,2 + 424: fc521ae3 bne tp,t0,3f8 + +00000428 : + 428: 01700193 li gp,23 + 42c: 00000213 li tp,0 + 430: 00001117 auipc sp,0x1 + 434: bd010113 addi sp,sp,-1072 # 1000 + 438: 00000013 nop + 43c: 00000013 nop + 440: 000030b7 lui ra,0x3 + 444: 00108093 addi ra,ra,1 # 3001 <_end+0x1f79> + 448: 00111523 sh ra,10(sp) + 44c: 00a11f03 lh t5,10(sp) + 450: 00003eb7 lui t4,0x3 + 454: 001e8e93 addi t4,t4,1 # 3001 <_end+0x1f79> + 458: 03df1463 bne t5,t4,480 + 45c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 460: 00200293 li t0,2 + 464: fc5216e3 bne tp,t0,430 + 468: 0000c537 lui a0,0xc + 46c: eef50513 addi a0,a0,-273 # beef <_end+0xae67> + 470: 00001597 auipc a1,0x1 + 474: b9058593 addi a1,a1,-1136 # 1000 + 478: 00a59323 sh a0,6(a1) + 47c: 00301863 bne zero,gp,48c + +00000480 : + 480: 00100d13 li s10,1 + 484: 00000d93 li s11,0 + +00000488 : + 488: 0000006f j 488 + +0000048c : + 48c: 00100d13 li s10,1 + 490: 00100d93 li s11,1 + +00000494 : + 494: 0000006f j 494 + ... + +Disassembly of section .data: + +00001000 : + 1000: jal t4,ffffc3ee <_end+0xffffb366> + +00001002 : + 1002: jal t4,ffffc3f0 <_end+0xffffb368> + +00001004 : + 1004: jal t4,ffffc3f2 <_end+0xffffb36a> + +00001006 : + 1006: jal t4,ffffc3f4 <_end+0xffffb36c> + +00001008 : + 1008: jal t4,ffffc3f6 <_end+0xffffb36e> + +0000100a : + 100a: jal t4,ffffc3f8 <_end+0xffffb370> + +0000100c : + 100c: jal t4,ffffc3fa <_end+0xffffb372> + +0000100e : + 100e: jal t4,ffffc3fc <_end+0xffffb374> + +00001010 : + 1010: jal t4,ffffc3fe <_end+0xffffb376> + +00001012 : + 1012: 0000beef jal t4,c012 <_end+0xaf8a> + ... + +Disassembly of section .tohost: + +00001040 : + ... + +00001080 : + ... diff --git a/tests/isa/generated/rv32ui-p-sh.verilog b/tests/isa/generated/rv32ui-p-sh.verilog new file mode 100644 index 0000000..8a3fba2 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sh.verilog @@ -0,0 +1,87 @@ +@00000000 +13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF +13 01 A0 0A 23 90 20 00 03 9F 00 00 93 0E A0 0A +93 01 20 00 63 1E DF 45 97 10 00 00 93 80 80 FD +37 B1 FF FF 13 01 01 A0 23 91 20 00 03 9F 20 00 +B7 BE FF FF 93 8E 0E A0 93 01 30 00 63 1A DF 43 +97 10 00 00 93 80 00 FB 37 11 EF BE 13 01 01 AA +23 92 20 00 03 AF 40 00 B7 1E EF BE 93 8E 0E AA +93 01 40 00 63 16 DF 41 97 10 00 00 93 80 80 F8 +37 A1 FF FF 13 01 A1 00 23 93 20 00 03 9F 60 00 +B7 AE FF FF 93 8E AE 00 93 01 50 00 63 12 DF 3F +97 10 00 00 93 80 E0 F6 13 01 A0 0A 23 9D 20 FE +03 9F A0 FF 93 0E A0 0A 93 01 60 00 63 12 DF 3D +97 10 00 00 93 80 E0 F4 37 B1 FF FF 13 01 01 A0 +23 9E 20 FE 03 9F C0 FF B7 BE FF FF 93 8E 0E A0 +93 01 70 00 63 1E DF 39 97 10 00 00 93 80 60 F2 +37 11 00 00 13 01 01 AA 23 9F 20 FE 03 9F E0 FF +B7 1E 00 00 93 8E 0E AA 93 01 80 00 63 1A DF 37 +97 10 00 00 93 80 E0 EF 37 A1 FF FF 13 01 A1 00 +23 90 20 00 03 9F 00 00 B7 AE FF FF 93 8E AE 00 +93 01 90 00 63 16 DF 35 97 10 00 00 93 80 80 ED +37 51 34 12 13 01 81 67 13 82 00 FE 23 10 22 02 +83 92 00 00 B7 5E 00 00 93 8E 8E 67 93 01 A0 00 +63 90 D2 33 97 10 00 00 93 80 C0 EA 37 31 00 00 +13 01 81 09 93 80 B0 FF A3 93 20 00 17 12 00 00 +13 02 62 E9 83 12 02 00 B7 3E 00 00 93 8E 8E 09 +93 01 B0 00 63 96 D2 2F 93 01 C0 00 13 02 00 00 +B7 D0 FF FF 93 80 D0 CD 17 11 00 00 13 01 81 E5 +23 10 11 00 03 1F 01 00 B7 DE FF FF 93 8E DE CD +63 10 DF 2D 13 02 12 00 93 02 20 00 E3 1A 52 FC +93 01 D0 00 13 02 00 00 B7 C0 FF FF 93 80 D0 CC +17 11 00 00 13 01 01 E2 13 00 00 00 23 11 11 00 +03 1F 21 00 B7 CE FF FF 93 8E DE CC 63 12 DF 29 +13 02 12 00 93 02 20 00 E3 18 52 FC 93 01 E0 00 +13 02 00 00 B7 C0 FF FF 93 80 C0 BC 17 11 00 00 +13 01 41 DE 13 00 00 00 13 00 00 00 23 12 11 00 +03 1F 41 00 B7 CE FF FF 93 8E CE BC 63 12 DF 25 +13 02 12 00 93 02 20 00 E3 16 52 FC 93 01 F0 00 +13 02 00 00 B7 B0 FF FF 93 80 C0 BB 13 00 00 00 +17 11 00 00 13 01 01 DA 23 13 11 00 03 1F 61 00 +B7 BE FF FF 93 8E CE BB 63 14 DF 21 13 02 12 00 +93 02 20 00 E3 18 52 FC 93 01 00 01 13 02 00 00 +B7 B0 FF FF 93 80 B0 AB 13 00 00 00 17 11 00 00 +13 01 41 D6 13 00 00 00 23 14 11 00 03 1F 81 00 +B7 BE FF FF 93 8E BE AB 63 14 DF 1D 13 02 12 00 +93 02 20 00 E3 16 52 FC 93 01 10 01 13 02 00 00 +B7 E0 FF FF 93 80 B0 AA 13 00 00 00 13 00 00 00 +17 11 00 00 13 01 01 D2 23 15 11 00 03 1F A1 00 +B7 EE FF FF 93 8E BE AA 63 14 DF 19 13 02 12 00 +93 02 20 00 E3 16 52 FC 93 01 20 01 13 02 00 00 +17 11 00 00 13 01 01 CF B7 20 00 00 93 80 30 23 +23 10 11 00 03 1F 01 00 B7 2E 00 00 93 8E 3E 23 +63 18 DF 15 13 02 12 00 93 02 20 00 E3 1A 52 FC +93 01 30 01 13 02 00 00 17 11 00 00 13 01 81 CB +B7 10 00 00 93 80 30 22 13 00 00 00 23 11 11 00 +03 1F 21 00 B7 1E 00 00 93 8E 3E 22 63 1A DF 11 +13 02 12 00 93 02 20 00 E3 18 52 FC 93 01 40 01 +13 02 00 00 17 11 00 00 13 01 C1 C7 B7 10 00 00 +93 80 20 12 13 00 00 00 13 00 00 00 23 12 11 00 +03 1F 41 00 B7 1E 00 00 93 8E 2E 12 63 1A DF 0D +13 02 12 00 93 02 20 00 E3 16 52 FC 93 01 50 01 +13 02 00 00 17 11 00 00 13 01 C1 C3 13 00 00 00 +93 00 20 11 23 13 11 00 03 1F 61 00 93 0E 20 11 +63 10 DF 0B 13 02 12 00 93 02 20 00 E3 1C 52 FC +93 01 60 01 13 02 00 00 17 11 00 00 13 01 81 C0 +13 00 00 00 93 00 10 01 13 00 00 00 23 14 11 00 +03 1F 81 00 93 0E 10 01 63 14 DF 07 13 02 12 00 +93 02 20 00 E3 1A 52 FC 93 01 70 01 13 02 00 00 +17 11 00 00 13 01 01 BD 13 00 00 00 13 00 00 00 +B7 30 00 00 93 80 10 00 23 15 11 00 03 1F A1 00 +B7 3E 00 00 93 8E 1E 00 63 14 DF 03 13 02 12 00 +93 02 20 00 E3 16 52 FC 37 C5 00 00 13 05 F5 EE +97 15 00 00 93 85 05 B9 23 93 A5 00 63 18 30 00 +13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00 +93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00001000 +EF BE EF BE EF BE EF BE EF BE EF BE EF BE EF BE +EF BE EF BE 00 00 00 00 00 00 00 00 00 00 00 00 +@00001040 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-simple b/tests/isa/generated/rv32ui-p-simple new file mode 100644 index 0000000..23941b7 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-simple differ diff --git a/tests/isa/generated/rv32ui-p-simple.bin b/tests/isa/generated/rv32ui-p-simple.bin new file mode 100644 index 0000000..f7f7ec8 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-simple.bin differ diff --git a/tests/isa/generated/rv32ui-p-simple.dump b/tests/isa/generated/rv32ui-p-simple.dump new file mode 100644 index 0000000..019a84c --- /dev/null +++ b/tests/isa/generated/rv32ui-p-simple.dump @@ -0,0 +1,23 @@ + +generated/rv32ui-p-simple: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + 8: 00100d13 li s10,1 + c: 00100d93 li s11,1 + +00000010 : + 10: 0000006f j 10 + ... + +Disassembly of section .tohost: + +00000080 : + ... + +000000c0 : + ... diff --git a/tests/isa/generated/rv32ui-p-simple.verilog b/tests/isa/generated/rv32ui-p-simple.verilog new file mode 100644 index 0000000..3df5df1 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-simple.verilog @@ -0,0 +1,12 @@ +@00000000 +13 0D 00 00 93 0D 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000080 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-sll b/tests/isa/generated/rv32ui-p-sll new file mode 100644 index 0000000..cb620fd Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sll differ diff --git a/tests/isa/generated/rv32ui-p-sll.bin b/tests/isa/generated/rv32ui-p-sll.bin new file mode 100644 index 0000000..5a896b0 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sll.bin differ diff --git a/tests/isa/generated/rv32ui-p-sll.dump b/tests/isa/generated/rv32ui-p-sll.dump new file mode 100644 index 0000000..0f57c51 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sll.dump @@ -0,0 +1,454 @@ + +generated/rv32ui-p-sll: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00100093 li ra,1 + c: 00000113 li sp,0 + 10: 00209f33 sll t5,ra,sp + 14: 00100e93 li t4,1 + 18: 00200193 li gp,2 + 1c: 53df1e63 bne t5,t4,558 + +00000020 : + 20: 00100093 li ra,1 + 24: 00100113 li sp,1 + 28: 00209f33 sll t5,ra,sp + 2c: 00200e93 li t4,2 + 30: 00300193 li gp,3 + 34: 53df1263 bne t5,t4,558 + +00000038 : + 38: 00100093 li ra,1 + 3c: 00700113 li sp,7 + 40: 00209f33 sll t5,ra,sp + 44: 08000e93 li t4,128 + 48: 00400193 li gp,4 + 4c: 51df1663 bne t5,t4,558 + +00000050 : + 50: 00100093 li ra,1 + 54: 00e00113 li sp,14 + 58: 00209f33 sll t5,ra,sp + 5c: 00004eb7 lui t4,0x4 + 60: 00500193 li gp,5 + 64: 4fdf1a63 bne t5,t4,558 + +00000068 : + 68: 00100093 li ra,1 + 6c: 01f00113 li sp,31 + 70: 00209f33 sll t5,ra,sp + 74: 80000eb7 lui t4,0x80000 + 78: 00600193 li gp,6 + 7c: 4ddf1e63 bne t5,t4,558 + +00000080 : + 80: fff00093 li ra,-1 + 84: 00000113 li sp,0 + 88: 00209f33 sll t5,ra,sp + 8c: fff00e93 li t4,-1 + 90: 00700193 li gp,7 + 94: 4ddf1263 bne t5,t4,558 + +00000098 : + 98: fff00093 li ra,-1 + 9c: 00100113 li sp,1 + a0: 00209f33 sll t5,ra,sp + a4: ffe00e93 li t4,-2 + a8: 00800193 li gp,8 + ac: 4bdf1663 bne t5,t4,558 + +000000b0 : + b0: fff00093 li ra,-1 + b4: 00700113 li sp,7 + b8: 00209f33 sll t5,ra,sp + bc: f8000e93 li t4,-128 + c0: 00900193 li gp,9 + c4: 49df1a63 bne t5,t4,558 + +000000c8 : + c8: fff00093 li ra,-1 + cc: 00e00113 li sp,14 + d0: 00209f33 sll t5,ra,sp + d4: ffffceb7 lui t4,0xffffc + d8: 00a00193 li gp,10 + dc: 47df1e63 bne t5,t4,558 + +000000e0 : + e0: fff00093 li ra,-1 + e4: 01f00113 li sp,31 + e8: 00209f33 sll t5,ra,sp + ec: 80000eb7 lui t4,0x80000 + f0: 00b00193 li gp,11 + f4: 47df1263 bne t5,t4,558 + +000000f8 : + f8: 212120b7 lui ra,0x21212 + fc: 12108093 addi ra,ra,289 # 21212121 + 100: 00000113 li sp,0 + 104: 00209f33 sll t5,ra,sp + 108: 21212eb7 lui t4,0x21212 + 10c: 121e8e93 addi t4,t4,289 # 21212121 + 110: 00c00193 li gp,12 + 114: 45df1263 bne t5,t4,558 + +00000118 : + 118: 212120b7 lui ra,0x21212 + 11c: 12108093 addi ra,ra,289 # 21212121 + 120: 00100113 li sp,1 + 124: 00209f33 sll t5,ra,sp + 128: 42424eb7 lui t4,0x42424 + 12c: 242e8e93 addi t4,t4,578 # 42424242 + 130: 00d00193 li gp,13 + 134: 43df1263 bne t5,t4,558 + +00000138 : + 138: 212120b7 lui ra,0x21212 + 13c: 12108093 addi ra,ra,289 # 21212121 + 140: 00700113 li sp,7 + 144: 00209f33 sll t5,ra,sp + 148: 90909eb7 lui t4,0x90909 + 14c: 080e8e93 addi t4,t4,128 # 90909080 + 150: 00e00193 li gp,14 + 154: 41df1263 bne t5,t4,558 + +00000158 : + 158: 212120b7 lui ra,0x21212 + 15c: 12108093 addi ra,ra,289 # 21212121 + 160: 00e00113 li sp,14 + 164: 00209f33 sll t5,ra,sp + 168: 48484eb7 lui t4,0x48484 + 16c: 00f00193 li gp,15 + 170: 3fdf1463 bne t5,t4,558 + +00000174 : + 174: 212120b7 lui ra,0x21212 + 178: 12108093 addi ra,ra,289 # 21212121 + 17c: 01f00113 li sp,31 + 180: 00209f33 sll t5,ra,sp + 184: 80000eb7 lui t4,0x80000 + 188: 01000193 li gp,16 + 18c: 3ddf1663 bne t5,t4,558 + +00000190 : + 190: 212120b7 lui ra,0x21212 + 194: 12108093 addi ra,ra,289 # 21212121 + 198: fc000113 li sp,-64 + 19c: 00209f33 sll t5,ra,sp + 1a0: 21212eb7 lui t4,0x21212 + 1a4: 121e8e93 addi t4,t4,289 # 21212121 + 1a8: 01100193 li gp,17 + 1ac: 3bdf1663 bne t5,t4,558 + +000001b0 : + 1b0: 212120b7 lui ra,0x21212 + 1b4: 12108093 addi ra,ra,289 # 21212121 + 1b8: fc100113 li sp,-63 + 1bc: 00209f33 sll t5,ra,sp + 1c0: 42424eb7 lui t4,0x42424 + 1c4: 242e8e93 addi t4,t4,578 # 42424242 + 1c8: 01200193 li gp,18 + 1cc: 39df1663 bne t5,t4,558 + +000001d0 : + 1d0: 212120b7 lui ra,0x21212 + 1d4: 12108093 addi ra,ra,289 # 21212121 + 1d8: fc700113 li sp,-57 + 1dc: 00209f33 sll t5,ra,sp + 1e0: 90909eb7 lui t4,0x90909 + 1e4: 080e8e93 addi t4,t4,128 # 90909080 + 1e8: 01300193 li gp,19 + 1ec: 37df1663 bne t5,t4,558 + +000001f0 : + 1f0: 212120b7 lui ra,0x21212 + 1f4: 12108093 addi ra,ra,289 # 21212121 + 1f8: fce00113 li sp,-50 + 1fc: 00209f33 sll t5,ra,sp + 200: 48484eb7 lui t4,0x48484 + 204: 01400193 li gp,20 + 208: 35df1863 bne t5,t4,558 + +0000020c : + 20c: 00100093 li ra,1 + 210: 00700113 li sp,7 + 214: 002090b3 sll ra,ra,sp + 218: 08000e93 li t4,128 + 21c: 01600193 li gp,22 + 220: 33d09c63 bne ra,t4,558 + +00000224 : + 224: 00100093 li ra,1 + 228: 00e00113 li sp,14 + 22c: 00209133 sll sp,ra,sp + 230: 00004eb7 lui t4,0x4 + 234: 01700193 li gp,23 + 238: 33d11063 bne sp,t4,558 + +0000023c : + 23c: 00300093 li ra,3 + 240: 001090b3 sll ra,ra,ra + 244: 01800e93 li t4,24 + 248: 01800193 li gp,24 + 24c: 31d09663 bne ra,t4,558 + +00000250 : + 250: 00000213 li tp,0 + 254: 00100093 li ra,1 + 258: 00700113 li sp,7 + 25c: 00209f33 sll t5,ra,sp + 260: 000f0313 mv t1,t5 + 264: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 268: 00200293 li t0,2 + 26c: fe5214e3 bne tp,t0,254 + 270: 08000e93 li t4,128 + 274: 01900193 li gp,25 + 278: 2fd31063 bne t1,t4,558 + +0000027c : + 27c: 00000213 li tp,0 + 280: 00100093 li ra,1 + 284: 00e00113 li sp,14 + 288: 00209f33 sll t5,ra,sp + 28c: 00000013 nop + 290: 000f0313 mv t1,t5 + 294: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 298: 00200293 li t0,2 + 29c: fe5212e3 bne tp,t0,280 + 2a0: 00004eb7 lui t4,0x4 + 2a4: 01a00193 li gp,26 + 2a8: 2bd31863 bne t1,t4,558 + +000002ac : + 2ac: 00000213 li tp,0 + 2b0: 00100093 li ra,1 + 2b4: 01f00113 li sp,31 + 2b8: 00209f33 sll t5,ra,sp + 2bc: 00000013 nop + 2c0: 00000013 nop + 2c4: 000f0313 mv t1,t5 + 2c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2cc: 00200293 li t0,2 + 2d0: fe5210e3 bne tp,t0,2b0 + 2d4: 80000eb7 lui t4,0x80000 + 2d8: 01b00193 li gp,27 + 2dc: 27d31e63 bne t1,t4,558 + +000002e0 : + 2e0: 00000213 li tp,0 + 2e4: 00100093 li ra,1 + 2e8: 00700113 li sp,7 + 2ec: 00209f33 sll t5,ra,sp + 2f0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2f4: 00200293 li t0,2 + 2f8: fe5216e3 bne tp,t0,2e4 + 2fc: 08000e93 li t4,128 + 300: 01c00193 li gp,28 + 304: 25df1a63 bne t5,t4,558 + +00000308 : + 308: 00000213 li tp,0 + 30c: 00100093 li ra,1 + 310: 00e00113 li sp,14 + 314: 00000013 nop + 318: 00209f33 sll t5,ra,sp + 31c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 320: 00200293 li t0,2 + 324: fe5214e3 bne tp,t0,30c + 328: 00004eb7 lui t4,0x4 + 32c: 01d00193 li gp,29 + 330: 23df1463 bne t5,t4,558 + +00000334 : + 334: 00000213 li tp,0 + 338: 00100093 li ra,1 + 33c: 01f00113 li sp,31 + 340: 00000013 nop + 344: 00000013 nop + 348: 00209f33 sll t5,ra,sp + 34c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 350: 00200293 li t0,2 + 354: fe5212e3 bne tp,t0,338 + 358: 80000eb7 lui t4,0x80000 + 35c: 01e00193 li gp,30 + 360: 1fdf1c63 bne t5,t4,558 + +00000364 : + 364: 00000213 li tp,0 + 368: 00100093 li ra,1 + 36c: 00000013 nop + 370: 00700113 li sp,7 + 374: 00209f33 sll t5,ra,sp + 378: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 37c: 00200293 li t0,2 + 380: fe5214e3 bne tp,t0,368 + 384: 08000e93 li t4,128 + 388: 01f00193 li gp,31 + 38c: 1ddf1663 bne t5,t4,558 + +00000390 : + 390: 00000213 li tp,0 + 394: 00100093 li ra,1 + 398: 00000013 nop + 39c: 00e00113 li sp,14 + 3a0: 00000013 nop + 3a4: 00209f33 sll t5,ra,sp + 3a8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3ac: 00200293 li t0,2 + 3b0: fe5212e3 bne tp,t0,394 + 3b4: 00004eb7 lui t4,0x4 + 3b8: 02000193 li gp,32 + 3bc: 19df1e63 bne t5,t4,558 + +000003c0 : + 3c0: 00000213 li tp,0 + 3c4: 00100093 li ra,1 + 3c8: 00000013 nop + 3cc: 00000013 nop + 3d0: 01f00113 li sp,31 + 3d4: 00209f33 sll t5,ra,sp + 3d8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3dc: 00200293 li t0,2 + 3e0: fe5212e3 bne tp,t0,3c4 + 3e4: 80000eb7 lui t4,0x80000 + 3e8: 02100193 li gp,33 + 3ec: 17df1663 bne t5,t4,558 + +000003f0 : + 3f0: 00000213 li tp,0 + 3f4: 00700113 li sp,7 + 3f8: 00100093 li ra,1 + 3fc: 00209f33 sll t5,ra,sp + 400: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 404: 00200293 li t0,2 + 408: fe5216e3 bne tp,t0,3f4 + 40c: 08000e93 li t4,128 + 410: 02200193 li gp,34 + 414: 15df1263 bne t5,t4,558 + +00000418 : + 418: 00000213 li tp,0 + 41c: 00e00113 li sp,14 + 420: 00100093 li ra,1 + 424: 00000013 nop + 428: 00209f33 sll t5,ra,sp + 42c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 430: 00200293 li t0,2 + 434: fe5214e3 bne tp,t0,41c + 438: 00004eb7 lui t4,0x4 + 43c: 02300193 li gp,35 + 440: 11df1c63 bne t5,t4,558 + +00000444 : + 444: 00000213 li tp,0 + 448: 01f00113 li sp,31 + 44c: 00100093 li ra,1 + 450: 00000013 nop + 454: 00000013 nop + 458: 00209f33 sll t5,ra,sp + 45c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 460: 00200293 li t0,2 + 464: fe5212e3 bne tp,t0,448 + 468: 80000eb7 lui t4,0x80000 + 46c: 02400193 li gp,36 + 470: 0fdf1463 bne t5,t4,558 + +00000474 : + 474: 00000213 li tp,0 + 478: 00700113 li sp,7 + 47c: 00000013 nop + 480: 00100093 li ra,1 + 484: 00209f33 sll t5,ra,sp + 488: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 48c: 00200293 li t0,2 + 490: fe5214e3 bne tp,t0,478 + 494: 08000e93 li t4,128 + 498: 02500193 li gp,37 + 49c: 0bdf1e63 bne t5,t4,558 + +000004a0 : + 4a0: 00000213 li tp,0 + 4a4: 00e00113 li sp,14 + 4a8: 00000013 nop + 4ac: 00100093 li ra,1 + 4b0: 00000013 nop + 4b4: 00209f33 sll t5,ra,sp + 4b8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 4bc: 00200293 li t0,2 + 4c0: fe5212e3 bne tp,t0,4a4 + 4c4: 00004eb7 lui t4,0x4 + 4c8: 02600193 li gp,38 + 4cc: 09df1663 bne t5,t4,558 + +000004d0 : + 4d0: 00000213 li tp,0 + 4d4: 01f00113 li sp,31 + 4d8: 00000013 nop + 4dc: 00000013 nop + 4e0: 00100093 li ra,1 + 4e4: 00209f33 sll t5,ra,sp + 4e8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 4ec: 00200293 li t0,2 + 4f0: fe5212e3 bne tp,t0,4d4 + 4f4: 80000eb7 lui t4,0x80000 + 4f8: 02700193 li gp,39 + 4fc: 05df1e63 bne t5,t4,558 + +00000500 : + 500: 00f00093 li ra,15 + 504: 00101133 sll sp,zero,ra + 508: 00000e93 li t4,0 + 50c: 02800193 li gp,40 + 510: 05d11463 bne sp,t4,558 + +00000514 : + 514: 02000093 li ra,32 + 518: 00009133 sll sp,ra,zero + 51c: 02000e93 li t4,32 + 520: 02900193 li gp,41 + 524: 03d11a63 bne sp,t4,558 + +00000528 : + 528: 000010b3 sll ra,zero,zero + 52c: 00000e93 li t4,0 + 530: 02a00193 li gp,42 + 534: 03d09263 bne ra,t4,558 + +00000538 : + 538: 40000093 li ra,1024 + 53c: 00001137 lui sp,0x1 + 540: 80010113 addi sp,sp,-2048 # 800 <_end+0x1f8> + 544: 00209033 sll zero,ra,sp + 548: 00000e93 li t4,0 + 54c: 02b00193 li gp,43 + 550: 01d01463 bne zero,t4,558 + 554: 00301863 bne zero,gp,564 + +00000558 : + 558: 00100d13 li s10,1 + 55c: 00000d93 li s11,0 + +00000560 : + 560: 0000006f j 560 + +00000564 : + 564: 00100d13 li s10,1 + 568: 00100d93 li s11,1 + +0000056c : + 56c: 0000006f j 56c + ... + +Disassembly of section .tohost: + +000005c0 : + ... + +00000600 : + ... diff --git a/tests/isa/generated/rv32ui-p-sll.verilog b/tests/isa/generated/rv32ui-p-sll.verilog new file mode 100644 index 0000000..a0cb17c --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sll.verilog @@ -0,0 +1,96 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 10 00 13 01 00 00 +33 9F 20 00 93 0E 10 00 93 01 20 00 63 1E DF 53 +93 00 10 00 13 01 10 00 33 9F 20 00 93 0E 20 00 +93 01 30 00 63 12 DF 53 93 00 10 00 13 01 70 00 +33 9F 20 00 93 0E 00 08 93 01 40 00 63 16 DF 51 +93 00 10 00 13 01 E0 00 33 9F 20 00 B7 4E 00 00 +93 01 50 00 63 1A DF 4F 93 00 10 00 13 01 F0 01 +33 9F 20 00 B7 0E 00 80 93 01 60 00 63 1E DF 4D +93 00 F0 FF 13 01 00 00 33 9F 20 00 93 0E F0 FF +93 01 70 00 63 12 DF 4D 93 00 F0 FF 13 01 10 00 +33 9F 20 00 93 0E E0 FF 93 01 80 00 63 16 DF 4B +93 00 F0 FF 13 01 70 00 33 9F 20 00 93 0E 00 F8 +93 01 90 00 63 1A DF 49 93 00 F0 FF 13 01 E0 00 +33 9F 20 00 B7 CE FF FF 93 01 A0 00 63 1E DF 47 +93 00 F0 FF 13 01 F0 01 33 9F 20 00 B7 0E 00 80 +93 01 B0 00 63 12 DF 47 B7 20 21 21 93 80 10 12 +13 01 00 00 33 9F 20 00 B7 2E 21 21 93 8E 1E 12 +93 01 C0 00 63 12 DF 45 B7 20 21 21 93 80 10 12 +13 01 10 00 33 9F 20 00 B7 4E 42 42 93 8E 2E 24 +93 01 D0 00 63 12 DF 43 B7 20 21 21 93 80 10 12 +13 01 70 00 33 9F 20 00 B7 9E 90 90 93 8E 0E 08 +93 01 E0 00 63 12 DF 41 B7 20 21 21 93 80 10 12 +13 01 E0 00 33 9F 20 00 B7 4E 48 48 93 01 F0 00 +63 14 DF 3F B7 20 21 21 93 80 10 12 13 01 F0 01 +33 9F 20 00 B7 0E 00 80 93 01 00 01 63 16 DF 3D +B7 20 21 21 93 80 10 12 13 01 00 FC 33 9F 20 00 +B7 2E 21 21 93 8E 1E 12 93 01 10 01 63 16 DF 3B +B7 20 21 21 93 80 10 12 13 01 10 FC 33 9F 20 00 +B7 4E 42 42 93 8E 2E 24 93 01 20 01 63 16 DF 39 +B7 20 21 21 93 80 10 12 13 01 70 FC 33 9F 20 00 +B7 9E 90 90 93 8E 0E 08 93 01 30 01 63 16 DF 37 +B7 20 21 21 93 80 10 12 13 01 E0 FC 33 9F 20 00 +B7 4E 48 48 93 01 40 01 63 18 DF 35 93 00 10 00 +13 01 70 00 B3 90 20 00 93 0E 00 08 93 01 60 01 +63 9C D0 33 93 00 10 00 13 01 E0 00 33 91 20 00 +B7 4E 00 00 93 01 70 01 63 10 D1 33 93 00 30 00 +B3 90 10 00 93 0E 80 01 93 01 80 01 63 96 D0 31 +13 02 00 00 93 00 10 00 13 01 70 00 33 9F 20 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 14 52 FE +93 0E 00 08 93 01 90 01 63 10 D3 2F 13 02 00 00 +93 00 10 00 13 01 E0 00 33 9F 20 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 12 52 FE +B7 4E 00 00 93 01 A0 01 63 18 D3 2B 13 02 00 00 +93 00 10 00 13 01 F0 01 33 9F 20 00 13 00 00 00 +13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 10 52 FE B7 0E 00 80 93 01 B0 01 63 1E D3 27 +13 02 00 00 93 00 10 00 13 01 70 00 33 9F 20 00 +13 02 12 00 93 02 20 00 E3 16 52 FE 93 0E 00 08 +93 01 C0 01 63 1A DF 25 13 02 00 00 93 00 10 00 +13 01 E0 00 13 00 00 00 33 9F 20 00 13 02 12 00 +93 02 20 00 E3 14 52 FE B7 4E 00 00 93 01 D0 01 +63 14 DF 23 13 02 00 00 93 00 10 00 13 01 F0 01 +13 00 00 00 13 00 00 00 33 9F 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE B7 0E 00 80 93 01 E0 01 +63 1C DF 1F 13 02 00 00 93 00 10 00 13 00 00 00 +13 01 70 00 33 9F 20 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 00 08 93 01 F0 01 63 16 DF 1D +13 02 00 00 93 00 10 00 13 00 00 00 13 01 E0 00 +13 00 00 00 33 9F 20 00 13 02 12 00 93 02 20 00 +E3 12 52 FE B7 4E 00 00 93 01 00 02 63 1E DF 19 +13 02 00 00 93 00 10 00 13 00 00 00 13 00 00 00 +13 01 F0 01 33 9F 20 00 13 02 12 00 93 02 20 00 +E3 12 52 FE B7 0E 00 80 93 01 10 02 63 16 DF 17 +13 02 00 00 13 01 70 00 93 00 10 00 33 9F 20 00 +13 02 12 00 93 02 20 00 E3 16 52 FE 93 0E 00 08 +93 01 20 02 63 12 DF 15 13 02 00 00 13 01 E0 00 +93 00 10 00 13 00 00 00 33 9F 20 00 13 02 12 00 +93 02 20 00 E3 14 52 FE B7 4E 00 00 93 01 30 02 +63 1C DF 11 13 02 00 00 13 01 F0 01 93 00 10 00 +13 00 00 00 13 00 00 00 33 9F 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE B7 0E 00 80 93 01 40 02 +63 14 DF 0F 13 02 00 00 13 01 70 00 13 00 00 00 +93 00 10 00 33 9F 20 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 00 08 93 01 50 02 63 1E DF 0B +13 02 00 00 13 01 E0 00 13 00 00 00 93 00 10 00 +13 00 00 00 33 9F 20 00 13 02 12 00 93 02 20 00 +E3 12 52 FE B7 4E 00 00 93 01 60 02 63 16 DF 09 +13 02 00 00 13 01 F0 01 13 00 00 00 13 00 00 00 +93 00 10 00 33 9F 20 00 13 02 12 00 93 02 20 00 +E3 12 52 FE B7 0E 00 80 93 01 70 02 63 1E DF 05 +93 00 F0 00 33 11 10 00 93 0E 00 00 93 01 80 02 +63 14 D1 05 93 00 00 02 33 91 00 00 93 0E 00 02 +93 01 90 02 63 1A D1 03 B3 10 00 00 93 0E 00 00 +93 01 A0 02 63 92 D0 03 93 00 00 40 37 11 00 00 +13 01 01 80 33 90 20 00 93 0E 00 00 93 01 B0 02 +63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@000005C0 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-slli b/tests/isa/generated/rv32ui-p-slli new file mode 100644 index 0000000..01a3f9f Binary files /dev/null and b/tests/isa/generated/rv32ui-p-slli differ diff --git a/tests/isa/generated/rv32ui-p-slli.bin b/tests/isa/generated/rv32ui-p-slli.bin new file mode 100644 index 0000000..491ab4c Binary files /dev/null and b/tests/isa/generated/rv32ui-p-slli.bin differ diff --git a/tests/isa/generated/rv32ui-p-slli.dump b/tests/isa/generated/rv32ui-p-slli.dump new file mode 100644 index 0000000..a113443 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-slli.dump @@ -0,0 +1,241 @@ + +generated/rv32ui-p-slli: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00100093 li ra,1 + c: 00009f13 slli t5,ra,0x0 + 10: 00100e93 li t4,1 + 14: 00200193 li gp,2 + 18: 27df1a63 bne t5,t4,28c + +0000001c : + 1c: 00100093 li ra,1 + 20: 00109f13 slli t5,ra,0x1 + 24: 00200e93 li t4,2 + 28: 00300193 li gp,3 + 2c: 27df1063 bne t5,t4,28c + +00000030 : + 30: 00100093 li ra,1 + 34: 00709f13 slli t5,ra,0x7 + 38: 08000e93 li t4,128 + 3c: 00400193 li gp,4 + 40: 25df1663 bne t5,t4,28c + +00000044 : + 44: 00100093 li ra,1 + 48: 00e09f13 slli t5,ra,0xe + 4c: 00004eb7 lui t4,0x4 + 50: 00500193 li gp,5 + 54: 23df1c63 bne t5,t4,28c + +00000058 : + 58: 00100093 li ra,1 + 5c: 01f09f13 slli t5,ra,0x1f + 60: 80000eb7 lui t4,0x80000 + 64: 00600193 li gp,6 + 68: 23df1263 bne t5,t4,28c + +0000006c : + 6c: fff00093 li ra,-1 + 70: 00009f13 slli t5,ra,0x0 + 74: fff00e93 li t4,-1 + 78: 00700193 li gp,7 + 7c: 21df1863 bne t5,t4,28c + +00000080 : + 80: fff00093 li ra,-1 + 84: 00109f13 slli t5,ra,0x1 + 88: ffe00e93 li t4,-2 + 8c: 00800193 li gp,8 + 90: 1fdf1e63 bne t5,t4,28c + +00000094 : + 94: fff00093 li ra,-1 + 98: 00709f13 slli t5,ra,0x7 + 9c: f8000e93 li t4,-128 + a0: 00900193 li gp,9 + a4: 1fdf1463 bne t5,t4,28c + +000000a8 : + a8: fff00093 li ra,-1 + ac: 00e09f13 slli t5,ra,0xe + b0: ffffceb7 lui t4,0xffffc + b4: 00a00193 li gp,10 + b8: 1ddf1a63 bne t5,t4,28c + +000000bc : + bc: fff00093 li ra,-1 + c0: 01f09f13 slli t5,ra,0x1f + c4: 80000eb7 lui t4,0x80000 + c8: 00b00193 li gp,11 + cc: 1ddf1063 bne t5,t4,28c + +000000d0 : + d0: 212120b7 lui ra,0x21212 + d4: 12108093 addi ra,ra,289 # 21212121 + d8: 00009f13 slli t5,ra,0x0 + dc: 21212eb7 lui t4,0x21212 + e0: 121e8e93 addi t4,t4,289 # 21212121 + e4: 00c00193 li gp,12 + e8: 1bdf1263 bne t5,t4,28c + +000000ec : + ec: 212120b7 lui ra,0x21212 + f0: 12108093 addi ra,ra,289 # 21212121 + f4: 00109f13 slli t5,ra,0x1 + f8: 42424eb7 lui t4,0x42424 + fc: 242e8e93 addi t4,t4,578 # 42424242 + 100: 00d00193 li gp,13 + 104: 19df1463 bne t5,t4,28c + +00000108 : + 108: 212120b7 lui ra,0x21212 + 10c: 12108093 addi ra,ra,289 # 21212121 + 110: 00709f13 slli t5,ra,0x7 + 114: 90909eb7 lui t4,0x90909 + 118: 080e8e93 addi t4,t4,128 # 90909080 + 11c: 00e00193 li gp,14 + 120: 17df1663 bne t5,t4,28c + +00000124 : + 124: 212120b7 lui ra,0x21212 + 128: 12108093 addi ra,ra,289 # 21212121 + 12c: 00e09f13 slli t5,ra,0xe + 130: 48484eb7 lui t4,0x48484 + 134: 00f00193 li gp,15 + 138: 15df1a63 bne t5,t4,28c + +0000013c : + 13c: 212120b7 lui ra,0x21212 + 140: 12108093 addi ra,ra,289 # 21212121 + 144: 01f09f13 slli t5,ra,0x1f + 148: 80000eb7 lui t4,0x80000 + 14c: 01000193 li gp,16 + 150: 13df1e63 bne t5,t4,28c + +00000154 : + 154: 00100093 li ra,1 + 158: 00709093 slli ra,ra,0x7 + 15c: 08000e93 li t4,128 + 160: 01100193 li gp,17 + 164: 13d09463 bne ra,t4,28c + +00000168 : + 168: 00000213 li tp,0 + 16c: 00100093 li ra,1 + 170: 00709f13 slli t5,ra,0x7 + 174: 000f0313 mv t1,t5 + 178: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 17c: 00200293 li t0,2 + 180: fe5216e3 bne tp,t0,16c + 184: 08000e93 li t4,128 + 188: 01200193 li gp,18 + 18c: 11d31063 bne t1,t4,28c + +00000190 : + 190: 00000213 li tp,0 + 194: 00100093 li ra,1 + 198: 00e09f13 slli t5,ra,0xe + 19c: 00000013 nop + 1a0: 000f0313 mv t1,t5 + 1a4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1a8: 00200293 li t0,2 + 1ac: fe5214e3 bne tp,t0,194 + 1b0: 00004eb7 lui t4,0x4 + 1b4: 01300193 li gp,19 + 1b8: 0dd31a63 bne t1,t4,28c + +000001bc : + 1bc: 00000213 li tp,0 + 1c0: 00100093 li ra,1 + 1c4: 01f09f13 slli t5,ra,0x1f + 1c8: 00000013 nop + 1cc: 00000013 nop + 1d0: 000f0313 mv t1,t5 + 1d4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1d8: 00200293 li t0,2 + 1dc: fe5212e3 bne tp,t0,1c0 + 1e0: 80000eb7 lui t4,0x80000 + 1e4: 01400193 li gp,20 + 1e8: 0bd31263 bne t1,t4,28c + +000001ec : + 1ec: 00000213 li tp,0 + 1f0: 00100093 li ra,1 + 1f4: 00709f13 slli t5,ra,0x7 + 1f8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1fc: 00200293 li t0,2 + 200: fe5218e3 bne tp,t0,1f0 + 204: 08000e93 li t4,128 + 208: 01500193 li gp,21 + 20c: 09df1063 bne t5,t4,28c + +00000210 : + 210: 00000213 li tp,0 + 214: 00100093 li ra,1 + 218: 00000013 nop + 21c: 00e09f13 slli t5,ra,0xe + 220: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 224: 00200293 li t0,2 + 228: fe5216e3 bne tp,t0,214 + 22c: 00004eb7 lui t4,0x4 + 230: 01600193 li gp,22 + 234: 05df1c63 bne t5,t4,28c + +00000238 : + 238: 00000213 li tp,0 + 23c: 00100093 li ra,1 + 240: 00000013 nop + 244: 00000013 nop + 248: 01f09f13 slli t5,ra,0x1f + 24c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 250: 00200293 li t0,2 + 254: fe5214e3 bne tp,t0,23c + 258: 80000eb7 lui t4,0x80000 + 25c: 01700193 li gp,23 + 260: 03df1663 bne t5,t4,28c + +00000264 : + 264: 01f01093 slli ra,zero,0x1f + 268: 00000e93 li t4,0 + 26c: 01800193 li gp,24 + 270: 01d09e63 bne ra,t4,28c + +00000274 : + 274: 02100093 li ra,33 + 278: 01409013 slli zero,ra,0x14 + 27c: 00000e93 li t4,0 + 280: 01900193 li gp,25 + 284: 01d01463 bne zero,t4,28c + 288: 00301863 bne zero,gp,298 + +0000028c : + 28c: 00100d13 li s10,1 + 290: 00000d93 li s11,0 + +00000294 : + 294: 0000006f j 294 + +00000298 : + 298: 00100d13 li s10,1 + 29c: 00100d93 li s11,1 + +000002a0 : + 2a0: 0000006f j 2a0 + ... + +Disassembly of section .tohost: + +00000300 : + ... + +00000340 : + ... diff --git a/tests/isa/generated/rv32ui-p-slli.verilog b/tests/isa/generated/rv32ui-p-slli.verilog new file mode 100644 index 0000000..1ca8c1a --- /dev/null +++ b/tests/isa/generated/rv32ui-p-slli.verilog @@ -0,0 +1,52 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 10 00 13 9F 00 00 +93 0E 10 00 93 01 20 00 63 1A DF 27 93 00 10 00 +13 9F 10 00 93 0E 20 00 93 01 30 00 63 10 DF 27 +93 00 10 00 13 9F 70 00 93 0E 00 08 93 01 40 00 +63 16 DF 25 93 00 10 00 13 9F E0 00 B7 4E 00 00 +93 01 50 00 63 1C DF 23 93 00 10 00 13 9F F0 01 +B7 0E 00 80 93 01 60 00 63 12 DF 23 93 00 F0 FF +13 9F 00 00 93 0E F0 FF 93 01 70 00 63 18 DF 21 +93 00 F0 FF 13 9F 10 00 93 0E E0 FF 93 01 80 00 +63 1E DF 1F 93 00 F0 FF 13 9F 70 00 93 0E 00 F8 +93 01 90 00 63 14 DF 1F 93 00 F0 FF 13 9F E0 00 +B7 CE FF FF 93 01 A0 00 63 1A DF 1D 93 00 F0 FF +13 9F F0 01 B7 0E 00 80 93 01 B0 00 63 10 DF 1D +B7 20 21 21 93 80 10 12 13 9F 00 00 B7 2E 21 21 +93 8E 1E 12 93 01 C0 00 63 12 DF 1B B7 20 21 21 +93 80 10 12 13 9F 10 00 B7 4E 42 42 93 8E 2E 24 +93 01 D0 00 63 14 DF 19 B7 20 21 21 93 80 10 12 +13 9F 70 00 B7 9E 90 90 93 8E 0E 08 93 01 E0 00 +63 16 DF 17 B7 20 21 21 93 80 10 12 13 9F E0 00 +B7 4E 48 48 93 01 F0 00 63 1A DF 15 B7 20 21 21 +93 80 10 12 13 9F F0 01 B7 0E 00 80 93 01 00 01 +63 1E DF 13 93 00 10 00 93 90 70 00 93 0E 00 08 +93 01 10 01 63 94 D0 13 13 02 00 00 93 00 10 00 +13 9F 70 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 16 52 FE 93 0E 00 08 93 01 20 01 63 10 D3 11 +13 02 00 00 93 00 10 00 13 9F E0 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 14 52 FE +B7 4E 00 00 93 01 30 01 63 1A D3 0D 13 02 00 00 +93 00 10 00 13 9F F0 01 13 00 00 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 12 52 FE +B7 0E 00 80 93 01 40 01 63 12 D3 0B 13 02 00 00 +93 00 10 00 13 9F 70 00 13 02 12 00 93 02 20 00 +E3 18 52 FE 93 0E 00 08 93 01 50 01 63 10 DF 09 +13 02 00 00 93 00 10 00 13 00 00 00 13 9F E0 00 +13 02 12 00 93 02 20 00 E3 16 52 FE B7 4E 00 00 +93 01 60 01 63 1C DF 05 13 02 00 00 93 00 10 00 +13 00 00 00 13 00 00 00 13 9F F0 01 13 02 12 00 +93 02 20 00 E3 14 52 FE B7 0E 00 80 93 01 70 01 +63 16 DF 03 93 10 F0 01 93 0E 00 00 93 01 80 01 +63 9E D0 01 93 00 10 02 13 90 40 01 93 0E 00 00 +93 01 90 01 63 14 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000300 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-slt b/tests/isa/generated/rv32ui-p-slt new file mode 100644 index 0000000..858b3b5 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-slt differ diff --git a/tests/isa/generated/rv32ui-p-slt.bin b/tests/isa/generated/rv32ui-p-slt.bin new file mode 100644 index 0000000..78df913 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-slt.bin differ diff --git a/tests/isa/generated/rv32ui-p-slt.dump b/tests/isa/generated/rv32ui-p-slt.dump new file mode 100644 index 0000000..289d843 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-slt.dump @@ -0,0 +1,412 @@ + +generated/rv32ui-p-slt: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00000093 li ra,0 + c: 00000113 li sp,0 + 10: 0020af33 slt t5,ra,sp + 14: 00000e93 li t4,0 + 18: 00200193 li gp,2 + 1c: 4bdf1a63 bne t5,t4,4d0 + +00000020 : + 20: 00100093 li ra,1 + 24: 00100113 li sp,1 + 28: 0020af33 slt t5,ra,sp + 2c: 00000e93 li t4,0 + 30: 00300193 li gp,3 + 34: 49df1e63 bne t5,t4,4d0 + +00000038 : + 38: 00300093 li ra,3 + 3c: 00700113 li sp,7 + 40: 0020af33 slt t5,ra,sp + 44: 00100e93 li t4,1 + 48: 00400193 li gp,4 + 4c: 49df1263 bne t5,t4,4d0 + +00000050 : + 50: 00700093 li ra,7 + 54: 00300113 li sp,3 + 58: 0020af33 slt t5,ra,sp + 5c: 00000e93 li t4,0 + 60: 00500193 li gp,5 + 64: 47df1663 bne t5,t4,4d0 + +00000068 : + 68: 00000093 li ra,0 + 6c: ffff8137 lui sp,0xffff8 + 70: 0020af33 slt t5,ra,sp + 74: 00000e93 li t4,0 + 78: 00600193 li gp,6 + 7c: 45df1a63 bne t5,t4,4d0 + +00000080 : + 80: 800000b7 lui ra,0x80000 + 84: 00000113 li sp,0 + 88: 0020af33 slt t5,ra,sp + 8c: 00100e93 li t4,1 + 90: 00700193 li gp,7 + 94: 43df1e63 bne t5,t4,4d0 + +00000098 : + 98: 800000b7 lui ra,0x80000 + 9c: ffff8137 lui sp,0xffff8 + a0: 0020af33 slt t5,ra,sp + a4: 00100e93 li t4,1 + a8: 00800193 li gp,8 + ac: 43df1263 bne t5,t4,4d0 + +000000b0 : + b0: 00000093 li ra,0 + b4: 00008137 lui sp,0x8 + b8: fff10113 addi sp,sp,-1 # 7fff + bc: 0020af33 slt t5,ra,sp + c0: 00100e93 li t4,1 + c4: 00900193 li gp,9 + c8: 41df1463 bne t5,t4,4d0 + +000000cc : + cc: 800000b7 lui ra,0x80000 + d0: fff08093 addi ra,ra,-1 # 7fffffff + d4: 00000113 li sp,0 + d8: 0020af33 slt t5,ra,sp + dc: 00000e93 li t4,0 + e0: 00a00193 li gp,10 + e4: 3fdf1663 bne t5,t4,4d0 + +000000e8 : + e8: 800000b7 lui ra,0x80000 + ec: fff08093 addi ra,ra,-1 # 7fffffff + f0: 00008137 lui sp,0x8 + f4: fff10113 addi sp,sp,-1 # 7fff + f8: 0020af33 slt t5,ra,sp + fc: 00000e93 li t4,0 + 100: 00b00193 li gp,11 + 104: 3ddf1663 bne t5,t4,4d0 + +00000108 : + 108: 800000b7 lui ra,0x80000 + 10c: 00008137 lui sp,0x8 + 110: fff10113 addi sp,sp,-1 # 7fff + 114: 0020af33 slt t5,ra,sp + 118: 00100e93 li t4,1 + 11c: 00c00193 li gp,12 + 120: 3bdf1863 bne t5,t4,4d0 + +00000124 : + 124: 800000b7 lui ra,0x80000 + 128: fff08093 addi ra,ra,-1 # 7fffffff + 12c: ffff8137 lui sp,0xffff8 + 130: 0020af33 slt t5,ra,sp + 134: 00000e93 li t4,0 + 138: 00d00193 li gp,13 + 13c: 39df1a63 bne t5,t4,4d0 + +00000140 : + 140: 00000093 li ra,0 + 144: fff00113 li sp,-1 + 148: 0020af33 slt t5,ra,sp + 14c: 00000e93 li t4,0 + 150: 00e00193 li gp,14 + 154: 37df1e63 bne t5,t4,4d0 + +00000158 : + 158: fff00093 li ra,-1 + 15c: 00100113 li sp,1 + 160: 0020af33 slt t5,ra,sp + 164: 00100e93 li t4,1 + 168: 00f00193 li gp,15 + 16c: 37df1263 bne t5,t4,4d0 + +00000170 : + 170: fff00093 li ra,-1 + 174: fff00113 li sp,-1 + 178: 0020af33 slt t5,ra,sp + 17c: 00000e93 li t4,0 + 180: 01000193 li gp,16 + 184: 35df1663 bne t5,t4,4d0 + +00000188 : + 188: 00e00093 li ra,14 + 18c: 00d00113 li sp,13 + 190: 0020a0b3 slt ra,ra,sp + 194: 00000e93 li t4,0 + 198: 01100193 li gp,17 + 19c: 33d09a63 bne ra,t4,4d0 + +000001a0 : + 1a0: 00b00093 li ra,11 + 1a4: 00d00113 li sp,13 + 1a8: 0020a133 slt sp,ra,sp + 1ac: 00100e93 li t4,1 + 1b0: 01200193 li gp,18 + 1b4: 31d11e63 bne sp,t4,4d0 + +000001b8 : + 1b8: 00d00093 li ra,13 + 1bc: 0010a0b3 slt ra,ra,ra + 1c0: 00000e93 li t4,0 + 1c4: 01300193 li gp,19 + 1c8: 31d09463 bne ra,t4,4d0 + +000001cc : + 1cc: 00000213 li tp,0 + 1d0: 00b00093 li ra,11 + 1d4: 00d00113 li sp,13 + 1d8: 0020af33 slt t5,ra,sp + 1dc: 000f0313 mv t1,t5 + 1e0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1e4: 00200293 li t0,2 + 1e8: fe5214e3 bne tp,t0,1d0 + 1ec: 00100e93 li t4,1 + 1f0: 01400193 li gp,20 + 1f4: 2dd31e63 bne t1,t4,4d0 + +000001f8 : + 1f8: 00000213 li tp,0 + 1fc: 00e00093 li ra,14 + 200: 00d00113 li sp,13 + 204: 0020af33 slt t5,ra,sp + 208: 00000013 nop + 20c: 000f0313 mv t1,t5 + 210: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 214: 00200293 li t0,2 + 218: fe5212e3 bne tp,t0,1fc + 21c: 00000e93 li t4,0 + 220: 01500193 li gp,21 + 224: 2bd31663 bne t1,t4,4d0 + +00000228 : + 228: 00000213 li tp,0 + 22c: 00c00093 li ra,12 + 230: 00d00113 li sp,13 + 234: 0020af33 slt t5,ra,sp + 238: 00000013 nop + 23c: 00000013 nop + 240: 000f0313 mv t1,t5 + 244: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 248: 00200293 li t0,2 + 24c: fe5210e3 bne tp,t0,22c + 250: 00100e93 li t4,1 + 254: 01600193 li gp,22 + 258: 27d31c63 bne t1,t4,4d0 + +0000025c : + 25c: 00000213 li tp,0 + 260: 00e00093 li ra,14 + 264: 00d00113 li sp,13 + 268: 0020af33 slt t5,ra,sp + 26c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 270: 00200293 li t0,2 + 274: fe5216e3 bne tp,t0,260 + 278: 00000e93 li t4,0 + 27c: 01700193 li gp,23 + 280: 25df1863 bne t5,t4,4d0 + +00000284 : + 284: 00000213 li tp,0 + 288: 00b00093 li ra,11 + 28c: 00d00113 li sp,13 + 290: 00000013 nop + 294: 0020af33 slt t5,ra,sp + 298: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 29c: 00200293 li t0,2 + 2a0: fe5214e3 bne tp,t0,288 + 2a4: 00100e93 li t4,1 + 2a8: 01800193 li gp,24 + 2ac: 23df1263 bne t5,t4,4d0 + +000002b0 : + 2b0: 00000213 li tp,0 + 2b4: 00f00093 li ra,15 + 2b8: 00d00113 li sp,13 + 2bc: 00000013 nop + 2c0: 00000013 nop + 2c4: 0020af33 slt t5,ra,sp + 2c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2cc: 00200293 li t0,2 + 2d0: fe5212e3 bne tp,t0,2b4 + 2d4: 00000e93 li t4,0 + 2d8: 01900193 li gp,25 + 2dc: 1fdf1a63 bne t5,t4,4d0 + +000002e0 : + 2e0: 00000213 li tp,0 + 2e4: 00a00093 li ra,10 + 2e8: 00000013 nop + 2ec: 00d00113 li sp,13 + 2f0: 0020af33 slt t5,ra,sp + 2f4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2f8: 00200293 li t0,2 + 2fc: fe5214e3 bne tp,t0,2e4 + 300: 00100e93 li t4,1 + 304: 01a00193 li gp,26 + 308: 1ddf1463 bne t5,t4,4d0 + +0000030c : + 30c: 00000213 li tp,0 + 310: 01000093 li ra,16 + 314: 00000013 nop + 318: 00d00113 li sp,13 + 31c: 00000013 nop + 320: 0020af33 slt t5,ra,sp + 324: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 328: 00200293 li t0,2 + 32c: fe5212e3 bne tp,t0,310 + 330: 00000e93 li t4,0 + 334: 01b00193 li gp,27 + 338: 19df1c63 bne t5,t4,4d0 + +0000033c : + 33c: 00000213 li tp,0 + 340: 00900093 li ra,9 + 344: 00000013 nop + 348: 00000013 nop + 34c: 00d00113 li sp,13 + 350: 0020af33 slt t5,ra,sp + 354: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 358: 00200293 li t0,2 + 35c: fe5212e3 bne tp,t0,340 + 360: 00100e93 li t4,1 + 364: 01c00193 li gp,28 + 368: 17df1463 bne t5,t4,4d0 + +0000036c : + 36c: 00000213 li tp,0 + 370: 00d00113 li sp,13 + 374: 01100093 li ra,17 + 378: 0020af33 slt t5,ra,sp + 37c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 380: 00200293 li t0,2 + 384: fe5216e3 bne tp,t0,370 + 388: 00000e93 li t4,0 + 38c: 01d00193 li gp,29 + 390: 15df1063 bne t5,t4,4d0 + +00000394 : + 394: 00000213 li tp,0 + 398: 00d00113 li sp,13 + 39c: 00800093 li ra,8 + 3a0: 00000013 nop + 3a4: 0020af33 slt t5,ra,sp + 3a8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3ac: 00200293 li t0,2 + 3b0: fe5214e3 bne tp,t0,398 + 3b4: 00100e93 li t4,1 + 3b8: 01e00193 li gp,30 + 3bc: 11df1a63 bne t5,t4,4d0 + +000003c0 : + 3c0: 00000213 li tp,0 + 3c4: 00d00113 li sp,13 + 3c8: 01200093 li ra,18 + 3cc: 00000013 nop + 3d0: 00000013 nop + 3d4: 0020af33 slt t5,ra,sp + 3d8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3dc: 00200293 li t0,2 + 3e0: fe5212e3 bne tp,t0,3c4 + 3e4: 00000e93 li t4,0 + 3e8: 01f00193 li gp,31 + 3ec: 0fdf1263 bne t5,t4,4d0 + +000003f0 : + 3f0: 00000213 li tp,0 + 3f4: 00d00113 li sp,13 + 3f8: 00000013 nop + 3fc: 00700093 li ra,7 + 400: 0020af33 slt t5,ra,sp + 404: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 408: 00200293 li t0,2 + 40c: fe5214e3 bne tp,t0,3f4 + 410: 00100e93 li t4,1 + 414: 02000193 li gp,32 + 418: 0bdf1c63 bne t5,t4,4d0 + +0000041c : + 41c: 00000213 li tp,0 + 420: 00d00113 li sp,13 + 424: 00000013 nop + 428: 01300093 li ra,19 + 42c: 00000013 nop + 430: 0020af33 slt t5,ra,sp + 434: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 438: 00200293 li t0,2 + 43c: fe5212e3 bne tp,t0,420 + 440: 00000e93 li t4,0 + 444: 02100193 li gp,33 + 448: 09df1463 bne t5,t4,4d0 + +0000044c : + 44c: 00000213 li tp,0 + 450: 00d00113 li sp,13 + 454: 00000013 nop + 458: 00000013 nop + 45c: 00600093 li ra,6 + 460: 0020af33 slt t5,ra,sp + 464: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 468: 00200293 li t0,2 + 46c: fe5212e3 bne tp,t0,450 + 470: 00100e93 li t4,1 + 474: 02200193 li gp,34 + 478: 05df1c63 bne t5,t4,4d0 + +0000047c : + 47c: fff00093 li ra,-1 + 480: 00102133 sgtz sp,ra + 484: 00000e93 li t4,0 + 488: 02300193 li gp,35 + 48c: 05d11263 bne sp,t4,4d0 + +00000490 : + 490: fff00093 li ra,-1 + 494: 0000a133 sltz sp,ra + 498: 00100e93 li t4,1 + 49c: 02400193 li gp,36 + 4a0: 03d11863 bne sp,t4,4d0 + +000004a4 : + 4a4: 000020b3 sltz ra,zero + 4a8: 00000e93 li t4,0 + 4ac: 02500193 li gp,37 + 4b0: 03d09063 bne ra,t4,4d0 + +000004b4 : + 4b4: 01000093 li ra,16 + 4b8: 01e00113 li sp,30 + 4bc: 0020a033 slt zero,ra,sp + 4c0: 00000e93 li t4,0 + 4c4: 02600193 li gp,38 + 4c8: 01d01463 bne zero,t4,4d0 + 4cc: 00301863 bne zero,gp,4dc + +000004d0 : + 4d0: 00100d13 li s10,1 + 4d4: 00000d93 li s11,0 + +000004d8 : + 4d8: 0000006f j 4d8 + +000004dc : + 4dc: 00100d13 li s10,1 + 4e0: 00100d93 li s11,1 + +000004e4 : + 4e4: 0000006f j 4e4 + ... + +Disassembly of section .tohost: + +00000540 : + ... + +00000580 : + ... diff --git a/tests/isa/generated/rv32ui-p-slt.verilog b/tests/isa/generated/rv32ui-p-slt.verilog new file mode 100644 index 0000000..c0768b8 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-slt.verilog @@ -0,0 +1,88 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 00 00 13 01 00 00 +33 AF 20 00 93 0E 00 00 93 01 20 00 63 1A DF 4B +93 00 10 00 13 01 10 00 33 AF 20 00 93 0E 00 00 +93 01 30 00 63 1E DF 49 93 00 30 00 13 01 70 00 +33 AF 20 00 93 0E 10 00 93 01 40 00 63 12 DF 49 +93 00 70 00 13 01 30 00 33 AF 20 00 93 0E 00 00 +93 01 50 00 63 16 DF 47 93 00 00 00 37 81 FF FF +33 AF 20 00 93 0E 00 00 93 01 60 00 63 1A DF 45 +B7 00 00 80 13 01 00 00 33 AF 20 00 93 0E 10 00 +93 01 70 00 63 1E DF 43 B7 00 00 80 37 81 FF FF +33 AF 20 00 93 0E 10 00 93 01 80 00 63 12 DF 43 +93 00 00 00 37 81 00 00 13 01 F1 FF 33 AF 20 00 +93 0E 10 00 93 01 90 00 63 14 DF 41 B7 00 00 80 +93 80 F0 FF 13 01 00 00 33 AF 20 00 93 0E 00 00 +93 01 A0 00 63 16 DF 3F B7 00 00 80 93 80 F0 FF +37 81 00 00 13 01 F1 FF 33 AF 20 00 93 0E 00 00 +93 01 B0 00 63 16 DF 3D B7 00 00 80 37 81 00 00 +13 01 F1 FF 33 AF 20 00 93 0E 10 00 93 01 C0 00 +63 18 DF 3B B7 00 00 80 93 80 F0 FF 37 81 FF FF +33 AF 20 00 93 0E 00 00 93 01 D0 00 63 1A DF 39 +93 00 00 00 13 01 F0 FF 33 AF 20 00 93 0E 00 00 +93 01 E0 00 63 1E DF 37 93 00 F0 FF 13 01 10 00 +33 AF 20 00 93 0E 10 00 93 01 F0 00 63 12 DF 37 +93 00 F0 FF 13 01 F0 FF 33 AF 20 00 93 0E 00 00 +93 01 00 01 63 16 DF 35 93 00 E0 00 13 01 D0 00 +B3 A0 20 00 93 0E 00 00 93 01 10 01 63 9A D0 33 +93 00 B0 00 13 01 D0 00 33 A1 20 00 93 0E 10 00 +93 01 20 01 63 1E D1 31 93 00 D0 00 B3 A0 10 00 +93 0E 00 00 93 01 30 01 63 94 D0 31 13 02 00 00 +93 00 B0 00 13 01 D0 00 33 AF 20 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 10 00 +93 01 40 01 63 1E D3 2D 13 02 00 00 93 00 E0 00 +13 01 D0 00 33 AF 20 00 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 00 00 +93 01 50 01 63 16 D3 2B 13 02 00 00 93 00 C0 00 +13 01 D0 00 33 AF 20 00 13 00 00 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE +93 0E 10 00 93 01 60 01 63 1C D3 27 13 02 00 00 +93 00 E0 00 13 01 D0 00 33 AF 20 00 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 0E 00 00 93 01 70 01 +63 18 DF 25 13 02 00 00 93 00 B0 00 13 01 D0 00 +13 00 00 00 33 AF 20 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 10 00 93 01 80 01 63 12 DF 23 +13 02 00 00 93 00 F0 00 13 01 D0 00 13 00 00 00 +13 00 00 00 33 AF 20 00 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E 00 00 93 01 90 01 63 1A DF 1F +13 02 00 00 93 00 A0 00 13 00 00 00 13 01 D0 00 +33 AF 20 00 13 02 12 00 93 02 20 00 E3 14 52 FE +93 0E 10 00 93 01 A0 01 63 14 DF 1D 13 02 00 00 +93 00 00 01 13 00 00 00 13 01 D0 00 13 00 00 00 +33 AF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E 00 00 93 01 B0 01 63 1C DF 19 13 02 00 00 +93 00 90 00 13 00 00 00 13 00 00 00 13 01 D0 00 +33 AF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E 10 00 93 01 C0 01 63 14 DF 17 13 02 00 00 +13 01 D0 00 93 00 10 01 33 AF 20 00 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 0E 00 00 93 01 D0 01 +63 10 DF 15 13 02 00 00 13 01 D0 00 93 00 80 00 +13 00 00 00 33 AF 20 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 10 00 93 01 E0 01 63 1A DF 11 +13 02 00 00 13 01 D0 00 93 00 20 01 13 00 00 00 +13 00 00 00 33 AF 20 00 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E 00 00 93 01 F0 01 63 12 DF 0F +13 02 00 00 13 01 D0 00 13 00 00 00 93 00 70 00 +33 AF 20 00 13 02 12 00 93 02 20 00 E3 14 52 FE +93 0E 10 00 93 01 00 02 63 1C DF 0B 13 02 00 00 +13 01 D0 00 13 00 00 00 93 00 30 01 13 00 00 00 +33 AF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E 00 00 93 01 10 02 63 14 DF 09 13 02 00 00 +13 01 D0 00 13 00 00 00 13 00 00 00 93 00 60 00 +33 AF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E 10 00 93 01 20 02 63 1C DF 05 93 00 F0 FF +33 21 10 00 93 0E 00 00 93 01 30 02 63 12 D1 05 +93 00 F0 FF 33 A1 00 00 93 0E 10 00 93 01 40 02 +63 18 D1 03 B3 20 00 00 93 0E 00 00 93 01 50 02 +63 90 D0 03 93 00 00 01 13 01 E0 01 33 A0 20 00 +93 0E 00 00 93 01 60 02 63 14 D0 01 63 18 30 00 +13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00 +93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000540 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-slti b/tests/isa/generated/rv32ui-p-slti new file mode 100644 index 0000000..2ad5022 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-slti differ diff --git a/tests/isa/generated/rv32ui-p-slti.bin b/tests/isa/generated/rv32ui-p-slti.bin new file mode 100644 index 0000000..6dd6037 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-slti.bin differ diff --git a/tests/isa/generated/rv32ui-p-slti.dump b/tests/isa/generated/rv32ui-p-slti.dump new file mode 100644 index 0000000..547ac38 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-slti.dump @@ -0,0 +1,237 @@ + +generated/rv32ui-p-slti: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00000093 li ra,0 + c: 0000af13 slti t5,ra,0 + 10: 00000e93 li t4,0 + 14: 00200193 li gp,2 + 18: 27df1263 bne t5,t4,27c + +0000001c : + 1c: 00100093 li ra,1 + 20: 0010af13 slti t5,ra,1 + 24: 00000e93 li t4,0 + 28: 00300193 li gp,3 + 2c: 25df1863 bne t5,t4,27c + +00000030 : + 30: 00300093 li ra,3 + 34: 0070af13 slti t5,ra,7 + 38: 00100e93 li t4,1 + 3c: 00400193 li gp,4 + 40: 23df1e63 bne t5,t4,27c + +00000044 : + 44: 00700093 li ra,7 + 48: 0030af13 slti t5,ra,3 + 4c: 00000e93 li t4,0 + 50: 00500193 li gp,5 + 54: 23df1463 bne t5,t4,27c + +00000058 : + 58: 00000093 li ra,0 + 5c: 8000af13 slti t5,ra,-2048 + 60: 00000e93 li t4,0 + 64: 00600193 li gp,6 + 68: 21df1a63 bne t5,t4,27c + +0000006c : + 6c: 800000b7 lui ra,0x80000 + 70: 0000af13 slti t5,ra,0 + 74: 00100e93 li t4,1 + 78: 00700193 li gp,7 + 7c: 21df1063 bne t5,t4,27c + +00000080 : + 80: 800000b7 lui ra,0x80000 + 84: 8000af13 slti t5,ra,-2048 + 88: 00100e93 li t4,1 + 8c: 00800193 li gp,8 + 90: 1fdf1663 bne t5,t4,27c + +00000094 : + 94: 00000093 li ra,0 + 98: 7ff0af13 slti t5,ra,2047 + 9c: 00100e93 li t4,1 + a0: 00900193 li gp,9 + a4: 1ddf1c63 bne t5,t4,27c + +000000a8 : + a8: 800000b7 lui ra,0x80000 + ac: fff08093 addi ra,ra,-1 # 7fffffff + b0: 0000af13 slti t5,ra,0 + b4: 00000e93 li t4,0 + b8: 00a00193 li gp,10 + bc: 1ddf1063 bne t5,t4,27c + +000000c0 : + c0: 800000b7 lui ra,0x80000 + c4: fff08093 addi ra,ra,-1 # 7fffffff + c8: 7ff0af13 slti t5,ra,2047 + cc: 00000e93 li t4,0 + d0: 00b00193 li gp,11 + d4: 1bdf1463 bne t5,t4,27c + +000000d8 : + d8: 800000b7 lui ra,0x80000 + dc: 7ff0af13 slti t5,ra,2047 + e0: 00100e93 li t4,1 + e4: 00c00193 li gp,12 + e8: 19df1a63 bne t5,t4,27c + +000000ec : + ec: 800000b7 lui ra,0x80000 + f0: fff08093 addi ra,ra,-1 # 7fffffff + f4: 8000af13 slti t5,ra,-2048 + f8: 00000e93 li t4,0 + fc: 00d00193 li gp,13 + 100: 17df1e63 bne t5,t4,27c + +00000104 : + 104: 00000093 li ra,0 + 108: fff0af13 slti t5,ra,-1 + 10c: 00000e93 li t4,0 + 110: 00e00193 li gp,14 + 114: 17df1463 bne t5,t4,27c + +00000118 : + 118: fff00093 li ra,-1 + 11c: 0010af13 slti t5,ra,1 + 120: 00100e93 li t4,1 + 124: 00f00193 li gp,15 + 128: 15df1a63 bne t5,t4,27c + +0000012c : + 12c: fff00093 li ra,-1 + 130: fff0af13 slti t5,ra,-1 + 134: 00000e93 li t4,0 + 138: 01000193 li gp,16 + 13c: 15df1063 bne t5,t4,27c + +00000140 : + 140: 00b00093 li ra,11 + 144: 00d0a093 slti ra,ra,13 + 148: 00100e93 li t4,1 + 14c: 01100193 li gp,17 + 150: 13d09663 bne ra,t4,27c + +00000154 : + 154: 00000213 li tp,0 + 158: 00f00093 li ra,15 + 15c: 00a0af13 slti t5,ra,10 + 160: 000f0313 mv t1,t5 + 164: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 168: 00200293 li t0,2 + 16c: fe5216e3 bne tp,t0,158 + 170: 00000e93 li t4,0 + 174: 01200193 li gp,18 + 178: 11d31263 bne t1,t4,27c + +0000017c : + 17c: 00000213 li tp,0 + 180: 00a00093 li ra,10 + 184: 0100af13 slti t5,ra,16 + 188: 00000013 nop + 18c: 000f0313 mv t1,t5 + 190: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 194: 00200293 li t0,2 + 198: fe5214e3 bne tp,t0,180 + 19c: 00100e93 li t4,1 + 1a0: 01300193 li gp,19 + 1a4: 0dd31c63 bne t1,t4,27c + +000001a8 : + 1a8: 00000213 li tp,0 + 1ac: 01000093 li ra,16 + 1b0: 0090af13 slti t5,ra,9 + 1b4: 00000013 nop + 1b8: 00000013 nop + 1bc: 000f0313 mv t1,t5 + 1c0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1c4: 00200293 li t0,2 + 1c8: fe5212e3 bne tp,t0,1ac + 1cc: 00000e93 li t4,0 + 1d0: 01400193 li gp,20 + 1d4: 0bd31463 bne t1,t4,27c + +000001d8 : + 1d8: 00000213 li tp,0 + 1dc: 00b00093 li ra,11 + 1e0: 00f0af13 slti t5,ra,15 + 1e4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1e8: 00200293 li t0,2 + 1ec: fe5218e3 bne tp,t0,1dc + 1f0: 00100e93 li t4,1 + 1f4: 01500193 li gp,21 + 1f8: 09df1263 bne t5,t4,27c + +000001fc : + 1fc: 00000213 li tp,0 + 200: 01100093 li ra,17 + 204: 00000013 nop + 208: 0080af13 slti t5,ra,8 + 20c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 210: 00200293 li t0,2 + 214: fe5216e3 bne tp,t0,200 + 218: 00000e93 li t4,0 + 21c: 01600193 li gp,22 + 220: 05df1e63 bne t5,t4,27c + +00000224 : + 224: 00000213 li tp,0 + 228: 00c00093 li ra,12 + 22c: 00000013 nop + 230: 00000013 nop + 234: 00e0af13 slti t5,ra,14 + 238: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 23c: 00200293 li t0,2 + 240: fe5214e3 bne tp,t0,228 + 244: 00100e93 li t4,1 + 248: 01700193 li gp,23 + 24c: 03df1863 bne t5,t4,27c + +00000250 : + 250: fff02093 slti ra,zero,-1 + 254: 00000e93 li t4,0 + 258: 01800193 li gp,24 + 25c: 03d09063 bne ra,t4,27c + +00000260 : + 260: 00ff00b7 lui ra,0xff0 + 264: 0ff08093 addi ra,ra,255 # ff00ff + 268: fff0a013 slti zero,ra,-1 + 26c: 00000e93 li t4,0 + 270: 01900193 li gp,25 + 274: 01d01463 bne zero,t4,27c + 278: 00301863 bne zero,gp,288 + +0000027c : + 27c: 00100d13 li s10,1 + 280: 00000d93 li s11,0 + +00000284 : + 284: 0000006f j 284 + +00000288 : + 288: 00100d13 li s10,1 + 28c: 00100d93 li s11,1 + +00000290 : + 290: 0000006f j 290 + ... + +Disassembly of section .tohost: + +00000300 : + ... + +00000340 : + ... diff --git a/tests/isa/generated/rv32ui-p-slti.verilog b/tests/isa/generated/rv32ui-p-slti.verilog new file mode 100644 index 0000000..921d8ad --- /dev/null +++ b/tests/isa/generated/rv32ui-p-slti.verilog @@ -0,0 +1,52 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 00 00 13 AF 00 00 +93 0E 00 00 93 01 20 00 63 12 DF 27 93 00 10 00 +13 AF 10 00 93 0E 00 00 93 01 30 00 63 18 DF 25 +93 00 30 00 13 AF 70 00 93 0E 10 00 93 01 40 00 +63 1E DF 23 93 00 70 00 13 AF 30 00 93 0E 00 00 +93 01 50 00 63 14 DF 23 93 00 00 00 13 AF 00 80 +93 0E 00 00 93 01 60 00 63 1A DF 21 B7 00 00 80 +13 AF 00 00 93 0E 10 00 93 01 70 00 63 10 DF 21 +B7 00 00 80 13 AF 00 80 93 0E 10 00 93 01 80 00 +63 16 DF 1F 93 00 00 00 13 AF F0 7F 93 0E 10 00 +93 01 90 00 63 1C DF 1D B7 00 00 80 93 80 F0 FF +13 AF 00 00 93 0E 00 00 93 01 A0 00 63 10 DF 1D +B7 00 00 80 93 80 F0 FF 13 AF F0 7F 93 0E 00 00 +93 01 B0 00 63 14 DF 1B B7 00 00 80 13 AF F0 7F +93 0E 10 00 93 01 C0 00 63 1A DF 19 B7 00 00 80 +93 80 F0 FF 13 AF 00 80 93 0E 00 00 93 01 D0 00 +63 1E DF 17 93 00 00 00 13 AF F0 FF 93 0E 00 00 +93 01 E0 00 63 14 DF 17 93 00 F0 FF 13 AF 10 00 +93 0E 10 00 93 01 F0 00 63 1A DF 15 93 00 F0 FF +13 AF F0 FF 93 0E 00 00 93 01 00 01 63 10 DF 15 +93 00 B0 00 93 A0 D0 00 93 0E 10 00 93 01 10 01 +63 96 D0 13 13 02 00 00 93 00 F0 00 13 AF A0 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 16 52 FE +93 0E 00 00 93 01 20 01 63 12 D3 11 13 02 00 00 +93 00 A0 00 13 AF 00 01 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 10 00 +93 01 30 01 63 1C D3 0D 13 02 00 00 93 00 00 01 +13 AF 90 00 13 00 00 00 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 00 00 +93 01 40 01 63 14 D3 0B 13 02 00 00 93 00 B0 00 +13 AF F0 00 13 02 12 00 93 02 20 00 E3 18 52 FE +93 0E 10 00 93 01 50 01 63 12 DF 09 13 02 00 00 +93 00 10 01 13 00 00 00 13 AF 80 00 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 0E 00 00 93 01 60 01 +63 1E DF 05 13 02 00 00 93 00 C0 00 13 00 00 00 +13 00 00 00 13 AF E0 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 10 00 93 01 70 01 63 18 DF 03 +93 20 F0 FF 93 0E 00 00 93 01 80 01 63 90 D0 03 +B7 00 FF 00 93 80 F0 0F 13 A0 F0 FF 93 0E 00 00 +93 01 90 01 63 14 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000300 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-sltiu b/tests/isa/generated/rv32ui-p-sltiu new file mode 100644 index 0000000..aa0ba18 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sltiu differ diff --git a/tests/isa/generated/rv32ui-p-sltiu.bin b/tests/isa/generated/rv32ui-p-sltiu.bin new file mode 100644 index 0000000..89e9309 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sltiu.bin differ diff --git a/tests/isa/generated/rv32ui-p-sltiu.dump b/tests/isa/generated/rv32ui-p-sltiu.dump new file mode 100644 index 0000000..2fbdf57 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sltiu.dump @@ -0,0 +1,237 @@ + +generated/rv32ui-p-sltiu: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00000093 li ra,0 + c: 0000bf13 sltiu t5,ra,0 + 10: 00000e93 li t4,0 + 14: 00200193 li gp,2 + 18: 27df1263 bne t5,t4,27c + +0000001c : + 1c: 00100093 li ra,1 + 20: 0010bf13 seqz t5,ra + 24: 00000e93 li t4,0 + 28: 00300193 li gp,3 + 2c: 25df1863 bne t5,t4,27c + +00000030 : + 30: 00300093 li ra,3 + 34: 0070bf13 sltiu t5,ra,7 + 38: 00100e93 li t4,1 + 3c: 00400193 li gp,4 + 40: 23df1e63 bne t5,t4,27c + +00000044 : + 44: 00700093 li ra,7 + 48: 0030bf13 sltiu t5,ra,3 + 4c: 00000e93 li t4,0 + 50: 00500193 li gp,5 + 54: 23df1463 bne t5,t4,27c + +00000058 : + 58: 00000093 li ra,0 + 5c: 8000bf13 sltiu t5,ra,-2048 + 60: 00100e93 li t4,1 + 64: 00600193 li gp,6 + 68: 21df1a63 bne t5,t4,27c + +0000006c : + 6c: 800000b7 lui ra,0x80000 + 70: 0000bf13 sltiu t5,ra,0 + 74: 00000e93 li t4,0 + 78: 00700193 li gp,7 + 7c: 21df1063 bne t5,t4,27c + +00000080 : + 80: 800000b7 lui ra,0x80000 + 84: 8000bf13 sltiu t5,ra,-2048 + 88: 00100e93 li t4,1 + 8c: 00800193 li gp,8 + 90: 1fdf1663 bne t5,t4,27c + +00000094 : + 94: 00000093 li ra,0 + 98: 7ff0bf13 sltiu t5,ra,2047 + 9c: 00100e93 li t4,1 + a0: 00900193 li gp,9 + a4: 1ddf1c63 bne t5,t4,27c + +000000a8 : + a8: 800000b7 lui ra,0x80000 + ac: fff08093 addi ra,ra,-1 # 7fffffff + b0: 0000bf13 sltiu t5,ra,0 + b4: 00000e93 li t4,0 + b8: 00a00193 li gp,10 + bc: 1ddf1063 bne t5,t4,27c + +000000c0 : + c0: 800000b7 lui ra,0x80000 + c4: fff08093 addi ra,ra,-1 # 7fffffff + c8: 7ff0bf13 sltiu t5,ra,2047 + cc: 00000e93 li t4,0 + d0: 00b00193 li gp,11 + d4: 1bdf1463 bne t5,t4,27c + +000000d8 : + d8: 800000b7 lui ra,0x80000 + dc: 7ff0bf13 sltiu t5,ra,2047 + e0: 00000e93 li t4,0 + e4: 00c00193 li gp,12 + e8: 19df1a63 bne t5,t4,27c + +000000ec : + ec: 800000b7 lui ra,0x80000 + f0: fff08093 addi ra,ra,-1 # 7fffffff + f4: 8000bf13 sltiu t5,ra,-2048 + f8: 00100e93 li t4,1 + fc: 00d00193 li gp,13 + 100: 17df1e63 bne t5,t4,27c + +00000104 : + 104: 00000093 li ra,0 + 108: fff0bf13 sltiu t5,ra,-1 + 10c: 00100e93 li t4,1 + 110: 00e00193 li gp,14 + 114: 17df1463 bne t5,t4,27c + +00000118 : + 118: fff00093 li ra,-1 + 11c: 0010bf13 seqz t5,ra + 120: 00000e93 li t4,0 + 124: 00f00193 li gp,15 + 128: 15df1a63 bne t5,t4,27c + +0000012c : + 12c: fff00093 li ra,-1 + 130: fff0bf13 sltiu t5,ra,-1 + 134: 00000e93 li t4,0 + 138: 01000193 li gp,16 + 13c: 15df1063 bne t5,t4,27c + +00000140 : + 140: 00b00093 li ra,11 + 144: 00d0b093 sltiu ra,ra,13 + 148: 00100e93 li t4,1 + 14c: 01100193 li gp,17 + 150: 13d09663 bne ra,t4,27c + +00000154 : + 154: 00000213 li tp,0 + 158: 00f00093 li ra,15 + 15c: 00a0bf13 sltiu t5,ra,10 + 160: 000f0313 mv t1,t5 + 164: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 168: 00200293 li t0,2 + 16c: fe5216e3 bne tp,t0,158 + 170: 00000e93 li t4,0 + 174: 01200193 li gp,18 + 178: 11d31263 bne t1,t4,27c + +0000017c : + 17c: 00000213 li tp,0 + 180: 00a00093 li ra,10 + 184: 0100bf13 sltiu t5,ra,16 + 188: 00000013 nop + 18c: 000f0313 mv t1,t5 + 190: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 194: 00200293 li t0,2 + 198: fe5214e3 bne tp,t0,180 + 19c: 00100e93 li t4,1 + 1a0: 01300193 li gp,19 + 1a4: 0dd31c63 bne t1,t4,27c + +000001a8 : + 1a8: 00000213 li tp,0 + 1ac: 01000093 li ra,16 + 1b0: 0090bf13 sltiu t5,ra,9 + 1b4: 00000013 nop + 1b8: 00000013 nop + 1bc: 000f0313 mv t1,t5 + 1c0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1c4: 00200293 li t0,2 + 1c8: fe5212e3 bne tp,t0,1ac + 1cc: 00000e93 li t4,0 + 1d0: 01400193 li gp,20 + 1d4: 0bd31463 bne t1,t4,27c + +000001d8 : + 1d8: 00000213 li tp,0 + 1dc: 00b00093 li ra,11 + 1e0: 00f0bf13 sltiu t5,ra,15 + 1e4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1e8: 00200293 li t0,2 + 1ec: fe5218e3 bne tp,t0,1dc + 1f0: 00100e93 li t4,1 + 1f4: 01500193 li gp,21 + 1f8: 09df1263 bne t5,t4,27c + +000001fc : + 1fc: 00000213 li tp,0 + 200: 01100093 li ra,17 + 204: 00000013 nop + 208: 0080bf13 sltiu t5,ra,8 + 20c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 210: 00200293 li t0,2 + 214: fe5216e3 bne tp,t0,200 + 218: 00000e93 li t4,0 + 21c: 01600193 li gp,22 + 220: 05df1e63 bne t5,t4,27c + +00000224 : + 224: 00000213 li tp,0 + 228: 00c00093 li ra,12 + 22c: 00000013 nop + 230: 00000013 nop + 234: 00e0bf13 sltiu t5,ra,14 + 238: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 23c: 00200293 li t0,2 + 240: fe5214e3 bne tp,t0,228 + 244: 00100e93 li t4,1 + 248: 01700193 li gp,23 + 24c: 03df1863 bne t5,t4,27c + +00000250 : + 250: fff03093 sltiu ra,zero,-1 + 254: 00100e93 li t4,1 + 258: 01800193 li gp,24 + 25c: 03d09063 bne ra,t4,27c + +00000260 : + 260: 00ff00b7 lui ra,0xff0 + 264: 0ff08093 addi ra,ra,255 # ff00ff + 268: fff0b013 sltiu zero,ra,-1 + 26c: 00000e93 li t4,0 + 270: 01900193 li gp,25 + 274: 01d01463 bne zero,t4,27c + 278: 00301863 bne zero,gp,288 + +0000027c : + 27c: 00100d13 li s10,1 + 280: 00000d93 li s11,0 + +00000284 : + 284: 0000006f j 284 + +00000288 : + 288: 00100d13 li s10,1 + 28c: 00100d93 li s11,1 + +00000290 : + 290: 0000006f j 290 + ... + +Disassembly of section .tohost: + +00000300 : + ... + +00000340 : + ... diff --git a/tests/isa/generated/rv32ui-p-sltiu.verilog b/tests/isa/generated/rv32ui-p-sltiu.verilog new file mode 100644 index 0000000..2315f1f --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sltiu.verilog @@ -0,0 +1,52 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 00 00 13 BF 00 00 +93 0E 00 00 93 01 20 00 63 12 DF 27 93 00 10 00 +13 BF 10 00 93 0E 00 00 93 01 30 00 63 18 DF 25 +93 00 30 00 13 BF 70 00 93 0E 10 00 93 01 40 00 +63 1E DF 23 93 00 70 00 13 BF 30 00 93 0E 00 00 +93 01 50 00 63 14 DF 23 93 00 00 00 13 BF 00 80 +93 0E 10 00 93 01 60 00 63 1A DF 21 B7 00 00 80 +13 BF 00 00 93 0E 00 00 93 01 70 00 63 10 DF 21 +B7 00 00 80 13 BF 00 80 93 0E 10 00 93 01 80 00 +63 16 DF 1F 93 00 00 00 13 BF F0 7F 93 0E 10 00 +93 01 90 00 63 1C DF 1D B7 00 00 80 93 80 F0 FF +13 BF 00 00 93 0E 00 00 93 01 A0 00 63 10 DF 1D +B7 00 00 80 93 80 F0 FF 13 BF F0 7F 93 0E 00 00 +93 01 B0 00 63 14 DF 1B B7 00 00 80 13 BF F0 7F +93 0E 00 00 93 01 C0 00 63 1A DF 19 B7 00 00 80 +93 80 F0 FF 13 BF 00 80 93 0E 10 00 93 01 D0 00 +63 1E DF 17 93 00 00 00 13 BF F0 FF 93 0E 10 00 +93 01 E0 00 63 14 DF 17 93 00 F0 FF 13 BF 10 00 +93 0E 00 00 93 01 F0 00 63 1A DF 15 93 00 F0 FF +13 BF F0 FF 93 0E 00 00 93 01 00 01 63 10 DF 15 +93 00 B0 00 93 B0 D0 00 93 0E 10 00 93 01 10 01 +63 96 D0 13 13 02 00 00 93 00 F0 00 13 BF A0 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 16 52 FE +93 0E 00 00 93 01 20 01 63 12 D3 11 13 02 00 00 +93 00 A0 00 13 BF 00 01 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 10 00 +93 01 30 01 63 1C D3 0D 13 02 00 00 93 00 00 01 +13 BF 90 00 13 00 00 00 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 00 00 +93 01 40 01 63 14 D3 0B 13 02 00 00 93 00 B0 00 +13 BF F0 00 13 02 12 00 93 02 20 00 E3 18 52 FE +93 0E 10 00 93 01 50 01 63 12 DF 09 13 02 00 00 +93 00 10 01 13 00 00 00 13 BF 80 00 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 0E 00 00 93 01 60 01 +63 1E DF 05 13 02 00 00 93 00 C0 00 13 00 00 00 +13 00 00 00 13 BF E0 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 10 00 93 01 70 01 63 18 DF 03 +93 30 F0 FF 93 0E 10 00 93 01 80 01 63 90 D0 03 +B7 00 FF 00 93 80 F0 0F 13 B0 F0 FF 93 0E 00 00 +93 01 90 01 63 14 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000300 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-sltu b/tests/isa/generated/rv32ui-p-sltu new file mode 100644 index 0000000..c8bbf26 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sltu differ diff --git a/tests/isa/generated/rv32ui-p-sltu.bin b/tests/isa/generated/rv32ui-p-sltu.bin new file mode 100644 index 0000000..577af70 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sltu.bin differ diff --git a/tests/isa/generated/rv32ui-p-sltu.dump b/tests/isa/generated/rv32ui-p-sltu.dump new file mode 100644 index 0000000..780dc20 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sltu.dump @@ -0,0 +1,412 @@ + +generated/rv32ui-p-sltu: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00000093 li ra,0 + c: 00000113 li sp,0 + 10: 0020bf33 sltu t5,ra,sp + 14: 00000e93 li t4,0 + 18: 00200193 li gp,2 + 1c: 4bdf1a63 bne t5,t4,4d0 + +00000020 : + 20: 00100093 li ra,1 + 24: 00100113 li sp,1 + 28: 0020bf33 sltu t5,ra,sp + 2c: 00000e93 li t4,0 + 30: 00300193 li gp,3 + 34: 49df1e63 bne t5,t4,4d0 + +00000038 : + 38: 00300093 li ra,3 + 3c: 00700113 li sp,7 + 40: 0020bf33 sltu t5,ra,sp + 44: 00100e93 li t4,1 + 48: 00400193 li gp,4 + 4c: 49df1263 bne t5,t4,4d0 + +00000050 : + 50: 00700093 li ra,7 + 54: 00300113 li sp,3 + 58: 0020bf33 sltu t5,ra,sp + 5c: 00000e93 li t4,0 + 60: 00500193 li gp,5 + 64: 47df1663 bne t5,t4,4d0 + +00000068 : + 68: 00000093 li ra,0 + 6c: ffff8137 lui sp,0xffff8 + 70: 0020bf33 sltu t5,ra,sp + 74: 00100e93 li t4,1 + 78: 00600193 li gp,6 + 7c: 45df1a63 bne t5,t4,4d0 + +00000080 : + 80: 800000b7 lui ra,0x80000 + 84: 00000113 li sp,0 + 88: 0020bf33 sltu t5,ra,sp + 8c: 00000e93 li t4,0 + 90: 00700193 li gp,7 + 94: 43df1e63 bne t5,t4,4d0 + +00000098 : + 98: 800000b7 lui ra,0x80000 + 9c: ffff8137 lui sp,0xffff8 + a0: 0020bf33 sltu t5,ra,sp + a4: 00100e93 li t4,1 + a8: 00800193 li gp,8 + ac: 43df1263 bne t5,t4,4d0 + +000000b0 : + b0: 00000093 li ra,0 + b4: 00008137 lui sp,0x8 + b8: fff10113 addi sp,sp,-1 # 7fff + bc: 0020bf33 sltu t5,ra,sp + c0: 00100e93 li t4,1 + c4: 00900193 li gp,9 + c8: 41df1463 bne t5,t4,4d0 + +000000cc : + cc: 800000b7 lui ra,0x80000 + d0: fff08093 addi ra,ra,-1 # 7fffffff + d4: 00000113 li sp,0 + d8: 0020bf33 sltu t5,ra,sp + dc: 00000e93 li t4,0 + e0: 00a00193 li gp,10 + e4: 3fdf1663 bne t5,t4,4d0 + +000000e8 : + e8: 800000b7 lui ra,0x80000 + ec: fff08093 addi ra,ra,-1 # 7fffffff + f0: 00008137 lui sp,0x8 + f4: fff10113 addi sp,sp,-1 # 7fff + f8: 0020bf33 sltu t5,ra,sp + fc: 00000e93 li t4,0 + 100: 00b00193 li gp,11 + 104: 3ddf1663 bne t5,t4,4d0 + +00000108 : + 108: 800000b7 lui ra,0x80000 + 10c: 00008137 lui sp,0x8 + 110: fff10113 addi sp,sp,-1 # 7fff + 114: 0020bf33 sltu t5,ra,sp + 118: 00000e93 li t4,0 + 11c: 00c00193 li gp,12 + 120: 3bdf1863 bne t5,t4,4d0 + +00000124 : + 124: 800000b7 lui ra,0x80000 + 128: fff08093 addi ra,ra,-1 # 7fffffff + 12c: ffff8137 lui sp,0xffff8 + 130: 0020bf33 sltu t5,ra,sp + 134: 00100e93 li t4,1 + 138: 00d00193 li gp,13 + 13c: 39df1a63 bne t5,t4,4d0 + +00000140 : + 140: 00000093 li ra,0 + 144: fff00113 li sp,-1 + 148: 0020bf33 sltu t5,ra,sp + 14c: 00100e93 li t4,1 + 150: 00e00193 li gp,14 + 154: 37df1e63 bne t5,t4,4d0 + +00000158 : + 158: fff00093 li ra,-1 + 15c: 00100113 li sp,1 + 160: 0020bf33 sltu t5,ra,sp + 164: 00000e93 li t4,0 + 168: 00f00193 li gp,15 + 16c: 37df1263 bne t5,t4,4d0 + +00000170 : + 170: fff00093 li ra,-1 + 174: fff00113 li sp,-1 + 178: 0020bf33 sltu t5,ra,sp + 17c: 00000e93 li t4,0 + 180: 01000193 li gp,16 + 184: 35df1663 bne t5,t4,4d0 + +00000188 : + 188: 00e00093 li ra,14 + 18c: 00d00113 li sp,13 + 190: 0020b0b3 sltu ra,ra,sp + 194: 00000e93 li t4,0 + 198: 01100193 li gp,17 + 19c: 33d09a63 bne ra,t4,4d0 + +000001a0 : + 1a0: 00b00093 li ra,11 + 1a4: 00d00113 li sp,13 + 1a8: 0020b133 sltu sp,ra,sp + 1ac: 00100e93 li t4,1 + 1b0: 01200193 li gp,18 + 1b4: 31d11e63 bne sp,t4,4d0 + +000001b8 : + 1b8: 00d00093 li ra,13 + 1bc: 0010b0b3 sltu ra,ra,ra + 1c0: 00000e93 li t4,0 + 1c4: 01300193 li gp,19 + 1c8: 31d09463 bne ra,t4,4d0 + +000001cc : + 1cc: 00000213 li tp,0 + 1d0: 00b00093 li ra,11 + 1d4: 00d00113 li sp,13 + 1d8: 0020bf33 sltu t5,ra,sp + 1dc: 000f0313 mv t1,t5 + 1e0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1e4: 00200293 li t0,2 + 1e8: fe5214e3 bne tp,t0,1d0 + 1ec: 00100e93 li t4,1 + 1f0: 01400193 li gp,20 + 1f4: 2dd31e63 bne t1,t4,4d0 + +000001f8 : + 1f8: 00000213 li tp,0 + 1fc: 00e00093 li ra,14 + 200: 00d00113 li sp,13 + 204: 0020bf33 sltu t5,ra,sp + 208: 00000013 nop + 20c: 000f0313 mv t1,t5 + 210: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 214: 00200293 li t0,2 + 218: fe5212e3 bne tp,t0,1fc + 21c: 00000e93 li t4,0 + 220: 01500193 li gp,21 + 224: 2bd31663 bne t1,t4,4d0 + +00000228 : + 228: 00000213 li tp,0 + 22c: 00c00093 li ra,12 + 230: 00d00113 li sp,13 + 234: 0020bf33 sltu t5,ra,sp + 238: 00000013 nop + 23c: 00000013 nop + 240: 000f0313 mv t1,t5 + 244: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 248: 00200293 li t0,2 + 24c: fe5210e3 bne tp,t0,22c + 250: 00100e93 li t4,1 + 254: 01600193 li gp,22 + 258: 27d31c63 bne t1,t4,4d0 + +0000025c : + 25c: 00000213 li tp,0 + 260: 00e00093 li ra,14 + 264: 00d00113 li sp,13 + 268: 0020bf33 sltu t5,ra,sp + 26c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 270: 00200293 li t0,2 + 274: fe5216e3 bne tp,t0,260 + 278: 00000e93 li t4,0 + 27c: 01700193 li gp,23 + 280: 25df1863 bne t5,t4,4d0 + +00000284 : + 284: 00000213 li tp,0 + 288: 00b00093 li ra,11 + 28c: 00d00113 li sp,13 + 290: 00000013 nop + 294: 0020bf33 sltu t5,ra,sp + 298: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 29c: 00200293 li t0,2 + 2a0: fe5214e3 bne tp,t0,288 + 2a4: 00100e93 li t4,1 + 2a8: 01800193 li gp,24 + 2ac: 23df1263 bne t5,t4,4d0 + +000002b0 : + 2b0: 00000213 li tp,0 + 2b4: 00f00093 li ra,15 + 2b8: 00d00113 li sp,13 + 2bc: 00000013 nop + 2c0: 00000013 nop + 2c4: 0020bf33 sltu t5,ra,sp + 2c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2cc: 00200293 li t0,2 + 2d0: fe5212e3 bne tp,t0,2b4 + 2d4: 00000e93 li t4,0 + 2d8: 01900193 li gp,25 + 2dc: 1fdf1a63 bne t5,t4,4d0 + +000002e0 : + 2e0: 00000213 li tp,0 + 2e4: 00a00093 li ra,10 + 2e8: 00000013 nop + 2ec: 00d00113 li sp,13 + 2f0: 0020bf33 sltu t5,ra,sp + 2f4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2f8: 00200293 li t0,2 + 2fc: fe5214e3 bne tp,t0,2e4 + 300: 00100e93 li t4,1 + 304: 01a00193 li gp,26 + 308: 1ddf1463 bne t5,t4,4d0 + +0000030c : + 30c: 00000213 li tp,0 + 310: 01000093 li ra,16 + 314: 00000013 nop + 318: 00d00113 li sp,13 + 31c: 00000013 nop + 320: 0020bf33 sltu t5,ra,sp + 324: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 328: 00200293 li t0,2 + 32c: fe5212e3 bne tp,t0,310 + 330: 00000e93 li t4,0 + 334: 01b00193 li gp,27 + 338: 19df1c63 bne t5,t4,4d0 + +0000033c : + 33c: 00000213 li tp,0 + 340: 00900093 li ra,9 + 344: 00000013 nop + 348: 00000013 nop + 34c: 00d00113 li sp,13 + 350: 0020bf33 sltu t5,ra,sp + 354: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 358: 00200293 li t0,2 + 35c: fe5212e3 bne tp,t0,340 + 360: 00100e93 li t4,1 + 364: 01c00193 li gp,28 + 368: 17df1463 bne t5,t4,4d0 + +0000036c : + 36c: 00000213 li tp,0 + 370: 00d00113 li sp,13 + 374: 01100093 li ra,17 + 378: 0020bf33 sltu t5,ra,sp + 37c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 380: 00200293 li t0,2 + 384: fe5216e3 bne tp,t0,370 + 388: 00000e93 li t4,0 + 38c: 01d00193 li gp,29 + 390: 15df1063 bne t5,t4,4d0 + +00000394 : + 394: 00000213 li tp,0 + 398: 00d00113 li sp,13 + 39c: 00800093 li ra,8 + 3a0: 00000013 nop + 3a4: 0020bf33 sltu t5,ra,sp + 3a8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3ac: 00200293 li t0,2 + 3b0: fe5214e3 bne tp,t0,398 + 3b4: 00100e93 li t4,1 + 3b8: 01e00193 li gp,30 + 3bc: 11df1a63 bne t5,t4,4d0 + +000003c0 : + 3c0: 00000213 li tp,0 + 3c4: 00d00113 li sp,13 + 3c8: 01200093 li ra,18 + 3cc: 00000013 nop + 3d0: 00000013 nop + 3d4: 0020bf33 sltu t5,ra,sp + 3d8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3dc: 00200293 li t0,2 + 3e0: fe5212e3 bne tp,t0,3c4 + 3e4: 00000e93 li t4,0 + 3e8: 01f00193 li gp,31 + 3ec: 0fdf1263 bne t5,t4,4d0 + +000003f0 : + 3f0: 00000213 li tp,0 + 3f4: 00d00113 li sp,13 + 3f8: 00000013 nop + 3fc: 00700093 li ra,7 + 400: 0020bf33 sltu t5,ra,sp + 404: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 408: 00200293 li t0,2 + 40c: fe5214e3 bne tp,t0,3f4 + 410: 00100e93 li t4,1 + 414: 02000193 li gp,32 + 418: 0bdf1c63 bne t5,t4,4d0 + +0000041c : + 41c: 00000213 li tp,0 + 420: 00d00113 li sp,13 + 424: 00000013 nop + 428: 01300093 li ra,19 + 42c: 00000013 nop + 430: 0020bf33 sltu t5,ra,sp + 434: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 438: 00200293 li t0,2 + 43c: fe5212e3 bne tp,t0,420 + 440: 00000e93 li t4,0 + 444: 02100193 li gp,33 + 448: 09df1463 bne t5,t4,4d0 + +0000044c : + 44c: 00000213 li tp,0 + 450: 00d00113 li sp,13 + 454: 00000013 nop + 458: 00000013 nop + 45c: 00600093 li ra,6 + 460: 0020bf33 sltu t5,ra,sp + 464: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 468: 00200293 li t0,2 + 46c: fe5212e3 bne tp,t0,450 + 470: 00100e93 li t4,1 + 474: 02200193 li gp,34 + 478: 05df1c63 bne t5,t4,4d0 + +0000047c : + 47c: fff00093 li ra,-1 + 480: 00103133 snez sp,ra + 484: 00100e93 li t4,1 + 488: 02300193 li gp,35 + 48c: 05d11263 bne sp,t4,4d0 + +00000490 : + 490: fff00093 li ra,-1 + 494: 0000b133 sltu sp,ra,zero + 498: 00000e93 li t4,0 + 49c: 02400193 li gp,36 + 4a0: 03d11863 bne sp,t4,4d0 + +000004a4 : + 4a4: 000030b3 snez ra,zero + 4a8: 00000e93 li t4,0 + 4ac: 02500193 li gp,37 + 4b0: 03d09063 bne ra,t4,4d0 + +000004b4 : + 4b4: 01000093 li ra,16 + 4b8: 01e00113 li sp,30 + 4bc: 0020b033 sltu zero,ra,sp + 4c0: 00000e93 li t4,0 + 4c4: 02600193 li gp,38 + 4c8: 01d01463 bne zero,t4,4d0 + 4cc: 00301863 bne zero,gp,4dc + +000004d0 : + 4d0: 00100d13 li s10,1 + 4d4: 00000d93 li s11,0 + +000004d8 : + 4d8: 0000006f j 4d8 + +000004dc : + 4dc: 00100d13 li s10,1 + 4e0: 00100d93 li s11,1 + +000004e4 : + 4e4: 0000006f j 4e4 + ... + +Disassembly of section .tohost: + +00000540 : + ... + +00000580 : + ... diff --git a/tests/isa/generated/rv32ui-p-sltu.verilog b/tests/isa/generated/rv32ui-p-sltu.verilog new file mode 100644 index 0000000..755e67c --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sltu.verilog @@ -0,0 +1,88 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 00 00 13 01 00 00 +33 BF 20 00 93 0E 00 00 93 01 20 00 63 1A DF 4B +93 00 10 00 13 01 10 00 33 BF 20 00 93 0E 00 00 +93 01 30 00 63 1E DF 49 93 00 30 00 13 01 70 00 +33 BF 20 00 93 0E 10 00 93 01 40 00 63 12 DF 49 +93 00 70 00 13 01 30 00 33 BF 20 00 93 0E 00 00 +93 01 50 00 63 16 DF 47 93 00 00 00 37 81 FF FF +33 BF 20 00 93 0E 10 00 93 01 60 00 63 1A DF 45 +B7 00 00 80 13 01 00 00 33 BF 20 00 93 0E 00 00 +93 01 70 00 63 1E DF 43 B7 00 00 80 37 81 FF FF +33 BF 20 00 93 0E 10 00 93 01 80 00 63 12 DF 43 +93 00 00 00 37 81 00 00 13 01 F1 FF 33 BF 20 00 +93 0E 10 00 93 01 90 00 63 14 DF 41 B7 00 00 80 +93 80 F0 FF 13 01 00 00 33 BF 20 00 93 0E 00 00 +93 01 A0 00 63 16 DF 3F B7 00 00 80 93 80 F0 FF +37 81 00 00 13 01 F1 FF 33 BF 20 00 93 0E 00 00 +93 01 B0 00 63 16 DF 3D B7 00 00 80 37 81 00 00 +13 01 F1 FF 33 BF 20 00 93 0E 00 00 93 01 C0 00 +63 18 DF 3B B7 00 00 80 93 80 F0 FF 37 81 FF FF +33 BF 20 00 93 0E 10 00 93 01 D0 00 63 1A DF 39 +93 00 00 00 13 01 F0 FF 33 BF 20 00 93 0E 10 00 +93 01 E0 00 63 1E DF 37 93 00 F0 FF 13 01 10 00 +33 BF 20 00 93 0E 00 00 93 01 F0 00 63 12 DF 37 +93 00 F0 FF 13 01 F0 FF 33 BF 20 00 93 0E 00 00 +93 01 00 01 63 16 DF 35 93 00 E0 00 13 01 D0 00 +B3 B0 20 00 93 0E 00 00 93 01 10 01 63 9A D0 33 +93 00 B0 00 13 01 D0 00 33 B1 20 00 93 0E 10 00 +93 01 20 01 63 1E D1 31 93 00 D0 00 B3 B0 10 00 +93 0E 00 00 93 01 30 01 63 94 D0 31 13 02 00 00 +93 00 B0 00 13 01 D0 00 33 BF 20 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 10 00 +93 01 40 01 63 1E D3 2D 13 02 00 00 93 00 E0 00 +13 01 D0 00 33 BF 20 00 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 00 00 +93 01 50 01 63 16 D3 2B 13 02 00 00 93 00 C0 00 +13 01 D0 00 33 BF 20 00 13 00 00 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE +93 0E 10 00 93 01 60 01 63 1C D3 27 13 02 00 00 +93 00 E0 00 13 01 D0 00 33 BF 20 00 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 0E 00 00 93 01 70 01 +63 18 DF 25 13 02 00 00 93 00 B0 00 13 01 D0 00 +13 00 00 00 33 BF 20 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 10 00 93 01 80 01 63 12 DF 23 +13 02 00 00 93 00 F0 00 13 01 D0 00 13 00 00 00 +13 00 00 00 33 BF 20 00 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E 00 00 93 01 90 01 63 1A DF 1F +13 02 00 00 93 00 A0 00 13 00 00 00 13 01 D0 00 +33 BF 20 00 13 02 12 00 93 02 20 00 E3 14 52 FE +93 0E 10 00 93 01 A0 01 63 14 DF 1D 13 02 00 00 +93 00 00 01 13 00 00 00 13 01 D0 00 13 00 00 00 +33 BF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E 00 00 93 01 B0 01 63 1C DF 19 13 02 00 00 +93 00 90 00 13 00 00 00 13 00 00 00 13 01 D0 00 +33 BF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E 10 00 93 01 C0 01 63 14 DF 17 13 02 00 00 +13 01 D0 00 93 00 10 01 33 BF 20 00 13 02 12 00 +93 02 20 00 E3 16 52 FE 93 0E 00 00 93 01 D0 01 +63 10 DF 15 13 02 00 00 13 01 D0 00 93 00 80 00 +13 00 00 00 33 BF 20 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 10 00 93 01 E0 01 63 1A DF 11 +13 02 00 00 13 01 D0 00 93 00 20 01 13 00 00 00 +13 00 00 00 33 BF 20 00 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E 00 00 93 01 F0 01 63 12 DF 0F +13 02 00 00 13 01 D0 00 13 00 00 00 93 00 70 00 +33 BF 20 00 13 02 12 00 93 02 20 00 E3 14 52 FE +93 0E 10 00 93 01 00 02 63 1C DF 0B 13 02 00 00 +13 01 D0 00 13 00 00 00 93 00 30 01 13 00 00 00 +33 BF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E 00 00 93 01 10 02 63 14 DF 09 13 02 00 00 +13 01 D0 00 13 00 00 00 13 00 00 00 93 00 60 00 +33 BF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E 10 00 93 01 20 02 63 1C DF 05 93 00 F0 FF +33 31 10 00 93 0E 10 00 93 01 30 02 63 12 D1 05 +93 00 F0 FF 33 B1 00 00 93 0E 00 00 93 01 40 02 +63 18 D1 03 B3 30 00 00 93 0E 00 00 93 01 50 02 +63 90 D0 03 93 00 00 01 13 01 E0 01 33 B0 20 00 +93 0E 00 00 93 01 60 02 63 14 D0 01 63 18 30 00 +13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00 +93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000540 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-sra b/tests/isa/generated/rv32ui-p-sra new file mode 100644 index 0000000..dbef4a1 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sra differ diff --git a/tests/isa/generated/rv32ui-p-sra.bin b/tests/isa/generated/rv32ui-p-sra.bin new file mode 100644 index 0000000..a94ea3f Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sra.bin differ diff --git a/tests/isa/generated/rv32ui-p-sra.dump b/tests/isa/generated/rv32ui-p-sra.dump new file mode 100644 index 0000000..31c19aa --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sra.dump @@ -0,0 +1,475 @@ + +generated/rv32ui-p-sra: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 800000b7 lui ra,0x80000 + c: 00000113 li sp,0 + 10: 4020df33 sra t5,ra,sp + 14: 80000eb7 lui t4,0x80000 + 18: 00200193 li gp,2 + 1c: 59df1463 bne t5,t4,5a4 + +00000020 : + 20: 800000b7 lui ra,0x80000 + 24: 00100113 li sp,1 + 28: 4020df33 sra t5,ra,sp + 2c: c0000eb7 lui t4,0xc0000 + 30: 00300193 li gp,3 + 34: 57df1863 bne t5,t4,5a4 + +00000038 : + 38: 800000b7 lui ra,0x80000 + 3c: 00700113 li sp,7 + 40: 4020df33 sra t5,ra,sp + 44: ff000eb7 lui t4,0xff000 + 48: 00400193 li gp,4 + 4c: 55df1c63 bne t5,t4,5a4 + +00000050 : + 50: 800000b7 lui ra,0x80000 + 54: 00e00113 li sp,14 + 58: 4020df33 sra t5,ra,sp + 5c: fffe0eb7 lui t4,0xfffe0 + 60: 00500193 li gp,5 + 64: 55df1063 bne t5,t4,5a4 + +00000068 : + 68: 800000b7 lui ra,0x80000 + 6c: 00108093 addi ra,ra,1 # 80000001 + 70: 01f00113 li sp,31 + 74: 4020df33 sra t5,ra,sp + 78: fff00e93 li t4,-1 + 7c: 00600193 li gp,6 + 80: 53df1263 bne t5,t4,5a4 + +00000084 : + 84: 800000b7 lui ra,0x80000 + 88: fff08093 addi ra,ra,-1 # 7fffffff + 8c: 00000113 li sp,0 + 90: 4020df33 sra t5,ra,sp + 94: 80000eb7 lui t4,0x80000 + 98: fffe8e93 addi t4,t4,-1 # 7fffffff + 9c: 00700193 li gp,7 + a0: 51df1263 bne t5,t4,5a4 + +000000a4 : + a4: 800000b7 lui ra,0x80000 + a8: fff08093 addi ra,ra,-1 # 7fffffff + ac: 00100113 li sp,1 + b0: 4020df33 sra t5,ra,sp + b4: 40000eb7 lui t4,0x40000 + b8: fffe8e93 addi t4,t4,-1 # 3fffffff + bc: 00800193 li gp,8 + c0: 4fdf1263 bne t5,t4,5a4 + +000000c4 : + c4: 800000b7 lui ra,0x80000 + c8: fff08093 addi ra,ra,-1 # 7fffffff + cc: 00700113 li sp,7 + d0: 4020df33 sra t5,ra,sp + d4: 01000eb7 lui t4,0x1000 + d8: fffe8e93 addi t4,t4,-1 # ffffff + dc: 00900193 li gp,9 + e0: 4ddf1263 bne t5,t4,5a4 + +000000e4 : + e4: 800000b7 lui ra,0x80000 + e8: fff08093 addi ra,ra,-1 # 7fffffff + ec: 00e00113 li sp,14 + f0: 4020df33 sra t5,ra,sp + f4: 00020eb7 lui t4,0x20 + f8: fffe8e93 addi t4,t4,-1 # 1ffff + fc: 00a00193 li gp,10 + 100: 4bdf1263 bne t5,t4,5a4 + +00000104 : + 104: 800000b7 lui ra,0x80000 + 108: fff08093 addi ra,ra,-1 # 7fffffff + 10c: 01f00113 li sp,31 + 110: 4020df33 sra t5,ra,sp + 114: 00000e93 li t4,0 + 118: 00b00193 li gp,11 + 11c: 49df1463 bne t5,t4,5a4 + +00000120 : + 120: 818180b7 lui ra,0x81818 + 124: 18108093 addi ra,ra,385 # 81818181 + 128: 00000113 li sp,0 + 12c: 4020df33 sra t5,ra,sp + 130: 81818eb7 lui t4,0x81818 + 134: 181e8e93 addi t4,t4,385 # 81818181 + 138: 00c00193 li gp,12 + 13c: 47df1463 bne t5,t4,5a4 + +00000140 : + 140: 818180b7 lui ra,0x81818 + 144: 18108093 addi ra,ra,385 # 81818181 + 148: 00100113 li sp,1 + 14c: 4020df33 sra t5,ra,sp + 150: c0c0ceb7 lui t4,0xc0c0c + 154: 0c0e8e93 addi t4,t4,192 # c0c0c0c0 + 158: 00d00193 li gp,13 + 15c: 45df1463 bne t5,t4,5a4 + +00000160 : + 160: 818180b7 lui ra,0x81818 + 164: 18108093 addi ra,ra,385 # 81818181 + 168: 00700113 li sp,7 + 16c: 4020df33 sra t5,ra,sp + 170: ff030eb7 lui t4,0xff030 + 174: 303e8e93 addi t4,t4,771 # ff030303 + 178: 00e00193 li gp,14 + 17c: 43df1463 bne t5,t4,5a4 + +00000180 : + 180: 818180b7 lui ra,0x81818 + 184: 18108093 addi ra,ra,385 # 81818181 + 188: 00e00113 li sp,14 + 18c: 4020df33 sra t5,ra,sp + 190: fffe0eb7 lui t4,0xfffe0 + 194: 606e8e93 addi t4,t4,1542 # fffe0606 + 198: 00f00193 li gp,15 + 19c: 41df1463 bne t5,t4,5a4 + +000001a0 : + 1a0: 818180b7 lui ra,0x81818 + 1a4: 18108093 addi ra,ra,385 # 81818181 + 1a8: 01f00113 li sp,31 + 1ac: 4020df33 sra t5,ra,sp + 1b0: fff00e93 li t4,-1 + 1b4: 01000193 li gp,16 + 1b8: 3fdf1663 bne t5,t4,5a4 + +000001bc : + 1bc: 818180b7 lui ra,0x81818 + 1c0: 18108093 addi ra,ra,385 # 81818181 + 1c4: fc000113 li sp,-64 + 1c8: 4020df33 sra t5,ra,sp + 1cc: 81818eb7 lui t4,0x81818 + 1d0: 181e8e93 addi t4,t4,385 # 81818181 + 1d4: 01100193 li gp,17 + 1d8: 3ddf1663 bne t5,t4,5a4 + +000001dc : + 1dc: 818180b7 lui ra,0x81818 + 1e0: 18108093 addi ra,ra,385 # 81818181 + 1e4: fc100113 li sp,-63 + 1e8: 4020df33 sra t5,ra,sp + 1ec: c0c0ceb7 lui t4,0xc0c0c + 1f0: 0c0e8e93 addi t4,t4,192 # c0c0c0c0 + 1f4: 01200193 li gp,18 + 1f8: 3bdf1663 bne t5,t4,5a4 + +000001fc : + 1fc: 818180b7 lui ra,0x81818 + 200: 18108093 addi ra,ra,385 # 81818181 + 204: fc700113 li sp,-57 + 208: 4020df33 sra t5,ra,sp + 20c: ff030eb7 lui t4,0xff030 + 210: 303e8e93 addi t4,t4,771 # ff030303 + 214: 01300193 li gp,19 + 218: 39df1663 bne t5,t4,5a4 + +0000021c : + 21c: 818180b7 lui ra,0x81818 + 220: 18108093 addi ra,ra,385 # 81818181 + 224: fce00113 li sp,-50 + 228: 4020df33 sra t5,ra,sp + 22c: fffe0eb7 lui t4,0xfffe0 + 230: 606e8e93 addi t4,t4,1542 # fffe0606 + 234: 01400193 li gp,20 + 238: 37df1663 bne t5,t4,5a4 + +0000023c : + 23c: 818180b7 lui ra,0x81818 + 240: 18108093 addi ra,ra,385 # 81818181 + 244: fff00113 li sp,-1 + 248: 4020df33 sra t5,ra,sp + 24c: fff00e93 li t4,-1 + 250: 01500193 li gp,21 + 254: 35df1863 bne t5,t4,5a4 + +00000258 : + 258: 800000b7 lui ra,0x80000 + 25c: 00700113 li sp,7 + 260: 4020d0b3 sra ra,ra,sp + 264: ff000eb7 lui t4,0xff000 + 268: 01600193 li gp,22 + 26c: 33d09c63 bne ra,t4,5a4 + +00000270 : + 270: 800000b7 lui ra,0x80000 + 274: 00e00113 li sp,14 + 278: 4020d133 sra sp,ra,sp + 27c: fffe0eb7 lui t4,0xfffe0 + 280: 01700193 li gp,23 + 284: 33d11063 bne sp,t4,5a4 + +00000288 : + 288: 00700093 li ra,7 + 28c: 4010d0b3 sra ra,ra,ra + 290: 00000e93 li t4,0 + 294: 01800193 li gp,24 + 298: 31d09663 bne ra,t4,5a4 + +0000029c : + 29c: 00000213 li tp,0 + 2a0: 800000b7 lui ra,0x80000 + 2a4: 00700113 li sp,7 + 2a8: 4020df33 sra t5,ra,sp + 2ac: 000f0313 mv t1,t5 + 2b0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2b4: 00200293 li t0,2 + 2b8: fe5214e3 bne tp,t0,2a0 + 2bc: ff000eb7 lui t4,0xff000 + 2c0: 01900193 li gp,25 + 2c4: 2fd31063 bne t1,t4,5a4 + +000002c8 : + 2c8: 00000213 li tp,0 + 2cc: 800000b7 lui ra,0x80000 + 2d0: 00e00113 li sp,14 + 2d4: 4020df33 sra t5,ra,sp + 2d8: 00000013 nop + 2dc: 000f0313 mv t1,t5 + 2e0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2e4: 00200293 li t0,2 + 2e8: fe5212e3 bne tp,t0,2cc + 2ec: fffe0eb7 lui t4,0xfffe0 + 2f0: 01a00193 li gp,26 + 2f4: 2bd31863 bne t1,t4,5a4 + +000002f8 : + 2f8: 00000213 li tp,0 + 2fc: 800000b7 lui ra,0x80000 + 300: 01f00113 li sp,31 + 304: 4020df33 sra t5,ra,sp + 308: 00000013 nop + 30c: 00000013 nop + 310: 000f0313 mv t1,t5 + 314: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 318: 00200293 li t0,2 + 31c: fe5210e3 bne tp,t0,2fc + 320: fff00e93 li t4,-1 + 324: 01b00193 li gp,27 + 328: 27d31e63 bne t1,t4,5a4 + +0000032c : + 32c: 00000213 li tp,0 + 330: 800000b7 lui ra,0x80000 + 334: 00700113 li sp,7 + 338: 4020df33 sra t5,ra,sp + 33c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 340: 00200293 li t0,2 + 344: fe5216e3 bne tp,t0,330 + 348: ff000eb7 lui t4,0xff000 + 34c: 01c00193 li gp,28 + 350: 25df1a63 bne t5,t4,5a4 + +00000354 : + 354: 00000213 li tp,0 + 358: 800000b7 lui ra,0x80000 + 35c: 00e00113 li sp,14 + 360: 00000013 nop + 364: 4020df33 sra t5,ra,sp + 368: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 36c: 00200293 li t0,2 + 370: fe5214e3 bne tp,t0,358 + 374: fffe0eb7 lui t4,0xfffe0 + 378: 01d00193 li gp,29 + 37c: 23df1463 bne t5,t4,5a4 + +00000380 : + 380: 00000213 li tp,0 + 384: 800000b7 lui ra,0x80000 + 388: 01f00113 li sp,31 + 38c: 00000013 nop + 390: 00000013 nop + 394: 4020df33 sra t5,ra,sp + 398: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 39c: 00200293 li t0,2 + 3a0: fe5212e3 bne tp,t0,384 + 3a4: fff00e93 li t4,-1 + 3a8: 01e00193 li gp,30 + 3ac: 1fdf1c63 bne t5,t4,5a4 + +000003b0 : + 3b0: 00000213 li tp,0 + 3b4: 800000b7 lui ra,0x80000 + 3b8: 00000013 nop + 3bc: 00700113 li sp,7 + 3c0: 4020df33 sra t5,ra,sp + 3c4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3c8: 00200293 li t0,2 + 3cc: fe5214e3 bne tp,t0,3b4 + 3d0: ff000eb7 lui t4,0xff000 + 3d4: 01f00193 li gp,31 + 3d8: 1ddf1663 bne t5,t4,5a4 + +000003dc : + 3dc: 00000213 li tp,0 + 3e0: 800000b7 lui ra,0x80000 + 3e4: 00000013 nop + 3e8: 00e00113 li sp,14 + 3ec: 00000013 nop + 3f0: 4020df33 sra t5,ra,sp + 3f4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3f8: 00200293 li t0,2 + 3fc: fe5212e3 bne tp,t0,3e0 + 400: fffe0eb7 lui t4,0xfffe0 + 404: 02000193 li gp,32 + 408: 19df1e63 bne t5,t4,5a4 + +0000040c : + 40c: 00000213 li tp,0 + 410: 800000b7 lui ra,0x80000 + 414: 00000013 nop + 418: 00000013 nop + 41c: 01f00113 li sp,31 + 420: 4020df33 sra t5,ra,sp + 424: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 428: 00200293 li t0,2 + 42c: fe5212e3 bne tp,t0,410 + 430: fff00e93 li t4,-1 + 434: 02100193 li gp,33 + 438: 17df1663 bne t5,t4,5a4 + +0000043c : + 43c: 00000213 li tp,0 + 440: 00700113 li sp,7 + 444: 800000b7 lui ra,0x80000 + 448: 4020df33 sra t5,ra,sp + 44c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 450: 00200293 li t0,2 + 454: fe5216e3 bne tp,t0,440 + 458: ff000eb7 lui t4,0xff000 + 45c: 02200193 li gp,34 + 460: 15df1263 bne t5,t4,5a4 + +00000464 : + 464: 00000213 li tp,0 + 468: 00e00113 li sp,14 + 46c: 800000b7 lui ra,0x80000 + 470: 00000013 nop + 474: 4020df33 sra t5,ra,sp + 478: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 47c: 00200293 li t0,2 + 480: fe5214e3 bne tp,t0,468 + 484: fffe0eb7 lui t4,0xfffe0 + 488: 02300193 li gp,35 + 48c: 11df1c63 bne t5,t4,5a4 + +00000490 : + 490: 00000213 li tp,0 + 494: 01f00113 li sp,31 + 498: 800000b7 lui ra,0x80000 + 49c: 00000013 nop + 4a0: 00000013 nop + 4a4: 4020df33 sra t5,ra,sp + 4a8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 4ac: 00200293 li t0,2 + 4b0: fe5212e3 bne tp,t0,494 + 4b4: fff00e93 li t4,-1 + 4b8: 02400193 li gp,36 + 4bc: 0fdf1463 bne t5,t4,5a4 + +000004c0 : + 4c0: 00000213 li tp,0 + 4c4: 00700113 li sp,7 + 4c8: 00000013 nop + 4cc: 800000b7 lui ra,0x80000 + 4d0: 4020df33 sra t5,ra,sp + 4d4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 4d8: 00200293 li t0,2 + 4dc: fe5214e3 bne tp,t0,4c4 + 4e0: ff000eb7 lui t4,0xff000 + 4e4: 02500193 li gp,37 + 4e8: 0bdf1e63 bne t5,t4,5a4 + +000004ec : + 4ec: 00000213 li tp,0 + 4f0: 00e00113 li sp,14 + 4f4: 00000013 nop + 4f8: 800000b7 lui ra,0x80000 + 4fc: 00000013 nop + 500: 4020df33 sra t5,ra,sp + 504: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 508: 00200293 li t0,2 + 50c: fe5212e3 bne tp,t0,4f0 + 510: fffe0eb7 lui t4,0xfffe0 + 514: 02600193 li gp,38 + 518: 09df1663 bne t5,t4,5a4 + +0000051c : + 51c: 00000213 li tp,0 + 520: 01f00113 li sp,31 + 524: 00000013 nop + 528: 00000013 nop + 52c: 800000b7 lui ra,0x80000 + 530: 4020df33 sra t5,ra,sp + 534: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 538: 00200293 li t0,2 + 53c: fe5212e3 bne tp,t0,520 + 540: fff00e93 li t4,-1 + 544: 02700193 li gp,39 + 548: 05df1e63 bne t5,t4,5a4 + +0000054c : + 54c: 00f00093 li ra,15 + 550: 40105133 sra sp,zero,ra + 554: 00000e93 li t4,0 + 558: 02800193 li gp,40 + 55c: 05d11463 bne sp,t4,5a4 + +00000560 : + 560: 02000093 li ra,32 + 564: 4000d133 sra sp,ra,zero + 568: 02000e93 li t4,32 + 56c: 02900193 li gp,41 + 570: 03d11a63 bne sp,t4,5a4 + +00000574 : + 574: 400050b3 sra ra,zero,zero + 578: 00000e93 li t4,0 + 57c: 02a00193 li gp,42 + 580: 03d09263 bne ra,t4,5a4 + +00000584 : + 584: 40000093 li ra,1024 + 588: 00001137 lui sp,0x1 + 58c: 80010113 addi sp,sp,-2048 # 800 <_end+0x1b8> + 590: 4020d033 sra zero,ra,sp + 594: 00000e93 li t4,0 + 598: 02b00193 li gp,43 + 59c: 01d01463 bne zero,t4,5a4 + 5a0: 00301863 bne zero,gp,5b0 + +000005a4 : + 5a4: 00100d13 li s10,1 + 5a8: 00000d93 li s11,0 + +000005ac : + 5ac: 0000006f j 5ac + +000005b0 : + 5b0: 00100d13 li s10,1 + 5b4: 00100d93 li s11,1 + +000005b8 : + 5b8: 0000006f j 5b8 + ... + +Disassembly of section .tohost: + +00000600 : + ... + +00000640 : + ... diff --git a/tests/isa/generated/rv32ui-p-sra.verilog b/tests/isa/generated/rv32ui-p-sra.verilog new file mode 100644 index 0000000..98afbb9 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sra.verilog @@ -0,0 +1,100 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 00 00 80 13 01 00 00 +33 DF 20 40 B7 0E 00 80 93 01 20 00 63 14 DF 59 +B7 00 00 80 13 01 10 00 33 DF 20 40 B7 0E 00 C0 +93 01 30 00 63 18 DF 57 B7 00 00 80 13 01 70 00 +33 DF 20 40 B7 0E 00 FF 93 01 40 00 63 1C DF 55 +B7 00 00 80 13 01 E0 00 33 DF 20 40 B7 0E FE FF +93 01 50 00 63 10 DF 55 B7 00 00 80 93 80 10 00 +13 01 F0 01 33 DF 20 40 93 0E F0 FF 93 01 60 00 +63 12 DF 53 B7 00 00 80 93 80 F0 FF 13 01 00 00 +33 DF 20 40 B7 0E 00 80 93 8E FE FF 93 01 70 00 +63 12 DF 51 B7 00 00 80 93 80 F0 FF 13 01 10 00 +33 DF 20 40 B7 0E 00 40 93 8E FE FF 93 01 80 00 +63 12 DF 4F B7 00 00 80 93 80 F0 FF 13 01 70 00 +33 DF 20 40 B7 0E 00 01 93 8E FE FF 93 01 90 00 +63 12 DF 4D B7 00 00 80 93 80 F0 FF 13 01 E0 00 +33 DF 20 40 B7 0E 02 00 93 8E FE FF 93 01 A0 00 +63 12 DF 4B B7 00 00 80 93 80 F0 FF 13 01 F0 01 +33 DF 20 40 93 0E 00 00 93 01 B0 00 63 14 DF 49 +B7 80 81 81 93 80 10 18 13 01 00 00 33 DF 20 40 +B7 8E 81 81 93 8E 1E 18 93 01 C0 00 63 14 DF 47 +B7 80 81 81 93 80 10 18 13 01 10 00 33 DF 20 40 +B7 CE C0 C0 93 8E 0E 0C 93 01 D0 00 63 14 DF 45 +B7 80 81 81 93 80 10 18 13 01 70 00 33 DF 20 40 +B7 0E 03 FF 93 8E 3E 30 93 01 E0 00 63 14 DF 43 +B7 80 81 81 93 80 10 18 13 01 E0 00 33 DF 20 40 +B7 0E FE FF 93 8E 6E 60 93 01 F0 00 63 14 DF 41 +B7 80 81 81 93 80 10 18 13 01 F0 01 33 DF 20 40 +93 0E F0 FF 93 01 00 01 63 16 DF 3F B7 80 81 81 +93 80 10 18 13 01 00 FC 33 DF 20 40 B7 8E 81 81 +93 8E 1E 18 93 01 10 01 63 16 DF 3D B7 80 81 81 +93 80 10 18 13 01 10 FC 33 DF 20 40 B7 CE C0 C0 +93 8E 0E 0C 93 01 20 01 63 16 DF 3B B7 80 81 81 +93 80 10 18 13 01 70 FC 33 DF 20 40 B7 0E 03 FF +93 8E 3E 30 93 01 30 01 63 16 DF 39 B7 80 81 81 +93 80 10 18 13 01 E0 FC 33 DF 20 40 B7 0E FE FF +93 8E 6E 60 93 01 40 01 63 16 DF 37 B7 80 81 81 +93 80 10 18 13 01 F0 FF 33 DF 20 40 93 0E F0 FF +93 01 50 01 63 18 DF 35 B7 00 00 80 13 01 70 00 +B3 D0 20 40 B7 0E 00 FF 93 01 60 01 63 9C D0 33 +B7 00 00 80 13 01 E0 00 33 D1 20 40 B7 0E FE FF +93 01 70 01 63 10 D1 33 93 00 70 00 B3 D0 10 40 +93 0E 00 00 93 01 80 01 63 96 D0 31 13 02 00 00 +B7 00 00 80 13 01 70 00 33 DF 20 40 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 14 52 FE B7 0E 00 FF +93 01 90 01 63 10 D3 2F 13 02 00 00 B7 00 00 80 +13 01 E0 00 33 DF 20 40 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 12 52 FE B7 0E FE FF +93 01 A0 01 63 18 D3 2B 13 02 00 00 B7 00 00 80 +13 01 F0 01 33 DF 20 40 13 00 00 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE +93 0E F0 FF 93 01 B0 01 63 1E D3 27 13 02 00 00 +B7 00 00 80 13 01 70 00 33 DF 20 40 13 02 12 00 +93 02 20 00 E3 16 52 FE B7 0E 00 FF 93 01 C0 01 +63 1A DF 25 13 02 00 00 B7 00 00 80 13 01 E0 00 +13 00 00 00 33 DF 20 40 13 02 12 00 93 02 20 00 +E3 14 52 FE B7 0E FE FF 93 01 D0 01 63 14 DF 23 +13 02 00 00 B7 00 00 80 13 01 F0 01 13 00 00 00 +13 00 00 00 33 DF 20 40 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E F0 FF 93 01 E0 01 63 1C DF 1F +13 02 00 00 B7 00 00 80 13 00 00 00 13 01 70 00 +33 DF 20 40 13 02 12 00 93 02 20 00 E3 14 52 FE +B7 0E 00 FF 93 01 F0 01 63 16 DF 1D 13 02 00 00 +B7 00 00 80 13 00 00 00 13 01 E0 00 13 00 00 00 +33 DF 20 40 13 02 12 00 93 02 20 00 E3 12 52 FE +B7 0E FE FF 93 01 00 02 63 1E DF 19 13 02 00 00 +B7 00 00 80 13 00 00 00 13 00 00 00 13 01 F0 01 +33 DF 20 40 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E F0 FF 93 01 10 02 63 16 DF 17 13 02 00 00 +13 01 70 00 B7 00 00 80 33 DF 20 40 13 02 12 00 +93 02 20 00 E3 16 52 FE B7 0E 00 FF 93 01 20 02 +63 12 DF 15 13 02 00 00 13 01 E0 00 B7 00 00 80 +13 00 00 00 33 DF 20 40 13 02 12 00 93 02 20 00 +E3 14 52 FE B7 0E FE FF 93 01 30 02 63 1C DF 11 +13 02 00 00 13 01 F0 01 B7 00 00 80 13 00 00 00 +13 00 00 00 33 DF 20 40 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E F0 FF 93 01 40 02 63 14 DF 0F +13 02 00 00 13 01 70 00 13 00 00 00 B7 00 00 80 +33 DF 20 40 13 02 12 00 93 02 20 00 E3 14 52 FE +B7 0E 00 FF 93 01 50 02 63 1E DF 0B 13 02 00 00 +13 01 E0 00 13 00 00 00 B7 00 00 80 13 00 00 00 +33 DF 20 40 13 02 12 00 93 02 20 00 E3 12 52 FE +B7 0E FE FF 93 01 60 02 63 16 DF 09 13 02 00 00 +13 01 F0 01 13 00 00 00 13 00 00 00 B7 00 00 80 +33 DF 20 40 13 02 12 00 93 02 20 00 E3 12 52 FE +93 0E F0 FF 93 01 70 02 63 1E DF 05 93 00 F0 00 +33 51 10 40 93 0E 00 00 93 01 80 02 63 14 D1 05 +93 00 00 02 33 D1 00 40 93 0E 00 02 93 01 90 02 +63 1A D1 03 B3 50 00 40 93 0E 00 00 93 01 A0 02 +63 92 D0 03 93 00 00 40 37 11 00 00 13 01 01 80 +33 D0 20 40 93 0E 00 00 93 01 B0 02 63 14 D0 01 +63 18 30 00 13 0D 10 00 93 0D 00 00 6F 00 00 00 +13 0D 10 00 93 0D 10 00 6F 00 00 00 00 00 00 00 +00 00 00 00 +@00000600 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-srai b/tests/isa/generated/rv32ui-p-srai new file mode 100644 index 0000000..2a24667 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-srai differ diff --git a/tests/isa/generated/rv32ui-p-srai.bin b/tests/isa/generated/rv32ui-p-srai.bin new file mode 100644 index 0000000..8dba9e6 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-srai.bin differ diff --git a/tests/isa/generated/rv32ui-p-srai.dump b/tests/isa/generated/rv32ui-p-srai.dump new file mode 100644 index 0000000..b4a138d --- /dev/null +++ b/tests/isa/generated/rv32ui-p-srai.dump @@ -0,0 +1,254 @@ + +generated/rv32ui-p-srai: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00000093 li ra,0 + c: 4000df13 srai t5,ra,0x0 + 10: 00000e93 li t4,0 + 14: 00200193 li gp,2 + 18: 2bdf1463 bne t5,t4,2c0 + +0000001c : + 1c: 800000b7 lui ra,0x80000 + 20: 4010df13 srai t5,ra,0x1 + 24: c0000eb7 lui t4,0xc0000 + 28: 00300193 li gp,3 + 2c: 29df1a63 bne t5,t4,2c0 + +00000030 : + 30: 800000b7 lui ra,0x80000 + 34: 4070df13 srai t5,ra,0x7 + 38: ff000eb7 lui t4,0xff000 + 3c: 00400193 li gp,4 + 40: 29df1063 bne t5,t4,2c0 + +00000044 : + 44: 800000b7 lui ra,0x80000 + 48: 40e0df13 srai t5,ra,0xe + 4c: fffe0eb7 lui t4,0xfffe0 + 50: 00500193 li gp,5 + 54: 27df1663 bne t5,t4,2c0 + +00000058 : + 58: 800000b7 lui ra,0x80000 + 5c: 00108093 addi ra,ra,1 # 80000001 + 60: 41f0df13 srai t5,ra,0x1f + 64: fff00e93 li t4,-1 + 68: 00600193 li gp,6 + 6c: 25df1a63 bne t5,t4,2c0 + +00000070 : + 70: 800000b7 lui ra,0x80000 + 74: fff08093 addi ra,ra,-1 # 7fffffff + 78: 4000df13 srai t5,ra,0x0 + 7c: 80000eb7 lui t4,0x80000 + 80: fffe8e93 addi t4,t4,-1 # 7fffffff + 84: 00700193 li gp,7 + 88: 23df1c63 bne t5,t4,2c0 + +0000008c : + 8c: 800000b7 lui ra,0x80000 + 90: fff08093 addi ra,ra,-1 # 7fffffff + 94: 4010df13 srai t5,ra,0x1 + 98: 40000eb7 lui t4,0x40000 + 9c: fffe8e93 addi t4,t4,-1 # 3fffffff + a0: 00800193 li gp,8 + a4: 21df1e63 bne t5,t4,2c0 + +000000a8 : + a8: 800000b7 lui ra,0x80000 + ac: fff08093 addi ra,ra,-1 # 7fffffff + b0: 4070df13 srai t5,ra,0x7 + b4: 01000eb7 lui t4,0x1000 + b8: fffe8e93 addi t4,t4,-1 # ffffff + bc: 00900193 li gp,9 + c0: 21df1063 bne t5,t4,2c0 + +000000c4 : + c4: 800000b7 lui ra,0x80000 + c8: fff08093 addi ra,ra,-1 # 7fffffff + cc: 40e0df13 srai t5,ra,0xe + d0: 00020eb7 lui t4,0x20 + d4: fffe8e93 addi t4,t4,-1 # 1ffff + d8: 00a00193 li gp,10 + dc: 1fdf1263 bne t5,t4,2c0 + +000000e0 : + e0: 800000b7 lui ra,0x80000 + e4: fff08093 addi ra,ra,-1 # 7fffffff + e8: 41f0df13 srai t5,ra,0x1f + ec: 00000e93 li t4,0 + f0: 00b00193 li gp,11 + f4: 1ddf1663 bne t5,t4,2c0 + +000000f8 : + f8: 818180b7 lui ra,0x81818 + fc: 18108093 addi ra,ra,385 # 81818181 + 100: 4000df13 srai t5,ra,0x0 + 104: 81818eb7 lui t4,0x81818 + 108: 181e8e93 addi t4,t4,385 # 81818181 + 10c: 00c00193 li gp,12 + 110: 1bdf1863 bne t5,t4,2c0 + +00000114 : + 114: 818180b7 lui ra,0x81818 + 118: 18108093 addi ra,ra,385 # 81818181 + 11c: 4010df13 srai t5,ra,0x1 + 120: c0c0ceb7 lui t4,0xc0c0c + 124: 0c0e8e93 addi t4,t4,192 # c0c0c0c0 + 128: 00d00193 li gp,13 + 12c: 19df1a63 bne t5,t4,2c0 + +00000130 : + 130: 818180b7 lui ra,0x81818 + 134: 18108093 addi ra,ra,385 # 81818181 + 138: 4070df13 srai t5,ra,0x7 + 13c: ff030eb7 lui t4,0xff030 + 140: 303e8e93 addi t4,t4,771 # ff030303 + 144: 00e00193 li gp,14 + 148: 17df1c63 bne t5,t4,2c0 + +0000014c : + 14c: 818180b7 lui ra,0x81818 + 150: 18108093 addi ra,ra,385 # 81818181 + 154: 40e0df13 srai t5,ra,0xe + 158: fffe0eb7 lui t4,0xfffe0 + 15c: 606e8e93 addi t4,t4,1542 # fffe0606 + 160: 00f00193 li gp,15 + 164: 15df1e63 bne t5,t4,2c0 + +00000168 : + 168: 818180b7 lui ra,0x81818 + 16c: 18108093 addi ra,ra,385 # 81818181 + 170: 41f0df13 srai t5,ra,0x1f + 174: fff00e93 li t4,-1 + 178: 01000193 li gp,16 + 17c: 15df1263 bne t5,t4,2c0 + +00000180 : + 180: 800000b7 lui ra,0x80000 + 184: 4070d093 srai ra,ra,0x7 + 188: ff000eb7 lui t4,0xff000 + 18c: 01100193 li gp,17 + 190: 13d09863 bne ra,t4,2c0 + +00000194 : + 194: 00000213 li tp,0 + 198: 800000b7 lui ra,0x80000 + 19c: 4070df13 srai t5,ra,0x7 + 1a0: 000f0313 mv t1,t5 + 1a4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1a8: 00200293 li t0,2 + 1ac: fe5216e3 bne tp,t0,198 + 1b0: ff000eb7 lui t4,0xff000 + 1b4: 01200193 li gp,18 + 1b8: 11d31463 bne t1,t4,2c0 + +000001bc : + 1bc: 00000213 li tp,0 + 1c0: 800000b7 lui ra,0x80000 + 1c4: 40e0df13 srai t5,ra,0xe + 1c8: 00000013 nop + 1cc: 000f0313 mv t1,t5 + 1d0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1d4: 00200293 li t0,2 + 1d8: fe5214e3 bne tp,t0,1c0 + 1dc: fffe0eb7 lui t4,0xfffe0 + 1e0: 01300193 li gp,19 + 1e4: 0dd31e63 bne t1,t4,2c0 + +000001e8 : + 1e8: 00000213 li tp,0 + 1ec: 800000b7 lui ra,0x80000 + 1f0: 00108093 addi ra,ra,1 # 80000001 + 1f4: 41f0df13 srai t5,ra,0x1f + 1f8: 00000013 nop + 1fc: 00000013 nop + 200: 000f0313 mv t1,t5 + 204: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 208: 00200293 li t0,2 + 20c: fe5210e3 bne tp,t0,1ec + 210: fff00e93 li t4,-1 + 214: 01400193 li gp,20 + 218: 0bd31463 bne t1,t4,2c0 + +0000021c : + 21c: 00000213 li tp,0 + 220: 800000b7 lui ra,0x80000 + 224: 4070df13 srai t5,ra,0x7 + 228: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 22c: 00200293 li t0,2 + 230: fe5218e3 bne tp,t0,220 + 234: ff000eb7 lui t4,0xff000 + 238: 01500193 li gp,21 + 23c: 09df1263 bne t5,t4,2c0 + +00000240 : + 240: 00000213 li tp,0 + 244: 800000b7 lui ra,0x80000 + 248: 00000013 nop + 24c: 40e0df13 srai t5,ra,0xe + 250: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 254: 00200293 li t0,2 + 258: fe5216e3 bne tp,t0,244 + 25c: fffe0eb7 lui t4,0xfffe0 + 260: 01600193 li gp,22 + 264: 05df1e63 bne t5,t4,2c0 + +00000268 : + 268: 00000213 li tp,0 + 26c: 800000b7 lui ra,0x80000 + 270: 00108093 addi ra,ra,1 # 80000001 + 274: 00000013 nop + 278: 00000013 nop + 27c: 41f0df13 srai t5,ra,0x1f + 280: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 284: 00200293 li t0,2 + 288: fe5212e3 bne tp,t0,26c + 28c: fff00e93 li t4,-1 + 290: 01700193 li gp,23 + 294: 03df1663 bne t5,t4,2c0 + +00000298 : + 298: 40405093 srai ra,zero,0x4 + 29c: 00000e93 li t4,0 + 2a0: 01800193 li gp,24 + 2a4: 01d09e63 bne ra,t4,2c0 + +000002a8 : + 2a8: 02100093 li ra,33 + 2ac: 40a0d013 srai zero,ra,0xa + 2b0: 00000e93 li t4,0 + 2b4: 01900193 li gp,25 + 2b8: 01d01463 bne zero,t4,2c0 + 2bc: 00301863 bne zero,gp,2cc + +000002c0 : + 2c0: 00100d13 li s10,1 + 2c4: 00000d93 li s11,0 + +000002c8 : + 2c8: 0000006f j 2c8 + +000002cc : + 2cc: 00100d13 li s10,1 + 2d0: 00100d93 li s11,1 + +000002d4 : + 2d4: 0000006f j 2d4 + ... + +Disassembly of section .tohost: + +00000340 : + ... + +00000380 : + ... diff --git a/tests/isa/generated/rv32ui-p-srai.verilog b/tests/isa/generated/rv32ui-p-srai.verilog new file mode 100644 index 0000000..59dd888 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-srai.verilog @@ -0,0 +1,56 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 00 00 13 DF 00 40 +93 0E 00 00 93 01 20 00 63 14 DF 2B B7 00 00 80 +13 DF 10 40 B7 0E 00 C0 93 01 30 00 63 1A DF 29 +B7 00 00 80 13 DF 70 40 B7 0E 00 FF 93 01 40 00 +63 10 DF 29 B7 00 00 80 13 DF E0 40 B7 0E FE FF +93 01 50 00 63 16 DF 27 B7 00 00 80 93 80 10 00 +13 DF F0 41 93 0E F0 FF 93 01 60 00 63 1A DF 25 +B7 00 00 80 93 80 F0 FF 13 DF 00 40 B7 0E 00 80 +93 8E FE FF 93 01 70 00 63 1C DF 23 B7 00 00 80 +93 80 F0 FF 13 DF 10 40 B7 0E 00 40 93 8E FE FF +93 01 80 00 63 1E DF 21 B7 00 00 80 93 80 F0 FF +13 DF 70 40 B7 0E 00 01 93 8E FE FF 93 01 90 00 +63 10 DF 21 B7 00 00 80 93 80 F0 FF 13 DF E0 40 +B7 0E 02 00 93 8E FE FF 93 01 A0 00 63 12 DF 1F +B7 00 00 80 93 80 F0 FF 13 DF F0 41 93 0E 00 00 +93 01 B0 00 63 16 DF 1D B7 80 81 81 93 80 10 18 +13 DF 00 40 B7 8E 81 81 93 8E 1E 18 93 01 C0 00 +63 18 DF 1B B7 80 81 81 93 80 10 18 13 DF 10 40 +B7 CE C0 C0 93 8E 0E 0C 93 01 D0 00 63 1A DF 19 +B7 80 81 81 93 80 10 18 13 DF 70 40 B7 0E 03 FF +93 8E 3E 30 93 01 E0 00 63 1C DF 17 B7 80 81 81 +93 80 10 18 13 DF E0 40 B7 0E FE FF 93 8E 6E 60 +93 01 F0 00 63 1E DF 15 B7 80 81 81 93 80 10 18 +13 DF F0 41 93 0E F0 FF 93 01 00 01 63 12 DF 15 +B7 00 00 80 93 D0 70 40 B7 0E 00 FF 93 01 10 01 +63 98 D0 13 13 02 00 00 B7 00 00 80 13 DF 70 40 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 16 52 FE +B7 0E 00 FF 93 01 20 01 63 14 D3 11 13 02 00 00 +B7 00 00 80 13 DF E0 40 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 14 52 FE B7 0E FE FF +93 01 30 01 63 1E D3 0D 13 02 00 00 B7 00 00 80 +93 80 10 00 13 DF F0 41 13 00 00 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE +93 0E F0 FF 93 01 40 01 63 14 D3 0B 13 02 00 00 +B7 00 00 80 13 DF 70 40 13 02 12 00 93 02 20 00 +E3 18 52 FE B7 0E 00 FF 93 01 50 01 63 12 DF 09 +13 02 00 00 B7 00 00 80 13 00 00 00 13 DF E0 40 +13 02 12 00 93 02 20 00 E3 16 52 FE B7 0E FE FF +93 01 60 01 63 1E DF 05 13 02 00 00 B7 00 00 80 +93 80 10 00 13 00 00 00 13 00 00 00 13 DF F0 41 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E F0 FF +93 01 70 01 63 16 DF 03 93 50 40 40 93 0E 00 00 +93 01 80 01 63 9E D0 01 93 00 10 02 13 D0 A0 40 +93 0E 00 00 93 01 90 01 63 14 D0 01 63 18 30 00 +13 0D 10 00 93 0D 00 00 6F 00 00 00 13 0D 10 00 +93 0D 10 00 6F 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000340 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-srl b/tests/isa/generated/rv32ui-p-srl new file mode 100644 index 0000000..886aac3 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-srl differ diff --git a/tests/isa/generated/rv32ui-p-srl.bin b/tests/isa/generated/rv32ui-p-srl.bin new file mode 100644 index 0000000..a2bd30b Binary files /dev/null and b/tests/isa/generated/rv32ui-p-srl.bin differ diff --git a/tests/isa/generated/rv32ui-p-srl.dump b/tests/isa/generated/rv32ui-p-srl.dump new file mode 100644 index 0000000..42fb494 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-srl.dump @@ -0,0 +1,469 @@ + +generated/rv32ui-p-srl: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 800000b7 lui ra,0x80000 + c: 00000113 li sp,0 + 10: 0020df33 srl t5,ra,sp + 14: 80000eb7 lui t4,0x80000 + 18: 00200193 li gp,2 + 1c: 57df1863 bne t5,t4,58c + +00000020 : + 20: 800000b7 lui ra,0x80000 + 24: 00100113 li sp,1 + 28: 0020df33 srl t5,ra,sp + 2c: 40000eb7 lui t4,0x40000 + 30: 00300193 li gp,3 + 34: 55df1c63 bne t5,t4,58c + +00000038 : + 38: 800000b7 lui ra,0x80000 + 3c: 00700113 li sp,7 + 40: 0020df33 srl t5,ra,sp + 44: 01000eb7 lui t4,0x1000 + 48: 00400193 li gp,4 + 4c: 55df1063 bne t5,t4,58c + +00000050 : + 50: 800000b7 lui ra,0x80000 + 54: 00e00113 li sp,14 + 58: 0020df33 srl t5,ra,sp + 5c: 00020eb7 lui t4,0x20 + 60: 00500193 li gp,5 + 64: 53df1463 bne t5,t4,58c + +00000068 : + 68: 800000b7 lui ra,0x80000 + 6c: 00108093 addi ra,ra,1 # 80000001 + 70: 01f00113 li sp,31 + 74: 0020df33 srl t5,ra,sp + 78: 00100e93 li t4,1 + 7c: 00600193 li gp,6 + 80: 51df1663 bne t5,t4,58c + +00000084 : + 84: fff00093 li ra,-1 + 88: 00000113 li sp,0 + 8c: 0020df33 srl t5,ra,sp + 90: fff00e93 li t4,-1 + 94: 00700193 li gp,7 + 98: 4fdf1a63 bne t5,t4,58c + +0000009c : + 9c: fff00093 li ra,-1 + a0: 00100113 li sp,1 + a4: 0020df33 srl t5,ra,sp + a8: 80000eb7 lui t4,0x80000 + ac: fffe8e93 addi t4,t4,-1 # 7fffffff + b0: 00800193 li gp,8 + b4: 4ddf1c63 bne t5,t4,58c + +000000b8 : + b8: fff00093 li ra,-1 + bc: 00700113 li sp,7 + c0: 0020df33 srl t5,ra,sp + c4: 02000eb7 lui t4,0x2000 + c8: fffe8e93 addi t4,t4,-1 # 1ffffff + cc: 00900193 li gp,9 + d0: 4bdf1e63 bne t5,t4,58c + +000000d4 : + d4: fff00093 li ra,-1 + d8: 00e00113 li sp,14 + dc: 0020df33 srl t5,ra,sp + e0: 00040eb7 lui t4,0x40 + e4: fffe8e93 addi t4,t4,-1 # 3ffff + e8: 00a00193 li gp,10 + ec: 4bdf1063 bne t5,t4,58c + +000000f0 : + f0: fff00093 li ra,-1 + f4: 01f00113 li sp,31 + f8: 0020df33 srl t5,ra,sp + fc: 00100e93 li t4,1 + 100: 00b00193 li gp,11 + 104: 49df1463 bne t5,t4,58c + +00000108 : + 108: 212120b7 lui ra,0x21212 + 10c: 12108093 addi ra,ra,289 # 21212121 + 110: 00000113 li sp,0 + 114: 0020df33 srl t5,ra,sp + 118: 21212eb7 lui t4,0x21212 + 11c: 121e8e93 addi t4,t4,289 # 21212121 + 120: 00c00193 li gp,12 + 124: 47df1463 bne t5,t4,58c + +00000128 : + 128: 212120b7 lui ra,0x21212 + 12c: 12108093 addi ra,ra,289 # 21212121 + 130: 00100113 li sp,1 + 134: 0020df33 srl t5,ra,sp + 138: 10909eb7 lui t4,0x10909 + 13c: 090e8e93 addi t4,t4,144 # 10909090 + 140: 00d00193 li gp,13 + 144: 45df1463 bne t5,t4,58c + +00000148 : + 148: 212120b7 lui ra,0x21212 + 14c: 12108093 addi ra,ra,289 # 21212121 + 150: 00700113 li sp,7 + 154: 0020df33 srl t5,ra,sp + 158: 00424eb7 lui t4,0x424 + 15c: 242e8e93 addi t4,t4,578 # 424242 + 160: 00e00193 li gp,14 + 164: 43df1463 bne t5,t4,58c + +00000168 : + 168: 212120b7 lui ra,0x21212 + 16c: 12108093 addi ra,ra,289 # 21212121 + 170: 00e00113 li sp,14 + 174: 0020df33 srl t5,ra,sp + 178: 00008eb7 lui t4,0x8 + 17c: 484e8e93 addi t4,t4,1156 # 8484 + 180: 00f00193 li gp,15 + 184: 41df1463 bne t5,t4,58c + +00000188 : + 188: 212120b7 lui ra,0x21212 + 18c: 12108093 addi ra,ra,289 # 21212121 + 190: 01f00113 li sp,31 + 194: 0020df33 srl t5,ra,sp + 198: 00000e93 li t4,0 + 19c: 01000193 li gp,16 + 1a0: 3fdf1663 bne t5,t4,58c + +000001a4 : + 1a4: 212120b7 lui ra,0x21212 + 1a8: 12108093 addi ra,ra,289 # 21212121 + 1ac: fc000113 li sp,-64 + 1b0: 0020df33 srl t5,ra,sp + 1b4: 21212eb7 lui t4,0x21212 + 1b8: 121e8e93 addi t4,t4,289 # 21212121 + 1bc: 01100193 li gp,17 + 1c0: 3ddf1663 bne t5,t4,58c + +000001c4 : + 1c4: 212120b7 lui ra,0x21212 + 1c8: 12108093 addi ra,ra,289 # 21212121 + 1cc: fc100113 li sp,-63 + 1d0: 0020df33 srl t5,ra,sp + 1d4: 10909eb7 lui t4,0x10909 + 1d8: 090e8e93 addi t4,t4,144 # 10909090 + 1dc: 01200193 li gp,18 + 1e0: 3bdf1663 bne t5,t4,58c + +000001e4 : + 1e4: 212120b7 lui ra,0x21212 + 1e8: 12108093 addi ra,ra,289 # 21212121 + 1ec: fc700113 li sp,-57 + 1f0: 0020df33 srl t5,ra,sp + 1f4: 00424eb7 lui t4,0x424 + 1f8: 242e8e93 addi t4,t4,578 # 424242 + 1fc: 01300193 li gp,19 + 200: 39df1663 bne t5,t4,58c + +00000204 : + 204: 212120b7 lui ra,0x21212 + 208: 12108093 addi ra,ra,289 # 21212121 + 20c: fce00113 li sp,-50 + 210: 0020df33 srl t5,ra,sp + 214: 00008eb7 lui t4,0x8 + 218: 484e8e93 addi t4,t4,1156 # 8484 + 21c: 01400193 li gp,20 + 220: 37df1663 bne t5,t4,58c + +00000224 : + 224: 212120b7 lui ra,0x21212 + 228: 12108093 addi ra,ra,289 # 21212121 + 22c: fff00113 li sp,-1 + 230: 0020df33 srl t5,ra,sp + 234: 00000e93 li t4,0 + 238: 01500193 li gp,21 + 23c: 35df1863 bne t5,t4,58c + +00000240 : + 240: 800000b7 lui ra,0x80000 + 244: 00700113 li sp,7 + 248: 0020d0b3 srl ra,ra,sp + 24c: 01000eb7 lui t4,0x1000 + 250: 01600193 li gp,22 + 254: 33d09c63 bne ra,t4,58c + +00000258 : + 258: 800000b7 lui ra,0x80000 + 25c: 00e00113 li sp,14 + 260: 0020d133 srl sp,ra,sp + 264: 00020eb7 lui t4,0x20 + 268: 01700193 li gp,23 + 26c: 33d11063 bne sp,t4,58c + +00000270 : + 270: 00700093 li ra,7 + 274: 0010d0b3 srl ra,ra,ra + 278: 00000e93 li t4,0 + 27c: 01800193 li gp,24 + 280: 31d09663 bne ra,t4,58c + +00000284 : + 284: 00000213 li tp,0 + 288: 800000b7 lui ra,0x80000 + 28c: 00700113 li sp,7 + 290: 0020df33 srl t5,ra,sp + 294: 000f0313 mv t1,t5 + 298: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 29c: 00200293 li t0,2 + 2a0: fe5214e3 bne tp,t0,288 + 2a4: 01000eb7 lui t4,0x1000 + 2a8: 01900193 li gp,25 + 2ac: 2fd31063 bne t1,t4,58c + +000002b0 : + 2b0: 00000213 li tp,0 + 2b4: 800000b7 lui ra,0x80000 + 2b8: 00e00113 li sp,14 + 2bc: 0020df33 srl t5,ra,sp + 2c0: 00000013 nop + 2c4: 000f0313 mv t1,t5 + 2c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2cc: 00200293 li t0,2 + 2d0: fe5212e3 bne tp,t0,2b4 + 2d4: 00020eb7 lui t4,0x20 + 2d8: 01a00193 li gp,26 + 2dc: 2bd31863 bne t1,t4,58c + +000002e0 : + 2e0: 00000213 li tp,0 + 2e4: 800000b7 lui ra,0x80000 + 2e8: 01f00113 li sp,31 + 2ec: 0020df33 srl t5,ra,sp + 2f0: 00000013 nop + 2f4: 00000013 nop + 2f8: 000f0313 mv t1,t5 + 2fc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 300: 00200293 li t0,2 + 304: fe5210e3 bne tp,t0,2e4 + 308: 00100e93 li t4,1 + 30c: 01b00193 li gp,27 + 310: 27d31e63 bne t1,t4,58c + +00000314 : + 314: 00000213 li tp,0 + 318: 800000b7 lui ra,0x80000 + 31c: 00700113 li sp,7 + 320: 0020df33 srl t5,ra,sp + 324: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 328: 00200293 li t0,2 + 32c: fe5216e3 bne tp,t0,318 + 330: 01000eb7 lui t4,0x1000 + 334: 01c00193 li gp,28 + 338: 25df1a63 bne t5,t4,58c + +0000033c : + 33c: 00000213 li tp,0 + 340: 800000b7 lui ra,0x80000 + 344: 00e00113 li sp,14 + 348: 00000013 nop + 34c: 0020df33 srl t5,ra,sp + 350: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 354: 00200293 li t0,2 + 358: fe5214e3 bne tp,t0,340 + 35c: 00020eb7 lui t4,0x20 + 360: 01d00193 li gp,29 + 364: 23df1463 bne t5,t4,58c + +00000368 : + 368: 00000213 li tp,0 + 36c: 800000b7 lui ra,0x80000 + 370: 01f00113 li sp,31 + 374: 00000013 nop + 378: 00000013 nop + 37c: 0020df33 srl t5,ra,sp + 380: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 384: 00200293 li t0,2 + 388: fe5212e3 bne tp,t0,36c + 38c: 00100e93 li t4,1 + 390: 01e00193 li gp,30 + 394: 1fdf1c63 bne t5,t4,58c + +00000398 : + 398: 00000213 li tp,0 + 39c: 800000b7 lui ra,0x80000 + 3a0: 00000013 nop + 3a4: 00700113 li sp,7 + 3a8: 0020df33 srl t5,ra,sp + 3ac: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3b0: 00200293 li t0,2 + 3b4: fe5214e3 bne tp,t0,39c + 3b8: 01000eb7 lui t4,0x1000 + 3bc: 01f00193 li gp,31 + 3c0: 1ddf1663 bne t5,t4,58c + +000003c4 : + 3c4: 00000213 li tp,0 + 3c8: 800000b7 lui ra,0x80000 + 3cc: 00000013 nop + 3d0: 00e00113 li sp,14 + 3d4: 00000013 nop + 3d8: 0020df33 srl t5,ra,sp + 3dc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3e0: 00200293 li t0,2 + 3e4: fe5212e3 bne tp,t0,3c8 + 3e8: 00020eb7 lui t4,0x20 + 3ec: 02000193 li gp,32 + 3f0: 19df1e63 bne t5,t4,58c + +000003f4 : + 3f4: 00000213 li tp,0 + 3f8: 800000b7 lui ra,0x80000 + 3fc: 00000013 nop + 400: 00000013 nop + 404: 01f00113 li sp,31 + 408: 0020df33 srl t5,ra,sp + 40c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 410: 00200293 li t0,2 + 414: fe5212e3 bne tp,t0,3f8 + 418: 00100e93 li t4,1 + 41c: 02100193 li gp,33 + 420: 17df1663 bne t5,t4,58c + +00000424 : + 424: 00000213 li tp,0 + 428: 00700113 li sp,7 + 42c: 800000b7 lui ra,0x80000 + 430: 0020df33 srl t5,ra,sp + 434: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 438: 00200293 li t0,2 + 43c: fe5216e3 bne tp,t0,428 + 440: 01000eb7 lui t4,0x1000 + 444: 02200193 li gp,34 + 448: 15df1263 bne t5,t4,58c + +0000044c : + 44c: 00000213 li tp,0 + 450: 00e00113 li sp,14 + 454: 800000b7 lui ra,0x80000 + 458: 00000013 nop + 45c: 0020df33 srl t5,ra,sp + 460: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 464: 00200293 li t0,2 + 468: fe5214e3 bne tp,t0,450 + 46c: 00020eb7 lui t4,0x20 + 470: 02300193 li gp,35 + 474: 11df1c63 bne t5,t4,58c + +00000478 : + 478: 00000213 li tp,0 + 47c: 01f00113 li sp,31 + 480: 800000b7 lui ra,0x80000 + 484: 00000013 nop + 488: 00000013 nop + 48c: 0020df33 srl t5,ra,sp + 490: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 494: 00200293 li t0,2 + 498: fe5212e3 bne tp,t0,47c + 49c: 00100e93 li t4,1 + 4a0: 02400193 li gp,36 + 4a4: 0fdf1463 bne t5,t4,58c + +000004a8 : + 4a8: 00000213 li tp,0 + 4ac: 00700113 li sp,7 + 4b0: 00000013 nop + 4b4: 800000b7 lui ra,0x80000 + 4b8: 0020df33 srl t5,ra,sp + 4bc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 4c0: 00200293 li t0,2 + 4c4: fe5214e3 bne tp,t0,4ac + 4c8: 01000eb7 lui t4,0x1000 + 4cc: 02500193 li gp,37 + 4d0: 0bdf1e63 bne t5,t4,58c + +000004d4 : + 4d4: 00000213 li tp,0 + 4d8: 00e00113 li sp,14 + 4dc: 00000013 nop + 4e0: 800000b7 lui ra,0x80000 + 4e4: 00000013 nop + 4e8: 0020df33 srl t5,ra,sp + 4ec: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 4f0: 00200293 li t0,2 + 4f4: fe5212e3 bne tp,t0,4d8 + 4f8: 00020eb7 lui t4,0x20 + 4fc: 02600193 li gp,38 + 500: 09df1663 bne t5,t4,58c + +00000504 : + 504: 00000213 li tp,0 + 508: 01f00113 li sp,31 + 50c: 00000013 nop + 510: 00000013 nop + 514: 800000b7 lui ra,0x80000 + 518: 0020df33 srl t5,ra,sp + 51c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 520: 00200293 li t0,2 + 524: fe5212e3 bne tp,t0,508 + 528: 00100e93 li t4,1 + 52c: 02700193 li gp,39 + 530: 05df1e63 bne t5,t4,58c + +00000534 : + 534: 00f00093 li ra,15 + 538: 00105133 srl sp,zero,ra + 53c: 00000e93 li t4,0 + 540: 02800193 li gp,40 + 544: 05d11463 bne sp,t4,58c + +00000548 : + 548: 02000093 li ra,32 + 54c: 0000d133 srl sp,ra,zero + 550: 02000e93 li t4,32 + 554: 02900193 li gp,41 + 558: 03d11a63 bne sp,t4,58c + +0000055c : + 55c: 000050b3 srl ra,zero,zero + 560: 00000e93 li t4,0 + 564: 02a00193 li gp,42 + 568: 03d09263 bne ra,t4,58c + +0000056c : + 56c: 40000093 li ra,1024 + 570: 00001137 lui sp,0x1 + 574: 80010113 addi sp,sp,-2048 # 800 <_end+0x1b8> + 578: 0020d033 srl zero,ra,sp + 57c: 00000e93 li t4,0 + 580: 02b00193 li gp,43 + 584: 01d01463 bne zero,t4,58c + 588: 00301863 bne zero,gp,598 + +0000058c : + 58c: 00100d13 li s10,1 + 590: 00000d93 li s11,0 + +00000594 : + 594: 0000006f j 594 + +00000598 : + 598: 00100d13 li s10,1 + 59c: 00100d93 li s11,1 + +000005a0 : + 5a0: 0000006f j 5a0 + ... + +Disassembly of section .tohost: + +00000600 : + ... + +00000640 : + ... diff --git a/tests/isa/generated/rv32ui-p-srl.verilog b/tests/isa/generated/rv32ui-p-srl.verilog new file mode 100644 index 0000000..8d60c38 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-srl.verilog @@ -0,0 +1,100 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 00 00 80 13 01 00 00 +33 DF 20 00 B7 0E 00 80 93 01 20 00 63 18 DF 57 +B7 00 00 80 13 01 10 00 33 DF 20 00 B7 0E 00 40 +93 01 30 00 63 1C DF 55 B7 00 00 80 13 01 70 00 +33 DF 20 00 B7 0E 00 01 93 01 40 00 63 10 DF 55 +B7 00 00 80 13 01 E0 00 33 DF 20 00 B7 0E 02 00 +93 01 50 00 63 14 DF 53 B7 00 00 80 93 80 10 00 +13 01 F0 01 33 DF 20 00 93 0E 10 00 93 01 60 00 +63 16 DF 51 93 00 F0 FF 13 01 00 00 33 DF 20 00 +93 0E F0 FF 93 01 70 00 63 1A DF 4F 93 00 F0 FF +13 01 10 00 33 DF 20 00 B7 0E 00 80 93 8E FE FF +93 01 80 00 63 1C DF 4D 93 00 F0 FF 13 01 70 00 +33 DF 20 00 B7 0E 00 02 93 8E FE FF 93 01 90 00 +63 1E DF 4B 93 00 F0 FF 13 01 E0 00 33 DF 20 00 +B7 0E 04 00 93 8E FE FF 93 01 A0 00 63 10 DF 4B +93 00 F0 FF 13 01 F0 01 33 DF 20 00 93 0E 10 00 +93 01 B0 00 63 14 DF 49 B7 20 21 21 93 80 10 12 +13 01 00 00 33 DF 20 00 B7 2E 21 21 93 8E 1E 12 +93 01 C0 00 63 14 DF 47 B7 20 21 21 93 80 10 12 +13 01 10 00 33 DF 20 00 B7 9E 90 10 93 8E 0E 09 +93 01 D0 00 63 14 DF 45 B7 20 21 21 93 80 10 12 +13 01 70 00 33 DF 20 00 B7 4E 42 00 93 8E 2E 24 +93 01 E0 00 63 14 DF 43 B7 20 21 21 93 80 10 12 +13 01 E0 00 33 DF 20 00 B7 8E 00 00 93 8E 4E 48 +93 01 F0 00 63 14 DF 41 B7 20 21 21 93 80 10 12 +13 01 F0 01 33 DF 20 00 93 0E 00 00 93 01 00 01 +63 16 DF 3F B7 20 21 21 93 80 10 12 13 01 00 FC +33 DF 20 00 B7 2E 21 21 93 8E 1E 12 93 01 10 01 +63 16 DF 3D B7 20 21 21 93 80 10 12 13 01 10 FC +33 DF 20 00 B7 9E 90 10 93 8E 0E 09 93 01 20 01 +63 16 DF 3B B7 20 21 21 93 80 10 12 13 01 70 FC +33 DF 20 00 B7 4E 42 00 93 8E 2E 24 93 01 30 01 +63 16 DF 39 B7 20 21 21 93 80 10 12 13 01 E0 FC +33 DF 20 00 B7 8E 00 00 93 8E 4E 48 93 01 40 01 +63 16 DF 37 B7 20 21 21 93 80 10 12 13 01 F0 FF +33 DF 20 00 93 0E 00 00 93 01 50 01 63 18 DF 35 +B7 00 00 80 13 01 70 00 B3 D0 20 00 B7 0E 00 01 +93 01 60 01 63 9C D0 33 B7 00 00 80 13 01 E0 00 +33 D1 20 00 B7 0E 02 00 93 01 70 01 63 10 D1 33 +93 00 70 00 B3 D0 10 00 93 0E 00 00 93 01 80 01 +63 96 D0 31 13 02 00 00 B7 00 00 80 13 01 70 00 +33 DF 20 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 14 52 FE B7 0E 00 01 93 01 90 01 63 10 D3 2F +13 02 00 00 B7 00 00 80 13 01 E0 00 33 DF 20 00 +13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 12 52 FE B7 0E 02 00 93 01 A0 01 63 18 D3 2B +13 02 00 00 B7 00 00 80 13 01 F0 01 33 DF 20 00 +13 00 00 00 13 00 00 00 13 03 0F 00 13 02 12 00 +93 02 20 00 E3 10 52 FE 93 0E 10 00 93 01 B0 01 +63 1E D3 27 13 02 00 00 B7 00 00 80 13 01 70 00 +33 DF 20 00 13 02 12 00 93 02 20 00 E3 16 52 FE +B7 0E 00 01 93 01 C0 01 63 1A DF 25 13 02 00 00 +B7 00 00 80 13 01 E0 00 13 00 00 00 33 DF 20 00 +13 02 12 00 93 02 20 00 E3 14 52 FE B7 0E 02 00 +93 01 D0 01 63 14 DF 23 13 02 00 00 B7 00 00 80 +13 01 F0 01 13 00 00 00 13 00 00 00 33 DF 20 00 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 10 00 +93 01 E0 01 63 1C DF 1F 13 02 00 00 B7 00 00 80 +13 00 00 00 13 01 70 00 33 DF 20 00 13 02 12 00 +93 02 20 00 E3 14 52 FE B7 0E 00 01 93 01 F0 01 +63 16 DF 1D 13 02 00 00 B7 00 00 80 13 00 00 00 +13 01 E0 00 13 00 00 00 33 DF 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE B7 0E 02 00 93 01 00 02 +63 1E DF 19 13 02 00 00 B7 00 00 80 13 00 00 00 +13 00 00 00 13 01 F0 01 33 DF 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E 10 00 93 01 10 02 +63 16 DF 17 13 02 00 00 13 01 70 00 B7 00 00 80 +33 DF 20 00 13 02 12 00 93 02 20 00 E3 16 52 FE +B7 0E 00 01 93 01 20 02 63 12 DF 15 13 02 00 00 +13 01 E0 00 B7 00 00 80 13 00 00 00 33 DF 20 00 +13 02 12 00 93 02 20 00 E3 14 52 FE B7 0E 02 00 +93 01 30 02 63 1C DF 11 13 02 00 00 13 01 F0 01 +B7 00 00 80 13 00 00 00 13 00 00 00 33 DF 20 00 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 10 00 +93 01 40 02 63 14 DF 0F 13 02 00 00 13 01 70 00 +13 00 00 00 B7 00 00 80 33 DF 20 00 13 02 12 00 +93 02 20 00 E3 14 52 FE B7 0E 00 01 93 01 50 02 +63 1E DF 0B 13 02 00 00 13 01 E0 00 13 00 00 00 +B7 00 00 80 13 00 00 00 33 DF 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE B7 0E 02 00 93 01 60 02 +63 16 DF 09 13 02 00 00 13 01 F0 01 13 00 00 00 +13 00 00 00 B7 00 00 80 33 DF 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E 10 00 93 01 70 02 +63 1E DF 05 93 00 F0 00 33 51 10 00 93 0E 00 00 +93 01 80 02 63 14 D1 05 93 00 00 02 33 D1 00 00 +93 0E 00 02 93 01 90 02 63 1A D1 03 B3 50 00 00 +93 0E 00 00 93 01 A0 02 63 92 D0 03 93 00 00 40 +37 11 00 00 13 01 01 80 33 D0 20 00 93 0E 00 00 +93 01 B0 02 63 14 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000600 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-srli b/tests/isa/generated/rv32ui-p-srli new file mode 100644 index 0000000..6a59f97 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-srli differ diff --git a/tests/isa/generated/rv32ui-p-srli.bin b/tests/isa/generated/rv32ui-p-srli.bin new file mode 100644 index 0000000..03d976d Binary files /dev/null and b/tests/isa/generated/rv32ui-p-srli.bin differ diff --git a/tests/isa/generated/rv32ui-p-srli.dump b/tests/isa/generated/rv32ui-p-srli.dump new file mode 100644 index 0000000..06328a8 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-srli.dump @@ -0,0 +1,249 @@ + +generated/rv32ui-p-srli: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 800000b7 lui ra,0x80000 + c: 0000df13 srli t5,ra,0x0 + 10: 80000eb7 lui t4,0x80000 + 14: 00200193 li gp,2 + 18: 29df1863 bne t5,t4,2a8 + +0000001c : + 1c: 800000b7 lui ra,0x80000 + 20: 0010df13 srli t5,ra,0x1 + 24: 40000eb7 lui t4,0x40000 + 28: 00300193 li gp,3 + 2c: 27df1e63 bne t5,t4,2a8 + +00000030 : + 30: 800000b7 lui ra,0x80000 + 34: 0070df13 srli t5,ra,0x7 + 38: 01000eb7 lui t4,0x1000 + 3c: 00400193 li gp,4 + 40: 27df1463 bne t5,t4,2a8 + +00000044 : + 44: 800000b7 lui ra,0x80000 + 48: 00e0df13 srli t5,ra,0xe + 4c: 00020eb7 lui t4,0x20 + 50: 00500193 li gp,5 + 54: 25df1a63 bne t5,t4,2a8 + +00000058 : + 58: 800000b7 lui ra,0x80000 + 5c: 00108093 addi ra,ra,1 # 80000001 + 60: 01f0df13 srli t5,ra,0x1f + 64: 00100e93 li t4,1 + 68: 00600193 li gp,6 + 6c: 23df1e63 bne t5,t4,2a8 + +00000070 : + 70: fff00093 li ra,-1 + 74: 0000df13 srli t5,ra,0x0 + 78: fff00e93 li t4,-1 + 7c: 00700193 li gp,7 + 80: 23df1463 bne t5,t4,2a8 + +00000084 : + 84: fff00093 li ra,-1 + 88: 0010df13 srli t5,ra,0x1 + 8c: 80000eb7 lui t4,0x80000 + 90: fffe8e93 addi t4,t4,-1 # 7fffffff + 94: 00800193 li gp,8 + 98: 21df1863 bne t5,t4,2a8 + +0000009c : + 9c: fff00093 li ra,-1 + a0: 0070df13 srli t5,ra,0x7 + a4: 02000eb7 lui t4,0x2000 + a8: fffe8e93 addi t4,t4,-1 # 1ffffff + ac: 00900193 li gp,9 + b0: 1fdf1c63 bne t5,t4,2a8 + +000000b4 : + b4: fff00093 li ra,-1 + b8: 00e0df13 srli t5,ra,0xe + bc: 00040eb7 lui t4,0x40 + c0: fffe8e93 addi t4,t4,-1 # 3ffff + c4: 00a00193 li gp,10 + c8: 1fdf1063 bne t5,t4,2a8 + +000000cc : + cc: fff00093 li ra,-1 + d0: 01f0df13 srli t5,ra,0x1f + d4: 00100e93 li t4,1 + d8: 00b00193 li gp,11 + dc: 1ddf1663 bne t5,t4,2a8 + +000000e0 : + e0: 212120b7 lui ra,0x21212 + e4: 12108093 addi ra,ra,289 # 21212121 + e8: 0000df13 srli t5,ra,0x0 + ec: 21212eb7 lui t4,0x21212 + f0: 121e8e93 addi t4,t4,289 # 21212121 + f4: 00c00193 li gp,12 + f8: 1bdf1863 bne t5,t4,2a8 + +000000fc : + fc: 212120b7 lui ra,0x21212 + 100: 12108093 addi ra,ra,289 # 21212121 + 104: 0010df13 srli t5,ra,0x1 + 108: 10909eb7 lui t4,0x10909 + 10c: 090e8e93 addi t4,t4,144 # 10909090 + 110: 00d00193 li gp,13 + 114: 19df1a63 bne t5,t4,2a8 + +00000118 : + 118: 212120b7 lui ra,0x21212 + 11c: 12108093 addi ra,ra,289 # 21212121 + 120: 0070df13 srli t5,ra,0x7 + 124: 00424eb7 lui t4,0x424 + 128: 242e8e93 addi t4,t4,578 # 424242 + 12c: 00e00193 li gp,14 + 130: 17df1c63 bne t5,t4,2a8 + +00000134 : + 134: 212120b7 lui ra,0x21212 + 138: 12108093 addi ra,ra,289 # 21212121 + 13c: 00e0df13 srli t5,ra,0xe + 140: 00008eb7 lui t4,0x8 + 144: 484e8e93 addi t4,t4,1156 # 8484 + 148: 00f00193 li gp,15 + 14c: 15df1e63 bne t5,t4,2a8 + +00000150 : + 150: 212120b7 lui ra,0x21212 + 154: 12108093 addi ra,ra,289 # 21212121 + 158: 01f0df13 srli t5,ra,0x1f + 15c: 00000e93 li t4,0 + 160: 01000193 li gp,16 + 164: 15df1263 bne t5,t4,2a8 + +00000168 : + 168: 800000b7 lui ra,0x80000 + 16c: 0070d093 srli ra,ra,0x7 + 170: 01000eb7 lui t4,0x1000 + 174: 01100193 li gp,17 + 178: 13d09863 bne ra,t4,2a8 + +0000017c : + 17c: 00000213 li tp,0 + 180: 800000b7 lui ra,0x80000 + 184: 0070df13 srli t5,ra,0x7 + 188: 000f0313 mv t1,t5 + 18c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 190: 00200293 li t0,2 + 194: fe5216e3 bne tp,t0,180 + 198: 01000eb7 lui t4,0x1000 + 19c: 01200193 li gp,18 + 1a0: 11d31463 bne t1,t4,2a8 + +000001a4 : + 1a4: 00000213 li tp,0 + 1a8: 800000b7 lui ra,0x80000 + 1ac: 00e0df13 srli t5,ra,0xe + 1b0: 00000013 nop + 1b4: 000f0313 mv t1,t5 + 1b8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1bc: 00200293 li t0,2 + 1c0: fe5214e3 bne tp,t0,1a8 + 1c4: 00020eb7 lui t4,0x20 + 1c8: 01300193 li gp,19 + 1cc: 0dd31e63 bne t1,t4,2a8 + +000001d0 : + 1d0: 00000213 li tp,0 + 1d4: 800000b7 lui ra,0x80000 + 1d8: 00108093 addi ra,ra,1 # 80000001 + 1dc: 01f0df13 srli t5,ra,0x1f + 1e0: 00000013 nop + 1e4: 00000013 nop + 1e8: 000f0313 mv t1,t5 + 1ec: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1f0: 00200293 li t0,2 + 1f4: fe5210e3 bne tp,t0,1d4 + 1f8: 00100e93 li t4,1 + 1fc: 01400193 li gp,20 + 200: 0bd31463 bne t1,t4,2a8 + +00000204 : + 204: 00000213 li tp,0 + 208: 800000b7 lui ra,0x80000 + 20c: 0070df13 srli t5,ra,0x7 + 210: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 214: 00200293 li t0,2 + 218: fe5218e3 bne tp,t0,208 + 21c: 01000eb7 lui t4,0x1000 + 220: 01500193 li gp,21 + 224: 09df1263 bne t5,t4,2a8 + +00000228 : + 228: 00000213 li tp,0 + 22c: 800000b7 lui ra,0x80000 + 230: 00000013 nop + 234: 00e0df13 srli t5,ra,0xe + 238: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 23c: 00200293 li t0,2 + 240: fe5216e3 bne tp,t0,22c + 244: 00020eb7 lui t4,0x20 + 248: 01600193 li gp,22 + 24c: 05df1e63 bne t5,t4,2a8 + +00000250 : + 250: 00000213 li tp,0 + 254: 800000b7 lui ra,0x80000 + 258: 00108093 addi ra,ra,1 # 80000001 + 25c: 00000013 nop + 260: 00000013 nop + 264: 01f0df13 srli t5,ra,0x1f + 268: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 26c: 00200293 li t0,2 + 270: fe5212e3 bne tp,t0,254 + 274: 00100e93 li t4,1 + 278: 01700193 li gp,23 + 27c: 03df1663 bne t5,t4,2a8 + +00000280 : + 280: 00405093 srli ra,zero,0x4 + 284: 00000e93 li t4,0 + 288: 01800193 li gp,24 + 28c: 01d09e63 bne ra,t4,2a8 + +00000290 : + 290: 02100093 li ra,33 + 294: 00a0d013 srli zero,ra,0xa + 298: 00000e93 li t4,0 + 29c: 01900193 li gp,25 + 2a0: 01d01463 bne zero,t4,2a8 + 2a4: 00301863 bne zero,gp,2b4 + +000002a8 : + 2a8: 00100d13 li s10,1 + 2ac: 00000d93 li s11,0 + +000002b0 : + 2b0: 0000006f j 2b0 + +000002b4 : + 2b4: 00100d13 li s10,1 + 2b8: 00100d93 li s11,1 + +000002bc : + 2bc: 0000006f j 2bc + 2c0: 0000 unimp + ... + +Disassembly of section .tohost: + +00000300 : + ... + +00000340 : + ... diff --git a/tests/isa/generated/rv32ui-p-srli.verilog b/tests/isa/generated/rv32ui-p-srli.verilog new file mode 100644 index 0000000..9558f1d --- /dev/null +++ b/tests/isa/generated/rv32ui-p-srli.verilog @@ -0,0 +1,52 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 00 00 80 13 DF 00 00 +B7 0E 00 80 93 01 20 00 63 18 DF 29 B7 00 00 80 +13 DF 10 00 B7 0E 00 40 93 01 30 00 63 1E DF 27 +B7 00 00 80 13 DF 70 00 B7 0E 00 01 93 01 40 00 +63 14 DF 27 B7 00 00 80 13 DF E0 00 B7 0E 02 00 +93 01 50 00 63 1A DF 25 B7 00 00 80 93 80 10 00 +13 DF F0 01 93 0E 10 00 93 01 60 00 63 1E DF 23 +93 00 F0 FF 13 DF 00 00 93 0E F0 FF 93 01 70 00 +63 14 DF 23 93 00 F0 FF 13 DF 10 00 B7 0E 00 80 +93 8E FE FF 93 01 80 00 63 18 DF 21 93 00 F0 FF +13 DF 70 00 B7 0E 00 02 93 8E FE FF 93 01 90 00 +63 1C DF 1F 93 00 F0 FF 13 DF E0 00 B7 0E 04 00 +93 8E FE FF 93 01 A0 00 63 10 DF 1F 93 00 F0 FF +13 DF F0 01 93 0E 10 00 93 01 B0 00 63 16 DF 1D +B7 20 21 21 93 80 10 12 13 DF 00 00 B7 2E 21 21 +93 8E 1E 12 93 01 C0 00 63 18 DF 1B B7 20 21 21 +93 80 10 12 13 DF 10 00 B7 9E 90 10 93 8E 0E 09 +93 01 D0 00 63 1A DF 19 B7 20 21 21 93 80 10 12 +13 DF 70 00 B7 4E 42 00 93 8E 2E 24 93 01 E0 00 +63 1C DF 17 B7 20 21 21 93 80 10 12 13 DF E0 00 +B7 8E 00 00 93 8E 4E 48 93 01 F0 00 63 1E DF 15 +B7 20 21 21 93 80 10 12 13 DF F0 01 93 0E 00 00 +93 01 00 01 63 12 DF 15 B7 00 00 80 93 D0 70 00 +B7 0E 00 01 93 01 10 01 63 98 D0 13 13 02 00 00 +B7 00 00 80 13 DF 70 00 13 03 0F 00 13 02 12 00 +93 02 20 00 E3 16 52 FE B7 0E 00 01 93 01 20 01 +63 14 D3 11 13 02 00 00 B7 00 00 80 13 DF E0 00 +13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 14 52 FE B7 0E 02 00 93 01 30 01 63 1E D3 0D +13 02 00 00 B7 00 00 80 93 80 10 00 13 DF F0 01 +13 00 00 00 13 00 00 00 13 03 0F 00 13 02 12 00 +93 02 20 00 E3 10 52 FE 93 0E 10 00 93 01 40 01 +63 14 D3 0B 13 02 00 00 B7 00 00 80 13 DF 70 00 +13 02 12 00 93 02 20 00 E3 18 52 FE B7 0E 00 01 +93 01 50 01 63 12 DF 09 13 02 00 00 B7 00 00 80 +13 00 00 00 13 DF E0 00 13 02 12 00 93 02 20 00 +E3 16 52 FE B7 0E 02 00 93 01 60 01 63 1E DF 05 +13 02 00 00 B7 00 00 80 93 80 10 00 13 00 00 00 +13 00 00 00 13 DF F0 01 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E 10 00 93 01 70 01 63 16 DF 03 +93 50 40 00 93 0E 00 00 93 01 80 01 63 9E D0 01 +93 00 10 02 13 D0 A0 00 93 0E 00 00 93 01 90 01 +63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 +@00000300 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-sub b/tests/isa/generated/rv32ui-p-sub new file mode 100644 index 0000000..858f941 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sub differ diff --git a/tests/isa/generated/rv32ui-p-sub.bin b/tests/isa/generated/rv32ui-p-sub.bin new file mode 100644 index 0000000..96d5e2b Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sub.bin differ diff --git a/tests/isa/generated/rv32ui-p-sub.dump b/tests/isa/generated/rv32ui-p-sub.dump new file mode 100644 index 0000000..60dc8d3 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sub.dump @@ -0,0 +1,408 @@ + +generated/rv32ui-p-sub: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00000093 li ra,0 + c: 00000113 li sp,0 + 10: 40208f33 sub t5,ra,sp + 14: 00000e93 li t4,0 + 18: 00200193 li gp,2 + 1c: 4bdf1663 bne t5,t4,4c8 + +00000020 : + 20: 00100093 li ra,1 + 24: 00100113 li sp,1 + 28: 40208f33 sub t5,ra,sp + 2c: 00000e93 li t4,0 + 30: 00300193 li gp,3 + 34: 49df1a63 bne t5,t4,4c8 + +00000038 : + 38: 00300093 li ra,3 + 3c: 00700113 li sp,7 + 40: 40208f33 sub t5,ra,sp + 44: ffc00e93 li t4,-4 + 48: 00400193 li gp,4 + 4c: 47df1e63 bne t5,t4,4c8 + +00000050 : + 50: 00000093 li ra,0 + 54: ffff8137 lui sp,0xffff8 + 58: 40208f33 sub t5,ra,sp + 5c: 00008eb7 lui t4,0x8 + 60: 00500193 li gp,5 + 64: 47df1263 bne t5,t4,4c8 + +00000068 : + 68: 800000b7 lui ra,0x80000 + 6c: 00000113 li sp,0 + 70: 40208f33 sub t5,ra,sp + 74: 80000eb7 lui t4,0x80000 + 78: 00600193 li gp,6 + 7c: 45df1663 bne t5,t4,4c8 + +00000080 : + 80: 800000b7 lui ra,0x80000 + 84: ffff8137 lui sp,0xffff8 + 88: 40208f33 sub t5,ra,sp + 8c: 80008eb7 lui t4,0x80008 + 90: 00700193 li gp,7 + 94: 43df1a63 bne t5,t4,4c8 + +00000098 : + 98: 00000093 li ra,0 + 9c: 00008137 lui sp,0x8 + a0: fff10113 addi sp,sp,-1 # 7fff + a4: 40208f33 sub t5,ra,sp + a8: ffff8eb7 lui t4,0xffff8 + ac: 001e8e93 addi t4,t4,1 # ffff8001 + b0: 00800193 li gp,8 + b4: 41df1a63 bne t5,t4,4c8 + +000000b8 : + b8: 800000b7 lui ra,0x80000 + bc: fff08093 addi ra,ra,-1 # 7fffffff + c0: 00000113 li sp,0 + c4: 40208f33 sub t5,ra,sp + c8: 80000eb7 lui t4,0x80000 + cc: fffe8e93 addi t4,t4,-1 # 7fffffff + d0: 00900193 li gp,9 + d4: 3fdf1a63 bne t5,t4,4c8 + +000000d8 : + d8: 800000b7 lui ra,0x80000 + dc: fff08093 addi ra,ra,-1 # 7fffffff + e0: 00008137 lui sp,0x8 + e4: fff10113 addi sp,sp,-1 # 7fff + e8: 40208f33 sub t5,ra,sp + ec: 7fff8eb7 lui t4,0x7fff8 + f0: 00a00193 li gp,10 + f4: 3ddf1a63 bne t5,t4,4c8 + +000000f8 : + f8: 800000b7 lui ra,0x80000 + fc: 00008137 lui sp,0x8 + 100: fff10113 addi sp,sp,-1 # 7fff + 104: 40208f33 sub t5,ra,sp + 108: 7fff8eb7 lui t4,0x7fff8 + 10c: 001e8e93 addi t4,t4,1 # 7fff8001 + 110: 00b00193 li gp,11 + 114: 3bdf1a63 bne t5,t4,4c8 + +00000118 : + 118: 800000b7 lui ra,0x80000 + 11c: fff08093 addi ra,ra,-1 # 7fffffff + 120: ffff8137 lui sp,0xffff8 + 124: 40208f33 sub t5,ra,sp + 128: 80008eb7 lui t4,0x80008 + 12c: fffe8e93 addi t4,t4,-1 # 80007fff + 130: 00c00193 li gp,12 + 134: 39df1a63 bne t5,t4,4c8 + +00000138 : + 138: 00000093 li ra,0 + 13c: fff00113 li sp,-1 + 140: 40208f33 sub t5,ra,sp + 144: 00100e93 li t4,1 + 148: 00d00193 li gp,13 + 14c: 37df1e63 bne t5,t4,4c8 + +00000150 : + 150: fff00093 li ra,-1 + 154: 00100113 li sp,1 + 158: 40208f33 sub t5,ra,sp + 15c: ffe00e93 li t4,-2 + 160: 00e00193 li gp,14 + 164: 37df1263 bne t5,t4,4c8 + +00000168 : + 168: fff00093 li ra,-1 + 16c: fff00113 li sp,-1 + 170: 40208f33 sub t5,ra,sp + 174: 00000e93 li t4,0 + 178: 00f00193 li gp,15 + 17c: 35df1663 bne t5,t4,4c8 + +00000180 : + 180: 00d00093 li ra,13 + 184: 00b00113 li sp,11 + 188: 402080b3 sub ra,ra,sp + 18c: 00200e93 li t4,2 + 190: 01000193 li gp,16 + 194: 33d09a63 bne ra,t4,4c8 + +00000198 : + 198: 00e00093 li ra,14 + 19c: 00b00113 li sp,11 + 1a0: 40208133 sub sp,ra,sp + 1a4: 00300e93 li t4,3 + 1a8: 01100193 li gp,17 + 1ac: 31d11e63 bne sp,t4,4c8 + +000001b0 : + 1b0: 00d00093 li ra,13 + 1b4: 401080b3 sub ra,ra,ra + 1b8: 00000e93 li t4,0 + 1bc: 01200193 li gp,18 + 1c0: 31d09463 bne ra,t4,4c8 + +000001c4 : + 1c4: 00000213 li tp,0 + 1c8: 00d00093 li ra,13 + 1cc: 00b00113 li sp,11 + 1d0: 40208f33 sub t5,ra,sp + 1d4: 000f0313 mv t1,t5 + 1d8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1dc: 00200293 li t0,2 + 1e0: fe5214e3 bne tp,t0,1c8 + 1e4: 00200e93 li t4,2 + 1e8: 01300193 li gp,19 + 1ec: 2dd31e63 bne t1,t4,4c8 + +000001f0 : + 1f0: 00000213 li tp,0 + 1f4: 00e00093 li ra,14 + 1f8: 00b00113 li sp,11 + 1fc: 40208f33 sub t5,ra,sp + 200: 00000013 nop + 204: 000f0313 mv t1,t5 + 208: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 20c: 00200293 li t0,2 + 210: fe5212e3 bne tp,t0,1f4 + 214: 00300e93 li t4,3 + 218: 01400193 li gp,20 + 21c: 2bd31663 bne t1,t4,4c8 + +00000220 : + 220: 00000213 li tp,0 + 224: 00f00093 li ra,15 + 228: 00b00113 li sp,11 + 22c: 40208f33 sub t5,ra,sp + 230: 00000013 nop + 234: 00000013 nop + 238: 000f0313 mv t1,t5 + 23c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 240: 00200293 li t0,2 + 244: fe5210e3 bne tp,t0,224 + 248: 00400e93 li t4,4 + 24c: 01500193 li gp,21 + 250: 27d31c63 bne t1,t4,4c8 + +00000254 : + 254: 00000213 li tp,0 + 258: 00d00093 li ra,13 + 25c: 00b00113 li sp,11 + 260: 40208f33 sub t5,ra,sp + 264: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 268: 00200293 li t0,2 + 26c: fe5216e3 bne tp,t0,258 + 270: 00200e93 li t4,2 + 274: 01600193 li gp,22 + 278: 25df1863 bne t5,t4,4c8 + +0000027c : + 27c: 00000213 li tp,0 + 280: 00e00093 li ra,14 + 284: 00b00113 li sp,11 + 288: 00000013 nop + 28c: 40208f33 sub t5,ra,sp + 290: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 294: 00200293 li t0,2 + 298: fe5214e3 bne tp,t0,280 + 29c: 00300e93 li t4,3 + 2a0: 01700193 li gp,23 + 2a4: 23df1263 bne t5,t4,4c8 + +000002a8 : + 2a8: 00000213 li tp,0 + 2ac: 00f00093 li ra,15 + 2b0: 00b00113 li sp,11 + 2b4: 00000013 nop + 2b8: 00000013 nop + 2bc: 40208f33 sub t5,ra,sp + 2c0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2c4: 00200293 li t0,2 + 2c8: fe5212e3 bne tp,t0,2ac + 2cc: 00400e93 li t4,4 + 2d0: 01800193 li gp,24 + 2d4: 1fdf1a63 bne t5,t4,4c8 + +000002d8 : + 2d8: 00000213 li tp,0 + 2dc: 00d00093 li ra,13 + 2e0: 00000013 nop + 2e4: 00b00113 li sp,11 + 2e8: 40208f33 sub t5,ra,sp + 2ec: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2f0: 00200293 li t0,2 + 2f4: fe5214e3 bne tp,t0,2dc + 2f8: 00200e93 li t4,2 + 2fc: 01900193 li gp,25 + 300: 1ddf1463 bne t5,t4,4c8 + +00000304 : + 304: 00000213 li tp,0 + 308: 00e00093 li ra,14 + 30c: 00000013 nop + 310: 00b00113 li sp,11 + 314: 00000013 nop + 318: 40208f33 sub t5,ra,sp + 31c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 320: 00200293 li t0,2 + 324: fe5212e3 bne tp,t0,308 + 328: 00300e93 li t4,3 + 32c: 01a00193 li gp,26 + 330: 19df1c63 bne t5,t4,4c8 + +00000334 : + 334: 00000213 li tp,0 + 338: 00f00093 li ra,15 + 33c: 00000013 nop + 340: 00000013 nop + 344: 00b00113 li sp,11 + 348: 40208f33 sub t5,ra,sp + 34c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 350: 00200293 li t0,2 + 354: fe5212e3 bne tp,t0,338 + 358: 00400e93 li t4,4 + 35c: 01b00193 li gp,27 + 360: 17df1463 bne t5,t4,4c8 + +00000364 : + 364: 00000213 li tp,0 + 368: 00b00113 li sp,11 + 36c: 00d00093 li ra,13 + 370: 40208f33 sub t5,ra,sp + 374: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 378: 00200293 li t0,2 + 37c: fe5216e3 bne tp,t0,368 + 380: 00200e93 li t4,2 + 384: 01c00193 li gp,28 + 388: 15df1063 bne t5,t4,4c8 + +0000038c : + 38c: 00000213 li tp,0 + 390: 00b00113 li sp,11 + 394: 00e00093 li ra,14 + 398: 00000013 nop + 39c: 40208f33 sub t5,ra,sp + 3a0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3a4: 00200293 li t0,2 + 3a8: fe5214e3 bne tp,t0,390 + 3ac: 00300e93 li t4,3 + 3b0: 01d00193 li gp,29 + 3b4: 11df1a63 bne t5,t4,4c8 + +000003b8 : + 3b8: 00000213 li tp,0 + 3bc: 00b00113 li sp,11 + 3c0: 00f00093 li ra,15 + 3c4: 00000013 nop + 3c8: 00000013 nop + 3cc: 40208f33 sub t5,ra,sp + 3d0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3d4: 00200293 li t0,2 + 3d8: fe5212e3 bne tp,t0,3bc + 3dc: 00400e93 li t4,4 + 3e0: 01e00193 li gp,30 + 3e4: 0fdf1263 bne t5,t4,4c8 + +000003e8 : + 3e8: 00000213 li tp,0 + 3ec: 00b00113 li sp,11 + 3f0: 00000013 nop + 3f4: 00d00093 li ra,13 + 3f8: 40208f33 sub t5,ra,sp + 3fc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 400: 00200293 li t0,2 + 404: fe5214e3 bne tp,t0,3ec + 408: 00200e93 li t4,2 + 40c: 01f00193 li gp,31 + 410: 0bdf1c63 bne t5,t4,4c8 + +00000414 : + 414: 00000213 li tp,0 + 418: 00b00113 li sp,11 + 41c: 00000013 nop + 420: 00e00093 li ra,14 + 424: 00000013 nop + 428: 40208f33 sub t5,ra,sp + 42c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 430: 00200293 li t0,2 + 434: fe5212e3 bne tp,t0,418 + 438: 00300e93 li t4,3 + 43c: 02000193 li gp,32 + 440: 09df1463 bne t5,t4,4c8 + +00000444 : + 444: 00000213 li tp,0 + 448: 00b00113 li sp,11 + 44c: 00000013 nop + 450: 00000013 nop + 454: 00f00093 li ra,15 + 458: 40208f33 sub t5,ra,sp + 45c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 460: 00200293 li t0,2 + 464: fe5212e3 bne tp,t0,448 + 468: 00400e93 li t4,4 + 46c: 02100193 li gp,33 + 470: 05df1c63 bne t5,t4,4c8 + +00000474 : + 474: ff100093 li ra,-15 + 478: 40100133 neg sp,ra + 47c: 00f00e93 li t4,15 + 480: 02200193 li gp,34 + 484: 05d11263 bne sp,t4,4c8 + +00000488 : + 488: 02000093 li ra,32 + 48c: 40008133 sub sp,ra,zero + 490: 02000e93 li t4,32 + 494: 02300193 li gp,35 + 498: 03d11863 bne sp,t4,4c8 + +0000049c : + 49c: 400000b3 neg ra,zero + 4a0: 00000e93 li t4,0 + 4a4: 02400193 li gp,36 + 4a8: 03d09063 bne ra,t4,4c8 + +000004ac : + 4ac: 01000093 li ra,16 + 4b0: 01e00113 li sp,30 + 4b4: 40208033 sub zero,ra,sp + 4b8: 00000e93 li t4,0 + 4bc: 02500193 li gp,37 + 4c0: 01d01463 bne zero,t4,4c8 + 4c4: 00301863 bne zero,gp,4d4 + +000004c8 : + 4c8: 00100d13 li s10,1 + 4cc: 00000d93 li s11,0 + +000004d0 : + 4d0: 0000006f j 4d0 + +000004d4 : + 4d4: 00100d13 li s10,1 + 4d8: 00100d93 li s11,1 + +000004dc : + 4dc: 0000006f j 4dc + ... + +Disassembly of section .tohost: + +00000540 : + ... + +00000580 : + ... diff --git a/tests/isa/generated/rv32ui-p-sub.verilog b/tests/isa/generated/rv32ui-p-sub.verilog new file mode 100644 index 0000000..1920e50 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sub.verilog @@ -0,0 +1,88 @@ +@00000000 +13 0D 00 00 93 0D 00 00 93 00 00 00 13 01 00 00 +33 8F 20 40 93 0E 00 00 93 01 20 00 63 16 DF 4B +93 00 10 00 13 01 10 00 33 8F 20 40 93 0E 00 00 +93 01 30 00 63 1A DF 49 93 00 30 00 13 01 70 00 +33 8F 20 40 93 0E C0 FF 93 01 40 00 63 1E DF 47 +93 00 00 00 37 81 FF FF 33 8F 20 40 B7 8E 00 00 +93 01 50 00 63 12 DF 47 B7 00 00 80 13 01 00 00 +33 8F 20 40 B7 0E 00 80 93 01 60 00 63 16 DF 45 +B7 00 00 80 37 81 FF FF 33 8F 20 40 B7 8E 00 80 +93 01 70 00 63 1A DF 43 93 00 00 00 37 81 00 00 +13 01 F1 FF 33 8F 20 40 B7 8E FF FF 93 8E 1E 00 +93 01 80 00 63 1A DF 41 B7 00 00 80 93 80 F0 FF +13 01 00 00 33 8F 20 40 B7 0E 00 80 93 8E FE FF +93 01 90 00 63 1A DF 3F B7 00 00 80 93 80 F0 FF +37 81 00 00 13 01 F1 FF 33 8F 20 40 B7 8E FF 7F +93 01 A0 00 63 1A DF 3D B7 00 00 80 37 81 00 00 +13 01 F1 FF 33 8F 20 40 B7 8E FF 7F 93 8E 1E 00 +93 01 B0 00 63 1A DF 3B B7 00 00 80 93 80 F0 FF +37 81 FF FF 33 8F 20 40 B7 8E 00 80 93 8E FE FF +93 01 C0 00 63 1A DF 39 93 00 00 00 13 01 F0 FF +33 8F 20 40 93 0E 10 00 93 01 D0 00 63 1E DF 37 +93 00 F0 FF 13 01 10 00 33 8F 20 40 93 0E E0 FF +93 01 E0 00 63 12 DF 37 93 00 F0 FF 13 01 F0 FF +33 8F 20 40 93 0E 00 00 93 01 F0 00 63 16 DF 35 +93 00 D0 00 13 01 B0 00 B3 80 20 40 93 0E 20 00 +93 01 00 01 63 9A D0 33 93 00 E0 00 13 01 B0 00 +33 81 20 40 93 0E 30 00 93 01 10 01 63 1E D1 31 +93 00 D0 00 B3 80 10 40 93 0E 00 00 93 01 20 01 +63 94 D0 31 13 02 00 00 93 00 D0 00 13 01 B0 00 +33 8F 20 40 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 14 52 FE 93 0E 20 00 93 01 30 01 63 1E D3 2D +13 02 00 00 93 00 E0 00 13 01 B0 00 33 8F 20 40 +13 00 00 00 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 12 52 FE 93 0E 30 00 93 01 40 01 63 16 D3 2B +13 02 00 00 93 00 F0 00 13 01 B0 00 33 8F 20 40 +13 00 00 00 13 00 00 00 13 03 0F 00 13 02 12 00 +93 02 20 00 E3 10 52 FE 93 0E 40 00 93 01 50 01 +63 1C D3 27 13 02 00 00 93 00 D0 00 13 01 B0 00 +33 8F 20 40 13 02 12 00 93 02 20 00 E3 16 52 FE +93 0E 20 00 93 01 60 01 63 18 DF 25 13 02 00 00 +93 00 E0 00 13 01 B0 00 13 00 00 00 33 8F 20 40 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 30 00 +93 01 70 01 63 12 DF 23 13 02 00 00 93 00 F0 00 +13 01 B0 00 13 00 00 00 13 00 00 00 33 8F 20 40 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 40 00 +93 01 80 01 63 1A DF 1F 13 02 00 00 93 00 D0 00 +13 00 00 00 13 01 B0 00 33 8F 20 40 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 0E 20 00 93 01 90 01 +63 14 DF 1D 13 02 00 00 93 00 E0 00 13 00 00 00 +13 01 B0 00 13 00 00 00 33 8F 20 40 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E 30 00 93 01 A0 01 +63 1C DF 19 13 02 00 00 93 00 F0 00 13 00 00 00 +13 00 00 00 13 01 B0 00 33 8F 20 40 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E 40 00 93 01 B0 01 +63 14 DF 17 13 02 00 00 13 01 B0 00 93 00 D0 00 +33 8F 20 40 13 02 12 00 93 02 20 00 E3 16 52 FE +93 0E 20 00 93 01 C0 01 63 10 DF 15 13 02 00 00 +13 01 B0 00 93 00 E0 00 13 00 00 00 33 8F 20 40 +13 02 12 00 93 02 20 00 E3 14 52 FE 93 0E 30 00 +93 01 D0 01 63 1A DF 11 13 02 00 00 13 01 B0 00 +93 00 F0 00 13 00 00 00 13 00 00 00 33 8F 20 40 +13 02 12 00 93 02 20 00 E3 12 52 FE 93 0E 40 00 +93 01 E0 01 63 12 DF 0F 13 02 00 00 13 01 B0 00 +13 00 00 00 93 00 D0 00 33 8F 20 40 13 02 12 00 +93 02 20 00 E3 14 52 FE 93 0E 20 00 93 01 F0 01 +63 1C DF 0B 13 02 00 00 13 01 B0 00 13 00 00 00 +93 00 E0 00 13 00 00 00 33 8F 20 40 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E 30 00 93 01 00 02 +63 14 DF 09 13 02 00 00 13 01 B0 00 13 00 00 00 +13 00 00 00 93 00 F0 00 33 8F 20 40 13 02 12 00 +93 02 20 00 E3 12 52 FE 93 0E 40 00 93 01 10 02 +63 1C DF 05 93 00 10 FF 33 01 10 40 93 0E F0 00 +93 01 20 02 63 12 D1 05 93 00 00 02 33 81 00 40 +93 0E 00 02 93 01 30 02 63 18 D1 03 B3 00 00 40 +93 0E 00 00 93 01 40 02 63 90 D0 03 93 00 00 01 +13 01 E0 01 33 80 20 40 93 0E 00 00 93 01 50 02 +63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000540 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-sw b/tests/isa/generated/rv32ui-p-sw new file mode 100644 index 0000000..750124a Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sw differ diff --git a/tests/isa/generated/rv32ui-p-sw.bin b/tests/isa/generated/rv32ui-p-sw.bin new file mode 100644 index 0000000..9acde40 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-sw.bin differ diff --git a/tests/isa/generated/rv32ui-p-sw.dump b/tests/isa/generated/rv32ui-p-sw.dump new file mode 100644 index 0000000..054a47a --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sw.dump @@ -0,0 +1,398 @@ + +generated/rv32ui-p-sw: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00001097 auipc ra,0x1 + c: ff808093 addi ra,ra,-8 # 1000 + 10: 00aa0137 lui sp,0xaa0 + 14: 0aa10113 addi sp,sp,170 # aa00aa <_end+0xa9f022> + 18: 0020a023 sw sp,0(ra) + 1c: 0000af03 lw t5,0(ra) + 20: 00aa0eb7 lui t4,0xaa0 + 24: 0aae8e93 addi t4,t4,170 # aa00aa <_end+0xa9f022> + 28: 00200193 li gp,2 + 2c: 47df1063 bne t5,t4,48c + +00000030 : + 30: 00001097 auipc ra,0x1 + 34: fd008093 addi ra,ra,-48 # 1000 + 38: aa00b137 lui sp,0xaa00b + 3c: a0010113 addi sp,sp,-1536 # aa00aa00 <_end+0xaa009978> + 40: 0020a223 sw sp,4(ra) + 44: 0040af03 lw t5,4(ra) + 48: aa00beb7 lui t4,0xaa00b + 4c: a00e8e93 addi t4,t4,-1536 # aa00aa00 <_end+0xaa009978> + 50: 00300193 li gp,3 + 54: 43df1c63 bne t5,t4,48c + +00000058 : + 58: 00001097 auipc ra,0x1 + 5c: fa808093 addi ra,ra,-88 # 1000 + 60: 0aa01137 lui sp,0xaa01 + 64: aa010113 addi sp,sp,-1376 # aa00aa0 <_end+0xa9ffa18> + 68: 0020a423 sw sp,8(ra) + 6c: 0080af03 lw t5,8(ra) + 70: 0aa01eb7 lui t4,0xaa01 + 74: aa0e8e93 addi t4,t4,-1376 # aa00aa0 <_end+0xa9ffa18> + 78: 00400193 li gp,4 + 7c: 41df1863 bne t5,t4,48c + +00000080 : + 80: 00001097 auipc ra,0x1 + 84: f8008093 addi ra,ra,-128 # 1000 + 88: a00aa137 lui sp,0xa00aa + 8c: 00a10113 addi sp,sp,10 # a00aa00a <_end+0xa00a8f82> + 90: 0020a623 sw sp,12(ra) + 94: 00c0af03 lw t5,12(ra) + 98: a00aaeb7 lui t4,0xa00aa + 9c: 00ae8e93 addi t4,t4,10 # a00aa00a <_end+0xa00a8f82> + a0: 00500193 li gp,5 + a4: 3fdf1463 bne t5,t4,48c + +000000a8 : + a8: 00001097 auipc ra,0x1 + ac: f7408093 addi ra,ra,-140 # 101c + b0: 00aa0137 lui sp,0xaa0 + b4: 0aa10113 addi sp,sp,170 # aa00aa <_end+0xa9f022> + b8: fe20aa23 sw sp,-12(ra) + bc: ff40af03 lw t5,-12(ra) + c0: 00aa0eb7 lui t4,0xaa0 + c4: 0aae8e93 addi t4,t4,170 # aa00aa <_end+0xa9f022> + c8: 00600193 li gp,6 + cc: 3ddf1063 bne t5,t4,48c + +000000d0 : + d0: 00001097 auipc ra,0x1 + d4: f4c08093 addi ra,ra,-180 # 101c + d8: aa00b137 lui sp,0xaa00b + dc: a0010113 addi sp,sp,-1536 # aa00aa00 <_end+0xaa009978> + e0: fe20ac23 sw sp,-8(ra) + e4: ff80af03 lw t5,-8(ra) + e8: aa00beb7 lui t4,0xaa00b + ec: a00e8e93 addi t4,t4,-1536 # aa00aa00 <_end+0xaa009978> + f0: 00700193 li gp,7 + f4: 39df1c63 bne t5,t4,48c + +000000f8 : + f8: 00001097 auipc ra,0x1 + fc: f2408093 addi ra,ra,-220 # 101c + 100: 0aa01137 lui sp,0xaa01 + 104: aa010113 addi sp,sp,-1376 # aa00aa0 <_end+0xa9ffa18> + 108: fe20ae23 sw sp,-4(ra) + 10c: ffc0af03 lw t5,-4(ra) + 110: 0aa01eb7 lui t4,0xaa01 + 114: aa0e8e93 addi t4,t4,-1376 # aa00aa0 <_end+0xa9ffa18> + 118: 00800193 li gp,8 + 11c: 37df1863 bne t5,t4,48c + +00000120 : + 120: 00001097 auipc ra,0x1 + 124: efc08093 addi ra,ra,-260 # 101c + 128: a00aa137 lui sp,0xa00aa + 12c: 00a10113 addi sp,sp,10 # a00aa00a <_end+0xa00a8f82> + 130: 0020a023 sw sp,0(ra) + 134: 0000af03 lw t5,0(ra) + 138: a00aaeb7 lui t4,0xa00aa + 13c: 00ae8e93 addi t4,t4,10 # a00aa00a <_end+0xa00a8f82> + 140: 00900193 li gp,9 + 144: 35df1463 bne t5,t4,48c + +00000148 : + 148: 00001097 auipc ra,0x1 + 14c: ed808093 addi ra,ra,-296 # 1020 + 150: 12345137 lui sp,0x12345 + 154: 67810113 addi sp,sp,1656 # 12345678 <_end+0x123445f0> + 158: fe008213 addi tp,ra,-32 + 15c: 02222023 sw sp,32(tp) # 20 + 160: 0000a283 lw t0,0(ra) + 164: 12345eb7 lui t4,0x12345 + 168: 678e8e93 addi t4,t4,1656 # 12345678 <_end+0x123445f0> + 16c: 00a00193 li gp,10 + 170: 31d29e63 bne t0,t4,48c + +00000174 : + 174: 00001097 auipc ra,0x1 + 178: eac08093 addi ra,ra,-340 # 1020 + 17c: 58213137 lui sp,0x58213 + 180: 09810113 addi sp,sp,152 # 58213098 <_end+0x58212010> + 184: ffd08093 addi ra,ra,-3 + 188: 0020a3a3 sw sp,7(ra) + 18c: 00001217 auipc tp,0x1 + 190: e9820213 addi tp,tp,-360 # 1024 + 194: 00022283 lw t0,0(tp) # 0 <_start> + 198: 58213eb7 lui t4,0x58213 + 19c: 098e8e93 addi t4,t4,152 # 58213098 <_end+0x58212010> + 1a0: 00b00193 li gp,11 + 1a4: 2fd29463 bne t0,t4,48c + +000001a8 : + 1a8: 00c00193 li gp,12 + 1ac: 00000213 li tp,0 + 1b0: aabbd0b7 lui ra,0xaabbd + 1b4: cdd08093 addi ra,ra,-803 # aabbccdd <_end+0xaabbbc55> + 1b8: 00001117 auipc sp,0x1 + 1bc: e4810113 addi sp,sp,-440 # 1000 + 1c0: 00112023 sw ra,0(sp) + 1c4: 00012f03 lw t5,0(sp) + 1c8: aabbdeb7 lui t4,0xaabbd + 1cc: cdde8e93 addi t4,t4,-803 # aabbccdd <_end+0xaabbbc55> + 1d0: 2bdf1e63 bne t5,t4,48c + 1d4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1d8: 00200293 li t0,2 + 1dc: fc521ae3 bne tp,t0,1b0 + +000001e0 : + 1e0: 00d00193 li gp,13 + 1e4: 00000213 li tp,0 + 1e8: daabc0b7 lui ra,0xdaabc + 1ec: ccd08093 addi ra,ra,-819 # daabbccd <_end+0xdaabac45> + 1f0: 00001117 auipc sp,0x1 + 1f4: e1010113 addi sp,sp,-496 # 1000 + 1f8: 00000013 nop + 1fc: 00112223 sw ra,4(sp) + 200: 00412f03 lw t5,4(sp) + 204: daabceb7 lui t4,0xdaabc + 208: ccde8e93 addi t4,t4,-819 # daabbccd <_end+0xdaabac45> + 20c: 29df1063 bne t5,t4,48c + 210: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 214: 00200293 li t0,2 + 218: fc5218e3 bne tp,t0,1e8 + +0000021c : + 21c: 00e00193 li gp,14 + 220: 00000213 li tp,0 + 224: ddaac0b7 lui ra,0xddaac + 228: bcc08093 addi ra,ra,-1076 # ddaabbcc <_end+0xddaaab44> + 22c: 00001117 auipc sp,0x1 + 230: dd410113 addi sp,sp,-556 # 1000 + 234: 00000013 nop + 238: 00000013 nop + 23c: 00112423 sw ra,8(sp) + 240: 00812f03 lw t5,8(sp) + 244: ddaaceb7 lui t4,0xddaac + 248: bcce8e93 addi t4,t4,-1076 # ddaabbcc <_end+0xddaaab44> + 24c: 25df1063 bne t5,t4,48c + 250: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 254: 00200293 li t0,2 + 258: fc5216e3 bne tp,t0,224 + +0000025c : + 25c: 00f00193 li gp,15 + 260: 00000213 li tp,0 + 264: cddab0b7 lui ra,0xcddab + 268: bbc08093 addi ra,ra,-1092 # cddaabbc <_end+0xcdda9b34> + 26c: 00000013 nop + 270: 00001117 auipc sp,0x1 + 274: d9010113 addi sp,sp,-624 # 1000 + 278: 00112623 sw ra,12(sp) + 27c: 00c12f03 lw t5,12(sp) + 280: cddabeb7 lui t4,0xcddab + 284: bbce8e93 addi t4,t4,-1092 # cddaabbc <_end+0xcdda9b34> + 288: 21df1263 bne t5,t4,48c + 28c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 290: 00200293 li t0,2 + 294: fc5218e3 bne tp,t0,264 + +00000298 : + 298: 01000193 li gp,16 + 29c: 00000213 li tp,0 + 2a0: ccddb0b7 lui ra,0xccddb + 2a4: abb08093 addi ra,ra,-1349 # ccddaabb <_end+0xccdd9a33> + 2a8: 00000013 nop + 2ac: 00001117 auipc sp,0x1 + 2b0: d5410113 addi sp,sp,-684 # 1000 + 2b4: 00000013 nop + 2b8: 00112823 sw ra,16(sp) + 2bc: 01012f03 lw t5,16(sp) + 2c0: ccddbeb7 lui t4,0xccddb + 2c4: abbe8e93 addi t4,t4,-1349 # ccddaabb <_end+0xccdd9a33> + 2c8: 1ddf1263 bne t5,t4,48c + 2cc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2d0: 00200293 li t0,2 + 2d4: fc5216e3 bne tp,t0,2a0 + +000002d8 : + 2d8: 01100193 li gp,17 + 2dc: 00000213 li tp,0 + 2e0: bccde0b7 lui ra,0xbccde + 2e4: aab08093 addi ra,ra,-1365 # bccddaab <_end+0xbccdca23> + 2e8: 00000013 nop + 2ec: 00000013 nop + 2f0: 00001117 auipc sp,0x1 + 2f4: d1010113 addi sp,sp,-752 # 1000 + 2f8: 00112a23 sw ra,20(sp) + 2fc: 01412f03 lw t5,20(sp) + 300: bccdeeb7 lui t4,0xbccde + 304: aabe8e93 addi t4,t4,-1365 # bccddaab <_end+0xbccdca23> + 308: 19df1263 bne t5,t4,48c + 30c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 310: 00200293 li t0,2 + 314: fc5216e3 bne tp,t0,2e0 + +00000318 : + 318: 01200193 li gp,18 + 31c: 00000213 li tp,0 + 320: 00001117 auipc sp,0x1 + 324: ce010113 addi sp,sp,-800 # 1000 + 328: 001120b7 lui ra,0x112 + 32c: 23308093 addi ra,ra,563 # 112233 <_end+0x1111ab> + 330: 00112023 sw ra,0(sp) + 334: 00012f03 lw t5,0(sp) + 338: 00112eb7 lui t4,0x112 + 33c: 233e8e93 addi t4,t4,563 # 112233 <_end+0x1111ab> + 340: 15df1663 bne t5,t4,48c + 344: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 348: 00200293 li t0,2 + 34c: fc521ae3 bne tp,t0,320 + +00000350 : + 350: 01300193 li gp,19 + 354: 00000213 li tp,0 + 358: 00001117 auipc sp,0x1 + 35c: ca810113 addi sp,sp,-856 # 1000 + 360: 300110b7 lui ra,0x30011 + 364: 22308093 addi ra,ra,547 # 30011223 <_end+0x3001019b> + 368: 00000013 nop + 36c: 00112223 sw ra,4(sp) + 370: 00412f03 lw t5,4(sp) + 374: 30011eb7 lui t4,0x30011 + 378: 223e8e93 addi t4,t4,547 # 30011223 <_end+0x3001019b> + 37c: 11df1863 bne t5,t4,48c + 380: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 384: 00200293 li t0,2 + 388: fc5218e3 bne tp,t0,358 + +0000038c : + 38c: 01400193 li gp,20 + 390: 00000213 li tp,0 + 394: 00001117 auipc sp,0x1 + 398: c6c10113 addi sp,sp,-916 # 1000 + 39c: 330010b7 lui ra,0x33001 + 3a0: 12208093 addi ra,ra,290 # 33001122 <_end+0x3300009a> + 3a4: 00000013 nop + 3a8: 00000013 nop + 3ac: 00112423 sw ra,8(sp) + 3b0: 00812f03 lw t5,8(sp) + 3b4: 33001eb7 lui t4,0x33001 + 3b8: 122e8e93 addi t4,t4,290 # 33001122 <_end+0x3300009a> + 3bc: 0ddf1863 bne t5,t4,48c + 3c0: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3c4: 00200293 li t0,2 + 3c8: fc5216e3 bne tp,t0,394 + +000003cc : + 3cc: 01500193 li gp,21 + 3d0: 00000213 li tp,0 + 3d4: 00001117 auipc sp,0x1 + 3d8: c2c10113 addi sp,sp,-980 # 1000 + 3dc: 00000013 nop + 3e0: 233000b7 lui ra,0x23300 + 3e4: 11208093 addi ra,ra,274 # 23300112 <_end+0x232ff08a> + 3e8: 00112623 sw ra,12(sp) + 3ec: 00c12f03 lw t5,12(sp) + 3f0: 23300eb7 lui t4,0x23300 + 3f4: 112e8e93 addi t4,t4,274 # 23300112 <_end+0x232ff08a> + 3f8: 09df1a63 bne t5,t4,48c + 3fc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 400: 00200293 li t0,2 + 404: fc5218e3 bne tp,t0,3d4 + +00000408 : + 408: 01600193 li gp,22 + 40c: 00000213 li tp,0 + 410: 00001117 auipc sp,0x1 + 414: bf010113 addi sp,sp,-1040 # 1000 + 418: 00000013 nop + 41c: 223300b7 lui ra,0x22330 + 420: 01108093 addi ra,ra,17 # 22330011 <_end+0x2232ef89> + 424: 00000013 nop + 428: 00112823 sw ra,16(sp) + 42c: 01012f03 lw t5,16(sp) + 430: 22330eb7 lui t4,0x22330 + 434: 011e8e93 addi t4,t4,17 # 22330011 <_end+0x2232ef89> + 438: 05df1a63 bne t5,t4,48c + 43c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 440: 00200293 li t0,2 + 444: fc5216e3 bne tp,t0,410 + +00000448 : + 448: 01700193 li gp,23 + 44c: 00000213 li tp,0 + 450: 00001117 auipc sp,0x1 + 454: bb010113 addi sp,sp,-1104 # 1000 + 458: 00000013 nop + 45c: 00000013 nop + 460: 122330b7 lui ra,0x12233 + 464: 00108093 addi ra,ra,1 # 12233001 <_end+0x12231f79> + 468: 00112a23 sw ra,20(sp) + 46c: 01412f03 lw t5,20(sp) + 470: 12233eb7 lui t4,0x12233 + 474: 001e8e93 addi t4,t4,1 # 12233001 <_end+0x12231f79> + 478: 01df1a63 bne t5,t4,48c + 47c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 480: 00200293 li t0,2 + 484: fc5216e3 bne tp,t0,450 + 488: 00301863 bne zero,gp,498 + +0000048c : + 48c: 00100d13 li s10,1 + 490: 00000d93 li s11,0 + +00000494 : + 494: 0000006f j 494 + +00000498 : + 498: 00100d13 li s10,1 + 49c: 00100d93 li s11,1 + +000004a0 : + 4a0: 0000006f j 4a0 + ... + +Disassembly of section .data: + +00001000 : + 1000: deadbeef jal t4,fffdc5ea <_end+0xfffdb562> + +00001004 : + 1004: deadbeef jal t4,fffdc5ee <_end+0xfffdb566> + +00001008 : + 1008: deadbeef jal t4,fffdc5f2 <_end+0xfffdb56a> + +0000100c : + 100c: deadbeef jal t4,fffdc5f6 <_end+0xfffdb56e> + +00001010 : + 1010: deadbeef jal t4,fffdc5fa <_end+0xfffdb572> + +00001014 : + 1014: deadbeef jal t4,fffdc5fe <_end+0xfffdb576> + +00001018 : + 1018: deadbeef jal t4,fffdc602 <_end+0xfffdb57a> + +0000101c : + 101c: deadbeef jal t4,fffdc606 <_end+0xfffdb57e> + +00001020 : + 1020: deadbeef jal t4,fffdc60a <_end+0xfffdb582> + +00001024 : + 1024: deadbeef jal t4,fffdc60e <_end+0xfffdb586> + ... + +Disassembly of section .tohost: + +00001040 : + ... + +00001080 : + ... diff --git a/tests/isa/generated/rv32ui-p-sw.verilog b/tests/isa/generated/rv32ui-p-sw.verilog new file mode 100644 index 0000000..1915c9b --- /dev/null +++ b/tests/isa/generated/rv32ui-p-sw.verilog @@ -0,0 +1,88 @@ +@00000000 +13 0D 00 00 93 0D 00 00 97 10 00 00 93 80 80 FF +37 01 AA 00 13 01 A1 0A 23 A0 20 00 03 AF 00 00 +B7 0E AA 00 93 8E AE 0A 93 01 20 00 63 10 DF 47 +97 10 00 00 93 80 00 FD 37 B1 00 AA 13 01 01 A0 +23 A2 20 00 03 AF 40 00 B7 BE 00 AA 93 8E 0E A0 +93 01 30 00 63 1C DF 43 97 10 00 00 93 80 80 FA +37 11 A0 0A 13 01 01 AA 23 A4 20 00 03 AF 80 00 +B7 1E A0 0A 93 8E 0E AA 93 01 40 00 63 18 DF 41 +97 10 00 00 93 80 00 F8 37 A1 0A A0 13 01 A1 00 +23 A6 20 00 03 AF C0 00 B7 AE 0A A0 93 8E AE 00 +93 01 50 00 63 14 DF 3F 97 10 00 00 93 80 40 F7 +37 01 AA 00 13 01 A1 0A 23 AA 20 FE 03 AF 40 FF +B7 0E AA 00 93 8E AE 0A 93 01 60 00 63 10 DF 3D +97 10 00 00 93 80 C0 F4 37 B1 00 AA 13 01 01 A0 +23 AC 20 FE 03 AF 80 FF B7 BE 00 AA 93 8E 0E A0 +93 01 70 00 63 1C DF 39 97 10 00 00 93 80 40 F2 +37 11 A0 0A 13 01 01 AA 23 AE 20 FE 03 AF C0 FF +B7 1E A0 0A 93 8E 0E AA 93 01 80 00 63 18 DF 37 +97 10 00 00 93 80 C0 EF 37 A1 0A A0 13 01 A1 00 +23 A0 20 00 03 AF 00 00 B7 AE 0A A0 93 8E AE 00 +93 01 90 00 63 14 DF 35 97 10 00 00 93 80 80 ED +37 51 34 12 13 01 81 67 13 82 00 FE 23 20 22 02 +83 A2 00 00 B7 5E 34 12 93 8E 8E 67 93 01 A0 00 +63 9E D2 31 97 10 00 00 93 80 C0 EA 37 31 21 58 +13 01 81 09 93 80 D0 FF A3 A3 20 00 17 12 00 00 +13 02 82 E9 83 22 02 00 B7 3E 21 58 93 8E 8E 09 +93 01 B0 00 63 94 D2 2F 93 01 C0 00 13 02 00 00 +B7 D0 BB AA 93 80 D0 CD 17 11 00 00 13 01 81 E4 +23 20 11 00 03 2F 01 00 B7 DE BB AA 93 8E DE CD +63 1E DF 2B 13 02 12 00 93 02 20 00 E3 1A 52 FC +93 01 D0 00 13 02 00 00 B7 C0 AB DA 93 80 D0 CC +17 11 00 00 13 01 01 E1 13 00 00 00 23 22 11 00 +03 2F 41 00 B7 CE AB DA 93 8E DE CC 63 10 DF 29 +13 02 12 00 93 02 20 00 E3 18 52 FC 93 01 E0 00 +13 02 00 00 B7 C0 AA DD 93 80 C0 BC 17 11 00 00 +13 01 41 DD 13 00 00 00 13 00 00 00 23 24 11 00 +03 2F 81 00 B7 CE AA DD 93 8E CE BC 63 10 DF 25 +13 02 12 00 93 02 20 00 E3 16 52 FC 93 01 F0 00 +13 02 00 00 B7 B0 DA CD 93 80 C0 BB 13 00 00 00 +17 11 00 00 13 01 01 D9 23 26 11 00 03 2F C1 00 +B7 BE DA CD 93 8E CE BB 63 12 DF 21 13 02 12 00 +93 02 20 00 E3 18 52 FC 93 01 00 01 13 02 00 00 +B7 B0 DD CC 93 80 B0 AB 13 00 00 00 17 11 00 00 +13 01 41 D5 13 00 00 00 23 28 11 00 03 2F 01 01 +B7 BE DD CC 93 8E BE AB 63 12 DF 1D 13 02 12 00 +93 02 20 00 E3 16 52 FC 93 01 10 01 13 02 00 00 +B7 E0 CD BC 93 80 B0 AA 13 00 00 00 13 00 00 00 +17 11 00 00 13 01 01 D1 23 2A 11 00 03 2F 41 01 +B7 EE CD BC 93 8E BE AA 63 12 DF 19 13 02 12 00 +93 02 20 00 E3 16 52 FC 93 01 20 01 13 02 00 00 +17 11 00 00 13 01 01 CE B7 20 11 00 93 80 30 23 +23 20 11 00 03 2F 01 00 B7 2E 11 00 93 8E 3E 23 +63 16 DF 15 13 02 12 00 93 02 20 00 E3 1A 52 FC +93 01 30 01 13 02 00 00 17 11 00 00 13 01 81 CA +B7 10 01 30 93 80 30 22 13 00 00 00 23 22 11 00 +03 2F 41 00 B7 1E 01 30 93 8E 3E 22 63 18 DF 11 +13 02 12 00 93 02 20 00 E3 18 52 FC 93 01 40 01 +13 02 00 00 17 11 00 00 13 01 C1 C6 B7 10 00 33 +93 80 20 12 13 00 00 00 13 00 00 00 23 24 11 00 +03 2F 81 00 B7 1E 00 33 93 8E 2E 12 63 18 DF 0D +13 02 12 00 93 02 20 00 E3 16 52 FC 93 01 50 01 +13 02 00 00 17 11 00 00 13 01 C1 C2 13 00 00 00 +B7 00 30 23 93 80 20 11 23 26 11 00 03 2F C1 00 +B7 0E 30 23 93 8E 2E 11 63 1A DF 09 13 02 12 00 +93 02 20 00 E3 18 52 FC 93 01 60 01 13 02 00 00 +17 11 00 00 13 01 01 BF 13 00 00 00 B7 00 33 22 +93 80 10 01 13 00 00 00 23 28 11 00 03 2F 01 01 +B7 0E 33 22 93 8E 1E 01 63 1A DF 05 13 02 12 00 +93 02 20 00 E3 16 52 FC 93 01 70 01 13 02 00 00 +17 11 00 00 13 01 01 BB 13 00 00 00 13 00 00 00 +B7 30 23 12 93 80 10 00 23 2A 11 00 03 2F 41 01 +B7 3E 23 12 93 8E 1E 00 63 1A DF 01 13 02 12 00 +93 02 20 00 E3 16 52 FC 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00001000 +EF BE AD DE EF BE AD DE EF BE AD DE EF BE AD DE +EF BE AD DE EF BE AD DE EF BE AD DE EF BE AD DE +EF BE AD DE EF BE AD DE 00 00 00 00 00 00 00 00 +@00001040 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-xor b/tests/isa/generated/rv32ui-p-xor new file mode 100644 index 0000000..917a111 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-xor differ diff --git a/tests/isa/generated/rv32ui-p-xor.bin b/tests/isa/generated/rv32ui-p-xor.bin new file mode 100644 index 0000000..20eb36b Binary files /dev/null and b/tests/isa/generated/rv32ui-p-xor.bin differ diff --git a/tests/isa/generated/rv32ui-p-xor.dump b/tests/isa/generated/rv32ui-p-xor.dump new file mode 100644 index 0000000..b7ee509 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-xor.dump @@ -0,0 +1,388 @@ + +generated/rv32ui-p-xor: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: ff0100b7 lui ra,0xff010 + c: f0008093 addi ra,ra,-256 # ff00ff00 + 10: 0f0f1137 lui sp,0xf0f1 + 14: f0f10113 addi sp,sp,-241 # f0f0f0f + 18: 0020cf33 xor t5,ra,sp + 1c: f00ffeb7 lui t4,0xf00ff + 20: 00fe8e93 addi t4,t4,15 # f00ff00f + 24: 00200193 li gp,2 + 28: 4bdf1063 bne t5,t4,4c8 + +0000002c : + 2c: 0ff010b7 lui ra,0xff01 + 30: ff008093 addi ra,ra,-16 # ff00ff0 + 34: f0f0f137 lui sp,0xf0f0f + 38: 0f010113 addi sp,sp,240 # f0f0f0f0 + 3c: 0020cf33 xor t5,ra,sp + 40: ff010eb7 lui t4,0xff010 + 44: f00e8e93 addi t4,t4,-256 # ff00ff00 + 48: 00300193 li gp,3 + 4c: 47df1e63 bne t5,t4,4c8 + +00000050 : + 50: 00ff00b7 lui ra,0xff0 + 54: 0ff08093 addi ra,ra,255 # ff00ff + 58: 0f0f1137 lui sp,0xf0f1 + 5c: f0f10113 addi sp,sp,-241 # f0f0f0f + 60: 0020cf33 xor t5,ra,sp + 64: 0ff01eb7 lui t4,0xff01 + 68: ff0e8e93 addi t4,t4,-16 # ff00ff0 + 6c: 00400193 li gp,4 + 70: 45df1c63 bne t5,t4,4c8 + +00000074 : + 74: f00ff0b7 lui ra,0xf00ff + 78: 00f08093 addi ra,ra,15 # f00ff00f + 7c: f0f0f137 lui sp,0xf0f0f + 80: 0f010113 addi sp,sp,240 # f0f0f0f0 + 84: 0020cf33 xor t5,ra,sp + 88: 00ff0eb7 lui t4,0xff0 + 8c: 0ffe8e93 addi t4,t4,255 # ff00ff + 90: 00500193 li gp,5 + 94: 43df1a63 bne t5,t4,4c8 + +00000098 : + 98: ff0100b7 lui ra,0xff010 + 9c: f0008093 addi ra,ra,-256 # ff00ff00 + a0: 0f0f1137 lui sp,0xf0f1 + a4: f0f10113 addi sp,sp,-241 # f0f0f0f + a8: 0020c0b3 xor ra,ra,sp + ac: f00ffeb7 lui t4,0xf00ff + b0: 00fe8e93 addi t4,t4,15 # f00ff00f + b4: 00600193 li gp,6 + b8: 41d09863 bne ra,t4,4c8 + +000000bc : + bc: ff0100b7 lui ra,0xff010 + c0: f0008093 addi ra,ra,-256 # ff00ff00 + c4: 0f0f1137 lui sp,0xf0f1 + c8: f0f10113 addi sp,sp,-241 # f0f0f0f + cc: 0020c133 xor sp,ra,sp + d0: f00ffeb7 lui t4,0xf00ff + d4: 00fe8e93 addi t4,t4,15 # f00ff00f + d8: 00700193 li gp,7 + dc: 3fd11663 bne sp,t4,4c8 + +000000e0 : + e0: ff0100b7 lui ra,0xff010 + e4: f0008093 addi ra,ra,-256 # ff00ff00 + e8: 0010c0b3 xor ra,ra,ra + ec: 00000e93 li t4,0 + f0: 00800193 li gp,8 + f4: 3dd09a63 bne ra,t4,4c8 + +000000f8 : + f8: 00000213 li tp,0 + fc: ff0100b7 lui ra,0xff010 + 100: f0008093 addi ra,ra,-256 # ff00ff00 + 104: 0f0f1137 lui sp,0xf0f1 + 108: f0f10113 addi sp,sp,-241 # f0f0f0f + 10c: 0020cf33 xor t5,ra,sp + 110: 000f0313 mv t1,t5 + 114: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 118: 00200293 li t0,2 + 11c: fe5210e3 bne tp,t0,fc + 120: f00ffeb7 lui t4,0xf00ff + 124: 00fe8e93 addi t4,t4,15 # f00ff00f + 128: 00900193 li gp,9 + 12c: 39d31e63 bne t1,t4,4c8 + +00000130 : + 130: 00000213 li tp,0 + 134: 0ff010b7 lui ra,0xff01 + 138: ff008093 addi ra,ra,-16 # ff00ff0 + 13c: f0f0f137 lui sp,0xf0f0f + 140: 0f010113 addi sp,sp,240 # f0f0f0f0 + 144: 0020cf33 xor t5,ra,sp + 148: 00000013 nop + 14c: 000f0313 mv t1,t5 + 150: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 154: 00200293 li t0,2 + 158: fc521ee3 bne tp,t0,134 + 15c: ff010eb7 lui t4,0xff010 + 160: f00e8e93 addi t4,t4,-256 # ff00ff00 + 164: 00a00193 li gp,10 + 168: 37d31063 bne t1,t4,4c8 + +0000016c : + 16c: 00000213 li tp,0 + 170: 00ff00b7 lui ra,0xff0 + 174: 0ff08093 addi ra,ra,255 # ff00ff + 178: 0f0f1137 lui sp,0xf0f1 + 17c: f0f10113 addi sp,sp,-241 # f0f0f0f + 180: 0020cf33 xor t5,ra,sp + 184: 00000013 nop + 188: 00000013 nop + 18c: 000f0313 mv t1,t5 + 190: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 194: 00200293 li t0,2 + 198: fc521ce3 bne tp,t0,170 + 19c: 0ff01eb7 lui t4,0xff01 + 1a0: ff0e8e93 addi t4,t4,-16 # ff00ff0 + 1a4: 00b00193 li gp,11 + 1a8: 33d31063 bne t1,t4,4c8 + +000001ac : + 1ac: 00000213 li tp,0 + 1b0: ff0100b7 lui ra,0xff010 + 1b4: f0008093 addi ra,ra,-256 # ff00ff00 + 1b8: 0f0f1137 lui sp,0xf0f1 + 1bc: f0f10113 addi sp,sp,-241 # f0f0f0f + 1c0: 0020cf33 xor t5,ra,sp + 1c4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1c8: 00200293 li t0,2 + 1cc: fe5212e3 bne tp,t0,1b0 + 1d0: f00ffeb7 lui t4,0xf00ff + 1d4: 00fe8e93 addi t4,t4,15 # f00ff00f + 1d8: 00c00193 li gp,12 + 1dc: 2fdf1663 bne t5,t4,4c8 + +000001e0 : + 1e0: 00000213 li tp,0 + 1e4: 0ff010b7 lui ra,0xff01 + 1e8: ff008093 addi ra,ra,-16 # ff00ff0 + 1ec: f0f0f137 lui sp,0xf0f0f + 1f0: 0f010113 addi sp,sp,240 # f0f0f0f0 + 1f4: 00000013 nop + 1f8: 0020cf33 xor t5,ra,sp + 1fc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 200: 00200293 li t0,2 + 204: fe5210e3 bne tp,t0,1e4 + 208: ff010eb7 lui t4,0xff010 + 20c: f00e8e93 addi t4,t4,-256 # ff00ff00 + 210: 00d00193 li gp,13 + 214: 2bdf1a63 bne t5,t4,4c8 + +00000218 : + 218: 00000213 li tp,0 + 21c: 00ff00b7 lui ra,0xff0 + 220: 0ff08093 addi ra,ra,255 # ff00ff + 224: 0f0f1137 lui sp,0xf0f1 + 228: f0f10113 addi sp,sp,-241 # f0f0f0f + 22c: 00000013 nop + 230: 00000013 nop + 234: 0020cf33 xor t5,ra,sp + 238: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 23c: 00200293 li t0,2 + 240: fc521ee3 bne tp,t0,21c + 244: 0ff01eb7 lui t4,0xff01 + 248: ff0e8e93 addi t4,t4,-16 # ff00ff0 + 24c: 00e00193 li gp,14 + 250: 27df1c63 bne t5,t4,4c8 + +00000254 : + 254: 00000213 li tp,0 + 258: ff0100b7 lui ra,0xff010 + 25c: f0008093 addi ra,ra,-256 # ff00ff00 + 260: 00000013 nop + 264: 0f0f1137 lui sp,0xf0f1 + 268: f0f10113 addi sp,sp,-241 # f0f0f0f + 26c: 0020cf33 xor t5,ra,sp + 270: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 274: 00200293 li t0,2 + 278: fe5210e3 bne tp,t0,258 + 27c: f00ffeb7 lui t4,0xf00ff + 280: 00fe8e93 addi t4,t4,15 # f00ff00f + 284: 00f00193 li gp,15 + 288: 25df1063 bne t5,t4,4c8 + +0000028c : + 28c: 00000213 li tp,0 + 290: 0ff010b7 lui ra,0xff01 + 294: ff008093 addi ra,ra,-16 # ff00ff0 + 298: 00000013 nop + 29c: f0f0f137 lui sp,0xf0f0f + 2a0: 0f010113 addi sp,sp,240 # f0f0f0f0 + 2a4: 00000013 nop + 2a8: 0020cf33 xor t5,ra,sp + 2ac: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2b0: 00200293 li t0,2 + 2b4: fc521ee3 bne tp,t0,290 + 2b8: ff010eb7 lui t4,0xff010 + 2bc: f00e8e93 addi t4,t4,-256 # ff00ff00 + 2c0: 01000193 li gp,16 + 2c4: 21df1263 bne t5,t4,4c8 + +000002c8 : + 2c8: 00000213 li tp,0 + 2cc: 00ff00b7 lui ra,0xff0 + 2d0: 0ff08093 addi ra,ra,255 # ff00ff + 2d4: 00000013 nop + 2d8: 00000013 nop + 2dc: 0f0f1137 lui sp,0xf0f1 + 2e0: f0f10113 addi sp,sp,-241 # f0f0f0f + 2e4: 0020cf33 xor t5,ra,sp + 2e8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 2ec: 00200293 li t0,2 + 2f0: fc521ee3 bne tp,t0,2cc + 2f4: 0ff01eb7 lui t4,0xff01 + 2f8: ff0e8e93 addi t4,t4,-16 # ff00ff0 + 2fc: 01100193 li gp,17 + 300: 1ddf1463 bne t5,t4,4c8 + +00000304 : + 304: 00000213 li tp,0 + 308: 0f0f1137 lui sp,0xf0f1 + 30c: f0f10113 addi sp,sp,-241 # f0f0f0f + 310: ff0100b7 lui ra,0xff010 + 314: f0008093 addi ra,ra,-256 # ff00ff00 + 318: 0020cf33 xor t5,ra,sp + 31c: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 320: 00200293 li t0,2 + 324: fe5212e3 bne tp,t0,308 + 328: f00ffeb7 lui t4,0xf00ff + 32c: 00fe8e93 addi t4,t4,15 # f00ff00f + 330: 01200193 li gp,18 + 334: 19df1a63 bne t5,t4,4c8 + +00000338 : + 338: 00000213 li tp,0 + 33c: f0f0f137 lui sp,0xf0f0f + 340: 0f010113 addi sp,sp,240 # f0f0f0f0 + 344: 0ff010b7 lui ra,0xff01 + 348: ff008093 addi ra,ra,-16 # ff00ff0 + 34c: 00000013 nop + 350: 0020cf33 xor t5,ra,sp + 354: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 358: 00200293 li t0,2 + 35c: fe5210e3 bne tp,t0,33c + 360: ff010eb7 lui t4,0xff010 + 364: f00e8e93 addi t4,t4,-256 # ff00ff00 + 368: 01300193 li gp,19 + 36c: 15df1e63 bne t5,t4,4c8 + +00000370 : + 370: 00000213 li tp,0 + 374: 0f0f1137 lui sp,0xf0f1 + 378: f0f10113 addi sp,sp,-241 # f0f0f0f + 37c: 00ff00b7 lui ra,0xff0 + 380: 0ff08093 addi ra,ra,255 # ff00ff + 384: 00000013 nop + 388: 00000013 nop + 38c: 0020cf33 xor t5,ra,sp + 390: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 394: 00200293 li t0,2 + 398: fc521ee3 bne tp,t0,374 + 39c: 0ff01eb7 lui t4,0xff01 + 3a0: ff0e8e93 addi t4,t4,-16 # ff00ff0 + 3a4: 01400193 li gp,20 + 3a8: 13df1063 bne t5,t4,4c8 + +000003ac : + 3ac: 00000213 li tp,0 + 3b0: 0f0f1137 lui sp,0xf0f1 + 3b4: f0f10113 addi sp,sp,-241 # f0f0f0f + 3b8: 00000013 nop + 3bc: ff0100b7 lui ra,0xff010 + 3c0: f0008093 addi ra,ra,-256 # ff00ff00 + 3c4: 0020cf33 xor t5,ra,sp + 3c8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 3cc: 00200293 li t0,2 + 3d0: fe5210e3 bne tp,t0,3b0 + 3d4: f00ffeb7 lui t4,0xf00ff + 3d8: 00fe8e93 addi t4,t4,15 # f00ff00f + 3dc: 01500193 li gp,21 + 3e0: 0fdf1463 bne t5,t4,4c8 + +000003e4 : + 3e4: 00000213 li tp,0 + 3e8: f0f0f137 lui sp,0xf0f0f + 3ec: 0f010113 addi sp,sp,240 # f0f0f0f0 + 3f0: 00000013 nop + 3f4: 0ff010b7 lui ra,0xff01 + 3f8: ff008093 addi ra,ra,-16 # ff00ff0 + 3fc: 00000013 nop + 400: 0020cf33 xor t5,ra,sp + 404: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 408: 00200293 li t0,2 + 40c: fc521ee3 bne tp,t0,3e8 + 410: ff010eb7 lui t4,0xff010 + 414: f00e8e93 addi t4,t4,-256 # ff00ff00 + 418: 01600193 li gp,22 + 41c: 0bdf1663 bne t5,t4,4c8 + +00000420 : + 420: 00000213 li tp,0 + 424: 0f0f1137 lui sp,0xf0f1 + 428: f0f10113 addi sp,sp,-241 # f0f0f0f + 42c: 00000013 nop + 430: 00000013 nop + 434: 00ff00b7 lui ra,0xff0 + 438: 0ff08093 addi ra,ra,255 # ff00ff + 43c: 0020cf33 xor t5,ra,sp + 440: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 444: 00200293 li t0,2 + 448: fc521ee3 bne tp,t0,424 + 44c: 0ff01eb7 lui t4,0xff01 + 450: ff0e8e93 addi t4,t4,-16 # ff00ff0 + 454: 01700193 li gp,23 + 458: 07df1863 bne t5,t4,4c8 + +0000045c : + 45c: ff0100b7 lui ra,0xff010 + 460: f0008093 addi ra,ra,-256 # ff00ff00 + 464: 00104133 xor sp,zero,ra + 468: ff010eb7 lui t4,0xff010 + 46c: f00e8e93 addi t4,t4,-256 # ff00ff00 + 470: 01800193 li gp,24 + 474: 05d11a63 bne sp,t4,4c8 + +00000478 : + 478: 00ff00b7 lui ra,0xff0 + 47c: 0ff08093 addi ra,ra,255 # ff00ff + 480: 0000c133 xor sp,ra,zero + 484: 00ff0eb7 lui t4,0xff0 + 488: 0ffe8e93 addi t4,t4,255 # ff00ff + 48c: 01900193 li gp,25 + 490: 03d11c63 bne sp,t4,4c8 + +00000494 : + 494: 000040b3 xor ra,zero,zero + 498: 00000e93 li t4,0 + 49c: 01a00193 li gp,26 + 4a0: 03d09463 bne ra,t4,4c8 + +000004a4 : + 4a4: 111110b7 lui ra,0x11111 + 4a8: 11108093 addi ra,ra,273 # 11111111 + 4ac: 22222137 lui sp,0x22222 + 4b0: 22210113 addi sp,sp,546 # 22222222 + 4b4: 0020c033 xor zero,ra,sp + 4b8: 00000e93 li t4,0 + 4bc: 01b00193 li gp,27 + 4c0: 01d01463 bne zero,t4,4c8 + 4c4: 00301863 bne zero,gp,4d4 + +000004c8 : + 4c8: 00100d13 li s10,1 + 4cc: 00000d93 li s11,0 + +000004d0 : + 4d0: 0000006f j 4d0 + +000004d4 : + 4d4: 00100d13 li s10,1 + 4d8: 00100d93 li s11,1 + +000004dc : + 4dc: 0000006f j 4dc + ... + +Disassembly of section .tohost: + +00000540 : + ... + +00000580 : + ... diff --git a/tests/isa/generated/rv32ui-p-xor.verilog b/tests/isa/generated/rv32ui-p-xor.verilog new file mode 100644 index 0000000..747b893 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-xor.verilog @@ -0,0 +1,88 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 00 01 FF 93 80 00 F0 +37 11 0F 0F 13 01 F1 F0 33 CF 20 00 B7 FE 0F F0 +93 8E FE 00 93 01 20 00 63 10 DF 4B B7 10 F0 0F +93 80 00 FF 37 F1 F0 F0 13 01 01 0F 33 CF 20 00 +B7 0E 01 FF 93 8E 0E F0 93 01 30 00 63 1E DF 47 +B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 +33 CF 20 00 B7 1E F0 0F 93 8E 0E FF 93 01 40 00 +63 1C DF 45 B7 F0 0F F0 93 80 F0 00 37 F1 F0 F0 +13 01 01 0F 33 CF 20 00 B7 0E FF 00 93 8E FE 0F +93 01 50 00 63 1A DF 43 B7 00 01 FF 93 80 00 F0 +37 11 0F 0F 13 01 F1 F0 B3 C0 20 00 B7 FE 0F F0 +93 8E FE 00 93 01 60 00 63 98 D0 41 B7 00 01 FF +93 80 00 F0 37 11 0F 0F 13 01 F1 F0 33 C1 20 00 +B7 FE 0F F0 93 8E FE 00 93 01 70 00 63 16 D1 3F +B7 00 01 FF 93 80 00 F0 B3 C0 10 00 93 0E 00 00 +93 01 80 00 63 9A D0 3D 13 02 00 00 B7 00 01 FF +93 80 00 F0 37 11 0F 0F 13 01 F1 F0 33 CF 20 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE +B7 FE 0F F0 93 8E FE 00 93 01 90 00 63 1E D3 39 +13 02 00 00 B7 10 F0 0F 93 80 00 FF 37 F1 F0 F0 +13 01 01 0F 33 CF 20 00 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 1E 52 FC B7 0E 01 FF +93 8E 0E F0 93 01 A0 00 63 10 D3 37 13 02 00 00 +B7 00 FF 00 93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 +33 CF 20 00 13 00 00 00 13 00 00 00 13 03 0F 00 +13 02 12 00 93 02 20 00 E3 1C 52 FC B7 1E F0 0F +93 8E 0E FF 93 01 B0 00 63 10 D3 33 13 02 00 00 +B7 00 01 FF 93 80 00 F0 37 11 0F 0F 13 01 F1 F0 +33 CF 20 00 13 02 12 00 93 02 20 00 E3 12 52 FE +B7 FE 0F F0 93 8E FE 00 93 01 C0 00 63 16 DF 2F +13 02 00 00 B7 10 F0 0F 93 80 00 FF 37 F1 F0 F0 +13 01 01 0F 13 00 00 00 33 CF 20 00 13 02 12 00 +93 02 20 00 E3 10 52 FE B7 0E 01 FF 93 8E 0E F0 +93 01 D0 00 63 1A DF 2B 13 02 00 00 B7 00 FF 00 +93 80 F0 0F 37 11 0F 0F 13 01 F1 F0 13 00 00 00 +13 00 00 00 33 CF 20 00 13 02 12 00 93 02 20 00 +E3 1E 52 FC B7 1E F0 0F 93 8E 0E FF 93 01 E0 00 +63 1C DF 27 13 02 00 00 B7 00 01 FF 93 80 00 F0 +13 00 00 00 37 11 0F 0F 13 01 F1 F0 33 CF 20 00 +13 02 12 00 93 02 20 00 E3 10 52 FE B7 FE 0F F0 +93 8E FE 00 93 01 F0 00 63 10 DF 25 13 02 00 00 +B7 10 F0 0F 93 80 00 FF 13 00 00 00 37 F1 F0 F0 +13 01 01 0F 13 00 00 00 33 CF 20 00 13 02 12 00 +93 02 20 00 E3 1E 52 FC B7 0E 01 FF 93 8E 0E F0 +93 01 00 01 63 12 DF 21 13 02 00 00 B7 00 FF 00 +93 80 F0 0F 13 00 00 00 13 00 00 00 37 11 0F 0F +13 01 F1 F0 33 CF 20 00 13 02 12 00 93 02 20 00 +E3 1E 52 FC B7 1E F0 0F 93 8E 0E FF 93 01 10 01 +63 14 DF 1D 13 02 00 00 37 11 0F 0F 13 01 F1 F0 +B7 00 01 FF 93 80 00 F0 33 CF 20 00 13 02 12 00 +93 02 20 00 E3 12 52 FE B7 FE 0F F0 93 8E FE 00 +93 01 20 01 63 1A DF 19 13 02 00 00 37 F1 F0 F0 +13 01 01 0F B7 10 F0 0F 93 80 00 FF 13 00 00 00 +33 CF 20 00 13 02 12 00 93 02 20 00 E3 10 52 FE +B7 0E 01 FF 93 8E 0E F0 93 01 30 01 63 1E DF 15 +13 02 00 00 37 11 0F 0F 13 01 F1 F0 B7 00 FF 00 +93 80 F0 0F 13 00 00 00 13 00 00 00 33 CF 20 00 +13 02 12 00 93 02 20 00 E3 1E 52 FC B7 1E F0 0F +93 8E 0E FF 93 01 40 01 63 10 DF 13 13 02 00 00 +37 11 0F 0F 13 01 F1 F0 13 00 00 00 B7 00 01 FF +93 80 00 F0 33 CF 20 00 13 02 12 00 93 02 20 00 +E3 10 52 FE B7 FE 0F F0 93 8E FE 00 93 01 50 01 +63 14 DF 0F 13 02 00 00 37 F1 F0 F0 13 01 01 0F +13 00 00 00 B7 10 F0 0F 93 80 00 FF 13 00 00 00 +33 CF 20 00 13 02 12 00 93 02 20 00 E3 1E 52 FC +B7 0E 01 FF 93 8E 0E F0 93 01 60 01 63 16 DF 0B +13 02 00 00 37 11 0F 0F 13 01 F1 F0 13 00 00 00 +13 00 00 00 B7 00 FF 00 93 80 F0 0F 33 CF 20 00 +13 02 12 00 93 02 20 00 E3 1E 52 FC B7 1E F0 0F +93 8E 0E FF 93 01 70 01 63 18 DF 07 B7 00 01 FF +93 80 00 F0 33 41 10 00 B7 0E 01 FF 93 8E 0E F0 +93 01 80 01 63 1A D1 05 B7 00 FF 00 93 80 F0 0F +33 C1 00 00 B7 0E FF 00 93 8E FE 0F 93 01 90 01 +63 1C D1 03 B3 40 00 00 93 0E 00 00 93 01 A0 01 +63 94 D0 03 B7 10 11 11 93 80 10 11 37 21 22 22 +13 01 21 22 33 C0 20 00 93 0E 00 00 93 01 B0 01 +63 14 D0 01 63 18 30 00 13 0D 10 00 93 0D 00 00 +6F 00 00 00 13 0D 10 00 93 0D 10 00 6F 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 +@00000540 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/generated/rv32ui-p-xori b/tests/isa/generated/rv32ui-p-xori new file mode 100644 index 0000000..8141dfe Binary files /dev/null and b/tests/isa/generated/rv32ui-p-xori differ diff --git a/tests/isa/generated/rv32ui-p-xori.bin b/tests/isa/generated/rv32ui-p-xori.bin new file mode 100644 index 0000000..4d1ede4 Binary files /dev/null and b/tests/isa/generated/rv32ui-p-xori.bin differ diff --git a/tests/isa/generated/rv32ui-p-xori.dump b/tests/isa/generated/rv32ui-p-xori.dump new file mode 100644 index 0000000..eaeda26 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-xori.dump @@ -0,0 +1,178 @@ + +generated/rv32ui-p-xori: file format elf32-littleriscv + + +Disassembly of section .text.init: + +00000000 <_start>: + 0: 00000d13 li s10,0 + 4: 00000d93 li s11,0 + +00000008 : + 8: 00ff10b7 lui ra,0xff1 + c: f0008093 addi ra,ra,-256 # ff0f00 + 10: f0f0cf13 xori t5,ra,-241 + 14: ff00feb7 lui t4,0xff00f + 18: 00fe8e93 addi t4,t4,15 # ff00f00f + 1c: 00200193 li gp,2 + 20: 1ddf1663 bne t5,t4,1ec + +00000024 : + 24: 0ff010b7 lui ra,0xff01 + 28: ff008093 addi ra,ra,-16 # ff00ff0 + 2c: 0f00cf13 xori t5,ra,240 + 30: 0ff01eb7 lui t4,0xff01 + 34: f00e8e93 addi t4,t4,-256 # ff00f00 + 38: 00300193 li gp,3 + 3c: 1bdf1863 bne t5,t4,1ec + +00000040 : + 40: 00ff10b7 lui ra,0xff1 + 44: 8ff08093 addi ra,ra,-1793 # ff08ff + 48: 70f0cf13 xori t5,ra,1807 + 4c: 00ff1eb7 lui t4,0xff1 + 50: ff0e8e93 addi t4,t4,-16 # ff0ff0 + 54: 00400193 li gp,4 + 58: 19df1a63 bne t5,t4,1ec + +0000005c : + 5c: f00ff0b7 lui ra,0xf00ff + 60: 00f08093 addi ra,ra,15 # f00ff00f + 64: 0f00cf13 xori t5,ra,240 + 68: f00ffeb7 lui t4,0xf00ff + 6c: 0ffe8e93 addi t4,t4,255 # f00ff0ff + 70: 00500193 li gp,5 + 74: 17df1c63 bne t5,t4,1ec + +00000078 : + 78: ff00f0b7 lui ra,0xff00f + 7c: 70008093 addi ra,ra,1792 # ff00f700 + 80: 70f0c093 xori ra,ra,1807 + 84: ff00feb7 lui t4,0xff00f + 88: 00fe8e93 addi t4,t4,15 # ff00f00f + 8c: 00600193 li gp,6 + 90: 15d09e63 bne ra,t4,1ec + +00000094 : + 94: 00000213 li tp,0 + 98: 0ff010b7 lui ra,0xff01 + 9c: ff008093 addi ra,ra,-16 # ff00ff0 + a0: 0f00cf13 xori t5,ra,240 + a4: 000f0313 mv t1,t5 + a8: 00120213 addi tp,tp,1 # 1 <_start+0x1> + ac: 00200293 li t0,2 + b0: fe5214e3 bne tp,t0,98 + b4: 0ff01eb7 lui t4,0xff01 + b8: f00e8e93 addi t4,t4,-256 # ff00f00 + bc: 00700193 li gp,7 + c0: 13d31663 bne t1,t4,1ec + +000000c4 : + c4: 00000213 li tp,0 + c8: 00ff10b7 lui ra,0xff1 + cc: 8ff08093 addi ra,ra,-1793 # ff08ff + d0: 70f0cf13 xori t5,ra,1807 + d4: 00000013 nop + d8: 000f0313 mv t1,t5 + dc: 00120213 addi tp,tp,1 # 1 <_start+0x1> + e0: 00200293 li t0,2 + e4: fe5212e3 bne tp,t0,c8 + e8: 00ff1eb7 lui t4,0xff1 + ec: ff0e8e93 addi t4,t4,-16 # ff0ff0 + f0: 00800193 li gp,8 + f4: 0fd31c63 bne t1,t4,1ec + +000000f8 : + f8: 00000213 li tp,0 + fc: f00ff0b7 lui ra,0xf00ff + 100: 00f08093 addi ra,ra,15 # f00ff00f + 104: 0f00cf13 xori t5,ra,240 + 108: 00000013 nop + 10c: 00000013 nop + 110: 000f0313 mv t1,t5 + 114: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 118: 00200293 li t0,2 + 11c: fe5210e3 bne tp,t0,fc + 120: f00ffeb7 lui t4,0xf00ff + 124: 0ffe8e93 addi t4,t4,255 # f00ff0ff + 128: 00900193 li gp,9 + 12c: 0dd31063 bne t1,t4,1ec + +00000130 : + 130: 00000213 li tp,0 + 134: 0ff010b7 lui ra,0xff01 + 138: ff008093 addi ra,ra,-16 # ff00ff0 + 13c: 0f00cf13 xori t5,ra,240 + 140: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 144: 00200293 li t0,2 + 148: fe5216e3 bne tp,t0,134 + 14c: 0ff01eb7 lui t4,0xff01 + 150: f00e8e93 addi t4,t4,-256 # ff00f00 + 154: 00a00193 li gp,10 + 158: 09df1a63 bne t5,t4,1ec + +0000015c : + 15c: 00000213 li tp,0 + 160: 00ff10b7 lui ra,0xff1 + 164: fff08093 addi ra,ra,-1 # ff0fff + 168: 00000013 nop + 16c: 00f0cf13 xori t5,ra,15 + 170: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 174: 00200293 li t0,2 + 178: fe5214e3 bne tp,t0,160 + 17c: 00ff1eb7 lui t4,0xff1 + 180: ff0e8e93 addi t4,t4,-16 # ff0ff0 + 184: 00b00193 li gp,11 + 188: 07df1263 bne t5,t4,1ec + +0000018c : + 18c: 00000213 li tp,0 + 190: f00ff0b7 lui ra,0xf00ff + 194: 00f08093 addi ra,ra,15 # f00ff00f + 198: 00000013 nop + 19c: 00000013 nop + 1a0: 0f00cf13 xori t5,ra,240 + 1a4: 00120213 addi tp,tp,1 # 1 <_start+0x1> + 1a8: 00200293 li t0,2 + 1ac: fe5212e3 bne tp,t0,190 + 1b0: f00ffeb7 lui t4,0xf00ff + 1b4: 0ffe8e93 addi t4,t4,255 # f00ff0ff + 1b8: 00c00193 li gp,12 + 1bc: 03df1863 bne t5,t4,1ec + +000001c0 : + 1c0: 0f004093 xori ra,zero,240 + 1c4: 0f000e93 li t4,240 + 1c8: 00d00193 li gp,13 + 1cc: 03d09063 bne ra,t4,1ec + +000001d0 : + 1d0: 00ff00b7 lui ra,0xff0 + 1d4: 0ff08093 addi ra,ra,255 # ff00ff + 1d8: 70f0c013 xori zero,ra,1807 + 1dc: 00000e93 li t4,0 + 1e0: 00e00193 li gp,14 + 1e4: 01d01463 bne zero,t4,1ec + 1e8: 00301863 bne zero,gp,1f8 + +000001ec : + 1ec: 00100d13 li s10,1 + 1f0: 00000d93 li s11,0 + +000001f4 : + 1f4: 0000006f j 1f4 + +000001f8 : + 1f8: 00100d13 li s10,1 + 1fc: 00100d93 li s11,1 + +00000200 : + 200: 0000006f j 200 + +Disassembly of section .tohost: + +00000240 : + ... + +00000280 : + ... diff --git a/tests/isa/generated/rv32ui-p-xori.verilog b/tests/isa/generated/rv32ui-p-xori.verilog new file mode 100644 index 0000000..9a39da8 --- /dev/null +++ b/tests/isa/generated/rv32ui-p-xori.verilog @@ -0,0 +1,40 @@ +@00000000 +13 0D 00 00 93 0D 00 00 B7 10 FF 00 93 80 00 F0 +13 CF F0 F0 B7 FE 00 FF 93 8E FE 00 93 01 20 00 +63 16 DF 1D B7 10 F0 0F 93 80 00 FF 13 CF 00 0F +B7 1E F0 0F 93 8E 0E F0 93 01 30 00 63 18 DF 1B +B7 10 FF 00 93 80 F0 8F 13 CF F0 70 B7 1E FF 00 +93 8E 0E FF 93 01 40 00 63 1A DF 19 B7 F0 0F F0 +93 80 F0 00 13 CF 00 0F B7 FE 0F F0 93 8E FE 0F +93 01 50 00 63 1C DF 17 B7 F0 00 FF 93 80 00 70 +93 C0 F0 70 B7 FE 00 FF 93 8E FE 00 93 01 60 00 +63 9E D0 15 13 02 00 00 B7 10 F0 0F 93 80 00 FF +13 CF 00 0F 13 03 0F 00 13 02 12 00 93 02 20 00 +E3 14 52 FE B7 1E F0 0F 93 8E 0E F0 93 01 70 00 +63 16 D3 13 13 02 00 00 B7 10 FF 00 93 80 F0 8F +13 CF F0 70 13 00 00 00 13 03 0F 00 13 02 12 00 +93 02 20 00 E3 12 52 FE B7 1E FF 00 93 8E 0E FF +93 01 80 00 63 1C D3 0F 13 02 00 00 B7 F0 0F F0 +93 80 F0 00 13 CF 00 0F 13 00 00 00 13 00 00 00 +13 03 0F 00 13 02 12 00 93 02 20 00 E3 10 52 FE +B7 FE 0F F0 93 8E FE 0F 93 01 90 00 63 10 D3 0D +13 02 00 00 B7 10 F0 0F 93 80 00 FF 13 CF 00 0F +13 02 12 00 93 02 20 00 E3 16 52 FE B7 1E F0 0F +93 8E 0E F0 93 01 A0 00 63 1A DF 09 13 02 00 00 +B7 10 FF 00 93 80 F0 FF 13 00 00 00 13 CF F0 00 +13 02 12 00 93 02 20 00 E3 14 52 FE B7 1E FF 00 +93 8E 0E FF 93 01 B0 00 63 12 DF 07 13 02 00 00 +B7 F0 0F F0 93 80 F0 00 13 00 00 00 13 00 00 00 +13 CF 00 0F 13 02 12 00 93 02 20 00 E3 12 52 FE +B7 FE 0F F0 93 8E FE 0F 93 01 C0 00 63 18 DF 03 +93 40 00 0F 93 0E 00 0F 93 01 D0 00 63 90 D0 03 +B7 00 FF 00 93 80 F0 0F 13 C0 F0 70 93 0E 00 00 +93 01 E0 00 63 14 D0 01 63 18 30 00 13 0D 10 00 +93 0D 00 00 6F 00 00 00 13 0D 10 00 93 0D 10 00 +6F 00 00 00 +@00000240 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 diff --git a/tests/isa/link.ld b/tests/isa/link.ld new file mode 100644 index 0000000..e9c685d --- /dev/null +++ b/tests/isa/link.ld @@ -0,0 +1,14 @@ +OUTPUT_ARCH( "riscv" ) +ENTRY(_start) + +SECTIONS +{ + . = 0x00000000; + .text.init : { *(.text.init) } + /*.tohost ALIGN(0x1000) : { *(.tohost) }*/ + /*.text ALIGN(0x1000) : { *(.text) }*/ + .data ALIGN(0x1000) : { *(.data) } + .bss : { *(.bss) } + _end = .; +} + diff --git a/tests/isa/riscv_test.h b/tests/isa/riscv_test.h new file mode 100644 index 0000000..74ae810 --- /dev/null +++ b/tests/isa/riscv_test.h @@ -0,0 +1,159 @@ +// See LICENSE for license details. + +#ifndef __RISCV_TEST_H +#define __RISCV_TEST_H + +#ifndef __riscv_xlen +#define __riscv_xlen 32 +#endif + +//----------------------------------------------------------------------- +// Begin Macro +//----------------------------------------------------------------------- + +#define RVTEST_RV64U \ + .macro init; \ + .endm + +#define RVTEST_RV64UF \ + .macro init; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV32U \ + .macro init; \ + .endm + +#define RVTEST_RV32UF \ + .macro init; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV64M \ + .macro init; \ + RVTEST_ENABLE_MACHINE; \ + .endm + +#define RVTEST_RV64S \ + .macro init; \ + RVTEST_ENABLE_SUPERVISOR; \ + .endm + +#define RVTEST_RV32M \ + .macro init; \ + RVTEST_ENABLE_MACHINE; \ + .endm + +#define RVTEST_RV32S \ + .macro init; \ + RVTEST_ENABLE_SUPERVISOR; \ + .endm + +#if __riscv_xlen == 64 +# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1: +#else +# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: +#endif + +#define INIT_PMP \ + la t0, 1f; \ + csrw mtvec, t0; \ + li t0, -1; /* Set up a PMP to permit all accesses */ \ + csrw pmpaddr0, t0; \ + li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \ + csrw pmpcfg0, t0; \ + .align 2; \ +1: + +#define INIT_SPTBR \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi sptbr, 0; \ + .align 2; \ +1: + +#define DELEGATE_NO_TRAPS \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi medeleg, 0; \ + csrwi mideleg, 0; \ + csrwi mie, 0; \ + .align 2; \ +1: + +#define RVTEST_ENABLE_SUPERVISOR \ + li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \ + csrs mstatus, a0; \ + li a0, SIP_SSIP | SIP_STIP; \ + csrs mideleg, a0; \ + +#define RVTEST_ENABLE_MACHINE \ + li a0, MSTATUS_MPP; \ + csrs mstatus, a0; \ + +#define RVTEST_FP_ENABLE \ + li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \ + csrs mstatus, a0; \ + csrwi fcsr, 0 + +#define RISCV_MULTICORE_DISABLE \ + csrr a0, mhartid; \ + 1: bnez a0, 1b + +#define EXTRA_TVEC_USER +#define EXTRA_TVEC_MACHINE +#define EXTRA_INIT +#define EXTRA_INIT_TIMER + +#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */ + +#define RVTEST_CODE_BEGIN \ + .section .text.init; \ + .align 6; \ + .globl _start; \ +_start: \ + li x26, 0x00; \ + li x27, 0x00; + +//----------------------------------------------------------------------- +// End Macro +//----------------------------------------------------------------------- + +#define RVTEST_CODE_END + + +//----------------------------------------------------------------------- +// Pass/Fail Macro +//----------------------------------------------------------------------- + +#define RVTEST_PASS \ + li x26, 0x01; \ + li x27, 0x01; \ +loop_pass: \ + j loop_pass + +#define TESTNUM gp + +#define RVTEST_FAIL \ + li x26, 0x01; \ + li x27, 0x00; \ +loop_fail: \ + j loop_fail + +//----------------------------------------------------------------------- +// Data Section Macro +//----------------------------------------------------------------------- + +#define EXTRA_DATA + +#define RVTEST_DATA_BEGIN \ + EXTRA_DATA \ + .pushsection .tohost,"aw",@progbits; \ + .align 6; .global tohost; tohost: .dword 0; \ + .align 6; .global fromhost; fromhost: .dword 0; \ + .popsection; \ + .align 4; .global begin_signature; begin_signature: + +#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: + +#endif diff --git a/tests/isa/rv32ui/Makefrag b/tests/isa/rv32ui/Makefrag new file mode 100644 index 0000000..55e4078 --- /dev/null +++ b/tests/isa/rv32ui/Makefrag @@ -0,0 +1,24 @@ +#======================================================================= +# Makefrag for rv32ui tests +#----------------------------------------------------------------------- + +rv32ui_sc_tests = \ + simple \ + add addi \ + and andi \ + auipc \ + beq bge bgeu blt bltu bne \ + fence_i \ + jal jalr \ + lb lbu lh lhu lw \ + lui \ + or ori \ + sb sh sw \ + sll slli \ + slt slti sltiu sltu \ + sra srai \ + srl srli \ + sub \ + xor xori \ + +rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests)) diff --git a/tests/isa/rv32ui/add.S b/tests/isa/rv32ui/add.S new file mode 100644 index 0000000..0696428 --- /dev/null +++ b/tests/isa/rv32ui/add.S @@ -0,0 +1,85 @@ +# See LICENSE for license details. + +#***************************************************************************** +# add.S +#----------------------------------------------------------------------------- +# +# Test add instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, add, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, add, 0x00000002, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, add, 0x0000000a, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, add, 0xffffffffffff8000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, add, 0xffffffff80000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, add, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, add, 0x0000000000007fff, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, add, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, add, 0x0000000080007ffe, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, add, 0xffffffff80007fff, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, add, 0x000000007fff7fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, add, 0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, add, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, add, 0xfffffffffffffffe, 0xffffffffffffffff, 0xffffffffffffffff ); + + TEST_RR_OP( 16, add, 0x0000000080000000, 0x0000000000000001, 0x000000007fffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, add, 24, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 18, add, 25, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 19, add, 26, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, add, 24, 13, 11 ); + TEST_RR_DEST_BYPASS( 21, 1, add, 25, 14, 11 ); + TEST_RR_DEST_BYPASS( 22, 2, add, 26, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, add, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, add, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, add, 26, 15, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, add, 24, 13, 11 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, add, 25, 14, 11 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, add, 26, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, add, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, add, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, add, 26, 15, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, add, 24, 13, 11 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, add, 25, 14, 11 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, add, 26, 15, 11 ); + + TEST_RR_ZEROSRC1( 35, add, 15, 15 ); + TEST_RR_ZEROSRC2( 36, add, 32, 32 ); + TEST_RR_ZEROSRC12( 37, add, 0 ); + TEST_RR_ZERODEST( 38, add, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/addi.S b/tests/isa/rv32ui/addi.S new file mode 100644 index 0000000..e6b67ca --- /dev/null +++ b/tests/isa/rv32ui/addi.S @@ -0,0 +1,71 @@ +# See LICENSE for license details. + +#***************************************************************************** +# addi.S +#----------------------------------------------------------------------------- +# +# Test addi instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, addi, 0x00000000, 0x00000000, 0x000 ); + TEST_IMM_OP( 3, addi, 0x00000002, 0x00000001, 0x001 ); + TEST_IMM_OP( 4, addi, 0x0000000a, 0x00000003, 0x007 ); + + TEST_IMM_OP( 5, addi, 0xfffffffffffff800, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 6, addi, 0xffffffff80000000, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 7, addi, 0xffffffff7ffff800, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 8, addi, 0x00000000000007ff, 0x00000000, 0x7ff ); + TEST_IMM_OP( 9, addi, 0x000000007fffffff, 0x7fffffff, 0x000 ); + TEST_IMM_OP( 10, addi, 0x00000000800007fe, 0x7fffffff, 0x7ff ); + + TEST_IMM_OP( 11, addi, 0xffffffff800007ff, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 12, addi, 0x000000007ffff7ff, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 13, addi, 0xffffffffffffffff, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 14, addi, 0x0000000000000000, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 15, addi, 0xfffffffffffffffe, 0xffffffffffffffff, 0xfff ); + + TEST_IMM_OP( 16, addi, 0x0000000080000000, 0x7fffffff, 0x001 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, addi, 24, 13, 11 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, addi, 24, 13, 11 ); + TEST_IMM_DEST_BYPASS( 19, 1, addi, 23, 13, 10 ); + TEST_IMM_DEST_BYPASS( 20, 2, addi, 22, 13, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, addi, 24, 13, 11 ); + TEST_IMM_SRC1_BYPASS( 22, 1, addi, 23, 13, 10 ); + TEST_IMM_SRC1_BYPASS( 23, 2, addi, 22, 13, 9 ); + + TEST_IMM_ZEROSRC1( 24, addi, 32, 32 ); + TEST_IMM_ZERODEST( 25, addi, 33, 50 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/and.S b/tests/isa/rv32ui/and.S new file mode 100644 index 0000000..3f63790 --- /dev/null +++ b/tests/isa/rv32ui/and.S @@ -0,0 +1,69 @@ +# See LICENSE for license details. + +#***************************************************************************** +# and.S +#----------------------------------------------------------------------------- +# +# Test and instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_OP( 3, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_OP( 4, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_OP( 5, and, 0xf000f000, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_EQ_DEST( 8, and, 0xff00ff00, 0xff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, and, 0x0f000f00, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, and, 0x00f000f0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, and, 0x000f000f, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, and, 0, 0xff00ff00 ); + TEST_RR_ZEROSRC2( 25, and, 0, 0x00ff00ff ); + TEST_RR_ZEROSRC12( 26, and, 0 ); + TEST_RR_ZERODEST( 27, and, 0x11111111, 0x22222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/andi.S b/tests/isa/rv32ui/andi.S new file mode 100644 index 0000000..913af9d --- /dev/null +++ b/tests/isa/rv32ui/andi.S @@ -0,0 +1,55 @@ +# See LICENSE for license details. + +#***************************************************************************** +# andi.S +#----------------------------------------------------------------------------- +# +# Test andi instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, andi, 0xff00ff00, 0xff00ff00, 0xf0f ); + TEST_IMM_OP( 3, andi, 0x000000f0, 0x0ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, andi, 0x0000000f, 0x00ff00ff, 0x70f ); + TEST_IMM_OP( 5, andi, 0x00000000, 0xf00ff00f, 0x0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 6, andi, 0x00000000, 0xff00ff00, 0x0f0 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 7, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); + TEST_IMM_DEST_BYPASS( 8, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); + TEST_IMM_DEST_BYPASS( 9, 2, andi, 0xf00ff00f, 0xf00ff00f, 0xf0f ); + + TEST_IMM_SRC1_BYPASS( 10, 0, andi, 0x00000700, 0x0ff00ff0, 0x70f ); + TEST_IMM_SRC1_BYPASS( 11, 1, andi, 0x000000f0, 0x00ff00ff, 0x0f0 ); + TEST_IMM_SRC1_BYPASS( 12, 2, andi, 0x0000000f, 0xf00ff00f, 0x70f ); + + TEST_IMM_ZEROSRC1( 13, andi, 0, 0x0f0 ); + TEST_IMM_ZERODEST( 14, andi, 0x00ff00ff, 0x70f ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/auipc.S b/tests/isa/rv32ui/auipc.S new file mode 100644 index 0000000..6fe5962 --- /dev/null +++ b/tests/isa/rv32ui/auipc.S @@ -0,0 +1,39 @@ +# See LICENSE for license details. + +#***************************************************************************** +# auipc.S +#----------------------------------------------------------------------------- +# +# Test auipc instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a0, 10000, \ + .align 3; \ + lla a0, 1f + 10000; \ + jal a1, 1f; \ + 1: sub a0, a0, a1; \ + ) + + TEST_CASE(3, a0, -10000, \ + .align 3; \ + lla a0, 1f - 10000; \ + jal a1, 1f; \ + 1: sub a0, a0, a1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/beq.S b/tests/isa/rv32ui/beq.S new file mode 100644 index 0000000..436db8c --- /dev/null +++ b/tests/isa/rv32ui/beq.S @@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# beq.S +#----------------------------------------------------------------------------- +# +# Test beq instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, beq, 0, 0 ); + TEST_BR2_OP_TAKEN( 3, beq, 1, 1 ); + TEST_BR2_OP_TAKEN( 4, beq, -1, -1 ); + + TEST_BR2_OP_NOTTAKEN( 5, beq, 0, 1 ); + TEST_BR2_OP_NOTTAKEN( 6, beq, 1, 0 ); + TEST_BR2_OP_NOTTAKEN( 7, beq, -1, 1 ); + TEST_BR2_OP_NOTTAKEN( 8, beq, 1, -1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, beq, 0, -1 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, beq, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, beq, 0, -1 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + beq x0, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/bge.S b/tests/isa/rv32ui/bge.S new file mode 100644 index 0000000..04aebbc --- /dev/null +++ b/tests/isa/rv32ui/bge.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bge.S +#----------------------------------------------------------------------------- +# +# Test bge instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bge, 0, 0 ); + TEST_BR2_OP_TAKEN( 3, bge, 1, 1 ); + TEST_BR2_OP_TAKEN( 4, bge, -1, -1 ); + TEST_BR2_OP_TAKEN( 5, bge, 1, 0 ); + TEST_BR2_OP_TAKEN( 6, bge, 1, -1 ); + TEST_BR2_OP_TAKEN( 7, bge, -1, -2 ); + + TEST_BR2_OP_NOTTAKEN( 8, bge, 0, 1 ); + TEST_BR2_OP_NOTTAKEN( 9, bge, -1, 1 ); + TEST_BR2_OP_NOTTAKEN( 10, bge, -2, -1 ); + TEST_BR2_OP_NOTTAKEN( 11, bge, -2, 1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 12, 0, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 13, 0, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 14, 0, 2, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 15, 1, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 16, 1, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 17, 2, 0, bge, -1, 0 ); + + TEST_BR2_SRC12_BYPASS( 18, 0, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 19, 0, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 20, 0, 2, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 21, 1, 0, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 22, 1, 1, bge, -1, 0 ); + TEST_BR2_SRC12_BYPASS( 23, 2, 0, bge, -1, 0 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 24, x1, 3, \ + li x1, 1; \ + bge x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/bgeu.S b/tests/isa/rv32ui/bgeu.S new file mode 100644 index 0000000..36b6b3a --- /dev/null +++ b/tests/isa/rv32ui/bgeu.S @@ -0,0 +1,76 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bgeu.S +#----------------------------------------------------------------------------- +# +# Test bgeu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bgeu, 0x00000000, 0x00000000 ); + TEST_BR2_OP_TAKEN( 3, bgeu, 0x00000001, 0x00000001 ); + TEST_BR2_OP_TAKEN( 4, bgeu, 0xffffffff, 0xffffffff ); + TEST_BR2_OP_TAKEN( 5, bgeu, 0x00000001, 0x00000000 ); + TEST_BR2_OP_TAKEN( 6, bgeu, 0xffffffff, 0xfffffffe ); + TEST_BR2_OP_TAKEN( 7, bgeu, 0xffffffff, 0x00000000 ); + + TEST_BR2_OP_NOTTAKEN( 8, bgeu, 0x00000000, 0x00000001 ); + TEST_BR2_OP_NOTTAKEN( 9, bgeu, 0xfffffffe, 0xffffffff ); + TEST_BR2_OP_NOTTAKEN( 10, bgeu, 0x00000000, 0xffffffff ); + TEST_BR2_OP_NOTTAKEN( 11, bgeu, 0x7fffffff, 0x80000000 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 12, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 13, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 14, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 15, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 16, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 17, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); + + TEST_BR2_SRC12_BYPASS( 18, 0, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 19, 0, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 20, 0, 2, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 21, 1, 0, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 22, 1, 1, bgeu, 0xefffffff, 0xf0000000 ); + TEST_BR2_SRC12_BYPASS( 23, 2, 0, bgeu, 0xefffffff, 0xf0000000 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 24, x1, 3, \ + li x1, 1; \ + bgeu x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/blt.S b/tests/isa/rv32ui/blt.S new file mode 100644 index 0000000..1c0ca69 --- /dev/null +++ b/tests/isa/rv32ui/blt.S @@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# blt.S +#----------------------------------------------------------------------------- +# +# Test blt instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, blt, 0, 1 ); + TEST_BR2_OP_TAKEN( 3, blt, -1, 1 ); + TEST_BR2_OP_TAKEN( 4, blt, -2, -1 ); + + TEST_BR2_OP_NOTTAKEN( 5, blt, 1, 0 ); + TEST_BR2_OP_NOTTAKEN( 6, blt, 1, -1 ); + TEST_BR2_OP_NOTTAKEN( 7, blt, -1, -2 ); + TEST_BR2_OP_NOTTAKEN( 8, blt, 1, -2 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, blt, 0, -1 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, blt, 0, -1 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, blt, 0, -1 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + blt x0, x1, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/bltu.S b/tests/isa/rv32ui/bltu.S new file mode 100644 index 0000000..4e880d6 --- /dev/null +++ b/tests/isa/rv32ui/bltu.S @@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bltu.S +#----------------------------------------------------------------------------- +# +# Test bltu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bltu, 0x00000000, 0x00000001 ); + TEST_BR2_OP_TAKEN( 3, bltu, 0xfffffffe, 0xffffffff ); + TEST_BR2_OP_TAKEN( 4, bltu, 0x00000000, 0xffffffff ); + + TEST_BR2_OP_NOTTAKEN( 5, bltu, 0x00000001, 0x00000000 ); + TEST_BR2_OP_NOTTAKEN( 6, bltu, 0xffffffff, 0xfffffffe ); + TEST_BR2_OP_NOTTAKEN( 7, bltu, 0xffffffff, 0x00000000 ); + TEST_BR2_OP_NOTTAKEN( 8, bltu, 0x80000000, 0x7fffffff ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, bltu, 0xf0000000, 0xefffffff ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, bltu, 0xf0000000, 0xefffffff ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, bltu, 0xf0000000, 0xefffffff ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + bltu x0, x1, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/bne.S b/tests/isa/rv32ui/bne.S new file mode 100644 index 0000000..3ca4e6c --- /dev/null +++ b/tests/isa/rv32ui/bne.S @@ -0,0 +1,73 @@ +# See LICENSE for license details. + +#***************************************************************************** +# bne.S +#----------------------------------------------------------------------------- +# +# Test bne instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Branch tests + #------------------------------------------------------------- + + # Each test checks both forward and backward branches + + TEST_BR2_OP_TAKEN( 2, bne, 0, 1 ); + TEST_BR2_OP_TAKEN( 3, bne, 1, 0 ); + TEST_BR2_OP_TAKEN( 4, bne, -1, 1 ); + TEST_BR2_OP_TAKEN( 5, bne, 1, -1 ); + + TEST_BR2_OP_NOTTAKEN( 6, bne, 0, 0 ); + TEST_BR2_OP_NOTTAKEN( 7, bne, 1, 1 ); + TEST_BR2_OP_NOTTAKEN( 8, bne, -1, -1 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_BR2_SRC12_BYPASS( 9, 0, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 10, 0, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 11, 0, 2, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 12, 1, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 13, 1, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 14, 2, 0, bne, 0, 0 ); + + TEST_BR2_SRC12_BYPASS( 15, 0, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 16, 0, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 17, 0, 2, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 18, 1, 0, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 19, 1, 1, bne, 0, 0 ); + TEST_BR2_SRC12_BYPASS( 20, 2, 0, bne, 0, 0 ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 21, x1, 3, \ + li x1, 1; \ + bne x1, x0, 1f; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ + addi x1, x1, 1; \ +1: addi x1, x1, 1; \ + addi x1, x1, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/fence_i.S b/tests/isa/rv32ui/fence_i.S new file mode 100644 index 0000000..cd0fe56 --- /dev/null +++ b/tests/isa/rv32ui/fence_i.S @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fence_i.S +#----------------------------------------------------------------------------- +# +# Test self-modifying code and the fence.i instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +li a3, 111 +lh a0, insn +lh a1, insn+2 + +# test I$ hit +.align 6 +sh a0, 1f, t0 +sh a1, 1f+2, t0 +fence.i + +1: addi a3, a3, 222 +TEST_CASE( 2, a3, 444, nop ) + +# test prefetcher hit +li a4, 100 +1: addi a4, a4, -1 +bnez a4, 1b + +sh a0, 1f, t0 +sh a1, 1f+2, t0 +fence.i + +.align 6 +1: addi a3, a3, 555 +TEST_CASE( 3, a3, 777, nop ) + +TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +insn: + addi a3, a3, 333 + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/jal.S b/tests/isa/rv32ui/jal.S new file mode 100644 index 0000000..00c65d8 --- /dev/null +++ b/tests/isa/rv32ui/jal.S @@ -0,0 +1,59 @@ +# See LICENSE for license details. + +#***************************************************************************** +# jal.S +#----------------------------------------------------------------------------- +# +# Test jal instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Test 2: Basic test + #------------------------------------------------------------- + +test_2: + li TESTNUM, 2 + li ra, 0 + + jal x4, target_2 +linkaddr_2: + nop + nop + + j fail + +target_2: + la x2, linkaddr_2 + bne x2, x4, fail + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + TEST_CASE( 3, ra, 3, \ + li ra, 1; \ + jal x0, 1f; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ + addi ra, ra, 1; \ +1: addi ra, ra, 1; \ + addi ra, ra, 1; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/jalr.S b/tests/isa/rv32ui/jalr.S new file mode 100644 index 0000000..d63bbe2 --- /dev/null +++ b/tests/isa/rv32ui/jalr.S @@ -0,0 +1,69 @@ +# See LICENSE for license details. + +#***************************************************************************** +# jalr.S +#----------------------------------------------------------------------------- +# +# Test jalr instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Test 2: Basic test + #------------------------------------------------------------- + +test_2: + li TESTNUM, 2 + li t0, 0 + la t1, target_2 + + jalr t0, t1, 0 +linkaddr_2: + j fail + +target_2: + la t1, linkaddr_2 + bne t0, t1, fail + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_JALR_SRC1_BYPASS( 4, 0, jalr ); + TEST_JALR_SRC1_BYPASS( 5, 1, jalr ); + TEST_JALR_SRC1_BYPASS( 6, 2, jalr ); + + #------------------------------------------------------------- + # Test delay slot instructions not executed nor bypassed + #------------------------------------------------------------- + + .option push + .option norvc + TEST_CASE( 7, t0, 4, \ + li t0, 1; \ + la t1, 1f; \ + jr t1, -4; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ + addi t0, t0, 1; \ +1: addi t0, t0, 1; \ + addi t0, t0, 1; \ + ) + .option pop + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/lb.S b/tests/isa/rv32ui/lb.S new file mode 100644 index 0000000..856dfe9 --- /dev/null +++ b/tests/isa/rv32ui/lb.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lb.S +#----------------------------------------------------------------------------- +# +# Test lb instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lb, 0xffffffffffffffff, 0, tdat ); + TEST_LD_OP( 3, lb, 0x0000000000000000, 1, tdat ); + TEST_LD_OP( 4, lb, 0xfffffffffffffff0, 2, tdat ); + TEST_LD_OP( 5, lb, 0x000000000000000f, 3, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lb, 0xffffffffffffffff, -3, tdat4 ); + TEST_LD_OP( 7, lb, 0x0000000000000000, -2, tdat4 ); + TEST_LD_OP( 8, lb, 0xfffffffffffffff0, -1, tdat4 ); + TEST_LD_OP( 9, lb, 0x000000000000000f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0xffffffffffffffff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lb x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x0000000000000000, \ + la x1, tdat; \ + addi x1, x1, -6; \ + lb x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lb, 0x000000000000000f, 1, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lb, 0x0000000000000000, 1, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lb, 0xfffffffffffffff0, 1, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lb, 0x000000000000000f, 1, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lb, 0x0000000000000000, 1, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lb x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lb x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .byte 0xff +tdat2: .byte 0x00 +tdat3: .byte 0xf0 +tdat4: .byte 0x0f + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/lbu.S b/tests/isa/rv32ui/lbu.S new file mode 100644 index 0000000..adc3a05 --- /dev/null +++ b/tests/isa/rv32ui/lbu.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lbu.S +#----------------------------------------------------------------------------- +# +# Test lbu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lbu, 0x00000000000000ff, 0, tdat ); + TEST_LD_OP( 3, lbu, 0x0000000000000000, 1, tdat ); + TEST_LD_OP( 4, lbu, 0x00000000000000f0, 2, tdat ); + TEST_LD_OP( 5, lbu, 0x000000000000000f, 3, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lbu, 0x00000000000000ff, -3, tdat4 ); + TEST_LD_OP( 7, lbu, 0x0000000000000000, -2, tdat4 ); + TEST_LD_OP( 8, lbu, 0x00000000000000f0, -1, tdat4 ); + TEST_LD_OP( 9, lbu, 0x000000000000000f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00000000000000ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lbu x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x0000000000000000, \ + la x1, tdat; \ + addi x1, x1, -6; \ + lbu x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lbu, 0x00000000000000f0, 1, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lbu, 0x000000000000000f, 1, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lbu, 0x0000000000000000, 1, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lbu, 0x00000000000000f0, 1, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lbu, 0x000000000000000f, 1, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lbu, 0x0000000000000000, 1, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lbu x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lbu x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .byte 0xff +tdat2: .byte 0x00 +tdat3: .byte 0xf0 +tdat4: .byte 0x0f + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/ld.S b/tests/isa/rv32ui/ld.S new file mode 100644 index 0000000..948c34b --- /dev/null +++ b/tests/isa/rv32ui/ld.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ld.S +#----------------------------------------------------------------------------- +# +# Test ld instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, ld, 0x00ff00ff00ff00ff, 0, tdat ); + TEST_LD_OP( 3, ld, 0xff00ff00ff00ff00, 8, tdat ); + TEST_LD_OP( 4, ld, 0x0ff00ff00ff00ff0, 16, tdat ); + TEST_LD_OP( 5, ld, 0xf00ff00ff00ff00f, 24, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, ld, 0x00ff00ff00ff00ff, -24, tdat4 ); + TEST_LD_OP( 7, ld, 0xff00ff00ff00ff00, -16, tdat4 ); + TEST_LD_OP( 8, ld, 0x0ff00ff00ff00ff0, -8, tdat4 ); + TEST_LD_OP( 9, ld, 0xf00ff00ff00ff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00ff00ff00ff00ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + ld x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xff00ff00ff00ff00, \ + la x1, tdat; \ + addi x1, x1, -3; \ + ld x5, 11(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, ld, 0x0ff00ff00ff00ff0, 8, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, ld, 0xf00ff00ff00ff00f, 8, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, ld, 0xff00ff00ff00ff00, 8, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + ld x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + ld x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .dword 0x00ff00ff00ff00ff +tdat2: .dword 0xff00ff00ff00ff00 +tdat3: .dword 0x0ff00ff00ff00ff0 +tdat4: .dword 0xf00ff00ff00ff00f + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/lh.S b/tests/isa/rv32ui/lh.S new file mode 100644 index 0000000..338ed69 --- /dev/null +++ b/tests/isa/rv32ui/lh.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lh.S +#----------------------------------------------------------------------------- +# +# Test lh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lh, 0x00000000000000ff, 0, tdat ); + TEST_LD_OP( 3, lh, 0xffffffffffffff00, 2, tdat ); + TEST_LD_OP( 4, lh, 0x0000000000000ff0, 4, tdat ); + TEST_LD_OP( 5, lh, 0xfffffffffffff00f, 6, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lh, 0x00000000000000ff, -6, tdat4 ); + TEST_LD_OP( 7, lh, 0xffffffffffffff00, -4, tdat4 ); + TEST_LD_OP( 8, lh, 0x0000000000000ff0, -2, tdat4 ); + TEST_LD_OP( 9, lh, 0xfffffffffffff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00000000000000ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lh x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xffffffffffffff00, \ + la x1, tdat; \ + addi x1, x1, -5; \ + lh x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lh, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lh, 0xffffffffffffff00, 2, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lh, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lh, 0xfffffffffffff00f, 2, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lh, 0xffffffffffffff00, 2, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lh x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lh x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .half 0x00ff +tdat2: .half 0xff00 +tdat3: .half 0x0ff0 +tdat4: .half 0xf00f + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/lhu.S b/tests/isa/rv32ui/lhu.S new file mode 100644 index 0000000..a4cc49b --- /dev/null +++ b/tests/isa/rv32ui/lhu.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lhu.S +#----------------------------------------------------------------------------- +# +# Test lhu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lhu, 0x00000000000000ff, 0, tdat ); + TEST_LD_OP( 3, lhu, 0x000000000000ff00, 2, tdat ); + TEST_LD_OP( 4, lhu, 0x0000000000000ff0, 4, tdat ); + TEST_LD_OP( 5, lhu, 0x000000000000f00f, 6, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lhu, 0x00000000000000ff, -6, tdat4 ); + TEST_LD_OP( 7, lhu, 0x000000000000ff00, -4, tdat4 ); + TEST_LD_OP( 8, lhu, 0x0000000000000ff0, -2, tdat4 ); + TEST_LD_OP( 9, lhu, 0x000000000000f00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x00000000000000ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lhu x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x000000000000ff00, \ + la x1, tdat; \ + addi x1, x1, -5; \ + lhu x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lhu, 0x000000000000f00f, 2, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lhu, 0x000000000000ff00, 2, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lhu, 0x0000000000000ff0, 2, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lhu, 0x000000000000f00f, 2, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lhu, 0x000000000000ff00, 2, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lhu x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lhu x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .half 0x00ff +tdat2: .half 0xff00 +tdat3: .half 0x0ff0 +tdat4: .half 0xf00f + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/lui.S b/tests/isa/rv32ui/lui.S new file mode 100644 index 0000000..8a4e70c --- /dev/null +++ b/tests/isa/rv32ui/lui.S @@ -0,0 +1,36 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lui.S +#----------------------------------------------------------------------------- +# +# Test lui instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_CASE( 2, x1, 0x0000000000000000, lui x1, 0x00000 ); + TEST_CASE( 3, x1, 0xfffffffffffff800, lui x1, 0xfffff;sra x1,x1,1); + TEST_CASE( 4, x1, 0x00000000000007ff, lui x1, 0x7ffff;sra x1,x1,20); + TEST_CASE( 5, x1, 0xfffffffffffff800, lui x1, 0x80000;sra x1,x1,20); + + TEST_CASE( 6, x0, 0, lui x0, 0x80000 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/lw.S b/tests/isa/rv32ui/lw.S new file mode 100644 index 0000000..40a73f1 --- /dev/null +++ b/tests/isa/rv32ui/lw.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lw.S +#----------------------------------------------------------------------------- +# +# Test lw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lw, 0x0000000000ff00ff, 0, tdat ); + TEST_LD_OP( 3, lw, 0xffffffffff00ff00, 4, tdat ); + TEST_LD_OP( 4, lw, 0x000000000ff00ff0, 8, tdat ); + TEST_LD_OP( 5, lw, 0xfffffffff00ff00f, 12, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lw, 0x0000000000ff00ff, -12, tdat4 ); + TEST_LD_OP( 7, lw, 0xffffffffff00ff00, -8, tdat4 ); + TEST_LD_OP( 8, lw, 0x000000000ff00ff0, -4, tdat4 ); + TEST_LD_OP( 9, lw, 0xfffffffff00ff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x0000000000ff00ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lw x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xffffffffff00ff00, \ + la x1, tdat; \ + addi x1, x1, -3; \ + lw x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lw, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lw, 0xfffffffff00ff00f, 4, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lw, 0xffffffffff00ff00, 4, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lw x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lw x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .word 0x00ff00ff +tdat2: .word 0xff00ff00 +tdat3: .word 0x0ff00ff0 +tdat4: .word 0xf00ff00f + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/lwu.S b/tests/isa/rv32ui/lwu.S new file mode 100644 index 0000000..9f7cf67 --- /dev/null +++ b/tests/isa/rv32ui/lwu.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lwu.S +#----------------------------------------------------------------------------- +# +# Test lwu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_LD_OP( 2, lwu, 0x0000000000ff00ff, 0, tdat ); + TEST_LD_OP( 3, lwu, 0x00000000ff00ff00, 4, tdat ); + TEST_LD_OP( 4, lwu, 0x000000000ff00ff0, 8, tdat ); + TEST_LD_OP( 5, lwu, 0x00000000f00ff00f, 12, tdat ); + + # Test with negative offset + + TEST_LD_OP( 6, lwu, 0x0000000000ff00ff, -12, tdat4 ); + TEST_LD_OP( 7, lwu, 0x00000000ff00ff00, -8, tdat4 ); + TEST_LD_OP( 8, lwu, 0x000000000ff00ff0, -4, tdat4 ); + TEST_LD_OP( 9, lwu, 0x00000000f00ff00f, 0, tdat4 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x0000000000ff00ff, \ + la x1, tdat; \ + addi x1, x1, -32; \ + lwu x5, 32(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x00000000ff00ff00, \ + la x1, tdat; \ + addi x1, x1, -3; \ + lwu x5, 7(x1); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_LD_DEST_BYPASS( 12, 0, lwu, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_DEST_BYPASS( 13, 1, lwu, 0x00000000f00ff00f, 4, tdat3 ); + TEST_LD_DEST_BYPASS( 14, 2, lwu, 0x00000000ff00ff00, 4, tdat1 ); + + TEST_LD_SRC1_BYPASS( 15, 0, lwu, 0x000000000ff00ff0, 4, tdat2 ); + TEST_LD_SRC1_BYPASS( 16, 1, lwu, 0x00000000f00ff00f, 4, tdat3 ); + TEST_LD_SRC1_BYPASS( 17, 2, lwu, 0x00000000ff00ff00, 4, tdat1 ); + + #------------------------------------------------------------- + # Test write-after-write hazard + #------------------------------------------------------------- + + TEST_CASE( 18, x2, 2, \ + la x5, tdat; \ + lwu x2, 0(x5); \ + li x2, 2; \ + ) + + TEST_CASE( 19, x2, 2, \ + la x5, tdat; \ + lwu x2, 0(x5); \ + nop; \ + li x2, 2; \ + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .word 0x00ff00ff +tdat2: .word 0xff00ff00 +tdat3: .word 0x0ff00ff0 +tdat4: .word 0xf00ff00f + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/or.S b/tests/isa/rv32ui/or.S new file mode 100644 index 0000000..6d84f53 --- /dev/null +++ b/tests/isa/rv32ui/or.S @@ -0,0 +1,69 @@ +# See LICENSE for license details. + +#***************************************************************************** +# or.S +#----------------------------------------------------------------------------- +# +# Test or instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_OP( 3, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_OP( 4, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_OP( 5, or, 0xf0fff0ff, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, or, 0xff00ff00, 0xff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, or, 0xff0fff0f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, or, 0xfff0fff0, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, or, 0x0fff0fff, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, or, 0xff00ff00, 0xff00ff00 ); + TEST_RR_ZEROSRC2( 25, or, 0x00ff00ff, 0x00ff00ff ); + TEST_RR_ZEROSRC12( 26, or, 0 ); + TEST_RR_ZERODEST( 27, or, 0x11111111, 0x22222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/ori.S b/tests/isa/rv32ui/ori.S new file mode 100644 index 0000000..437c00a --- /dev/null +++ b/tests/isa/rv32ui/ori.S @@ -0,0 +1,55 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ori.S +#----------------------------------------------------------------------------- +# +# Test ori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, ori, 0xffffffffffffff0f, 0xffffffffff00ff00, 0xf0f ); + TEST_IMM_OP( 3, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); + TEST_IMM_OP( 5, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 6, ori, 0xff00fff0, 0xff00ff00, 0x0f0 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 7, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_DEST_BYPASS( 8, 1, ori, 0x0000000000ff07ff, 0x0000000000ff00ff, 0x70f ); + TEST_IMM_DEST_BYPASS( 9, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_SRC1_BYPASS( 10, 0, ori, 0x000000000ff00ff0, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_SRC1_BYPASS( 11, 1, ori, 0xffffffffffffffff, 0x0000000000ff00ff, 0xf0f ); + TEST_IMM_SRC1_BYPASS( 12, 2, ori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_ZEROSRC1( 13, ori, 0x0f0, 0x0f0 ); + TEST_IMM_ZERODEST( 14, ori, 0x00ff00ff, 0x70f ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/sb.S b/tests/isa/rv32ui/sb.S new file mode 100644 index 0000000..19e32d6 --- /dev/null +++ b/tests/isa/rv32ui/sb.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sb.S +#----------------------------------------------------------------------------- +# +# Test sb instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, lb, sb, 0xffffffffffffffaa, 0, tdat ); + TEST_ST_OP( 3, lb, sb, 0x0000000000000000, 1, tdat ); + TEST_ST_OP( 4, lh, sb, 0xffffffffffffefa0, 2, tdat ); + TEST_ST_OP( 5, lb, sb, 0x000000000000000a, 3, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, lb, sb, 0xffffffffffffffaa, -3, tdat8 ); + TEST_ST_OP( 7, lb, sb, 0x0000000000000000, -2, tdat8 ); + TEST_ST_OP( 8, lb, sb, 0xffffffffffffffa0, -1, tdat8 ); + TEST_ST_OP( 9, lb, sb, 0x000000000000000a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x78, \ + la x1, tdat9; \ + li x2, 0x12345678; \ + addi x4, x1, -32; \ + sb x2, 32(x4); \ + lb x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0xffffffffffffff98, \ + la x1, tdat9; \ + li x2, 0x00003098; \ + addi x1, x1, -6; \ + sb x2, 7(x1); \ + la x4, tdat10; \ + lb x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, lb, sb, 0xffffffffffffffdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, lb, sb, 0xffffffffffffffcd, 1, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, lb, sb, 0xffffffffffffffcc, 2, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, lb, sb, 0xffffffffffffffbc, 3, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, lb, sb, 0xffffffffffffffbb, 4, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, lb, sb, 0xffffffffffffffab, 5, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, lb, sb, 0x33, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, lb, sb, 0x23, 1, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, lb, sb, 0x22, 2, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, lb, sb, 0x12, 3, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, lb, sb, 0x11, 4, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, lb, sb, 0x01, 5, tdat ); + + li a0, 0xef + la a1, tdat + sb a0, 3(a1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .byte 0xef +tdat2: .byte 0xef +tdat3: .byte 0xef +tdat4: .byte 0xef +tdat5: .byte 0xef +tdat6: .byte 0xef +tdat7: .byte 0xef +tdat8: .byte 0xef +tdat9: .byte 0xef +tdat10: .byte 0xef + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/sd.S b/tests/isa/rv32ui/sd.S new file mode 100644 index 0000000..b6fd66d --- /dev/null +++ b/tests/isa/rv32ui/sd.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sd.S +#----------------------------------------------------------------------------- +# +# Test sd instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, ld, sd, 0x00aa00aa00aa00aa, 0, tdat ); + TEST_ST_OP( 3, ld, sd, 0xaa00aa00aa00aa00, 8, tdat ); + TEST_ST_OP( 4, ld, sd, 0x0aa00aa00aa00aa0, 16, tdat ); + TEST_ST_OP( 5, ld, sd, 0xa00aa00aa00aa00a, 24, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, ld, sd, 0x00aa00aa00aa00aa, -24, tdat8 ); + TEST_ST_OP( 7, ld, sd, 0xaa00aa00aa00aa00, -16, tdat8 ); + TEST_ST_OP( 8, ld, sd, 0x0aa00aa00aa00aa0, -8, tdat8 ); + TEST_ST_OP( 9, ld, sd, 0xa00aa00aa00aa00a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x1234567812345678, \ + la x1, tdat9; \ + li x2, 0x1234567812345678; \ + addi x4, x1, -32; \ + sd x2, 32(x4); \ + ld x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x5821309858213098, \ + la x1, tdat9; \ + li x2, 0x5821309858213098; \ + addi x1, x1, -3; \ + sd x2, 11(x1); \ + la x4, tdat10; \ + ld x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, ld, sd, 0xabbccdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, ld, sd, 0xaabbccd, 8, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, ld, sd, 0xdaabbcc, 16, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, ld, sd, 0xddaabbc, 24, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, ld, sd, 0xcddaabb, 32, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, ld, sd, 0xccddaab, 40, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, ld, sd, 0x00112233, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, ld, sd, 0x30011223, 8, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, ld, sd, 0x33001122, 16, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, ld, sd, 0x23300112, 24, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, ld, sd, 0x22330011, 32, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, ld, sd, 0x12233001, 40, tdat ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .dword 0xdeadbeefdeadbeef +tdat2: .dword 0xdeadbeefdeadbeef +tdat3: .dword 0xdeadbeefdeadbeef +tdat4: .dword 0xdeadbeefdeadbeef +tdat5: .dword 0xdeadbeefdeadbeef +tdat6: .dword 0xdeadbeefdeadbeef +tdat7: .dword 0xdeadbeefdeadbeef +tdat8: .dword 0xdeadbeefdeadbeef +tdat9: .dword 0xdeadbeefdeadbeef +tdat10: .dword 0xdeadbeefdeadbeef + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/sh.S b/tests/isa/rv32ui/sh.S new file mode 100644 index 0000000..ea9eb23 --- /dev/null +++ b/tests/isa/rv32ui/sh.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sh.S +#----------------------------------------------------------------------------- +# +# Test sh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, lh, sh, 0x00000000000000aa, 0, tdat ); + TEST_ST_OP( 3, lh, sh, 0xffffffffffffaa00, 2, tdat ); + TEST_ST_OP( 4, lw, sh, 0xffffffffbeef0aa0, 4, tdat ); + TEST_ST_OP( 5, lh, sh, 0xffffffffffffa00a, 6, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, lh, sh, 0x00000000000000aa, -6, tdat8 ); + TEST_ST_OP( 7, lh, sh, 0xffffffffffffaa00, -4, tdat8 ); + TEST_ST_OP( 8, lh, sh, 0x0000000000000aa0, -2, tdat8 ); + TEST_ST_OP( 9, lh, sh, 0xffffffffffffa00a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x5678, \ + la x1, tdat9; \ + li x2, 0x12345678; \ + addi x4, x1, -32; \ + sh x2, 32(x4); \ + lh x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x3098, \ + la x1, tdat9; \ + li x2, 0x00003098; \ + addi x1, x1, -5; \ + sh x2, 7(x1); \ + la x4, tdat10; \ + lh x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, lh, sh, 0xffffffffffffccdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, lh, sh, 0xffffffffffffbccd, 2, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, lh, sh, 0xffffffffffffbbcc, 4, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, lh, sh, 0xffffffffffffabbc, 6, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, lh, sh, 0xffffffffffffaabb, 8, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, lh, sh, 0xffffffffffffdaab, 10, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, lh, sh, 0x2233, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, lh, sh, 0x1223, 2, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, lh, sh, 0x1122, 4, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, lh, sh, 0x0112, 6, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat ); + + li a0, 0xbeef + la a1, tdat + sh a0, 6(a1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .half 0xbeef +tdat2: .half 0xbeef +tdat3: .half 0xbeef +tdat4: .half 0xbeef +tdat5: .half 0xbeef +tdat6: .half 0xbeef +tdat7: .half 0xbeef +tdat8: .half 0xbeef +tdat9: .half 0xbeef +tdat10: .half 0xbeef + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/simple.S b/tests/isa/rv32ui/simple.S new file mode 100644 index 0000000..6c45fbd --- /dev/null +++ b/tests/isa/rv32ui/simple.S @@ -0,0 +1,27 @@ +# See LICENSE for license details. + +#***************************************************************************** +# simple.S +#----------------------------------------------------------------------------- +# +# This is the most basic self checking test. If your simulator does not +# pass thiss then there is little chance that it will pass any of the +# more complicated self checking tests. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +RVTEST_PASS + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/sll.S b/tests/isa/rv32ui/sll.S new file mode 100644 index 0000000..257aa9d --- /dev/null +++ b/tests/isa/rv32ui/sll.S @@ -0,0 +1,96 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sll.S +#----------------------------------------------------------------------------- +# +# Test sll instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sll, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_RR_OP( 3, sll, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_RR_OP( 4, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_OP( 5, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_OP( 6, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_OP( 7, sll, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_RR_OP( 8, sll, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_RR_OP( 9, sll, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_RR_OP( 10, sll, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_RR_OP( 11, sll, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_RR_OP( 12, sll, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_RR_OP( 13, sll, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_RR_OP( 14, sll, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_RR_OP( 15, sll, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_RR_OP( 16, sll, 0x1090909080000000, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom six bits + + TEST_RR_OP( 17, sll, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, sll, 0x0000000042424242, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, sll, 0x0000001090909080, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, sll, 0x0000084848484000, 0x0000000021212121, 0xffffffffffffffce ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 21, sll, 0x8000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sll, 0x00000080, 0x00000001, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sll, 0x00004000, 0x00000001, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sll, 24, 3 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sll, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sll, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sll, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_RR_ZEROSRC1( 40, sll, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sll, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sll, 0 ); + TEST_RR_ZERODEST( 43, sll, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/slli.S b/tests/isa/rv32ui/slli.S new file mode 100644 index 0000000..f28ea1c --- /dev/null +++ b/tests/isa/rv32ui/slli.S @@ -0,0 +1,74 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slli.S +#----------------------------------------------------------------------------- +# +# Test slli instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slli, 0x0000000000000001, 0x0000000000000001, 0 ); + TEST_IMM_OP( 3, slli, 0x0000000000000002, 0x0000000000000001, 1 ); + TEST_IMM_OP( 4, slli, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_OP( 5, slli, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_OP( 6, slli, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_OP( 7, slli, 0xffffffffffffffff, 0xffffffffffffffff, 0 ); + TEST_IMM_OP( 8, slli, 0xfffffffffffffffe, 0xffffffffffffffff, 1 ); + TEST_IMM_OP( 9, slli, 0xffffffffffffff80, 0xffffffffffffffff, 7 ); + TEST_IMM_OP( 10, slli, 0xffffffffffffc000, 0xffffffffffffffff, 14 ); + TEST_IMM_OP( 11, slli, 0xffffffff80000000, 0xffffffffffffffff, 31 ); + + TEST_IMM_OP( 12, slli, 0x0000000021212121, 0x0000000021212121, 0 ); + TEST_IMM_OP( 13, slli, 0x0000000042424242, 0x0000000021212121, 1 ); + TEST_IMM_OP( 14, slli, 0x0000001090909080, 0x0000000021212121, 7 ); + TEST_IMM_OP( 15, slli, 0x0000084848484000, 0x0000000021212121, 14 ); + TEST_IMM_OP( 16, slli, 0x1090909080000000, 0x0000000021212121, 31 ); + +#if __riscv_xlen == 64 + TEST_RR_OP( 50, sll, 0x8000000000000000, 0x0000000000000001, 63 ); + TEST_RR_OP( 51, sll, 0xffffff8000000000, 0xffffffffffffffff, 39 ); + TEST_RR_OP( 52, sll, 0x0909080000000000, 0x0000000021212121, 43 ); +#endif + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slli, 0x00000080, 0x00000001, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slli, 0x0000000000000080, 0x0000000000000001, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slli, 0x0000000000004000, 0x0000000000000001, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slli, 0x0000000080000000, 0x0000000000000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, slli, 0, 31 ); + TEST_IMM_ZERODEST( 25, slli, 33, 20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/slt.S b/tests/isa/rv32ui/slt.S new file mode 100644 index 0000000..644a51a --- /dev/null +++ b/tests/isa/rv32ui/slt.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slt.S +#----------------------------------------------------------------------------- +# +# Test slt instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, slt, 0, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, slt, 0, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, slt, 1, 0x0000000000000003, 0x0000000000000007 ); + TEST_RR_OP( 5, slt, 0, 0x0000000000000007, 0x0000000000000003 ); + + TEST_RR_OP( 6, slt, 0, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 7, slt, 1, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 8, slt, 1, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 9, slt, 1, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 10, slt, 0, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 11, slt, 0, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 12, slt, 1, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 13, slt, 0, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 14, slt, 0, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 15, slt, 1, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 16, slt, 0, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, slt, 0, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, slt, 1, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, slt, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, slt, 1, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, slt, 0, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, slt, 1, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, slt, 0, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, slt, 1, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, slt, 0, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, slt, 1, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, slt, 0, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, slt, 1, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, slt, 0, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, slt, 1, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, slt, 0, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, slt, 1, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, slt, 0, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, slt, 1, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, slt, 0, -1 ); + TEST_RR_ZEROSRC2( 36, slt, 1, -1 ); + TEST_RR_ZEROSRC12( 37, slt, 0 ); + TEST_RR_ZERODEST( 38, slt, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/slti.S b/tests/isa/rv32ui/slti.S new file mode 100644 index 0000000..9222fa4 --- /dev/null +++ b/tests/isa/rv32ui/slti.S @@ -0,0 +1,70 @@ +# See LICENSE for license details. + +#***************************************************************************** +# slti.S +#----------------------------------------------------------------------------- +# +# Test slti instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, slti, 0, 0x0000000000000000, 0x000 ); + TEST_IMM_OP( 3, slti, 0, 0x0000000000000001, 0x001 ); + TEST_IMM_OP( 4, slti, 1, 0x0000000000000003, 0x007 ); + TEST_IMM_OP( 5, slti, 0, 0x0000000000000007, 0x003 ); + + TEST_IMM_OP( 6, slti, 0, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 7, slti, 1, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 8, slti, 1, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 9, slti, 1, 0x0000000000000000, 0x7ff ); + TEST_IMM_OP( 10, slti, 0, 0x000000007fffffff, 0x000 ); + TEST_IMM_OP( 11, slti, 0, 0x000000007fffffff, 0x7ff ); + + TEST_IMM_OP( 12, slti, 1, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 13, slti, 0, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 14, slti, 0, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 15, slti, 1, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 16, slti, 0, 0xffffffffffffffff, 0xfff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, slti, 1, 11, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, slti, 0, 15, 10 ); + TEST_IMM_DEST_BYPASS( 19, 1, slti, 1, 10, 16 ); + TEST_IMM_DEST_BYPASS( 20, 2, slti, 0, 16, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, slti, 1, 11, 15 ); + TEST_IMM_SRC1_BYPASS( 22, 1, slti, 0, 17, 8 ); + TEST_IMM_SRC1_BYPASS( 23, 2, slti, 1, 12, 14 ); + + TEST_IMM_ZEROSRC1( 24, slti, 0, 0xfff ); + TEST_IMM_ZERODEST( 25, slti, 0x00ff00ff, 0xfff ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/sltiu.S b/tests/isa/rv32ui/sltiu.S new file mode 100644 index 0000000..f6a719b --- /dev/null +++ b/tests/isa/rv32ui/sltiu.S @@ -0,0 +1,70 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sltiu.S +#----------------------------------------------------------------------------- +# +# Test sltiu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, sltiu, 0, 0x0000000000000000, 0x000 ); + TEST_IMM_OP( 3, sltiu, 0, 0x0000000000000001, 0x001 ); + TEST_IMM_OP( 4, sltiu, 1, 0x0000000000000003, 0x007 ); + TEST_IMM_OP( 5, sltiu, 0, 0x0000000000000007, 0x003 ); + + TEST_IMM_OP( 6, sltiu, 1, 0x0000000000000000, 0x800 ); + TEST_IMM_OP( 7, sltiu, 0, 0xffffffff80000000, 0x000 ); + TEST_IMM_OP( 8, sltiu, 1, 0xffffffff80000000, 0x800 ); + + TEST_IMM_OP( 9, sltiu, 1, 0x0000000000000000, 0x7ff ); + TEST_IMM_OP( 10, sltiu, 0, 0x000000007fffffff, 0x000 ); + TEST_IMM_OP( 11, sltiu, 0, 0x000000007fffffff, 0x7ff ); + + TEST_IMM_OP( 12, sltiu, 0, 0xffffffff80000000, 0x7ff ); + TEST_IMM_OP( 13, sltiu, 1, 0x000000007fffffff, 0x800 ); + + TEST_IMM_OP( 14, sltiu, 1, 0x0000000000000000, 0xfff ); + TEST_IMM_OP( 15, sltiu, 0, 0xffffffffffffffff, 0x001 ); + TEST_IMM_OP( 16, sltiu, 0, 0xffffffffffffffff, 0xfff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, sltiu, 1, 11, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, sltiu, 0, 15, 10 ); + TEST_IMM_DEST_BYPASS( 19, 1, sltiu, 1, 10, 16 ); + TEST_IMM_DEST_BYPASS( 20, 2, sltiu, 0, 16, 9 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, sltiu, 1, 11, 15 ); + TEST_IMM_SRC1_BYPASS( 22, 1, sltiu, 0, 17, 8 ); + TEST_IMM_SRC1_BYPASS( 23, 2, sltiu, 1, 12, 14 ); + + TEST_IMM_ZEROSRC1( 24, sltiu, 1, 0xfff ); + TEST_IMM_ZERODEST( 25, sltiu, 0x00ff00ff, 0xfff ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/sltu.S b/tests/isa/rv32ui/sltu.S new file mode 100644 index 0000000..52ff685 --- /dev/null +++ b/tests/isa/rv32ui/sltu.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sltu.S +#----------------------------------------------------------------------------- +# +# Test sltu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sltu, 0, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, sltu, 0, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, sltu, 1, 0x00000003, 0x00000007 ); + TEST_RR_OP( 5, sltu, 0, 0x00000007, 0x00000003 ); + + TEST_RR_OP( 6, sltu, 1, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 7, sltu, 0, 0x80000000, 0x00000000 ); + TEST_RR_OP( 8, sltu, 1, 0x80000000, 0xffff8000 ); + + TEST_RR_OP( 9, sltu, 1, 0x00000000, 0x00007fff ); + TEST_RR_OP( 10, sltu, 0, 0x7fffffff, 0x00000000 ); + TEST_RR_OP( 11, sltu, 0, 0x7fffffff, 0x00007fff ); + + TEST_RR_OP( 12, sltu, 0, 0x80000000, 0x00007fff ); + TEST_RR_OP( 13, sltu, 1, 0x7fffffff, 0xffff8000 ); + + TEST_RR_OP( 14, sltu, 1, 0x00000000, 0xffffffff ); + TEST_RR_OP( 15, sltu, 0, 0xffffffff, 0x00000001 ); + TEST_RR_OP( 16, sltu, 0, 0xffffffff, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 17, sltu, 0, 14, 13 ); + TEST_RR_SRC2_EQ_DEST( 18, sltu, 1, 11, 13 ); + TEST_RR_SRC12_EQ_DEST( 19, sltu, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 20, 0, sltu, 1, 11, 13 ); + TEST_RR_DEST_BYPASS( 21, 1, sltu, 0, 14, 13 ); + TEST_RR_DEST_BYPASS( 22, 2, sltu, 1, 12, 13 ); + + TEST_RR_SRC12_BYPASS( 23, 0, 0, sltu, 0, 14, 13 ); + TEST_RR_SRC12_BYPASS( 24, 0, 1, sltu, 1, 11, 13 ); + TEST_RR_SRC12_BYPASS( 25, 0, 2, sltu, 0, 15, 13 ); + TEST_RR_SRC12_BYPASS( 26, 1, 0, sltu, 1, 10, 13 ); + TEST_RR_SRC12_BYPASS( 27, 1, 1, sltu, 0, 16, 13 ); + TEST_RR_SRC12_BYPASS( 28, 2, 0, sltu, 1, 9, 13 ); + + TEST_RR_SRC21_BYPASS( 29, 0, 0, sltu, 0, 17, 13 ); + TEST_RR_SRC21_BYPASS( 30, 0, 1, sltu, 1, 8, 13 ); + TEST_RR_SRC21_BYPASS( 31, 0, 2, sltu, 0, 18, 13 ); + TEST_RR_SRC21_BYPASS( 32, 1, 0, sltu, 1, 7, 13 ); + TEST_RR_SRC21_BYPASS( 33, 1, 1, sltu, 0, 19, 13 ); + TEST_RR_SRC21_BYPASS( 34, 2, 0, sltu, 1, 6, 13 ); + + TEST_RR_ZEROSRC1( 35, sltu, 1, -1 ); + TEST_RR_ZEROSRC2( 36, sltu, 0, -1 ); + TEST_RR_ZEROSRC12( 37, sltu, 0 ); + TEST_RR_ZERODEST( 38, sltu, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/sra.S b/tests/isa/rv32ui/sra.S new file mode 100644 index 0000000..9b359a3 --- /dev/null +++ b/tests/isa/rv32ui/sra.S @@ -0,0 +1,90 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sra.S +#----------------------------------------------------------------------------- +# +# Test sra instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sra, 0xffffffff80000000, 0xffffffff80000000, 0 ); + TEST_RR_OP( 3, sra, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_RR_OP( 4, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_OP( 5, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_OP( 6, sra, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_RR_OP( 7, sra, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_RR_OP( 8, sra, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_RR_OP( 9, sra, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_RR_OP( 10, sra, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_RR_OP( 11, sra, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_RR_OP( 12, sra, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_RR_OP( 13, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_RR_OP( 14, sra, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_RR_OP( 15, sra, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_RR_OP( 16, sra, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, sra, 0xffffffff81818181, 0xffffffff81818181, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, sra, 0xffffffffc0c0c0c0, 0xffffffff81818181, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, sra, 0xffffffffff030303, 0xffffffff81818181, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, sra, 0xfffffffffffe0606, 0xffffffff81818181, 0xffffffffffffffce ); + TEST_RR_OP( 21, sra, 0xffffffffffffffff, 0xffffffff81818181, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, sra, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, sra, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, sra, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, sra, 0xffffffffffffffff, 0xffffffff80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, sra, 0, 15 ); + TEST_RR_ZEROSRC2( 41, sra, 32, 32 ); + TEST_RR_ZEROSRC12( 42, sra, 0 ); + TEST_RR_ZERODEST( 43, sra, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/srai.S b/tests/isa/rv32ui/srai.S new file mode 100644 index 0000000..8d05213 --- /dev/null +++ b/tests/isa/rv32ui/srai.S @@ -0,0 +1,68 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srai.S +#----------------------------------------------------------------------------- +# +# Test srai instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, srai, 0xffffff8000000000, 0xffffff8000000000, 0 ); + TEST_IMM_OP( 3, srai, 0xffffffffc0000000, 0xffffffff80000000, 1 ); + TEST_IMM_OP( 4, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_OP( 5, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_OP( 6, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_OP( 7, srai, 0x000000007fffffff, 0x000000007fffffff, 0 ); + TEST_IMM_OP( 8, srai, 0x000000003fffffff, 0x000000007fffffff, 1 ); + TEST_IMM_OP( 9, srai, 0x0000000000ffffff, 0x000000007fffffff, 7 ); + TEST_IMM_OP( 10, srai, 0x000000000001ffff, 0x000000007fffffff, 14 ); + TEST_IMM_OP( 11, srai, 0x0000000000000000, 0x000000007fffffff, 31 ); + + TEST_IMM_OP( 12, srai, 0xffffffff81818181, 0xffffffff81818181, 0 ); + TEST_IMM_OP( 13, srai, 0xffffffffc0c0c0c0, 0xffffffff81818181, 1 ); + TEST_IMM_OP( 14, srai, 0xffffffffff030303, 0xffffffff81818181, 7 ); + TEST_IMM_OP( 15, srai, 0xfffffffffffe0606, 0xffffffff81818181, 14 ); + TEST_IMM_OP( 16, srai, 0xffffffffffffffff, 0xffffffff81818181, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, srai, 0xffffffffff000000, 0xffffffff80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, srai, 0xfffffffffffe0000, 0xffffffff80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, srai, 0xffffffffffffffff, 0xffffffff80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, srai, 0, 4 ); + TEST_IMM_ZERODEST( 25, srai, 33, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/srl.S b/tests/isa/rv32ui/srl.S new file mode 100644 index 0000000..c1e936a --- /dev/null +++ b/tests/isa/rv32ui/srl.S @@ -0,0 +1,93 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srl.S +#----------------------------------------------------------------------------- +# +# Test srl instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + +#define TEST_SRL(n, v, a) \ + TEST_RR_OP(n, srl, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) + + TEST_SRL( 2, 0xffffffff80000000, 0 ); + TEST_SRL( 3, 0xffffffff80000000, 1 ); + TEST_SRL( 4, 0xffffffff80000000, 7 ); + TEST_SRL( 5, 0xffffffff80000000, 14 ); + TEST_SRL( 6, 0xffffffff80000001, 31 ); + + TEST_SRL( 7, 0xffffffffffffffff, 0 ); + TEST_SRL( 8, 0xffffffffffffffff, 1 ); + TEST_SRL( 9, 0xffffffffffffffff, 7 ); + TEST_SRL( 10, 0xffffffffffffffff, 14 ); + TEST_SRL( 11, 0xffffffffffffffff, 31 ); + + TEST_SRL( 12, 0x0000000021212121, 0 ); + TEST_SRL( 13, 0x0000000021212121, 1 ); + TEST_SRL( 14, 0x0000000021212121, 7 ); + TEST_SRL( 15, 0x0000000021212121, 14 ); + TEST_SRL( 16, 0x0000000021212121, 31 ); + + # Verify that shifts only use bottom five bits + + TEST_RR_OP( 17, srl, 0x0000000021212121, 0x0000000021212121, 0xffffffffffffffc0 ); + TEST_RR_OP( 18, srl, 0x0000000010909090, 0x0000000021212121, 0xffffffffffffffc1 ); + TEST_RR_OP( 19, srl, 0x0000000000424242, 0x0000000021212121, 0xffffffffffffffc7 ); + TEST_RR_OP( 20, srl, 0x0000000000008484, 0x0000000021212121, 0xffffffffffffffce ); + TEST_RR_OP( 21, srl, 0x0000000000000000, 0x0000000021212121, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 22, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC2_EQ_DEST( 23, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_EQ_DEST( 24, srl, 0, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 25, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_DEST_BYPASS( 26, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_DEST_BYPASS( 27, 2, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC12_BYPASS( 28, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 29, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 30, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC12_BYPASS( 31, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC12_BYPASS( 32, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC12_BYPASS( 33, 2, 0, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_SRC21_BYPASS( 34, 0, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 35, 0, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 36, 0, 2, srl, 0x00000001, 0x80000000, 31 ); + TEST_RR_SRC21_BYPASS( 37, 1, 0, srl, 0x01000000, 0x80000000, 7 ); + TEST_RR_SRC21_BYPASS( 38, 1, 1, srl, 0x00020000, 0x80000000, 14 ); + TEST_RR_SRC21_BYPASS( 39, 2, 0, srl, 0x00000001, 0x80000000, 31 ); + + TEST_RR_ZEROSRC1( 40, srl, 0, 15 ); + TEST_RR_ZEROSRC2( 41, srl, 32, 32 ); + TEST_RR_ZEROSRC12( 42, srl, 0 ); + TEST_RR_ZERODEST( 43, srl, 1024, 2048 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/srli.S b/tests/isa/rv32ui/srli.S new file mode 100644 index 0000000..88ee8d2 --- /dev/null +++ b/tests/isa/rv32ui/srli.S @@ -0,0 +1,71 @@ +# See LICENSE for license details. + +#***************************************************************************** +# srli.S +#----------------------------------------------------------------------------- +# +# Test srli instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + +#define TEST_SRL(n, v, a) \ + TEST_IMM_OP(n, srli, ((v) & ((1 << (__riscv_xlen-1) << 1) - 1)) >> (a), v, a) + + TEST_SRL( 2, 0xffffffff80000000, 0 ); + TEST_SRL( 3, 0xffffffff80000000, 1 ); + TEST_SRL( 4, 0xffffffff80000000, 7 ); + TEST_SRL( 5, 0xffffffff80000000, 14 ); + TEST_SRL( 6, 0xffffffff80000001, 31 ); + + TEST_SRL( 7, 0xffffffffffffffff, 0 ); + TEST_SRL( 8, 0xffffffffffffffff, 1 ); + TEST_SRL( 9, 0xffffffffffffffff, 7 ); + TEST_SRL( 10, 0xffffffffffffffff, 14 ); + TEST_SRL( 11, 0xffffffffffffffff, 31 ); + + TEST_SRL( 12, 0x0000000021212121, 0 ); + TEST_SRL( 13, 0x0000000021212121, 1 ); + TEST_SRL( 14, 0x0000000021212121, 7 ); + TEST_SRL( 15, 0x0000000021212121, 14 ); + TEST_SRL( 16, 0x0000000021212121, 31 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 17, srli, 0x01000000, 0x80000000, 7 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 18, 0, srli, 0x01000000, 0x80000000, 7 ); + TEST_IMM_DEST_BYPASS( 19, 1, srli, 0x00020000, 0x80000000, 14 ); + TEST_IMM_DEST_BYPASS( 20, 2, srli, 0x00000001, 0x80000001, 31 ); + + TEST_IMM_SRC1_BYPASS( 21, 0, srli, 0x01000000, 0x80000000, 7 ); + TEST_IMM_SRC1_BYPASS( 22, 1, srli, 0x00020000, 0x80000000, 14 ); + TEST_IMM_SRC1_BYPASS( 23, 2, srli, 0x00000001, 0x80000001, 31 ); + + TEST_IMM_ZEROSRC1( 24, srli, 0, 4 ); + TEST_IMM_ZERODEST( 25, srli, 33, 10 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/sub.S b/tests/isa/rv32ui/sub.S new file mode 100644 index 0000000..005bdea --- /dev/null +++ b/tests/isa/rv32ui/sub.S @@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sub.S +#----------------------------------------------------------------------------- +# +# Test sub instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, sub, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000 ); + TEST_RR_OP( 3, sub, 0x0000000000000000, 0x0000000000000001, 0x0000000000000001 ); + TEST_RR_OP( 4, sub, 0xfffffffffffffffc, 0x0000000000000003, 0x0000000000000007 ); + + TEST_RR_OP( 5, sub, 0x0000000000008000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, sub, 0xffffffff80000000, 0xffffffff80000000, 0x0000000000000000 ); + TEST_RR_OP( 7, sub, 0xffffffff80008000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP( 8, sub, 0xffffffffffff8001, 0x0000000000000000, 0x0000000000007fff ); + TEST_RR_OP( 9, sub, 0x000000007fffffff, 0x000000007fffffff, 0x0000000000000000 ); + TEST_RR_OP( 10, sub, 0x000000007fff8000, 0x000000007fffffff, 0x0000000000007fff ); + + TEST_RR_OP( 11, sub, 0xffffffff7fff8001, 0xffffffff80000000, 0x0000000000007fff ); + TEST_RR_OP( 12, sub, 0x0000000080007fff, 0x000000007fffffff, 0xffffffffffff8000 ); + + TEST_RR_OP( 13, sub, 0x0000000000000001, 0x0000000000000000, 0xffffffffffffffff ); + TEST_RR_OP( 14, sub, 0xfffffffffffffffe, 0xffffffffffffffff, 0x0000000000000001 ); + TEST_RR_OP( 15, sub, 0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 16, sub, 2, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 17, sub, 3, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 18, sub, 0, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 19, 0, sub, 2, 13, 11 ); + TEST_RR_DEST_BYPASS( 20, 1, sub, 3, 14, 11 ); + TEST_RR_DEST_BYPASS( 21, 2, sub, 4, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 22, 0, 0, sub, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 23, 0, 1, sub, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 24, 0, 2, sub, 4, 15, 11 ); + TEST_RR_SRC12_BYPASS( 25, 1, 0, sub, 2, 13, 11 ); + TEST_RR_SRC12_BYPASS( 26, 1, 1, sub, 3, 14, 11 ); + TEST_RR_SRC12_BYPASS( 27, 2, 0, sub, 4, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 28, 0, 0, sub, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 29, 0, 1, sub, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 30, 0, 2, sub, 4, 15, 11 ); + TEST_RR_SRC21_BYPASS( 31, 1, 0, sub, 2, 13, 11 ); + TEST_RR_SRC21_BYPASS( 32, 1, 1, sub, 3, 14, 11 ); + TEST_RR_SRC21_BYPASS( 33, 2, 0, sub, 4, 15, 11 ); + + TEST_RR_ZEROSRC1( 34, sub, 15, -15 ); + TEST_RR_ZEROSRC2( 35, sub, 32, 32 ); + TEST_RR_ZEROSRC12( 36, sub, 0 ); + TEST_RR_ZERODEST( 37, sub, 16, 30 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/sw.S b/tests/isa/rv32ui/sw.S new file mode 100644 index 0000000..ab094b3 --- /dev/null +++ b/tests/isa/rv32ui/sw.S @@ -0,0 +1,92 @@ +# See LICENSE for license details. + +#***************************************************************************** +# sw.S +#----------------------------------------------------------------------------- +# +# Test sw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Basic tests + #------------------------------------------------------------- + + TEST_ST_OP( 2, lw, sw, 0x0000000000aa00aa, 0, tdat ); + TEST_ST_OP( 3, lw, sw, 0xffffffffaa00aa00, 4, tdat ); + TEST_ST_OP( 4, lw, sw, 0x000000000aa00aa0, 8, tdat ); + TEST_ST_OP( 5, lw, sw, 0xffffffffa00aa00a, 12, tdat ); + + # Test with negative offset + + TEST_ST_OP( 6, lw, sw, 0x0000000000aa00aa, -12, tdat8 ); + TEST_ST_OP( 7, lw, sw, 0xffffffffaa00aa00, -8, tdat8 ); + TEST_ST_OP( 8, lw, sw, 0x000000000aa00aa0, -4, tdat8 ); + TEST_ST_OP( 9, lw, sw, 0xffffffffa00aa00a, 0, tdat8 ); + + # Test with a negative base + + TEST_CASE( 10, x5, 0x12345678, \ + la x1, tdat9; \ + li x2, 0x12345678; \ + addi x4, x1, -32; \ + sw x2, 32(x4); \ + lw x5, 0(x1); \ + ) + + # Test with unaligned base + + TEST_CASE( 11, x5, 0x58213098, \ + la x1, tdat9; \ + li x2, 0x58213098; \ + addi x1, x1, -3; \ + sw x2, 7(x1); \ + la x4, tdat10; \ + lw x5, 0(x4); \ + ) + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_ST_SRC12_BYPASS( 12, 0, 0, lw, sw, 0xffffffffaabbccdd, 0, tdat ); + TEST_ST_SRC12_BYPASS( 13, 0, 1, lw, sw, 0xffffffffdaabbccd, 4, tdat ); + TEST_ST_SRC12_BYPASS( 14, 0, 2, lw, sw, 0xffffffffddaabbcc, 8, tdat ); + TEST_ST_SRC12_BYPASS( 15, 1, 0, lw, sw, 0xffffffffcddaabbc, 12, tdat ); + TEST_ST_SRC12_BYPASS( 16, 1, 1, lw, sw, 0xffffffffccddaabb, 16, tdat ); + TEST_ST_SRC12_BYPASS( 17, 2, 0, lw, sw, 0xffffffffbccddaab, 20, tdat ); + + TEST_ST_SRC21_BYPASS( 18, 0, 0, lw, sw, 0x00112233, 0, tdat ); + TEST_ST_SRC21_BYPASS( 19, 0, 1, lw, sw, 0x30011223, 4, tdat ); + TEST_ST_SRC21_BYPASS( 20, 0, 2, lw, sw, 0x33001122, 8, tdat ); + TEST_ST_SRC21_BYPASS( 21, 1, 0, lw, sw, 0x23300112, 12, tdat ); + TEST_ST_SRC21_BYPASS( 22, 1, 1, lw, sw, 0x22330011, 16, tdat ); + TEST_ST_SRC21_BYPASS( 23, 2, 0, lw, sw, 0x12233001, 20, tdat ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +tdat1: .word 0xdeadbeef +tdat2: .word 0xdeadbeef +tdat3: .word 0xdeadbeef +tdat4: .word 0xdeadbeef +tdat5: .word 0xdeadbeef +tdat6: .word 0xdeadbeef +tdat7: .word 0xdeadbeef +tdat8: .word 0xdeadbeef +tdat9: .word 0xdeadbeef +tdat10: .word 0xdeadbeef + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/xor.S b/tests/isa/rv32ui/xor.S new file mode 100644 index 0000000..c4e9552 --- /dev/null +++ b/tests/isa/rv32ui/xor.S @@ -0,0 +1,69 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xor.S +#----------------------------------------------------------------------------- +# +# Test xor instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_OP( 3, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_OP( 4, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_OP( 5, xor, 0x00ff00ff, 0xf00ff00f, 0xf0f0f0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 6, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC2_EQ_DEST( 7, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_EQ_DEST( 8, xor, 0x00000000, 0xff00ff00 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 9, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_DEST_BYPASS( 10, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_DEST_BYPASS( 11, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC12_BYPASS( 12, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 13, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 14, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 15, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC12_BYPASS( 16, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC12_BYPASS( 17, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_SRC21_BYPASS( 18, 0, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 19, 0, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 20, 0, 2, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 21, 1, 0, xor, 0xf00ff00f, 0xff00ff00, 0x0f0f0f0f ); + TEST_RR_SRC21_BYPASS( 22, 1, 1, xor, 0xff00ff00, 0x0ff00ff0, 0xf0f0f0f0 ); + TEST_RR_SRC21_BYPASS( 23, 2, 0, xor, 0x0ff00ff0, 0x00ff00ff, 0x0f0f0f0f ); + + TEST_RR_ZEROSRC1( 24, xor, 0xff00ff00, 0xff00ff00 ); + TEST_RR_ZEROSRC2( 25, xor, 0x00ff00ff, 0x00ff00ff ); + TEST_RR_ZEROSRC12( 26, xor, 0 ); + TEST_RR_ZERODEST( 27, xor, 0x11111111, 0x22222222 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/rv32ui/xori.S b/tests/isa/rv32ui/xori.S new file mode 100644 index 0000000..eb59d12 --- /dev/null +++ b/tests/isa/rv32ui/xori.S @@ -0,0 +1,55 @@ +# See LICENSE for license details. + +#***************************************************************************** +# xori.S +#----------------------------------------------------------------------------- +# +# Test xori instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Logical tests + #------------------------------------------------------------- + + TEST_IMM_OP( 2, xori, 0xffffffffff00f00f, 0x0000000000ff0f00, 0xf0f ); + TEST_IMM_OP( 3, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_OP( 4, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); + TEST_IMM_OP( 5, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_IMM_SRC1_EQ_DEST( 6, xori, 0xffffffffff00f00f, 0xffffffffff00f700, 0x70f ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_IMM_DEST_BYPASS( 7, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_DEST_BYPASS( 8, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff08ff, 0x70f ); + TEST_IMM_DEST_BYPASS( 9, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_SRC1_BYPASS( 10, 0, xori, 0x000000000ff00f00, 0x000000000ff00ff0, 0x0f0 ); + TEST_IMM_SRC1_BYPASS( 11, 1, xori, 0x0000000000ff0ff0, 0x0000000000ff0fff, 0x00f ); + TEST_IMM_SRC1_BYPASS( 12, 2, xori, 0xfffffffff00ff0ff, 0xfffffffff00ff00f, 0x0f0 ); + + TEST_IMM_ZEROSRC1( 13, xori, 0x0f0, 0x0f0 ); + TEST_IMM_ZERODEST( 14, xori, 0x00ff00ff, 0x70f ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/isa/test_macros.h b/tests/isa/test_macros.h new file mode 100644 index 0000000..095c85a --- /dev/null +++ b/tests/isa/test_macros.h @@ -0,0 +1,877 @@ +// See LICENSE for license details. + +#ifndef __TEST_MACROS_H +#define __TEST_MACROS_H + +#ifndef __riscv_xlen +#define __riscv_xlen 32 +#endif + +#----------------------------------------------------------------------- +# Helper macros +#----------------------------------------------------------------------- + +#define MASK_XLEN(x) ((x) & ((1 << (__riscv_xlen - 1) << 1) - 1)) +/////////////////////origin funct////////////////////////////////////////// +#define TEST_CASE( testnum, testreg, correctval, code... ) \ +test_ ## testnum: \ + code; \ + li x29, MASK_XLEN(correctval); \ + li TESTNUM, testnum; \ + bne testreg, x29, fail; + +// Dzj: Newly added specially for rv32ud +#define TEST_CASE_fclass( testnum, testreg, correctval,input, code... ) \ +test_ ## testnum: \ + la a0, test_ ## testnum ## _data ;\ + code; \ + li x29, MASK_XLEN(correctval); \ + li TESTNUM, testnum; \ + bne testreg, x29, fail;\ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .dword input; \ + .popsection + +// Dzj: Newly added specially for rv32ud +#define TEST_CASE_fcvt( testnum, testreg, correctval_high, correctval_low, code... ) \ +test_ ## testnum: \ + code; \ + li a6 , correctval_high; \ + li a5 , correctval_low; \ + li TESTNUM, testnum; \ + bne a3, a5, fail;\ + bne a4, a6, fail; +// +#define TEST_CASE_fcvt_w( testnum, testreg, correctval_high , correctval_low , code... ) \ +test_ ## testnum: \ + code; \ + li a5 , correctval_low; \ + li TESTNUM, testnum; \ + bne testreg, a5, fail; +// +#define TEST_CASE_ldst( testnum, testreg, correctval_high , correctval_low , code... ) \ +test_ ## testnum: \ + code; \ + li a6 , correctval_high; \ + li a5 , correctval_low; \ + li TESTNUM, testnum; \ + bne a3, a5, fail;\ + bne a4, a6, fail; +// +#define TEST_CASE_FSGNJD( testnum, testreg, correctval_high, correctval_low, code... ) \ +test_ ## testnum: \ + code; \ + li a6 , correctval_high; \ + li a5 , correctval_low; \ + li TESTNUM, testnum; \ + bne a3, a5, fail;\ + bne a4, a6, fail; +// +#define TEST_CASE_1_FSGNJS( testnum, testreg, correctval, code... ) \ +test_ ## testnum: \ + code; \ + li x29, MASK_XLEN(correctval); \ + li TESTNUM, testnum; \ + bne testreg, x29, fail; +// +#define TEST_CASE_2_FSGNJS( testnum, testreg, correctval_high, correctval_low, code... ) \ +test_ ## testnum: \ + code; \ + li a6 , correctval_high; \ + li a5 , correctval_low; \ + li TESTNUM, testnum; \ + bne a3, a5, fail;\ + bne a4, a6, fail; +// +#define TEST_CASE_1_FSGNJD_SP( testnum, testreg, correctval, code... ) \ +test_ ## testnum: \ + code; \ + li x29, MASK_XLEN(correctval); \ + li TESTNUM, testnum; \ + bne testreg, x29, fail; +// +#define TEST_CASE_2_FSGNJD_SP( testnum, testreg, correctval_high, correctval_low, code... ) \ +test_ ## testnum: \ + code; \ + li a6 , correctval_high; \ + li a5 , correctval_low; \ + li TESTNUM, testnum; \ + bne a3, a5, fail;\ + bne a4, a6, fail; +///////////////////////////////////////////////////////////////////////////////////// + +# We use a macro hack to simpify code generation for various numbers +# of bubble cycles. + +#define TEST_INSERT_NOPS_0 +#define TEST_INSERT_NOPS_1 nop; TEST_INSERT_NOPS_0 +#define TEST_INSERT_NOPS_2 nop; TEST_INSERT_NOPS_1 +#define TEST_INSERT_NOPS_3 nop; TEST_INSERT_NOPS_2 +#define TEST_INSERT_NOPS_4 nop; TEST_INSERT_NOPS_3 +#define TEST_INSERT_NOPS_5 nop; TEST_INSERT_NOPS_4 +#define TEST_INSERT_NOPS_6 nop; TEST_INSERT_NOPS_5 +#define TEST_INSERT_NOPS_7 nop; TEST_INSERT_NOPS_6 +#define TEST_INSERT_NOPS_8 nop; TEST_INSERT_NOPS_7 +#define TEST_INSERT_NOPS_9 nop; TEST_INSERT_NOPS_8 +#define TEST_INSERT_NOPS_10 nop; TEST_INSERT_NOPS_9 + + +#----------------------------------------------------------------------- +# RV64UI MACROS +#----------------------------------------------------------------------- + +#----------------------------------------------------------------------- +# Tests for instructions with immediate operand +#----------------------------------------------------------------------- + +#define SEXT_IMM(x) ((x) | (-(((x) >> 11) & 1) << 11)) + +#define TEST_IMM_OP( testnum, inst, result, val1, imm ) \ + TEST_CASE( testnum, x30, result, \ + li x1, MASK_XLEN(val1); \ + inst x30, x1, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_SRC1_EQ_DEST( testnum, inst, result, val1, imm ) \ + TEST_CASE( testnum, x1, result, \ + li x1, MASK_XLEN(val1); \ + inst x1, x1, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ + TEST_CASE( testnum, x6, result, \ + li x4, 0; \ +1: li x1, MASK_XLEN(val1); \ + inst x30, x1, SEXT_IMM(imm); \ + TEST_INSERT_NOPS_ ## nop_cycles \ + addi x6, x30, 0; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_IMM_SRC1_BYPASS( testnum, nop_cycles, inst, result, val1, imm ) \ + TEST_CASE( testnum, x30, result, \ + li x4, 0; \ +1: li x1, MASK_XLEN(val1); \ + TEST_INSERT_NOPS_ ## nop_cycles \ + inst x30, x1, SEXT_IMM(imm); \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_IMM_ZEROSRC1( testnum, inst, result, imm ) \ + TEST_CASE( testnum, x1, result, \ + inst x1, x0, SEXT_IMM(imm); \ + ) + +#define TEST_IMM_ZERODEST( testnum, inst, val1, imm ) \ + TEST_CASE( testnum, x0, 0, \ + li x1, MASK_XLEN(val1); \ + inst x0, x1, SEXT_IMM(imm); \ + ) + +#----------------------------------------------------------------------- +# Tests for an instruction with register operands +#----------------------------------------------------------------------- + +#define TEST_R_OP( testnum, inst, result, val1 ) \ + TEST_CASE( testnum, x30, result, \ + li x1, val1; \ + inst x30, x1; \ + ) + +#define TEST_R_SRC1_EQ_DEST( testnum, inst, result, val1 ) \ + TEST_CASE( testnum, x1, result, \ + li x1, val1; \ + inst x1, x1; \ + ) + +#define TEST_R_DEST_BYPASS( testnum, nop_cycles, inst, result, val1 ) \ + TEST_CASE( testnum, x6, result, \ + li x4, 0; \ +1: li x1, val1; \ + inst x30, x1; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + addi x6, x30, 0; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#----------------------------------------------------------------------- +# Tests for an instruction with register-register operands +#----------------------------------------------------------------------- + +#define TEST_RR_OP( testnum, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x30, result, \ + li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x30, x1, x2; \ + ) + +#define TEST_RR_SRC1_EQ_DEST( testnum, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x1, result, \ + li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x1, x1, x2; \ + ) + +#define TEST_RR_SRC2_EQ_DEST( testnum, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x2, result, \ + li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x2, x1, x2; \ + ) + +#define TEST_RR_SRC12_EQ_DEST( testnum, inst, result, val1 ) \ + TEST_CASE( testnum, x1, result, \ + li x1, MASK_XLEN(val1); \ + inst x1, x1, x1; \ + ) + +#define TEST_RR_DEST_BYPASS( testnum, nop_cycles, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x6, result, \ + li x4, 0; \ +1: li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x30, x1, x2; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + addi x6, x30, 0; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_RR_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x30, result, \ + li x4, 0; \ +1: li x1, MASK_XLEN(val1); \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x2, MASK_XLEN(val2); \ + TEST_INSERT_NOPS_ ## src2_nops \ + inst x30, x1, x2; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_RR_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, result, val1, val2 ) \ + TEST_CASE( testnum, x30, result, \ + li x4, 0; \ +1: li x2, MASK_XLEN(val2); \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x1, MASK_XLEN(val1); \ + TEST_INSERT_NOPS_ ## src2_nops \ + inst x30, x1, x2; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + ) + +#define TEST_RR_ZEROSRC1( testnum, inst, result, val ) \ + TEST_CASE( testnum, x2, result, \ + li x1, MASK_XLEN(val); \ + inst x2, x0, x1; \ + ) + +#define TEST_RR_ZEROSRC2( testnum, inst, result, val ) \ + TEST_CASE( testnum, x2, result, \ + li x1, MASK_XLEN(val); \ + inst x2, x1, x0; \ + ) + +#define TEST_RR_ZEROSRC12( testnum, inst, result ) \ + TEST_CASE( testnum, x1, result, \ + inst x1, x0, x0; \ + ) + +#define TEST_RR_ZERODEST( testnum, inst, val1, val2 ) \ + TEST_CASE( testnum, x0, 0, \ + li x1, MASK_XLEN(val1); \ + li x2, MASK_XLEN(val2); \ + inst x0, x1, x2; \ + ) + +#----------------------------------------------------------------------- +# Test memory instructions +#----------------------------------------------------------------------- + +#define TEST_LD_OP( testnum, inst, result, offset, base ) \ + TEST_CASE( testnum, x30, result, \ + la x1, base; \ + inst x30, offset(x1); \ + ) + +#define TEST_ST_OP( testnum, load_inst, store_inst, result, offset, base ) \ + TEST_CASE( testnum, x30, result, \ + la x1, base; \ + li x2, result; \ + store_inst x2, offset(x1); \ + load_inst x30, offset(x1); \ + ) + +#define TEST_LD_DEST_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x1, base; \ + inst x30, offset(x1); \ + TEST_INSERT_NOPS_ ## nop_cycles \ + addi x6, x30, 0; \ + li x29, result; \ + bne x6, x29, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b; \ + +#define TEST_LD_SRC1_BYPASS( testnum, nop_cycles, inst, result, offset, base ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x1, base; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + inst x30, offset(x1); \ + li x29, result; \ + bne x30, x29, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_ST_SRC12_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: li x1, result; \ + TEST_INSERT_NOPS_ ## src1_nops \ + la x2, base; \ + TEST_INSERT_NOPS_ ## src2_nops \ + store_inst x1, offset(x2); \ + load_inst x30, offset(x2); \ + li x29, result; \ + bne x30, x29, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_ST_SRC21_BYPASS( testnum, src1_nops, src2_nops, load_inst, store_inst, result, offset, base ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x2, base; \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x1, result; \ + TEST_INSERT_NOPS_ ## src2_nops \ + store_inst x1, offset(x2); \ + load_inst x30, offset(x2); \ + li x29, result; \ + bne x30, x29, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_BR2_OP_TAKEN( testnum, inst, val1, val2 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x1, val1; \ + li x2, val2; \ + inst x1, x2, 2f; \ + bne x0, TESTNUM, fail; \ +1: bne x0, TESTNUM, 3f; \ +2: inst x1, x2, 1b; \ + bne x0, TESTNUM, fail; \ +3: + +#define TEST_BR2_OP_NOTTAKEN( testnum, inst, val1, val2 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x1, val1; \ + li x2, val2; \ + inst x1, x2, 1f; \ + bne x0, TESTNUM, 2f; \ +1: bne x0, TESTNUM, fail; \ +2: inst x1, x2, 1b; \ +3: + +#define TEST_BR2_SRC12_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: li x1, val1; \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x2, val2; \ + TEST_INSERT_NOPS_ ## src2_nops \ + inst x1, x2, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_BR2_SRC21_BYPASS( testnum, src1_nops, src2_nops, inst, val1, val2 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: li x2, val2; \ + TEST_INSERT_NOPS_ ## src1_nops \ + li x1, val1; \ + TEST_INSERT_NOPS_ ## src2_nops \ + inst x1, x2, fail; \ + addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#----------------------------------------------------------------------- +# Test jump instructions +#----------------------------------------------------------------------- + +#define TEST_JR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x6, 2f; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + inst x6; \ + bne x0, TESTNUM, fail; \ +2: addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + +#define TEST_JALR_SRC1_BYPASS( testnum, nop_cycles, inst ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + li x4, 0; \ +1: la x6, 2f; \ + TEST_INSERT_NOPS_ ## nop_cycles \ + inst x19, x6, 0; \ + bne x0, TESTNUM, fail; \ +2: addi x4, x4, 1; \ + li x5, 2; \ + bne x4, x5, 1b \ + + +#----------------------------------------------------------------------- +# RV64UF MACROS +#----------------------------------------------------------------------- + +#----------------------------------------------------------------------- +# Tests floating-point instructions +#----------------------------------------------------------------------- + +#define qNaNf 0f:7fc00000 +#define sNaNf 0f:7f800001 +#define qNaN 0d:7ff8000000000000 +#define sNaN 0d:7ff0000000000001 +///////////////////////////origin funct////////////////////////////////////////////////////////// +#define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + flw f0, 0(a0); \ + flw f1, 4(a0); \ + flw f2, 8(a0); \ + lw a3, 12(a0); \ + code; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a0, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 2; \ + test_ ## testnum ## _data: \ + .float val1; \ + .float val2; \ + .float val3; \ + .result; \ + .popsection +//Dzj:Newly added specially for rv32ud +#define TEST_FP_OP_S_INTERNAL_fcvt( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + flw f0, 0(a0); \ + flw f1, 4(a0); \ + flw f2, 8(a0); \ + lw a3, 12(a0); \ + code; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a0, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 2; \ + test_ ## testnum ## _data: \ + .float val1; \ + .float val2; \ + .float val3; \ + .result; \ + .popsection + +////////////////////////////////////////////////////////////////////////////////////////////// +////////////////////////////////origin funct////////////////////////////////////////////////////// +#define TEST_FP_OP_D_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + ld a3, 24(a0); \ + code; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a0, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection +// +#define TEST_FP_OP_D_INTERNAL_fadd( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + lw a3, 24(a0); \ + lw a4, 28(a0);\ + code; \ + bne a4, a5, fail; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a6, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection +// +#define TEST_FP_OP_D_INTERNAL_fdiv( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + lw a3, 24(a0); \ + lw a4, 28(a0);\ + code; \ + bne a4, a5, fail; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a6, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection +// +#define TEST_FP_OP_D_INTERNAL_fcmp( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + lw a3, 24(a0); \ + code; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a3, a0, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection +// +#define TEST_FP_OP_D_INTERNAL_fcvt( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + lw a3, 24(a0); \ + lw a4, 28(a0);\ + code; \ + bne a4, a5, fail; \ + bne a6, a3, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection +// +#define TEST_FP_OP_D_INTERNAL_fcvt_w( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + lw a3, 24(a0); \ + code; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a0, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection +// +#define TEST_FP_OP_D_INTERNAL_fmadd( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + lw a3, 24(a0); \ + lw a4, 28(a0);\ + code; \ + bne a4, a5, fail; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a6, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection +// +#define TEST_FP_OP_D_INTERNAL_fmin( testnum, flags, result, val1, val2, val3, code... ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + fld f0, 0(a0); \ + fld f1, 8(a0); \ + fld f2, 16(a0); \ + lw a3, 24(a0); \ + lw a4, 28(a0);\ + code; \ + bne a4, a5, fail; \ + fsflags a1, x0; \ + li a2, flags; \ + bne a6, a3, fail; \ + bne a1, a2, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double val1; \ + .double val2; \ + .double val3; \ + .result; \ + .popsection +///////////////////////////////////////////////////////////////////////////////////////////////// +/////////////////////////////origin funct////////////////////////////////////////////////////////////// +#define TEST_FCVT_S_D( testnum, result, val1 ) \ + TEST_FP_OP_D_INTERNAL( testnum, 0, double result, val1, 0.0, 0.0, \ + fcvt.s.d f3, f0; fcvt.d.s f3, f3; fmv.x.d a0, f3) + + +#define TEST_FCVT_S_D_fcvt( testnum, result, val1 ) \ + TEST_FP_OP_D_INTERNAL_fcvt( testnum, 0, double result, val1, 0.0, 0.0, \ + fcvt.s.d f3, f0; fcvt.d.s f3, f3; fsd f3, 24(a0); lw a6 ,24(a0); lw a5,28(a0)) +/////////////////////////////////origin funct/////////////////////////////////////////////////////////////////////// +#define TEST_FCVT_D_S( testnum, result, val1 ) \ + TEST_FP_OP_S_INTERNAL( testnum, 0, float result, val1, 0.0, 0.0, \ + fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3) +// +#define TEST_FCVT_D_S_fcvt( testnum, result, val1 ) \ + TEST_FP_OP_S_INTERNAL_fcvt( testnum, 0, float result, val1, 0.0, 0.0, \ + fcvt.d.s f3, f0; fcvt.s.d f3, f3; fmv.x.s a0, f3) +//////////////////////////////////////////////////////////////////////////////////////////////// +#define TEST_FP_OP1_S( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.s a0, f3) +/////////////////////////////////origin funct//////////////////////////////////////////////// +#define TEST_FP_OP1_D( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.d a0, f3) +// +#define TEST_FP_OP1_D_fdiv( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_D_INTERNAL_fdiv( testnum, flags, double result, val1, 0.0, 0.0, \ + inst f3, f0;fsd f3, 24(a0); lw a6 ,24(a0); lw a5,28(a0)) +///////////////////////////////////////////////////////////////////////////////// +#define TEST_FP_OP1_S_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.s a0, f3) +///////////////////////////////origin funct///////////////////////////////////////////////// +#define TEST_FP_OP1_D_DWORD_RESULT( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst f3, f0; fmv.x.d a0, f3) +// +#define TEST_FP_OP1_D_DWORD_RESULT_fdiv( testnum, inst, flags, result, val1 ) \ + TEST_FP_OP_D_INTERNAL_fdiv( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst f3, f0; fsd f3, 24(a0); lw a6 ,24(a0); lw a5,28(a0)) +// +//////////////////////////////////////////////////////////////////////////////////////////// +#define TEST_FP_OP2_S( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, 0.0, \ + inst f3, f0, f1; fmv.x.s a0, f3) +/////////////////////////origin function///////////////////////////////// +#define TEST_FP_OP2_D( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, 0.0, \ + inst f3, f0, f1; fmv.x.d a0, f3) +// +#define TEST_FP_OP2_D_fadd( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D_INTERNAL_fadd( testnum, flags, double result, val1, val2, 0.0, \ + inst f3, f0, f1; fsd f3, 24(a0); lw a6 ,24(a0); lw a5,28(a0)) +// +#define TEST_FP_OP2_D_fdiv( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D_INTERNAL_fdiv( testnum, flags, double result, val1, val2, 0.0, \ + inst f3, f0, f1; fsd f3, 24(a0); lw a6 ,24(a0); lw a5,28(a0)) +// +#define TEST_FP_OP2_D_fmin( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D_INTERNAL_fmin( testnum, flags, double result, val1, val2, 0.0, \ + inst f3, f0, f1; fsd f3, 24(a0); lw a6 ,24(a0); lw a5,28(a0)) +/////////////////////////////////////////////////////////////////////////////// +#define TEST_FP_OP3_S( testnum, inst, flags, result, val1, val2, val3 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, float result, val1, val2, val3, \ + inst f3, f0, f1, f2; fmv.x.s a0, f3) +///////////////////////////origin funct////////////////////////////////////////////////////////// +#define TEST_FP_OP3_D( testnum, inst, flags, result, val1, val2, val3 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, double result, val1, val2, val3, \ + inst f3, f0, f1, f2; fmv.x.d a0, f3) + +#define TEST_FP_OP3_D_fmadd( testnum, inst, flags, result, val1, val2, val3 ) \ + TEST_FP_OP_D_INTERNAL_fmadd( testnum, flags, double result, val1, val2, val3, \ + inst f3, f0, f1, f2; fsd f3, 24(a0); lw a6 ,24(a0); lw a5,28(a0)) +//////////////////////////////////////////////////////////////////////////////////////// +#define TEST_FP_INT_OP_S( testnum, inst, flags, result, val1, rm ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, 0.0, 0.0, \ + inst a0, f0, rm) +//////////////////////////origin funct////////////////////////////////////////////////// +#define TEST_FP_INT_OP_D( testnum, inst, flags, result, val1, rm ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst a0, f0, rm) +// +#define TEST_FP_INT_OP_D_fcvt_w( testnum, inst, flags, result, val1, rm ) \ + TEST_FP_OP_D_INTERNAL_fcvt_w( testnum, flags, dword result, val1, 0.0, 0.0, \ + inst a0, f0, rm) +///////////////////////////////////////////////////////////////////////// +#define TEST_FP_CMP_OP_S( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_S_INTERNAL( testnum, flags, word result, val1, val2, 0.0, \ + inst a0, f0, f1) +///////////////////////////origin funct///////////////////////////////////////////// +#define TEST_FP_CMP_OP_D( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D_INTERNAL( testnum, flags, dword result, val1, val2, 0.0, \ + inst a0, f0, f1) +// +#define TEST_FP_CMP_OP_D_fcmp( testnum, inst, flags, result, val1, val2 ) \ + TEST_FP_OP_D_INTERNAL_fcmp( testnum, flags, dword result, val1, val2, 0.0, \ + inst a0, f0, f1) +/////////////////////////////////////////////////////////////////////////////////// +#define TEST_FCLASS_S(testnum, correct, input) \ + TEST_CASE(testnum, a0, correct, li a0, input; fmv.s.x fa0, a0; \ + fclass.s a0, fa0) +/////////////////////////origin function/////////////////////////////////////////////// +#define TEST_FCLASS_D(testnum, correct, input) \ + TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ + fclass.d a0, fa0) +// +#define TEST_FCLASS_D_fclass(testnum, correct, input) \ + TEST_CASE_fclass(testnum, a0, correct, input, fld fa0,(a0); \ + fclass.d a0, fa0) +////////////////////////////////////////////////////////////////////////////////////// +#define TEST_INT_FP_OP_S( testnum, inst, result, val1 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + lw a3, 0(a0); \ + li a0, val1; \ + inst f0, a0; \ + fsflags x0; \ + fmv.x.s a0, f0; \ + bne a0, a3, fail; \ + .pushsection .data; \ + .align 2; \ + test_ ## testnum ## _data: \ + .float result; \ + .popsection +////////////////////////////////origin function///////////////////////////////////////////////////// +#define TEST_INT_FP_OP_D( testnum, inst, result, val1 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + ld a3, 0(a0); \ + li a0, val1; \ + inst f0, a0; \ + fsflags x0; \ + fmv.x.d a0, f0; \ + bne a0, a3, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double result; \ + .popsection +//Dzj:Newly added specially for rv32ud +#define TEST_INT_FP_OP_D_fcvt( testnum, inst, result, val1 ) \ +test_ ## testnum: \ + li TESTNUM, testnum; \ + la a0, test_ ## testnum ## _data ;\ + lw a3, 0(a0);\ + lw a4, 4(a0);\ + li a1, val1; \ + inst f0, a1; \ + fsflags x0; \ + fsd f0, 0(a0);\ + lw a6, 0(a0);\ + lw a5, 4(a0);\ + bne a4, a5, fail; \ + bne a6, a3, fail; \ + .pushsection .data; \ + .align 3; \ + test_ ## testnum ## _data: \ + .double result; \ + .popsection +//////////////////////////////////////////////////////////////////////////////////////////////////////////////// +#----------------------------------------------------------------------- +# Pass and fail code (assumes test num is in TESTNUM) +#----------------------------------------------------------------------- + +#define TEST_PASSFAIL \ + bne x0, TESTNUM, pass; \ +fail: \ + RVTEST_FAIL; \ +pass: \ + RVTEST_PASS \ + + +#----------------------------------------------------------------------- +# Test data section +#----------------------------------------------------------------------- + +#define TEST_DATA + +#endif diff --git a/tools/BinToMem_CLI.exe b/tools/BinToMem_CLI.exe new file mode 100644 index 0000000..b46a0d4 Binary files /dev/null and b/tools/BinToMem_CLI.exe differ diff --git a/tools/BinToMem_GUI.exe b/tools/BinToMem_GUI.exe new file mode 100644 index 0000000..f479f97 Binary files /dev/null and b/tools/BinToMem_GUI.exe differ