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rtl🚌 use gnt and rvalid signal 

Signed-off-by: liangkangnan <liangkangnan@163.com>
pull/4/head
liangkangnan 2021-09-01 09:54:32 +08:00
parent f7231a2f15
commit ae3ff5a211
14 changed files with 232 additions and 117 deletions
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2
rtl/core/exu_mem.sv
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@ -183,7 +183,7 @@ module exu_mem(
endcase endcase
end end
assign mem_req_o = req_mem_i; assign mem_req_o = req_mem_i && (state_q == S_IDLE);
assign mem_addr_o = mem_addr_i; assign mem_addr_o = mem_addr_i;
// 暂停流水线 // 暂停流水线

4
rtl/debug/jtag_dm.sv
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@ -58,6 +58,8 @@ module jtag_dm #(
input wire [31:0] slave_addr_i, input wire [31:0] slave_addr_i,
input wire [3:0] slave_be_i, input wire [3:0] slave_be_i,
input wire [31:0] slave_wdata_i, input wire [31:0] slave_wdata_i,
output wire slave_gnt_o,
output wire slave_rvalid_o,
output wire [31:0] slave_rdata_o output wire [31:0] slave_rdata_o
); );
@ -497,6 +499,8 @@ module jtag_dm #(
.addr_i(slave_addr_i), .addr_i(slave_addr_i),
.be_i(slave_be_i), .be_i(slave_be_i),
.wdata_i(slave_wdata_i), .wdata_i(slave_wdata_i),
.gnt_o(slave_gnt_o),
.rvalid_o(slave_rvalid_o),
.rdata_o(slave_rdata_o) .rdata_o(slave_rdata_o)
); );

15
rtl/debug/jtag_mem.sv
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@ -43,6 +43,8 @@ module jtag_mem(
input wire [31:0] addr_i, input wire [31:0] addr_i,
input wire [3:0] be_i, input wire [3:0] be_i,
input wire [31:0] wdata_i, input wire [31:0] wdata_i,
output wire gnt_o,
output wire rvalid_o,
output wire [31:0] rdata_o output wire [31:0] rdata_o
); );
@ -180,6 +182,7 @@ module jtag_mem(
reg data_valid; reg data_valid;
reg cmdbusy; reg cmdbusy;
reg halted_aligned; reg halted_aligned;
reg rvalid_q;
wire fwd_rom_d; wire fwd_rom_d;
wire[31:0] rom_rdata; wire[31:0] rom_rdata;
reg[31:0] data_bits; reg[31:0] data_bits;
@ -204,7 +207,8 @@ module jtag_mem(
assign halted_o = halted_q; assign halted_o = halted_q;
assign resumeack_o = resuming_q; assign resumeack_o = resuming_q;
assign gnt_o = req_i;
assign rvalid_o = rvalid_q;
always @ (*) begin always @ (*) begin
state_d = state_q; state_d = state_q;
@ -292,7 +296,7 @@ module jtag_mem(
end end
// write // write
if (we_i) begin if (req_i & we_i) begin
case (addr_i[DbgAddressBits-1:0]) case (addr_i[DbgAddressBits-1:0])
HaltedAddr: begin HaltedAddr: begin
halted_d = 1'b1; halted_d = 1'b1;
@ -328,7 +332,7 @@ module jtag_mem(
default:; default:;
endcase endcase
// read // read
end else begin end else if (req_i & (!we_i)) begin
case (addr_i[DbgAddressBits-1:0]) case (addr_i[DbgAddressBits-1:0])
WhereToAddr: begin WhereToAddr: begin
if (cmdbusy & (cmd_type == CmdAccessRegister)) begin if (cmdbusy & (cmd_type == CmdAccessRegister)) begin
@ -472,12 +476,11 @@ module jtag_mem(
wire[31:0] rom_addr; wire[31:0] rom_addr;
assign rom_addr = addr_i; assign rom_addr = addr_i;
assign fwd_rom_d = addr_i[DbgAddressBits-1:0] >= `HaltAddress; assign fwd_rom_d = addr_i[DbgAddressBits-1:0] >= `HaltAddress;
debug_rom u_debug_rom ( debug_rom u_debug_rom (
.clk_i ( clk ), .clk_i ( clk ),
.req_i ( 1'b1 ), .req_i ( req_i ),
.addr_i ( rom_addr ), .addr_i ( rom_addr ),
.rdata_o ( rom_rdata ) .rdata_o ( rom_rdata )
); );
@ -488,11 +491,13 @@ module jtag_mem(
fwd_rom_q <= 1'b0; fwd_rom_q <= 1'b0;
halted_q <= 1'b0; halted_q <= 1'b0;
resuming_q <= 1'b0; resuming_q <= 1'b0;
rvalid_q <= 1'b0;
end else begin end else begin
rdata_q <= rdata_d; rdata_q <= rdata_d;
fwd_rom_q <= fwd_rom_d; fwd_rom_q <= fwd_rom_d;
halted_q <= halted_d; halted_q <= halted_d;
resuming_q <= resuming_d; resuming_q <= resuming_d;
rvalid_q <= req_i;
end end
end end

4
rtl/debug/jtag_top.sv
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@ -45,6 +45,8 @@ module jtag_top(
input wire [31:0] slave_addr_i, input wire [31:0] slave_addr_i,
input wire [3:0] slave_be_i, input wire [3:0] slave_be_i,
input wire [31:0] slave_wdata_i, input wire [31:0] slave_wdata_i,
output wire slave_gnt_o,
output wire slave_rvalid_o,
output wire [31:0] slave_rdata_o output wire [31:0] slave_rdata_o
); );
@ -88,6 +90,8 @@ module jtag_top(
.slave_addr_i (slave_addr_i), .slave_addr_i (slave_addr_i),
.slave_be_i (slave_be_i), .slave_be_i (slave_be_i),
.slave_wdata_i (slave_wdata_i), .slave_wdata_i (slave_wdata_i),
.slave_gnt_o (slave_gnt_o),
.slave_rvalid_o (slave_rvalid_o),
.slave_rdata_o (slave_rdata_o) .slave_rdata_o (slave_rdata_o)
); );

18
rtl/perips/gpio/gpio_top.sv
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@ -34,6 +34,8 @@ module gpio_top #(
input logic [ 3:0] be_i, input logic [ 3:0] be_i,
input logic [31:0] addr_i, input logic [31:0] addr_i,
input logic [31:0] data_i, input logic [31:0] data_i,
output logic gnt_o,
output logic rvalid_o,
output logic [31:0] data_o output logic [31:0] data_o
); );
@ -42,6 +44,8 @@ module gpio_top #(
logic [31:0] addr; logic [31:0] addr;
logic [31:0] reg_rdata; logic [31:0] reg_rdata;
assign gnt_o = req_i;
// 读信号 // 读信号
assign re = req_i & (!we_i); assign re = req_i & (!we_i);
// 写信号 // 写信号
@ -49,6 +53,16 @@ module gpio_top #(
// 去掉基地址 // 去掉基地址
assign addr = {16'h0, addr_i[15:0]}; assign addr = {16'h0, addr_i[15:0]};
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rvalid_o <= '0;
data_o <= '0;
end else begin
rvalid_o <= req_i;
data_o <= reg_rdata;
end
end
gpio_core #( gpio_core #(
.GPIO_NUM(GPIO_NUM) .GPIO_NUM(GPIO_NUM)
) u_gpio_core ( ) u_gpio_core (
@ -69,8 +83,4 @@ module gpio_top #(
.reg_rdata_o(reg_rdata) .reg_rdata_o(reg_rdata)
); );
always_ff @(posedge clk_i) begin
data_o <= reg_rdata;
end
endmodule endmodule

18
rtl/perips/i2c/i2c_top.sv
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@ -33,6 +33,8 @@ module i2c_top (
input logic [ 3:0] be_i, input logic [ 3:0] be_i,
input logic [31:0] addr_i, input logic [31:0] addr_i,
input logic [31:0] data_i, input logic [31:0] data_i,
output logic gnt_o,
output logic rvalid_o,
output logic [31:0] data_o output logic [31:0] data_o
); );
@ -41,6 +43,8 @@ module i2c_top (
logic [31:0] addr; logic [31:0] addr;
logic [31:0] reg_rdata; logic [31:0] reg_rdata;
assign gnt_o = req_i;
// 读信号 // 读信号
assign re = req_i & (!we_i); assign re = req_i & (!we_i);
// 写信号 // 写信号
@ -48,6 +52,16 @@ module i2c_top (
// 去掉基地址 // 去掉基地址
assign addr = {16'h0, addr_i[15:0]}; assign addr = {16'h0, addr_i[15:0]};
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rvalid_o <= '0;
data_o <= '0;
end else begin
rvalid_o <= req_i;
data_o <= reg_rdata;
end
end
i2c_core u_i2c_core ( i2c_core u_i2c_core (
.clk_i (clk_i), .clk_i (clk_i),
.rst_ni (rst_ni), .rst_ni (rst_ni),
@ -66,8 +80,4 @@ module i2c_top (
.reg_rdata_o(reg_rdata) .reg_rdata_o(reg_rdata)
); );
always_ff @(posedge clk_i) begin
data_o <= reg_rdata;
end
endmodule endmodule

41
rtl/perips/ram.sv
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@ -18,19 +18,36 @@
module ram #( module ram #(
parameter DP = 4096)( parameter DP = 4096
)(
input wire clk, input wire clk_i,
input wire rst_n, input wire rst_ni,
input wire[31:0] addr_i,
input wire[31:0] data_i,
input wire[3:0] sel_i,
input wire we_i,
output wire[31:0] data_o
input wire req_i,
input wire we_i,
input wire [ 3:0] be_i,
input wire [31:0] addr_i,
input wire [31:0] data_i,
output wire gnt_o,
output wire rvalid_o,
output wire [31:0] data_o
); );
wire[31:0] addr = {6'h0, addr_i[27:2]}; reg rvalid_q;
wire[31:0] addr;
assign addr = {6'h0, addr_i[27:2]};
assign gnt_o = req_i;
always @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rvalid_q <= 1'b0;
end else begin
rvalid_q <= req_i;
end
end
assign rvalid_o = rvalid_q;
gen_ram #( gen_ram #(
.DP(DP), .DP(DP),
@ -38,10 +55,10 @@ module ram #(
.MW(4), .MW(4),
.AW(32) .AW(32)
) u_gen_ram( ) u_gen_ram(
.clk(clk), .clk(clk_i),
.addr_i(addr), .addr_i(addr),
.data_i(data_i), .data_i(data_i),
.sel_i(sel_i), .sel_i(be_i),
.we_i(we_i), .we_i(we_i),
.data_o(data_o) .data_o(data_o)
); );

41
rtl/perips/rom.sv
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@ -18,19 +18,36 @@
module rom #( module rom #(
parameter DP = 4096)( parameter DP = 4096
)(
input wire clk, input wire clk_i,
input wire rst_n, input wire rst_ni,
input wire[31:0] addr_i,
input wire[31:0] data_i,
input wire[3:0] sel_i,
input wire we_i,
output wire[31:0] data_o
input wire req_i,
input wire we_i,
input wire [ 3:0] be_i,
input wire [31:0] addr_i,
input wire [31:0] data_i,
output wire gnt_o,
output wire rvalid_o,
output wire [31:0] data_o
); );
wire[31:0] addr = {6'h0, addr_i[27:2]}; reg rvalid_q;
wire[31:0] addr;
assign addr = {6'h0, addr_i[27:2]};
assign gnt_o = req_i;
always @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rvalid_q <= 1'b0;
end else begin
rvalid_q <= req_i;
end
end
assign rvalid_o = rvalid_q;
gen_ram #( gen_ram #(
.DP(DP), .DP(DP),
@ -38,10 +55,10 @@ module rom #(
.MW(4), .MW(4),
.AW(32) .AW(32)
) u_gen_ram( ) u_gen_ram(
.clk(clk), .clk(clk_i),
.addr_i(addr), .addr_i(addr),
.data_i(data_i), .data_i(data_i),
.sel_i(sel_i), .sel_i(be_i),
.we_i(we_i), .we_i(we_i),
.data_o(data_o) .data_o(data_o)
); );

18
rtl/perips/rvic/rvic_top.sv
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@ -28,6 +28,8 @@ module rvic_top (
input logic [ 3:0] be_i, input logic [ 3:0] be_i,
input logic [31:0] addr_i, input logic [31:0] addr_i,
input logic [31:0] data_i, input logic [31:0] data_i,
output logic gnt_o,
output logic rvalid_o,
output logic [31:0] data_o output logic [31:0] data_o
); );
@ -36,6 +38,8 @@ module rvic_top (
logic [31:0] addr; logic [31:0] addr;
logic [31:0] reg_rdata; logic [31:0] reg_rdata;
assign gnt_o = req_i;
// 读信号 // 读信号
assign re = req_i & (!we_i); assign re = req_i & (!we_i);
// 写信号 // 写信号
@ -43,6 +47,16 @@ module rvic_top (
// 去掉基地址 // 去掉基地址
assign addr = {16'h0, addr_i[15:0]}; assign addr = {16'h0, addr_i[15:0]};
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rvalid_o <= '0;
data_o <= '0;
end else begin
rvalid_o <= req_i;
data_o <= reg_rdata;
end
end
rvic_core u_rvic_core ( rvic_core u_rvic_core (
.clk_i (clk_i), .clk_i (clk_i),
.rst_ni (rst_ni), .rst_ni (rst_ni),
@ -57,8 +71,4 @@ module rvic_top (
.reg_rdata_o(reg_rdata) .reg_rdata_o(reg_rdata)
); );
always_ff @(posedge clk_i) begin
data_o <= reg_rdata;
end
endmodule endmodule

18
rtl/perips/timer/timer_top.sv
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@ -26,6 +26,8 @@ module timer_top (
input logic [ 3:0] be_i, input logic [ 3:0] be_i,
input logic [31:0] addr_i, input logic [31:0] addr_i,
input logic [31:0] data_i, input logic [31:0] data_i,
output logic gnt_o,
output logic rvalid_o,
output logic [31:0] data_o output logic [31:0] data_o
); );
@ -34,6 +36,8 @@ module timer_top (
logic [31:0] addr; logic [31:0] addr;
logic [31:0] reg_rdata; logic [31:0] reg_rdata;
assign gnt_o = req_i;
// 读信号 // 读信号
assign re = req_i & (!we_i); assign re = req_i & (!we_i);
// 写信号 // 写信号
@ -41,6 +45,16 @@ module timer_top (
// 去掉基地址 // 去掉基地址
assign addr = {16'h0, addr_i[15:0]}; assign addr = {16'h0, addr_i[15:0]};
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rvalid_o <= '0;
data_o <= '0;
end else begin
rvalid_o <= req_i;
data_o <= reg_rdata;
end
end
timer_core u_timer_core ( timer_core u_timer_core (
.clk_i (clk_i), .clk_i (clk_i),
.rst_ni (rst_ni), .rst_ni (rst_ni),
@ -53,8 +67,4 @@ module timer_top (
.reg_rdata_o(reg_rdata) .reg_rdata_o(reg_rdata)
); );
always_ff @(posedge clk_i) begin
data_o <= reg_rdata;
end
endmodule endmodule

18
rtl/perips/uart/uart_top.sv
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@ -28,6 +28,8 @@ module uart_top (
input logic [ 3:0] be_i, input logic [ 3:0] be_i,
input logic [31:0] addr_i, input logic [31:0] addr_i,
input logic [31:0] data_i, input logic [31:0] data_i,
output logic gnt_o,
output logic rvalid_o,
output logic [31:0] data_o output logic [31:0] data_o
); );
@ -36,6 +38,8 @@ module uart_top (
logic [31:0] addr; logic [31:0] addr;
logic [31:0] reg_rdata; logic [31:0] reg_rdata;
assign gnt_o = req_i;
// 读信号 // 读信号
assign re = req_i & (!we_i); assign re = req_i & (!we_i);
// 写信号 // 写信号
@ -43,6 +47,16 @@ module uart_top (
// 去掉基地址 // 去掉基地址
assign addr = {16'h0, addr_i[15:0]}; assign addr = {16'h0, addr_i[15:0]};
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rvalid_o <= '0;
data_o <= '0;
end else begin
rvalid_o <= req_i;
data_o <= reg_rdata;
end
end
uart_core u_uart_core ( uart_core u_uart_core (
.clk_i (clk_i), .clk_i (clk_i),
.rst_ni (rst_ni), .rst_ni (rst_ni),
@ -57,8 +71,4 @@ module uart_top (
.reg_rdata_o(reg_rdata) .reg_rdata_o(reg_rdata)
); );
always_ff @(posedge clk_i) begin
data_o <= reg_rdata;
end
endmodule endmodule

40
rtl/sys_bus/obi_interconnect.sv
View File

@ -15,12 +15,12 @@
*/ */
// obi总线交叉互联矩阵，支持一对多、多对一、多对多 // obi总线交叉互联矩阵，支持一对多、多对一、多对多
// master之间采用优先级总裁方式，LSB优先级最高，MSB优先级最低 // master之间采用优先级总裁方式：LSB优先级最高，MSB优先级最低
module obi_interconnect #( module obi_interconnect #(
parameter int MASTERS = 3, // number of masters parameter int MASTERS = 3, // number of masters
parameter int SLAVES = 5, // number of slaves parameter int SLAVES = 5, // number of slaves
parameter MASTER_BITS = MASTERS == 1 ? 1 : $clog2(MASTERS), parameter MASTER_BITS = MASTERS == 1 ? 1 : $clog2(MASTERS), // do not change
parameter SLAVE_BITS = SLAVES == 1 ? 1 : $clog2(SLAVES) parameter SLAVE_BITS = SLAVES == 1 ? 1 : $clog2(SLAVES) // do not change
)( )(
input logic clk_i, input logic clk_i,
input logic rst_ni, input logic rst_ni,
@ -93,7 +93,7 @@ module obi_interconnect #(
// slave信号赋值 // slave信号赋值
generate generate
for (s = 0; s < SLAVES; s = s + 1) begin: slave_signal for (s = 0; s < SLAVES; s = s + 1) begin: slave_signals
assign slave_req_o[s] = master_req_i[master_sel_int[s]] & granted_master[s]; assign slave_req_o[s] = master_req_i[master_sel_int[s]] & granted_master[s];
assign slave_we_o[s] = master_we_i[master_sel_int[s]] & granted_master[s]; assign slave_we_o[s] = master_we_i[master_sel_int[s]] & granted_master[s];
assign slave_be_o[s] = master_be_i[master_sel_int[s]]; assign slave_be_o[s] = master_be_i[master_sel_int[s]];
@ -102,45 +102,39 @@ module obi_interconnect #(
end end
endgenerate endgenerate
// 真正被slaves选中的master
logic [MASTERS-1:0] master_sel_or; logic [MASTERS-1:0] master_sel_or;
always_comb begin always_comb begin
master_sel_or = 'b0; master_sel_or = 'b0;
for (integer i = 0; i < SLAVES; i = i + 1) begin: gen_master_sel_or_vec for (integer i = 0; i < SLAVES; i = i + 1) begin: gen_master_sel_or_vec
master_sel_or = master_sel_or | master_sel_vec[i]; master_sel_or = master_sel_or | (master_sel_vec[i] & {MASTERS{granted_master[i]}});
end end
end end
// 保存master选中的slave
logic [SLAVE_BITS-1:0] slave_sel_int_q[MASTERS]; logic [SLAVE_BITS-1:0] slave_sel_int_q[MASTERS];
generate generate
for (m = 0; m < MASTERS; m = m + 1) begin: master_data_q for (m = 0; m < MASTERS; m = m + 1) begin: gen_save_selected_slaves
always_ff @ (posedge clk_i or negedge rst_ni) begin always_ff @ (posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin if (!rst_ni) begin
slave_sel_int_q[m] <= 'b0; slave_sel_int_q[m] <= 'b0;
end else begin end else begin
slave_sel_int_q[m] <= slave_sel_int[m]; if (slave_gnt_i[slave_sel_int[m]] & master_sel_or[m]) begin
slave_sel_int_q[m] <= slave_sel_int[m];
end
end end
end end
end end
endgenerate endgenerate
logic [MASTERS-1:0] master_sel_or_q;
always_ff @ (posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
master_sel_or_q <= 'b0;
end else begin
master_sel_or_q <= master_sel_or;
end
end
// master信号赋值 // master信号赋值
generate generate
for (m = 0; m < MASTERS; m = m + 1) begin: master_data for (m = 0; m < MASTERS; m = m + 1) begin: master_signals
assign master_gnt_o[m] = master_sel_or[m]; assign master_gnt_o[m] = slave_gnt_i[slave_sel_int[m]] & master_sel_or[m];
assign master_rdata_o[m] = slave_rdata_i[slave_sel_int_q[m]]; assign master_rdata_o[m] = slave_rdata_i[slave_sel_int_q[m]];
assign master_rvalid_o[m] = master_sel_or_q[m]; assign master_rvalid_o[m] = slave_rvalid_i[slave_sel_int_q[m]];
end end
endgenerate endgenerate

107
rtl/top/tinyriscv_soc_top.sv
View File

@ -185,13 +185,16 @@ module tinyriscv_soc_top #(
rom #( rom #(
.DP(`ROM_DEPTH) .DP(`ROM_DEPTH)
) u_rom ( ) u_rom (
.clk (clk), .clk_i (clk),
.rst_n (ndmreset_n), .rst_ni (ndmreset_n),
.addr_i (slave_addr[Rom]), .req_i (slave_req[Rom]),
.data_i (slave_wdata[Rom]), .addr_i (slave_addr[Rom]),
.sel_i (slave_be[Rom]), .data_i (slave_wdata[Rom]),
.we_i (slave_we[Rom]), .be_i (slave_be[Rom]),
.data_o (slave_rdata[Rom]) .we_i (slave_we[Rom]),
.gnt_o (slave_gnt[Rom]),
.rvalid_o (slave_rvalid[Rom]),
.data_o (slave_rdata[Rom])
); );
assign slave_addr_mask[Ram] = `RAM_ADDR_MASK; assign slave_addr_mask[Ram] = `RAM_ADDR_MASK;
@ -200,28 +203,33 @@ module tinyriscv_soc_top #(
ram #( ram #(
.DP(`RAM_DEPTH) .DP(`RAM_DEPTH)
) u_ram ( ) u_ram (
.clk (clk), .clk_i (clk),
.rst_n (ndmreset_n), .rst_ni (ndmreset_n),
.addr_i (slave_addr[Ram]), .req_i (slave_req[Ram]),
.data_i (slave_wdata[Ram]), .addr_i (slave_addr[Ram]),
.sel_i (slave_be[Ram]), .data_i (slave_wdata[Ram]),
.we_i (slave_we[Ram]), .be_i (slave_be[Ram]),
.data_o (slave_rdata[Ram]) .we_i (slave_we[Ram]),
.gnt_o (slave_gnt[Ram]),
.rvalid_o (slave_rvalid[Ram]),
.data_o (slave_rdata[Ram])
); );
assign slave_addr_mask[Timer0] = `TIMER0_ADDR_MASK; assign slave_addr_mask[Timer0] = `TIMER0_ADDR_MASK;
assign slave_addr_base[Timer0] = `TIMER0_ADDR_BASE; assign slave_addr_base[Timer0] = `TIMER0_ADDR_BASE;
// 3.定时器0模块 // 3.定时器0模块
timer_top timer0( timer_top timer0(
.clk_i (clk), .clk_i (clk),
.rst_ni (ndmreset_n), .rst_ni (ndmreset_n),
.irq_o (timer0_irq), .irq_o (timer0_irq),
.req_i (slave_req[Timer0]), .req_i (slave_req[Timer0]),
.we_i (slave_we[Timer0]), .we_i (slave_we[Timer0]),
.be_i (slave_be[Timer0]), .be_i (slave_be[Timer0]),
.addr_i (slave_addr[Timer0]), .addr_i (slave_addr[Timer0]),
.data_i (slave_wdata[Timer0]), .data_i (slave_wdata[Timer0]),
.data_o (slave_rdata[Timer0]) .gnt_o (slave_gnt[Timer0]),
.rvalid_o(slave_rvalid[Timer0]),
.data_o (slave_rdata[Timer0])
); );
for (genvar i = 0; i < GPIO_NUM; i = i + 1) begin : g_gpio_data for (genvar i = 0; i < GPIO_NUM; i = i + 1) begin : g_gpio_data
@ -249,6 +257,8 @@ module tinyriscv_soc_top #(
.be_i (slave_be[Gpio]), .be_i (slave_be[Gpio]),
.addr_i (slave_addr[Gpio]), .addr_i (slave_addr[Gpio]),
.data_i (slave_wdata[Gpio]), .data_i (slave_wdata[Gpio]),
.gnt_o (slave_gnt[Gpio]),
.rvalid_o (slave_rvalid[Gpio]),
.data_o (slave_rdata[Gpio]) .data_o (slave_rdata[Gpio])
); );
@ -256,17 +266,19 @@ module tinyriscv_soc_top #(
assign slave_addr_base[Uart0] = `UART0_ADDR_BASE; assign slave_addr_base[Uart0] = `UART0_ADDR_BASE;
// 5.串口0模块 // 5.串口0模块
uart_top uart0 ( uart_top uart0 (
.clk_i (clk), .clk_i (clk),
.rst_ni (ndmreset_n), .rst_ni (ndmreset_n),
.rx_i (uart_rx_pin), .rx_i (uart_rx_pin),
.tx_o (uart_tx_pin), .tx_o (uart_tx_pin),
.irq_o (uart0_irq), .irq_o (uart0_irq),
.req_i (slave_req[Uart0]), .req_i (slave_req[Uart0]),
.we_i (slave_we[Uart0]), .we_i (slave_we[Uart0]),
.be_i (slave_be[Uart0]), .be_i (slave_be[Uart0]),
.addr_i (slave_addr[Uart0]), .addr_i (slave_addr[Uart0]),
.data_i (slave_wdata[Uart0]), .data_i (slave_wdata[Uart0]),
.data_o (slave_rdata[Uart0]) .gnt_o (slave_gnt[Uart0]),
.rvalid_o (slave_rvalid[Uart0]),
.data_o (slave_rdata[Uart0])
); );
assign slave_addr_mask[Rvic] = `RVIC_ADDR_MASK; assign slave_addr_mask[Rvic] = `RVIC_ADDR_MASK;
@ -283,6 +295,8 @@ module tinyriscv_soc_top #(
.be_i (slave_be[Rvic]), .be_i (slave_be[Rvic]),
.addr_i (slave_addr[Rvic]), .addr_i (slave_addr[Rvic]),
.data_i (slave_wdata[Rvic]), .data_i (slave_wdata[Rvic]),
.gnt_o (slave_gnt[Rvic]),
.rvalid_o (slave_rvalid[Rvic]),
.data_o (slave_rdata[Rvic]) .data_o (slave_rdata[Rvic])
); );
@ -309,6 +323,8 @@ module tinyriscv_soc_top #(
.be_i (slave_be[I2c0]), .be_i (slave_be[I2c0]),
.addr_i (slave_addr[I2c0]), .addr_i (slave_addr[I2c0]),
.data_i (slave_wdata[I2c0]), .data_i (slave_wdata[I2c0]),
.gnt_o (slave_gnt[I2c0]),
.rvalid_o (slave_rvalid[I2c0]),
.data_o (slave_rdata[I2c0]) .data_o (slave_rdata[I2c0])
); );
@ -317,16 +333,17 @@ module tinyriscv_soc_top #(
assign slave_addr_base[SimCtrl] = `SIM_CTRL_ADDR_BASE; assign slave_addr_base[SimCtrl] = `SIM_CTRL_ADDR_BASE;
// 8.仿真控制模块 // 8.仿真控制模块
sim_ctrl u_sim_ctrl( sim_ctrl u_sim_ctrl(
.clk_i (clk), .clk_i (clk),
.rst_ni (ndmreset_n), .rst_ni (ndmreset_n),
.dump_wave_en_o(dump_wave_en_o), .dump_wave_en_o(dump_wave_en_o),
.req_i (), .req_i (slave_req[SimCtrl]),
.gnt_o (), .gnt_o (slave_gnt[SimCtrl]),
.addr_i (slave_addr[SimCtrl]), .addr_i (slave_addr[SimCtrl]),
.we_i (slave_we[SimCtrl]), .we_i (slave_we[SimCtrl]),
.be_i (slave_be[SimCtrl]), .be_i (slave_be[SimCtrl]),
.wdata_i(slave_wdata[SimCtrl]), .wdata_i (slave_wdata[SimCtrl]),
.rdata_o(slave_rdata[SimCtrl]) .rvalid_o (slave_rvalid[SimCtrl]),
.rdata_o (slave_rdata[SimCtrl])
); );
`endif `endif
@ -359,6 +376,8 @@ module tinyriscv_soc_top #(
`ifdef VERILATOR `ifdef VERILATOR
assign clk = clk_50m_i; assign clk = clk_50m_i;
`else `else
// 使用xilinx vivado中的mmcm IP进行分频
// 输入为50MHZ，输出为25MHZ
mmcm_main_clk u_mmcm_main_clk( mmcm_main_clk u_mmcm_main_clk(
.clk_out1(clk), .clk_out1(clk),
.resetn(rst_ext_ni), .resetn(rst_ext_ni),
@ -412,6 +431,8 @@ module tinyriscv_soc_top #(
.slave_addr_i (slave_addr[JtagDevice]), .slave_addr_i (slave_addr[JtagDevice]),
.slave_be_i (slave_be[JtagDevice]), .slave_be_i (slave_be[JtagDevice]),
.slave_wdata_i (slave_wdata[JtagDevice]), .slave_wdata_i (slave_wdata[JtagDevice]),
.slave_gnt_o (slave_gnt[JtagDevice]),
.slave_rvalid_o (slave_rvalid[JtagDevice]),
.slave_rdata_o (slave_rdata[JtagDevice]) .slave_rdata_o (slave_rdata[JtagDevice])
); );

5
sim/sim_ctrl.sv
View File

@ -30,6 +30,7 @@ module sim_ctrl(
input logic we_i, input logic we_i,
input logic[3:0] be_i, input logic[3:0] be_i,
input logic[31:0] wdata_i, input logic[31:0] wdata_i,
output logic rvalid_o,
output logic[31:0] rdata_o output logic[31:0] rdata_o
); );
@ -43,8 +44,10 @@ module sim_ctrl(
always_ff @ (posedge clk_i or negedge rst_ni) begin always_ff @ (posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin if (!rst_ni) begin
dump_wave_en_o <= 1'b0; dump_wave_en_o <= 1'b0;
rvalid_o <= 1'b0;
end else begin end else begin
if (we_i) begin rvalid_o <= req_i;
if (req_i & we_i) begin
case (reg_addr) case (reg_addr)
`REG_CTRL: begin `REG_CTRL: begin
if (be_i[0] & wdata_i[0]) begin if (be_i[0] & wdata_i[0]) begin