From b3cfa2dfa6c8a45ea1b567e35a3c78d9ff1fcbf0 Mon Sep 17 00:00:00 2001
From: liangkangnan <liangkangnan@163.com>
Date: Sat, 1 Apr 2023 14:12:59 +0800
Subject: [PATCH] rtl: do not need request all the access period

Signed-off-by: liangkangnan <liangkangnan@163.com>
---
 rtl/core/exu_mem.sv   | 10 ----------
 rtl/core/ifu.sv       | 21 +++++++++++++--------
 rtl/debug/jtag_sba.sv |  5 -----
 3 files changed, 13 insertions(+), 23 deletions(-)

diff --git a/rtl/core/exu_mem.sv b/rtl/core/exu_mem.sv
index 1896d18..eca5b41 100644
--- a/rtl/core/exu_mem.sv
+++ b/rtl/core/exu_mem.sv
@@ -166,13 +166,8 @@ module exu_mem(
 
             // 读内存
             S_WAIT_READ: begin
-                req_mem_d = 1'b1;
                 mem_stall_d = 1'b1;
-                if (~mem_gnt_i) begin
-                    state_d = S_IDLE;
-                end
                 if (mem_rvalid_i) begin
-                    req_mem_d = 1'b0;
                     state_d = S_IDLE;
                     mem_reg_we_d = 1'b1;
                     mem_stall_d = 1'b0;
@@ -181,13 +176,8 @@ module exu_mem(
 
             // 写内存
             S_WAIT_WRITE: begin
-                req_mem_d = 1'b1;
                 mem_stall_d = 1'b1;
-                if (~mem_gnt_i) begin
-                    state_d = S_IDLE;
-                end
                 if (mem_rvalid_i) begin
-                    req_mem_d = 1'b0;
                     state_d = S_IDLE;
                     mem_stall_d = 1'b0;
                 end
diff --git a/rtl/core/ifu.sv b/rtl/core/ifu.sv
index a5cdb58..f55e309 100644
--- a/rtl/core/ifu.sv
+++ b/rtl/core/ifu.sv
@@ -55,6 +55,7 @@ module ifu #(
     wire[31:0] fetch_addr_n;
     reg[31:0] fetch_addr_q;
     reg inst_valid_d;
+    reg instr_req_d;
 
     wire prdt_taken;
     wire[31:0] prdt_addr;
@@ -67,6 +68,7 @@ module ifu #(
     always @ (*) begin
         state_d = state_q;
         inst_valid_d = 0;
+        instr_req_d = 1'b0;
 
         case (state_q)
             // 复位
@@ -79,6 +81,7 @@ module ifu #(
 
             // 取指
             S_FETCH: begin
+                instr_req_d = 1'b1;
                 // 取指有效
                 if (req_valid) begin
                     state_d = S_VALID;
@@ -87,12 +90,14 @@ module ifu #(
 
             // 指令有效
             S_VALID: begin
-                // 取指无效
-                if (~req_valid) begin
-                    state_d = S_FETCH;
-                end
-                if (instr_rvalid_i) begin
-                    inst_valid_d = 1'b1;
+                if (instr_rvalid_i | flush_i) begin
+                    if (instr_rvalid_i) begin
+                        inst_valid_d = 1'b1;
+                    end
+                    instr_req_d = 1'b1;
+                    if (~req_valid) begin
+                        state_d = S_FETCH;
+                    end
                 end
             end
 
@@ -113,8 +118,8 @@ module ifu #(
                           inst_valid     ? fetch_addr_q + 4'h4:
                           fetch_addr_q;
 
-    // 取指请求(连续不断地取指)
-    assign instr_req_o  = (state_q != S_RESET);
+    // 取指请求
+    assign instr_req_o  = instr_req_d;
     // 取指地址(4字节对齐)
     assign instr_addr_o = {fetch_addr_n[31:2], 2'b00};
 
diff --git a/rtl/debug/jtag_sba.sv b/rtl/debug/jtag_sba.sv
index 59ef4af..ddb9b5c 100644
--- a/rtl/debug/jtag_sba.sv
+++ b/rtl/debug/jtag_sba.sv
@@ -151,12 +151,7 @@ module jtag_sba(
 
             // 等待读写完成
             S_WAIT: begin
-                master_req = 1'b1;
-                if (~master_gnt_i) begin
-                    state_d = S_IDLE;
-                end
                 if (master_rvalid_i) begin
-                    master_req = 1'b0;
                     state_d = S_IDLE;
                     if (sbautoincrement_i) begin
                         sbaddress = sbaddress_new;