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rtl: do not need request all the access period 

Signed-off-by: liangkangnan <liangkangnan@163.com>
verilator
liangkangnan 2023-04-01 14:12:59 +08:00
parent 1b296983eb
commit b3cfa2dfa6
3 changed files with 13 additions and 23 deletions
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10
rtl/core/exu_mem.sv
View File

@ -166,13 +166,8 @@ module exu_mem(
// 读内存 // 读内存
S_WAIT_READ: begin S_WAIT_READ: begin
req_mem_d = 1'b1;
mem_stall_d = 1'b1; mem_stall_d = 1'b1;
if (~mem_gnt_i) begin
state_d = S_IDLE;
end
if (mem_rvalid_i) begin if (mem_rvalid_i) begin
req_mem_d = 1'b0;
state_d = S_IDLE; state_d = S_IDLE;
mem_reg_we_d = 1'b1; mem_reg_we_d = 1'b1;
mem_stall_d = 1'b0; mem_stall_d = 1'b0;
@ -181,13 +176,8 @@ module exu_mem(
// 写内存 // 写内存
S_WAIT_WRITE: begin S_WAIT_WRITE: begin
req_mem_d = 1'b1;
mem_stall_d = 1'b1; mem_stall_d = 1'b1;
if (~mem_gnt_i) begin
state_d = S_IDLE;
end
if (mem_rvalid_i) begin if (mem_rvalid_i) begin
req_mem_d = 1'b0;
state_d = S_IDLE; state_d = S_IDLE;
mem_stall_d = 1'b0; mem_stall_d = 1'b0;
end end

15
rtl/core/ifu.sv
View File

@ -55,6 +55,7 @@ module ifu #(
wire[31:0] fetch_addr_n; wire[31:0] fetch_addr_n;
reg[31:0] fetch_addr_q; reg[31:0] fetch_addr_q;
reg inst_valid_d; reg inst_valid_d;
reg instr_req_d;
wire prdt_taken; wire prdt_taken;
wire[31:0] prdt_addr; wire[31:0] prdt_addr;
@ -67,6 +68,7 @@ module ifu #(
always @ (*) begin always @ (*) begin
state_d = state_q; state_d = state_q;
inst_valid_d = 0; inst_valid_d = 0;
instr_req_d = 1'b0;
case (state_q) case (state_q)
// 复位 // 复位
@ -79,6 +81,7 @@ module ifu #(
// 取指 // 取指
S_FETCH: begin S_FETCH: begin
instr_req_d = 1'b1;
// 取指有效 // 取指有效
if (req_valid) begin if (req_valid) begin
state_d = S_VALID; state_d = S_VALID;
@ -87,12 +90,14 @@ module ifu #(
// 指令有效 // 指令有效
S_VALID: begin S_VALID: begin
// 取指无效 if (instr_rvalid_i | flush_i) begin
if (instr_rvalid_i) begin
inst_valid_d = 1'b1;
end
instr_req_d = 1'b1;
if (~req_valid) begin if (~req_valid) begin
state_d = S_FETCH; state_d = S_FETCH;
end end
if (instr_rvalid_i) begin
inst_valid_d = 1'b1;
end end
end end
@ -113,8 +118,8 @@ module ifu #(
inst_valid ? fetch_addr_q + 4'h4: inst_valid ? fetch_addr_q + 4'h4:
fetch_addr_q; fetch_addr_q;
// 取指请求(连续不断地取指) // 取指请求
assign instr_req_o = (state_q != S_RESET); assign instr_req_o = instr_req_d;
// 取指地址(4字节对齐) // 取指地址(4字节对齐)
assign instr_addr_o = {fetch_addr_n[31:2], 2'b00}; assign instr_addr_o = {fetch_addr_n[31:2], 2'b00};

5
rtl/debug/jtag_sba.sv
View File

@ -151,12 +151,7 @@ module jtag_sba(
// 等待读写完成 // 等待读写完成
S_WAIT: begin S_WAIT: begin
master_req = 1'b1;
if (~master_gnt_i) begin
state_d = S_IDLE;
end
if (master_rvalid_i) begin if (master_rvalid_i) begin
master_req = 1'b0;
state_d = S_IDLE; state_d = S_IDLE;
if (sbautoincrement_i) begin if (sbautoincrement_i) begin
sbaddress = sbaddress_new; sbaddress = sbaddress_new;