parent
1dea4a0a5e
commit
eec414aa96
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@ -170,32 +170,32 @@ module csr_reg(
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// clint模块读CSR寄存器
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always @ (*) begin
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if (rst == `RstEnable) begin
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clint_data_o <= `ZeroWord;
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clint_data_o = `ZeroWord;
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end else begin
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case (clint_raddr_i[11:0])
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`CSR_CYCLE: begin
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clint_data_o <= cycle[31:0];
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clint_data_o = cycle[31:0];
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end
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`CSR_CYCLEH: begin
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clint_data_o <= cycle[63:32];
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clint_data_o = cycle[63:32];
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end
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`CSR_MTVEC: begin
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clint_data_o <= mtvec;
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clint_data_o = mtvec;
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end
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`CSR_MCAUSE: begin
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clint_data_o <= mcause;
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clint_data_o = mcause;
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end
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`CSR_MEPC: begin
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clint_data_o <= mepc;
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clint_data_o = mepc;
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end
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`CSR_MIE: begin
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clint_data_o <= mie;
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clint_data_o = mie;
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end
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`CSR_MSTATUS: begin
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clint_data_o <= mstatus;
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clint_data_o = mstatus;
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end
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default: begin
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clint_data_o <= `ZeroWord;
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clint_data_o = `ZeroWord;
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end
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endcase
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end
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@ -66,39 +66,39 @@ module regs(
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// 读寄存器1
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always @ (*) begin
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if (rst == `RstEnable) begin
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rdata1_o <= `ZeroWord;
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rdata1_o = `ZeroWord;
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end else if (raddr1_i == `RegNumLog2'h0) begin
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rdata1_o <= `ZeroWord;
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rdata1_o = `ZeroWord;
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// 如果读地址等于写地址,并且正在写操作,则直接返回写数据
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end else if (raddr1_i == waddr_i && we_i == `WriteEnable) begin
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rdata1_o <= wdata_i;
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rdata1_o = wdata_i;
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end else begin
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rdata1_o <= regs[raddr1_i];
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rdata1_o = regs[raddr1_i];
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end
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end
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// 读寄存器2
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always @ (*) begin
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if (rst == `RstEnable) begin
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rdata2_o <= `ZeroWord;
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rdata2_o = `ZeroWord;
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end else if (raddr2_i == `RegNumLog2'h0) begin
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rdata2_o <= `ZeroWord;
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rdata2_o = `ZeroWord;
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// 如果读地址等于写地址,并且正在写操作,则直接返回写数据
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end else if (raddr2_i == waddr_i && we_i == `WriteEnable) begin
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rdata2_o <= wdata_i;
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rdata2_o = wdata_i;
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end else begin
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rdata2_o <= regs[raddr2_i];
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rdata2_o = regs[raddr2_i];
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end
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end
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// jtag读寄存器
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always @ (*) begin
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if (rst == `RstEnable) begin
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jtag_data_o <= `ZeroWord;
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jtag_data_o = `ZeroWord;
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end else if (jtag_addr_i == `RegNumLog2'h0) begin
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jtag_data_o <= `ZeroWord;
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jtag_data_o = `ZeroWord;
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end else begin
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jtag_data_o <= regs[jtag_addr_i];
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jtag_data_o = regs[jtag_addr_i];
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end
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end
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