debug: fix step

Signed-off-by: liangkangnan <liangkangnan@163.com>

rtl/core/exception.sv

@@ -41,6 +41,7 @@ module exception (
     input wire rst_n,
 
     input wire inst_valid_i,
+    input wire inst_executed_i,
     input wire inst_ecall_i,                    // ecall指令
     input wire inst_ebreak_i,                   // ebreak指令
     input wire inst_mret_i,                     // mret指令
@@ -164,7 +165,7 @@ module exception (
     reg[31:0] exception_offset;
 
     always @ (*) begin
-        if (inst_ecall_i) begin
+        if (inst_ecall_i & inst_valid_i) begin
             exception_req = 1'b1;
             exception_cause = `CAUSE_EXCEP_ECALL_M;
             exception_offset = ECALL_OFFSET;
@@ -201,7 +202,7 @@ module exception (
         if (trigger_match_i & inst_valid_i) begin
             enter_debug_cause_trigger = 1'b1;
             dcsr_cause_d = `DCSR_CAUSE_TRIGGER;
-        end else if (inst_ebreak_i) begin
+        end else if (inst_ebreak_i & inst_valid_i) begin
             enter_debug_cause_ebreak = 1'b1;
             dcsr_cause_d = `DCSR_CAUSE_EBREAK;
         end else if ((inst_addr_i == `CPU_RESET_ADDR) & inst_valid_i & debug_req_i) begin
@@ -210,7 +211,7 @@ module exception (
         end else if ((~debug_mode_q) & debug_req_i & inst_valid_i) begin
             enter_debug_cause_debugger_req = 1'b1;
             dcsr_cause_d = `DCSR_CAUSE_DBGREQ;
-        end else if ((~debug_mode_q) & dcsr_i[2] & (state_q == S_IDLE)) begin
+        end else if ((~debug_mode_q) & dcsr_i[2] & inst_valid_i & inst_executed_i) begin
             enter_debug_cause_single_step = 1'b1;
             dcsr_cause_d = `DCSR_CAUSE_STEP;
         end

rtl/core/exu.sv

@@ -17,7 +17,6 @@
 `include "defines.sv"
 
 // 执行模块
-// 纯组合逻辑电路
 module exu(
 
     input wire clk,
@@ -62,6 +61,7 @@ module exu(
 
     //
     output wire inst_valid_o,
+    output wire inst_executed_o,
 
     // from idu_exu
     input wire inst_valid_i,
@@ -369,7 +369,8 @@ module exu(
 
     assign reg_we_o = commit_reg_we_o & (~int_stall_i);
 
-    assign jump_flag_o = ((bjp_cmp_res_o | bjp_op_jump_o | sys_op_fence_o) & (~int_stall_i)) | int_assert_i;
+    wire inst_jump = bjp_cmp_res_o | bjp_op_jump_o | sys_op_fence_o;
+    assign jump_flag_o = (inst_jump & (~int_stall_i)) | int_assert_i;
     assign jump_addr_o = int_assert_i? int_addr_i:
                          sys_op_fence_o? next_pc_i:
                          bjp_res_o;
@@ -385,4 +386,21 @@ module exu(
 
     assign inst_valid_o = hold_flag_o? 1'b0: inst_valid_i;
 
+    reg inst_executed_q;
+
+    always @ (posedge clk or negedge rst_n) begin
+        if (!rst_n) begin
+            inst_executed_q <= 1'b0;
+        end else begin
+            if (inst_valid_i) begin
+                inst_executed_q <= (inst_jump & (~int_stall_i)) |
+                                   reg_we_o |
+                                   csr_we_o |
+                                   mem_we_o;
+            end
+        end
+    end
+
+    assign inst_executed_o = inst_executed_q;
+
 endmodule

rtl/core/tinyriscv_core.sv

@@ -114,6 +114,7 @@ module tinyriscv_core #(
     wire ex_inst_mret_o;
     wire ex_inst_dret_o;
     wire ex_inst_valid_o;
+    wire ex_inst_executed_o;
 
     // gpr_reg模块输出信号
     wire[31:0] regs_rdata1_o;
@@ -300,6 +301,7 @@ module tinyriscv_core #(
         .csr_waddr_o(ex_csr_waddr_o),
         .inst_valid_o(ex_inst_valid_o),
         .inst_valid_i(ie_inst_valid_o),
+        .inst_executed_o(ex_inst_executed_o),
         .inst_i(ie_inst_o),
         .dec_info_bus_i(ie_dec_info_bus_o),
         .dec_imm_i(ie_dec_imm_o),
@@ -313,6 +315,7 @@ module tinyriscv_core #(
         .clk(clk),
         .rst_n(rst_n),
         .inst_valid_i(ie_inst_valid_o),
+        .inst_executed_i(ex_inst_executed_o),
         .inst_ecall_i(ex_inst_ecall_o),
         .inst_ebreak_i(ex_inst_ebreak_o),
         .inst_mret_i(ex_inst_mret_o),