liangkangnan
|
0ed81ff1a8
|
rtl: remove unused signals
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-08-29 22:35:43 +08:00 |
|
liangkangnan
|
10a3df3e5a
|
rtl: core: fix sync interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-08-15 16:05:06 +08:00 |
Blue Liang
|
fccb920070
|
rtl: core: optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-08-13 09:01:27 +08:00 |
|
Blue Liang
|
fa958a6153
|
rtl: rib: arbitrated by logic instead of clock
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-08-13 08:56:01 +08:00 |
|
liangkangnan
|
e23ad11e7e
|
rtl: fix sync interrupt return address
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-25 22:15:03 +08:00 |
|
liangkangnan
|
b39062a4ea
|
rtl: fix interrupt return address
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-25 16:23:45 +08:00 |
|
liangkangnan
|
b0c4d1fa4d
|
rtl:timer: update interrupt assert
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-12 22:33:15 +08:00 |
|
liangkangnan
|
a73b0ea36b
|
rtl: add uart_debug module
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-04 14:32:31 +08:00 |
|
liangkangnan
|
4c6c044afb
|
rtl: add uart rx function
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-06-26 22:40:44 +08:00 |
|
liangkangnan
|
2619f26eae
|
gpio: add input function
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-06-14 10:40:25 +08:00 |
|
liangkangnan
|
e28381dbcf
|
add support for ebreak inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-06-13 14:56:44 +08:00 |
|
liangkangnan
|
5b888bd483
|
rtl: core: fix data related for csr regs
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-06-05 22:22:49 +08:00 |
|
liangkangnan
|
de9a978417
|
fix: must exit openocd after download temporary
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-31 14:41:39 +08:00 |
|
liangkangnan
|
eec414aa96
|
use = instead of <=
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-31 14:38:57 +08:00 |
|
liangkangnan
|
834fcfb3ef
|
debug: optimization for jtag
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-13 21:27:40 +08:00 |
|
liangkangnan
|
260246f488
|
fix nop inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-07 22:40:31 +08:00 |
|
liangkangnan
|
07b33baf94
|
perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-05 18:31:08 +08:00 |
|
liangkangnan
|
837af2c977
|
use = instead of <= in combination logic
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-02 11:58:44 +08:00 |
|
liangkangnan
|
043bc23f8a
|
use = instead of <= in combination logic
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-02 11:57:25 +08:00 |
|
liangkangnan
|
d7bdc35911
|
fix uninitial reg var
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-02 11:53:48 +08:00 |
|
liangkangnan
|
aead35700c
|
add signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:15:46 +08:00 |
|
liangkangnan
|
d92352e1c2
|
use relative include path
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:15:00 +08:00 |
|
liangkangnan
|
02d19b9e6f
|
add mie and mstatus reg
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:13:12 +08:00 |
|
liangkangnan
|
4a530ab894
|
add ECALL inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:11:53 +08:00 |
|
liangkangnan
|
02bcee9aa9
|
sync for different clock
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:10:11 +08:00 |
|
liangkangnan
|
43aca8195c
|
add clint hold input signal
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:08:46 +08:00 |
|
liangkangnan
|
6cf86e0286
|
stop div when interrupt assert
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:04:44 +08:00 |
|
liangkangnan
|
09513f8f2c
|
support preemption
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-25 17:03:13 +08:00 |
|
liangkangnan
|
dcac95dfab
|
add code comments
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 20:14:37 +08:00 |
|
liangkangnan
|
18577d9b61
|
use oneshot mode
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:37:22 +08:00 |
|
liangkangnan
|
ce225394df
|
fix reg1 reg2 bits width
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:35:43 +08:00 |
|
liangkangnan
|
b29781a8de
|
optimize div
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:23:46 +08:00 |
|
liangkangnan
|
2638240d0b
|
add mepc reg
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:22:20 +08:00 |
|
liangkangnan
|
96f8d6e5a0
|
optimized: use statemachine
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-18 11:21:09 +08:00 |
|
liangkangnan
|
0e188d4934
|
reorganize example and optimize interrupt
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-11 19:03:49 +08:00 |
|
liangkangnan
|
b2827b2fb4
|
uart: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-06 19:54:40 +08:00 |
|
liangkangnan
|
e714a0ba63
|
add write dpc
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-06 14:34:12 +08:00 |
|
liangkangnan
|
a68f31b604
|
perips: add uart_tx and gpio
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-05 22:27:00 +08:00 |
|
liangkangnan
|
6660f18b3d
|
support CSR inst
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-04-05 22:22:34 +08:00 |
|
liangkangnan
|
ecb9fca8c1
|
update
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-29 23:19:14 +08:00 |
|
liangkangnan
|
8b51737477
|
add interrupt support and example
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-08 15:09:30 +08:00 |
|
liangkangnan
|
c7c9193982
|
add peripheral: timer
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-08 15:07:17 +08:00 |
|
liangkangnan
|
8208cbc100
|
support JTAG
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-03-01 14:55:36 +08:00 |
|
liangkangnan
|
0d4e8bb5f4
|
improve ex module
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-23 17:51:55 +08:00 |
|
liangkangnan
|
076610fb0d
|
rename openriscv to tinyriscv
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-23 17:01:45 +08:00 |
|
liangkangnan
|
97c7cee0ad
|
return to IDLE state when div completed
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-22 20:38:16 +08:00 |
|
liangkangnan
|
3b1807c467
|
fix: multi drive error
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-22 15:24:10 +08:00 |
|
liangkangnan
|
f0bd0845d6
|
fix implementation error by EDA tool
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-02-16 21:27:11 +08:00 |
|
Blue Liang
|
9420b85796
|
add div inst
Signed-off-by: Blue Liang <liangkangnan@163.com>
|
2020-01-13 08:26:41 +08:00 |
|
Blue Liang
|
97efd66e78
|
add mul instruction
Signed-off-by: Blue Liang <liangkangnan@163.com>
|
2020-01-02 16:12:13 +08:00 |