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294 Commits (22a038cc0925a9292936be63cb8e03d01ba058a4)

Author SHA1 Message Date
liangkangnan 05e2441d24 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-13 16:34:00 +08:00
liangkangnan 9ac1b31965 rtl: add reset module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-13 14:12:47 +08:00
liangkangnan 7803e89d68 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-13 11:10:06 +08:00
liangkangnan e53f681063 rtl: optimize csr regs 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-13 09:25:29 +08:00
liangkangnan bd2d372c66 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-12 19:18:35 +08:00
liangkangnan 16fa475ba7 rtl:perips: remove vld rdy signals 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-09 20:47:00 +08:00
liangkangnan ad775ef316 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-09 20:27:33 +08:00
liangkangnan f1f09584ee optimize ifu and lsu 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-09 20:22:34 +08:00
liangkangnan e3667e0ddd temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-01 11:29:00 +08:00
liangkangnan 9943d02600 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-31 18:00:19 +08:00
liangkangnan c070f0b49d temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-31 15:25:22 +08:00
liangkangnan 9322b595bc tools: add openocd ex arrt 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 19:21:02 +08:00
Blue Liang e2c07ec19b temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 19:10:02 +08:00
Blue Liang b4b54d831b temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 18:22:52 +08:00
liangkangnan f23b545499 tools: BinToMem.py: use unix format 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 15:26:19 +08:00
Blue Liang 8214134b89 tmp commit, unstable 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 15:14:50 +08:00
liangkangnan 5c87fc09ef tb: add jtag testbench 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-12-06 20:07:06 +08:00
liangkangnan fdc776ab5e rtl: debug: support reset cmd 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-12-06 20:06:12 +08:00
liangkangnan f03f42fc9b rtl: add reset ctrl module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-11-18 22:15:08 +08:00
liangkangnan ceddc1af24 test:example: move C examples to sdk directory 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-11-08 22:09:38 +08:00
liangkangnan 5c9f1a140e rtl: add mem access misaligned exception 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-11-08 22:08:03 +08:00
Blue Liang 60a4f7d6df rtl: add generate block name 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-26 17:01:04 +08:00
liangkangnan eb5647915a python scripts: remove verison 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-25 12:02:26 +08:00
liangkangnan 2b44f1e8f3 first release 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-23 21:26:18 +08:00
liangkangnan b15a130862 sim: compliance_test: add utils modules 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-06 21:00:04 +08:00
liangkangnan 4876225f60 rtl: utils: add full handshake CDC source 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-23 21:39:20 +08:00
liangkangnan 386ba909ba rtl: jtag: handle DM module in cpu clock domain 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-23 21:37:00 +08:00
liangkangnan 633a1d0b15 rtl: debug: fix latch 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-20 22:18:58 +08:00
liangkangnan 29623c8d2a rtl: div: fix error 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-14 22:22:42 +08:00
liangkangnan 045f482fe1 rtl: jtag: optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-13 17:47:18 +08:00
liangkangnan 442e9e8f5c tb: add jtag test result 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:54:56 +08:00
liangkangnan 8c3d7ac932 rtl: div: timing optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:17:34 +08:00
liangkangnan 90f57951e4 sim: add gen_buf.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:16:02 +08:00
liangkangnan 8468303ba7 rtl: add gen_buf.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:14:59 +08:00
liangkangnan b57bfe7736 rtl: timing optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-09 21:00:14 +08:00
liangkangnan 5e4ab8c33c sim: add gen_dff.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-09 20:59:22 +08:00
liangkangnan a4a723e1e7 rtl: add gen_dff.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-09 20:58:08 +08:00
liangkangnan b6754f002c rtl: div: optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-06 23:17:56 +08:00
liangkangnan 0ed81ff1a8 rtl: remove unused signals 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-29 22:35:43 +08:00
liangkangnan 3cd30247d2 tests: example: support sync interrupt handle 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-15 16:09:16 +08:00
liangkangnan 10a3df3e5a rtl: core: fix sync interrupt 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-15 16:05:06 +08:00
Blue Liang fccb920070 rtl: core: optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-13 09:01:27 +08:00
Blue Liang fa958a6153 rtl: rib: arbitrated by logic instead of clock 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-13 08:56:01 +08:00
liangkangnan 4b5904df81 README: add new plan 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-02 21:06:55 +08:00
liangkangnan e23ad11e7e rtl: fix sync interrupt return address 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 22:15:03 +08:00
liangkangnan b39062a4ea rtl: fix interrupt return address 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 16:23:45 +08:00
liangkangnan 233bb1fb23 fpga: constrs: do not constraint JTAG_CLK clk 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 16:20:54 +08:00
liangkangnan 6e4764f73d example: common.mk: add Makefile dep 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 15:24:50 +08:00
liangkangnan 1ccdeb1b81 example: coremark: fix build error 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-21 22:34:15 +08:00
liangkangnan b0c4d1fa4d rtl:timer: update interrupt assert 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-12 22:33:15 +08:00