liangkangnan
|
769f93c70a
|
fpga: cmod_a7: add sch doc
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2022-10-10 09:03:42 +08:00 |
|
liangkangnan
|
384320c7b1
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fpga: constrs: change for cmod_a7 extern board
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2022-10-10 09:02:45 +08:00 |
|
liangkangnan
|
ed2644b66e
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fpga:README: update bin file download address
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2022-08-18 20:00:06 +08:00 |
|
liangkangnan
|
53ae450762
|
fpga: update README.md
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2022-08-18 09:17:40 +08:00 |
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liangkangnan
|
490c52054b
|
fpga: xilinx: cmod_a7: add bin.tcl and mcs.tcl
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2022-08-12 19:33:49 +08:00 |
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liangkangnan
|
4c16dfb254
|
rtl: move top module into fpga dir
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2022-08-10 08:13:38 +08:00 |
|
liangkangnan
|
3666009efc
|
fpga: xilinx: add tcl scripts
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2022-05-07 17:55:56 +08:00 |
|
liangkangnan
|
15928977e1
|
rtl:perips: add flash_ctrl module
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-11-02 10:54:37 +08:00 |
|
liangkangnan
|
3903d9e7f4
|
rtl:pinmux: add more spi mux
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-09-17 09:06:47 +08:00 |
|
liangkangnan
|
3b7fa13a73
|
fpga:constrs: reassign pins
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-09-10 09:59:34 +08:00 |
|
liangkangnan
|
57690b00bd
|
rtl:perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-09-06 10:01:56 +08:00 |
|
liangkangnan
|
cd9e219d1b
|
fpga:xilinx:constrs: add i2c pin
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-08-19 09:44:36 +08:00 |
|
liangkangnan
|
53e4263706
|
rtl: ifu optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-07-03 15:09:13 +08:00 |
|
liangkangnan
|
a67fba652d
|
add mmcm module for xilinx fpga
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-05-20 11:05:39 +08:00 |
|
liangkangnan
|
10d8d35a13
|
rtl: fix combilation loop
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2021-05-02 14:51:12 +08:00 |
|
liangkangnan
|
f03f42fc9b
|
rtl: add reset ctrl module
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-11-18 22:15:08 +08:00 |
|
liangkangnan
|
2b44f1e8f3
|
first release
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-10-23 21:26:18 +08:00 |
|
liangkangnan
|
233bb1fb23
|
fpga: constrs: do not constraint JTAG_CLK clk
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-25 16:20:54 +08:00 |
|
liangkangnan
|
4049559948
|
fpga: README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-07 23:09:48 +08:00 |
|
liangkangnan
|
6642662e71
|
fpga: add burn mcs file
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-04 22:58:25 +08:00 |
|
liangkangnan
|
f7b3dc8327
|
fpga: README: add uart download
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-04 16:27:53 +08:00 |
|
liangkangnan
|
8c751095fd
|
fpga: constrs: add uart_debug_en pin
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-07-04 14:33:33 +08:00 |
|
liangkangnan
|
317061682d
|
fpga: constrs: add uart rx pin
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-06-26 22:41:48 +08:00 |
|
liangkangnan
|
f2010755bb
|
fpga: constrs: add spi flash config
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-06-14 22:13:44 +08:00 |
|
liangkangnan
|
5c70814fc6
|
fpga: constrs: add one more gpio
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-06-14 10:41:52 +08:00 |
|
liangkangnan
|
5f64a5f8ae
|
fpga: update README.md
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-06-07 21:55:28 +08:00 |
|
liangkangnan
|
1dea4a0a5e
|
fpga: README: exit openocd after download
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-31 12:14:29 +08:00 |
|
liangkangnan
|
09d45f9ea9
|
rename FPGA to fpga
Signed-off-by: liangkangnan <liangkangnan@163.com>
|
2020-05-31 12:05:28 +08:00 |