liangkangnan
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4c16dfb254
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rtl: move top module into fpga dir
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2022-08-10 08:13:38 +08:00 |
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liangkangnan
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3666009efc
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fpga: xilinx: add tcl scripts
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2022-05-07 17:55:56 +08:00 |
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liangkangnan
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15928977e1
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rtl:perips: add flash_ctrl module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-11-02 10:54:37 +08:00 |
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liangkangnan
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3903d9e7f4
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rtl:pinmux: add more spi mux
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-09-17 09:06:47 +08:00 |
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liangkangnan
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3b7fa13a73
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fpga:constrs: reassign pins
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-09-10 09:59:34 +08:00 |
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liangkangnan
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57690b00bd
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rtl:perips: add spi master
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-09-06 10:01:56 +08:00 |
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liangkangnan
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cd9e219d1b
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fpga:xilinx:constrs: add i2c pin
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-19 09:44:36 +08:00 |
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liangkangnan
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53e4263706
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rtl: ifu optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-03 15:09:13 +08:00 |
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liangkangnan
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a67fba652d
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add mmcm module for xilinx fpga
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-20 11:05:39 +08:00 |
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liangkangnan
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10d8d35a13
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rtl: fix combilation loop
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-02 14:51:12 +08:00 |