liangkangnan
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2b44f1e8f3
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first release
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-10-23 21:26:18 +08:00 |
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liangkangnan
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386ba909ba
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rtl: jtag: handle DM module in cpu clock domain
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-23 21:37:00 +08:00 |
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liangkangnan
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633a1d0b15
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rtl: debug: fix latch
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-20 22:18:58 +08:00 |
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liangkangnan
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045f482fe1
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rtl: jtag: optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-13 17:47:18 +08:00 |
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liangkangnan
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b57bfe7736
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rtl: timing optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-09-09 21:00:14 +08:00 |
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liangkangnan
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a73b0ea36b
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rtl: add uart_debug module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-07-04 14:32:31 +08:00 |
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liangkangnan
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de9a978417
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fix: must exit openocd after download temporary
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-31 14:41:39 +08:00 |
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liangkangnan
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834fcfb3ef
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debug: optimization for jtag
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-13 21:27:40 +08:00 |
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liangkangnan
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d7bdc35911
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fix uninitial reg var
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-05-02 11:53:48 +08:00 |
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liangkangnan
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02bcee9aa9
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sync for different clock
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-25 17:10:11 +08:00 |
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liangkangnan
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e714a0ba63
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add write dpc
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-04-06 14:34:12 +08:00 |
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liangkangnan
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ecb9fca8c1
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update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-29 23:19:14 +08:00 |
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liangkangnan
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8208cbc100
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support JTAG
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-03-01 14:55:36 +08:00 |