liangkangnan
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9387f56a33
|
sdk:examples: add uart_int
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-13 09:31:19 +08:00 |
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liangkangnan
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aaa5684cc9
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sdk:bsp: remove machine_timer
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-11 14:47:35 +08:00 |
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liangkangnan
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0437ff99da
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sdk: examples: remove machine_timer
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-10 11:30:08 +08:00 |
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liangkangnan
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79f83c1ad4
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tmp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-10 11:26:46 +08:00 |
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liangkangnan
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ad5adcb843
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tmp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-10 11:09:53 +08:00 |
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liangkangnan
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c4fe45ffaf
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sdk: examples: add timer
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-10 09:54:20 +08:00 |
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liangkangnan
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64041b4d2b
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rtl: perips: rewrite timer module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-10 09:47:37 +08:00 |
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liangkangnan
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f6c8a046c7
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tools:regtool: add README.md
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-07 15:26:12 +08:00 |
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liangkangnan
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c178a8fbb2
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tools: add regtool
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-07 15:07:44 +08:00 |
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liangkangnan
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72b982d133
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sdk:lib: rewrite uart
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-07 14:30:29 +08:00 |
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liangkangnan
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58f180a92f
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rtl: perips: rewrite uart module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-08-07 14:28:46 +08:00 |
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liangkangnan
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cba47c1f64
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use none-vector interrupt mode
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-26 09:54:38 +08:00 |
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liangkangnan
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9e7653a96a
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sdk:bsp: adapt to rvic
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-22 09:40:26 +08:00 |
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liangkangnan
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3227fb1ffd
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rtl:perips: add rvic
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-22 09:36:04 +08:00 |
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liangkangnan
|
e9044a7efe
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tests:random_instruction: add .gitignore
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-12 19:46:00 +08:00 |
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liangkangnan
|
5ebb41c477
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tests/random_instruction: add README.md
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-12 19:29:40 +08:00 |
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liangkangnan
|
8f3aa6bb2c
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tests: add random instruction
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-12 18:22:02 +08:00 |
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liangkangnan
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ac245a5d6c
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tools: add riscv-torture
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-12 18:13:01 +08:00 |
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liangkangnan
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18de7f2e00
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test: use csr_sstatus for test result
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-10 14:49:36 +08:00 |
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liangkangnan
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fd2c981317
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-09 15:18:09 +08:00 |
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liangkangnan
|
53e4263706
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rtl: ifu optimization
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-03 15:09:13 +08:00 |
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liangkangnan
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34218536c1
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-07-01 09:46:56 +08:00 |
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liangkangnan
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3269041c0b
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rtl: add config for branch predictor
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-28 11:31:04 +08:00 |
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liangkangnan
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2db9e7dbb9
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rtl: add sync_fifo module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-28 11:09:37 +08:00 |
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liangkangnan
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96d6976c44
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-19 16:33:50 +08:00 |
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liangkangnan
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5f56e8d0fb
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-18 20:04:46 +08:00 |
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liangkangnan
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4e99bd4f33
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README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-11 09:49:31 +08:00 |
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liangkangnan
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7196d33074
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rtl: add static branch predict unit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-11 09:44:26 +08:00 |
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liangkangnan
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e26dda807e
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README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-08 19:35:29 +08:00 |
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liangkangnan
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f9f78976fb
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rtl: core: optimize mem access
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 20:00:15 +08:00 |
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liangkangnan
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6121a21322
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rtl: top: make jtag host highest priority
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 19:59:07 +08:00 |
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liangkangnan
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4436e0cc6a
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tools: update openocd for win
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 19:48:41 +08:00 |
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liangkangnan
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b7b8572542
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tb: add tests type macro
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 16:59:26 +08:00 |
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liangkangnan
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d9a1f89fd2
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tests: riscv-compliance: add support
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 16:02:02 +08:00 |
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liangkangnan
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6059c4c3a7
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tests: isa: add support
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-05 15:11:33 +08:00 |
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liangkangnan
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c847244c5b
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rtl: perips: fix machine timer
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-06-03 09:23:50 +08:00 |
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liangkangnan
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646bc96419
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openocd: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-31 14:07:36 +08:00 |
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liangkangnan
|
6d8015727e
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-31 10:27:01 +08:00 |
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liangkangnan
|
247a5b6354
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-28 15:10:37 +08:00 |
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liangkangnan
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cd9ac0adae
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debug: change dmi addr bits to 7
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-28 10:37:50 +08:00 |
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liangkangnan
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fb461a6176
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-25 11:45:53 +08:00 |
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liangkangnan
|
c6163aaff1
|
temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-25 09:41:00 +08:00 |
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liangkangnan
|
fd5413791d
|
example: coremark: print tips after uart init
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-22 15:26:24 +08:00 |
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liangkangnan
|
87849fbd35
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README: update
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 17:08:46 +08:00 |
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liangkangnan
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5353371516
|
doc: add obi spec
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 17:06:39 +08:00 |
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liangkangnan
|
bffeebd0bf
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example:simple: add -g flag
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 17:05:56 +08:00 |
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liangkangnan
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b98e1c5538
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bsp: use self-build gcc
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 14:19:50 +08:00 |
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liangkangnan
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af63e677d9
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example: fix freertos
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 09:50:21 +08:00 |
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liangkangnan
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01c3159a83
|
use larger ram
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 09:43:34 +08:00 |
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liangkangnan
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a67fba652d
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add mmcm module for xilinx fpga
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-20 11:05:39 +08:00 |