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47 Commits (9a8637be12baf23dd230d54f84c04ee530d04021)

Author SHA1 Message Date
liangkangnan ae3ff5a211 rtl🚌 use gnt and rvalid signal 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-09-01 09:54:32 +08:00
liangkangnan 92e1e5a77a sim: add dump wave enable by softwave 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-08-20 11:50:21 +08:00
liangkangnan 18de7f2e00 test: use csr_sstatus for test result 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-07-10 14:49:36 +08:00
liangkangnan fd2c981317 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-07-09 15:18:09 +08:00
liangkangnan b7b8572542 tb: add tests type macro 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-06-05 16:59:26 +08:00
liangkangnan fb461a6176 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-25 11:45:53 +08:00
liangkangnan a67fba652d add mmcm module for xilinx fpga 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-20 11:05:39 +08:00
liangkangnan c7a374acb8 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-19 16:09:39 +08:00
liangkangnan 5811bdde13 debug: add hw breakpoint support 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-14 14:37:47 +08:00
liangkangnan 36147d9391 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-11 10:35:36 +08:00
liangkangnan 4a4c08bc69 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-05-04 21:11:43 +08:00
liangkangnan 53865371ce temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-30 16:41:24 +08:00
liangkangnan f9412fca3c temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-29 19:27:25 +08:00
liangkangnan ec65381ba9 temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-25 17:14:09 +08:00
liangkangnan 9ac1b31965 rtl: add reset module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-13 14:12:47 +08:00
liangkangnan f1f09584ee optimize ifu and lsu 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-04-09 20:22:34 +08:00
liangkangnan c070f0b49d temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-31 15:25:22 +08:00
Blue Liang 8214134b89 tmp commit, unstable 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 15:14:50 +08:00
liangkangnan 5c87fc09ef tb: add jtag testbench 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-12-06 20:07:06 +08:00
liangkangnan f03f42fc9b rtl: add reset ctrl module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-11-18 22:15:08 +08:00
liangkangnan eb5647915a python scripts: remove verison 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-25 12:02:26 +08:00
liangkangnan 2b44f1e8f3 first release 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-23 21:26:18 +08:00
liangkangnan b15a130862 sim: compliance_test: add utils modules 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-06 21:00:04 +08:00
liangkangnan 4876225f60 rtl: utils: add full handshake CDC source 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-23 21:39:20 +08:00
liangkangnan 90f57951e4 sim: add gen_buf.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:16:02 +08:00
liangkangnan 5e4ab8c33c sim: add gen_dff.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-09 20:59:22 +08:00
liangkangnan 15f10fbf35 sim: add uart_debug.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 17:21:50 +08:00
Blue Liang 4813893a34 sim: compliance_test: compare files line by line 
Signed-off-by: Blue Liang <liangkangnan@163.com>
 2020-06-28 20:26:12 +08:00
liangkangnan 1486b5aca8 sim: change uart_tx.v to uart.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-26 22:44:14 +08:00
liangkangnan c3e607ec55 sim: compliance_test: fix can not find ref file 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-06-05 22:16:36 +08:00
liangkangnan dfbb1ed6c1 sim: compliance_test: add README.md 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:47:55 +08:00
liangkangnan 8cb261b079 sim: add README.md 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:43:35 +08:00
liangkangnan 38c2245218 sim: remove tb file to tb dir 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:17:05 +08:00
liangkangnan f775abf1d7 sim: add compliance test script 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-27 23:08:43 +08:00
liangkangnan edee04cfe2 sim: fix vivado error 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-21 21:53:08 +08:00
liangkangnan 07b33baf94 perips: add spi master 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-05-05 18:31:08 +08:00
liangkangnan 0e188d4934 reorganize example and optimize interrupt 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-11 19:03:49 +08:00
liangkangnan 20d1055ea4 example: reorganization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-06 21:28:56 +08:00
liangkangnan a68f31b604 perips: add uart_tx and gpio 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-04-05 22:27:00 +08:00
liangkangnan ecb9fca8c1 update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-03-29 23:19:14 +08:00
liangkangnan a4148afa4d update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-03-08 15:29:53 +08:00
liangkangnan 8b51737477 add interrupt support and example 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-03-08 15:09:30 +08:00
liangkangnan c7c9193982 add peripheral: timer 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-03-08 15:07:17 +08:00
liangkangnan 8208cbc100 support JTAG 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-03-01 14:55:36 +08:00
liangkangnan 076610fb0d rename openriscv to tinyriscv 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-02-23 17:01:45 +08:00
Blue Liang 9420b85796 add div inst 
Signed-off-by: Blue Liang <liangkangnan@163.com>
 2020-01-13 08:26:41 +08:00
Blue Liang ac995f0b01 first release 
Signed-off-by: Blue Liang <liangkangnan@163.com>
 2019-12-04 08:47:19 +08:00