zcy
/
tinyriscv
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
181 Commits
3 Branches
9 Tags
66 MiB
Commit Graph

181 Commits (b4b54d831b58d133decdbd4d3bfe8a4b2ef2099e)

Author SHA1 Message Date
Blue Liang b4b54d831b temp commit 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 18:22:52 +08:00
liangkangnan f23b545499 tools: BinToMem.py: use unix format 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 15:26:19 +08:00
Blue Liang 8214134b89 tmp commit, unstable 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2021-03-29 15:14:50 +08:00
liangkangnan 5c87fc09ef tb: add jtag testbench 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-12-06 20:07:06 +08:00
liangkangnan fdc776ab5e rtl: debug: support reset cmd 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-12-06 20:06:12 +08:00
liangkangnan f03f42fc9b rtl: add reset ctrl module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-11-18 22:15:08 +08:00
liangkangnan ceddc1af24 test:example: move C examples to sdk directory 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-11-08 22:09:38 +08:00
liangkangnan 5c9f1a140e rtl: add mem access misaligned exception 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-11-08 22:08:03 +08:00
Blue Liang 60a4f7d6df rtl: add generate block name 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-26 17:01:04 +08:00
liangkangnan eb5647915a python scripts: remove verison 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-25 12:02:26 +08:00
liangkangnan 2b44f1e8f3 first release 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-23 21:26:18 +08:00
liangkangnan b15a130862 sim: compliance_test: add utils modules 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-10-06 21:00:04 +08:00
liangkangnan 4876225f60 rtl: utils: add full handshake CDC source 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-23 21:39:20 +08:00
liangkangnan 386ba909ba rtl: jtag: handle DM module in cpu clock domain 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-23 21:37:00 +08:00
liangkangnan 633a1d0b15 rtl: debug: fix latch 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-20 22:18:58 +08:00
liangkangnan 29623c8d2a rtl: div: fix error 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-14 22:22:42 +08:00
liangkangnan 045f482fe1 rtl: jtag: optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-13 17:47:18 +08:00
liangkangnan 442e9e8f5c tb: add jtag test result 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:54:56 +08:00
liangkangnan 8c3d7ac932 rtl: div: timing optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:17:34 +08:00
liangkangnan 90f57951e4 sim: add gen_buf.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:16:02 +08:00
liangkangnan 8468303ba7 rtl: add gen_buf.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-12 14:14:59 +08:00
liangkangnan b57bfe7736 rtl: timing optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-09 21:00:14 +08:00
liangkangnan 5e4ab8c33c sim: add gen_dff.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-09 20:59:22 +08:00
liangkangnan a4a723e1e7 rtl: add gen_dff.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-09 20:58:08 +08:00
liangkangnan b6754f002c rtl: div: optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-09-06 23:17:56 +08:00
liangkangnan 0ed81ff1a8 rtl: remove unused signals 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-29 22:35:43 +08:00
liangkangnan 3cd30247d2 tests: example: support sync interrupt handle 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-15 16:09:16 +08:00
liangkangnan 10a3df3e5a rtl: core: fix sync interrupt 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-15 16:05:06 +08:00
Blue Liang fccb920070 rtl: core: optimization 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-13 09:01:27 +08:00
Blue Liang fa958a6153 rtl: rib: arbitrated by logic instead of clock 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-13 08:56:01 +08:00
liangkangnan 4b5904df81 README: add new plan 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-08-02 21:06:55 +08:00
liangkangnan e23ad11e7e rtl: fix sync interrupt return address 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 22:15:03 +08:00
liangkangnan b39062a4ea rtl: fix interrupt return address 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 16:23:45 +08:00
liangkangnan 233bb1fb23 fpga: constrs: do not constraint JTAG_CLK clk 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 16:20:54 +08:00
liangkangnan 6e4764f73d example: common.mk: add Makefile dep 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-25 15:24:50 +08:00
liangkangnan 1ccdeb1b81 example: coremark: fix build error 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-21 22:34:15 +08:00
liangkangnan b0c4d1fa4d rtl:timer: update interrupt assert 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-12 22:33:15 +08:00
liangkangnan 6f5fe893cb README: update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-11 16:09:59 +08:00
liangkangnan 506abe158f README: update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-07 23:15:45 +08:00
liangkangnan 4049559948 fpga: README: update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-07 23:09:48 +08:00
liangkangnan 43c3510fc2 README.md: update 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-05 23:03:54 +08:00
liangkangnan 6642662e71 fpga: add burn mcs file 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 22:58:25 +08:00
liangkangnan 96b2eca546 tb: set uart debug disable 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 17:31:58 +08:00
liangkangnan 15f10fbf35 sim: add uart_debug.v 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 17:21:50 +08:00
liangkangnan f7b3dc8327 fpga: README: add uart download 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 16:27:53 +08:00
liangkangnan ab185de7f5 tools: add uart download script 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 14:36:02 +08:00
liangkangnan 1c51a4e515 README: add uart download 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 14:34:46 +08:00
liangkangnan 8c751095fd fpga: constrs: add uart_debug_en pin 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 14:33:33 +08:00
liangkangnan a73b0ea36b rtl: add uart_debug module 
Signed-off-by: liangkangnan <liangkangnan@163.com>
 2020-07-04 14:32:31 +08:00
Blue Liang 4813893a34 sim: compliance_test: compare files line by line 
Signed-off-by: Blue Liang <liangkangnan@163.com>
 2020-06-28 20:26:12 +08:00