liangkangnan
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b98e1c5538
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bsp: use self-build gcc
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 14:19:50 +08:00 |
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liangkangnan
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af63e677d9
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example: fix freertos
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 09:50:21 +08:00 |
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liangkangnan
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01c3159a83
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use larger ram
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-21 09:43:34 +08:00 |
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liangkangnan
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a67fba652d
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add mmcm module for xilinx fpga
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-20 11:05:39 +08:00 |
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liangkangnan
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5efa66ee64
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debug: fix breakpoint
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-19 19:09:17 +08:00 |
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liangkangnan
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c7a374acb8
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-19 16:09:39 +08:00 |
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liangkangnan
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f08fd1b17e
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debug: fix step
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-19 15:35:11 +08:00 |
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liangkangnan
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6cd6532423
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example: add uart loopback
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-17 16:56:52 +08:00 |
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liangkangnan
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136dc45a09
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change core clock to 25MHZ
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-17 16:40:25 +08:00 |
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liangkangnan
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536d28ede3
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-17 10:22:04 +08:00 |
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liangkangnan
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b0f4592322
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-15 14:52:30 +08:00 |
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liangkangnan
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6e466fbbf7
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add perips
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-14 21:00:57 +08:00 |
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liangkangnan
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5811bdde13
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debug: add hw breakpoint support
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-14 14:37:47 +08:00 |
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liangkangnan
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b02b38bddc
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-11 16:21:58 +08:00 |
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liangkangnan
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36147d9391
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-11 10:35:36 +08:00 |
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liangkangnan
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4a4c08bc69
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-04 21:11:43 +08:00 |
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liangkangnan
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10d8d35a13
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rtl: fix combilation loop
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-05-02 14:51:12 +08:00 |
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liangkangnan
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738fba1d6f
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-30 18:27:30 +08:00 |
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liangkangnan
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53865371ce
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-30 16:41:24 +08:00 |
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liangkangnan
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dfa8bf490e
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bus: fix bug
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-30 08:59:10 +08:00 |
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liangkangnan
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f9412fca3c
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-29 19:27:25 +08:00 |
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liangkangnan
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77812d60df
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-26 14:08:26 +08:00 |
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liangkangnan
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4da79b6046
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debug: add sba module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-26 09:48:19 +08:00 |
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liangkangnan
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65a26842c4
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-25 19:34:21 +08:00 |
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liangkangnan
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ec65381ba9
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-25 17:14:09 +08:00 |
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liangkangnan
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462cc4c786
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 19:49:09 +08:00 |
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liangkangnan
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05e2441d24
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 16:34:00 +08:00 |
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liangkangnan
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9ac1b31965
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rtl: add reset module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 14:12:47 +08:00 |
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liangkangnan
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7803e89d68
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 11:10:06 +08:00 |
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liangkangnan
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e53f681063
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rtl: optimize csr regs
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-13 09:25:29 +08:00 |
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liangkangnan
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bd2d372c66
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-12 19:18:35 +08:00 |
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liangkangnan
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16fa475ba7
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rtl:perips: remove vld rdy signals
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:47:00 +08:00 |
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liangkangnan
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ad775ef316
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:27:33 +08:00 |
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liangkangnan
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f1f09584ee
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optimize ifu and lsu
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-09 20:22:34 +08:00 |
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liangkangnan
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e3667e0ddd
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-04-01 11:29:00 +08:00 |
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liangkangnan
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9943d02600
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-31 18:00:19 +08:00 |
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liangkangnan
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c070f0b49d
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-31 15:25:22 +08:00 |
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liangkangnan
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9322b595bc
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tools: add openocd ex arrt
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-29 19:21:02 +08:00 |
Blue Liang
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e2c07ec19b
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-29 19:10:02 +08:00 |
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Blue Liang
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b4b54d831b
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temp commit
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-29 18:22:52 +08:00 |
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liangkangnan
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f23b545499
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tools: BinToMem.py: use unix format
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-29 15:26:19 +08:00 |
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Blue Liang
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8214134b89
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tmp commit, unstable
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2021-03-29 15:14:50 +08:00 |
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liangkangnan
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5c87fc09ef
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tb: add jtag testbench
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-12-06 20:07:06 +08:00 |
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liangkangnan
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fdc776ab5e
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rtl: debug: support reset cmd
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-12-06 20:06:12 +08:00 |
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liangkangnan
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f03f42fc9b
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rtl: add reset ctrl module
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-11-18 22:15:08 +08:00 |
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liangkangnan
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ceddc1af24
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test:example: move C examples to sdk directory
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-11-08 22:09:38 +08:00 |
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liangkangnan
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5c9f1a140e
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rtl: add mem access misaligned exception
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-11-08 22:08:03 +08:00 |
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Blue Liang
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60a4f7d6df
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rtl: add generate block name
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-10-26 17:01:04 +08:00 |
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liangkangnan
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eb5647915a
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python scripts: remove verison
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-10-25 12:02:26 +08:00 |
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liangkangnan
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2b44f1e8f3
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first release
Signed-off-by: liangkangnan <liangkangnan@163.com>
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2020-10-23 21:26:18 +08:00 |